drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c

   1 /*
   2  * Toppoly TD028TTEC1 panel support
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Neo 1973 code (jbt6k74.c):
   8  * Copyright (C) 2006-2007 by OpenMoko, Inc.
   9  * Author: Harald Welte <laforge@openmoko.org>
  10  *
  11  * Ported and adapted from Neo 1973 U-Boot by:
  12  * H. Nikolaus Schaller <hns@goldelico.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify it
  15  * under the terms of the GNU General Public License version 2 as published by
  16  * the Free Software Foundation.
  17  *
  18  * This program is distributed in the hope that it will be useful, but WITHOUT
  19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  21  * more details.
  22  *
  23  * You should have received a copy of the GNU General Public License along with
  24  * this program.  If not, see <http://www.gnu.org/licenses/>.
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/delay.h>
  29 #include <linux/spi/spi.h>
  30 #include <linux/gpio.h>
  31
  32 #include "../dss/omapdss.h"
  33
  34 struct panel_drv_data {
  35         struct omap_dss_device dssdev;
  36         struct omap_dss_device *in;
  37
  38         struct videomode vm;
  39
  40         struct spi_device *spi_dev;
  41 };
  42
  43 static const struct videomode td028ttec1_panel_vm = {
  44         .hactive        = 480,
  45         .vactive        = 640,
  46         .pixelclock     = 22153000,
  47         .hfront_porch   = 24,
  48         .hsync_len      = 8,
  49         .hback_porch    = 8,
  50         .vfront_porch   = 4,
  51         .vsync_len      = 2,
  52         .vback_porch    = 2,
  53
  54         .flags          = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
  55                           DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_SYNC_POSEDGE |
  56                           DISPLAY_FLAGS_PIXDATA_NEGEDGE,
  57         /*
  58          * Note: According to the panel documentation:
  59          * SYNC needs to be driven on the FALLING edge
  60          */
  61 };
  62
  63 #define JBT_COMMAND     0x000
  64 #define JBT_DATA        0x100
  65
  66 static int jbt_ret_write_0(struct panel_drv_data *ddata, u8 reg)
  67 {
  68         int rc;
  69         u16 tx_buf = JBT_COMMAND | reg;
  70
  71         rc = spi_write(ddata->spi_dev, (u8 *)&tx_buf,
  72                         1*sizeof(u16));
  73         if (rc != 0)
  74                 dev_err(&ddata->spi_dev->dev,
  75                         "jbt_ret_write_0 spi_write ret %d\n", rc);
  76
  77         return rc;
  78 }
  79
  80 static int jbt_reg_write_1(struct panel_drv_data *ddata, u8 reg, u8 data)
  81 {
  82         int rc;
  83         u16 tx_buf[2];
  84
  85         tx_buf[0] = JBT_COMMAND | reg;
  86         tx_buf[1] = JBT_DATA | data;
  87         rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
  88                         2*sizeof(u16));
  89         if (rc != 0)
  90                 dev_err(&ddata->spi_dev->dev,
  91                         "jbt_reg_write_1 spi_write ret %d\n", rc);
  92
  93         return rc;
  94 }
  95
  96 static int jbt_reg_write_2(struct panel_drv_data *ddata, u8 reg, u16 data)
  97 {
  98         int rc;
  99         u16 tx_buf[3];
 100
 101         tx_buf[0] = JBT_COMMAND | reg;
 102         tx_buf[1] = JBT_DATA | (data >> 8);
 103         tx_buf[2] = JBT_DATA | (data & 0xff);
 104
 105         rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
 106                         3*sizeof(u16));
 107
 108         if (rc != 0)
 109                 dev_err(&ddata->spi_dev->dev,
 110                         "jbt_reg_write_2 spi_write ret %d\n", rc);
 111
 112         return rc;
 113 }
 114
 115 enum jbt_register {
 116         JBT_REG_SLEEP_IN                = 0x10,
 117         JBT_REG_SLEEP_OUT               = 0x11,
 118
 119         JBT_REG_DISPLAY_OFF             = 0x28,
 120         JBT_REG_DISPLAY_ON              = 0x29,
 121
 122         JBT_REG_RGB_FORMAT              = 0x3a,
 123         JBT_REG_QUAD_RATE               = 0x3b,
 124
 125         JBT_REG_POWER_ON_OFF            = 0xb0,
 126         JBT_REG_BOOSTER_OP              = 0xb1,
 127         JBT_REG_BOOSTER_MODE            = 0xb2,
 128         JBT_REG_BOOSTER_FREQ            = 0xb3,
 129         JBT_REG_OPAMP_SYSCLK            = 0xb4,
 130         JBT_REG_VSC_VOLTAGE             = 0xb5,
 131         JBT_REG_VCOM_VOLTAGE            = 0xb6,
 132         JBT_REG_EXT_DISPL               = 0xb7,
 133         JBT_REG_OUTPUT_CONTROL          = 0xb8,
 134         JBT_REG_DCCLK_DCEV              = 0xb9,
 135         JBT_REG_DISPLAY_MODE1           = 0xba,
 136         JBT_REG_DISPLAY_MODE2           = 0xbb,
 137         JBT_REG_DISPLAY_MODE            = 0xbc,
 138         JBT_REG_ASW_SLEW                = 0xbd,
 139         JBT_REG_DUMMY_DISPLAY           = 0xbe,
 140         JBT_REG_DRIVE_SYSTEM            = 0xbf,
 141
 142         JBT_REG_SLEEP_OUT_FR_A          = 0xc0,
 143         JBT_REG_SLEEP_OUT_FR_B          = 0xc1,
 144         JBT_REG_SLEEP_OUT_FR_C          = 0xc2,
 145         JBT_REG_SLEEP_IN_LCCNT_D        = 0xc3,
 146         JBT_REG_SLEEP_IN_LCCNT_E        = 0xc4,
 147         JBT_REG_SLEEP_IN_LCCNT_F        = 0xc5,
 148         JBT_REG_SLEEP_IN_LCCNT_G        = 0xc6,
 149
 150         JBT_REG_GAMMA1_FINE_1           = 0xc7,
 151         JBT_REG_GAMMA1_FINE_2           = 0xc8,
 152         JBT_REG_GAMMA1_INCLINATION      = 0xc9,
 153         JBT_REG_GAMMA1_BLUE_OFFSET      = 0xca,
 154
 155         JBT_REG_BLANK_CONTROL           = 0xcf,
 156         JBT_REG_BLANK_TH_TV             = 0xd0,
 157         JBT_REG_CKV_ON_OFF              = 0xd1,
 158         JBT_REG_CKV_1_2                 = 0xd2,
 159         JBT_REG_OEV_TIMING              = 0xd3,
 160         JBT_REG_ASW_TIMING_1            = 0xd4,
 161         JBT_REG_ASW_TIMING_2            = 0xd5,
 162
 163         JBT_REG_HCLOCK_VGA              = 0xec,
 164         JBT_REG_HCLOCK_QVGA             = 0xed,
 165 };
 166
 167 #define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
 168
 169 static int td028ttec1_panel_connect(struct omap_dss_device *dssdev)
 170 {
 171         struct panel_drv_data *ddata = to_panel_data(dssdev);
 172         struct omap_dss_device *in = ddata->in;
 173         int r;
 174
 175         if (omapdss_device_is_connected(dssdev))
 176                 return 0;
 177
 178         r = in->ops.dpi->connect(in, dssdev);
 179         if (r)
 180                 return r;
 181
 182         return 0;
 183 }
 184
 185 static void td028ttec1_panel_disconnect(struct omap_dss_device *dssdev)
 186 {
 187         struct panel_drv_data *ddata = to_panel_data(dssdev);
 188         struct omap_dss_device *in = ddata->in;
 189
 190         if (!omapdss_device_is_connected(dssdev))
 191                 return;
 192
 193         in->ops.dpi->disconnect(in, dssdev);
 194 }
 195
 196 static int td028ttec1_panel_enable(struct omap_dss_device *dssdev)
 197 {
 198         struct panel_drv_data *ddata = to_panel_data(dssdev);
 199         struct omap_dss_device *in = ddata->in;
 200         int r;
 201
 202         if (!omapdss_device_is_connected(dssdev))
 203                 return -ENODEV;
 204
 205         if (omapdss_device_is_enabled(dssdev))
 206                 return 0;
 207
 208         in->ops.dpi->set_timings(in, &ddata->vm);
 209
 210         r = in->ops.dpi->enable(in);
 211         if (r)
 212                 return r;
 213
 214         dev_dbg(dssdev->dev, "td028ttec1_panel_enable() - state %d\n",
 215                 dssdev->state);
 216
 217         /* three times command zero */
 218         r |= jbt_ret_write_0(ddata, 0x00);
 219         usleep_range(1000, 2000);
 220         r |= jbt_ret_write_0(ddata, 0x00);
 221         usleep_range(1000, 2000);
 222         r |= jbt_ret_write_0(ddata, 0x00);
 223         usleep_range(1000, 2000);
 224
 225         if (r) {
 226                 dev_warn(dssdev->dev, "transfer error\n");
 227                 goto transfer_err;
 228         }
 229
 230         /* deep standby out */
 231         r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x17);
 232
 233         /* RGB I/F on, RAM write off, QVGA through, SIGCON enable */
 234         r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE, 0x80);
 235
 236         /* Quad mode off */
 237         r |= jbt_reg_write_1(ddata, JBT_REG_QUAD_RATE, 0x00);
 238
 239         /* AVDD on, XVDD on */
 240         r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x16);
 241
 242         /* Output control */
 243         r |= jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0xfff9);
 244
 245         /* Sleep mode off */
 246         r |= jbt_ret_write_0(ddata, JBT_REG_SLEEP_OUT);
 247
 248         /* at this point we have like 50% grey */
 249
 250         /* initialize register set */
 251         r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE1, 0x01);
 252         r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE2, 0x00);
 253         r |= jbt_reg_write_1(ddata, JBT_REG_RGB_FORMAT, 0x60);
 254         r |= jbt_reg_write_1(ddata, JBT_REG_DRIVE_SYSTEM, 0x10);
 255         r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_OP, 0x56);
 256         r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_MODE, 0x33);
 257         r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
 258         r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
 259         r |= jbt_reg_write_1(ddata, JBT_REG_OPAMP_SYSCLK, 0x02);
 260         r |= jbt_reg_write_1(ddata, JBT_REG_VSC_VOLTAGE, 0x2b);
 261         r |= jbt_reg_write_1(ddata, JBT_REG_VCOM_VOLTAGE, 0x40);
 262         r |= jbt_reg_write_1(ddata, JBT_REG_EXT_DISPL, 0x03);
 263         r |= jbt_reg_write_1(ddata, JBT_REG_DCCLK_DCEV, 0x04);
 264         /*
 265          * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
 266          * to avoid red / blue flicker
 267          */
 268         r |= jbt_reg_write_1(ddata, JBT_REG_ASW_SLEW, 0x04);
 269         r |= jbt_reg_write_1(ddata, JBT_REG_DUMMY_DISPLAY, 0x00);
 270
 271         r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_A, 0x11);
 272         r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_B, 0x11);
 273         r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_C, 0x11);
 274         r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
 275         r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
 276         r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
 277         r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
 278
 279         r |= jbt_reg_write_2(ddata, JBT_REG_GAMMA1_FINE_1, 0x5533);
 280         r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_FINE_2, 0x00);
 281         r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_INCLINATION, 0x00);
 282         r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
 283
 284         r |= jbt_reg_write_2(ddata, JBT_REG_HCLOCK_VGA, 0x1f0);
 285         r |= jbt_reg_write_1(ddata, JBT_REG_BLANK_CONTROL, 0x02);
 286         r |= jbt_reg_write_2(ddata, JBT_REG_BLANK_TH_TV, 0x0804);
 287
 288         r |= jbt_reg_write_1(ddata, JBT_REG_CKV_ON_OFF, 0x01);
 289         r |= jbt_reg_write_2(ddata, JBT_REG_CKV_1_2, 0x0000);
 290
 291         r |= jbt_reg_write_2(ddata, JBT_REG_OEV_TIMING, 0x0d0e);
 292         r |= jbt_reg_write_2(ddata, JBT_REG_ASW_TIMING_1, 0x11a4);
 293         r |= jbt_reg_write_1(ddata, JBT_REG_ASW_TIMING_2, 0x0e);
 294
 295         r |= jbt_ret_write_0(ddata, JBT_REG_DISPLAY_ON);
 296
 297         dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
 298
 299 transfer_err:
 300
 301         return r ? -EIO : 0;
 302 }
 303
 304 static void td028ttec1_panel_disable(struct omap_dss_device *dssdev)
 305 {
 306         struct panel_drv_data *ddata = to_panel_data(dssdev);
 307         struct omap_dss_device *in = ddata->in;
 308
 309         if (!omapdss_device_is_enabled(dssdev))
 310                 return;
 311
 312         dev_dbg(dssdev->dev, "td028ttec1_panel_disable()\n");
 313
 314         jbt_ret_write_0(ddata, JBT_REG_DISPLAY_OFF);
 315         jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0x8002);
 316         jbt_ret_write_0(ddata, JBT_REG_SLEEP_IN);
 317         jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x00);
 318
 319         in->ops.dpi->disable(in);
 320
 321         dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
 322 }
 323
 324 static void td028ttec1_panel_set_timings(struct omap_dss_device *dssdev,
 325                                          struct videomode *vm)
 326 {
 327         struct panel_drv_data *ddata = to_panel_data(dssdev);
 328         struct omap_dss_device *in = ddata->in;
 329
 330         ddata->vm = *vm;
 331         dssdev->panel.vm = *vm;
 332
 333         in->ops.dpi->set_timings(in, vm);
 334 }
 335
 336 static void td028ttec1_panel_get_timings(struct omap_dss_device *dssdev,
 337                                          struct videomode *vm)
 338 {
 339         struct panel_drv_data *ddata = to_panel_data(dssdev);
 340
 341         *vm = ddata->vm;
 342 }
 343
 344 static int td028ttec1_panel_check_timings(struct omap_dss_device *dssdev,
 345                                           struct videomode *vm)
 346 {
 347         struct panel_drv_data *ddata = to_panel_data(dssdev);
 348         struct omap_dss_device *in = ddata->in;
 349
 350         return in->ops.dpi->check_timings(in, vm);
 351 }
 352
 353 static struct omap_dss_driver td028ttec1_ops = {
 354         .connect        = td028ttec1_panel_connect,
 355         .disconnect     = td028ttec1_panel_disconnect,
 356
 357         .enable         = td028ttec1_panel_enable,
 358         .disable        = td028ttec1_panel_disable,
 359
 360         .set_timings    = td028ttec1_panel_set_timings,
 361         .get_timings    = td028ttec1_panel_get_timings,
 362         .check_timings  = td028ttec1_panel_check_timings,
 363 };
 364
 365 static int td028ttec1_probe_of(struct spi_device *spi)
 366 {
 367         struct device_node *node = spi->dev.of_node;
 368         struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
 369         struct omap_dss_device *in;
 370
 371         in = omapdss_of_find_source_for_first_ep(node);
 372         if (IS_ERR(in)) {
 373                 dev_err(&spi->dev, "failed to find video source\n");
 374                 return PTR_ERR(in);
 375         }
 376
 377         ddata->in = in;
 378
 379         return 0;
 380 }
 381
 382 static int td028ttec1_panel_probe(struct spi_device *spi)
 383 {
 384         struct panel_drv_data *ddata;
 385         struct omap_dss_device *dssdev;
 386         int r;
 387
 388         dev_dbg(&spi->dev, "%s\n", __func__);
 389
 390         spi->bits_per_word = 9;
 391         spi->mode = SPI_MODE_3;
 392
 393         r = spi_setup(spi);
 394         if (r < 0) {
 395                 dev_err(&spi->dev, "spi_setup failed: %d\n", r);
 396                 return r;
 397         }
 398
 399         ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL);
 400         if (ddata == NULL)
 401                 return -ENOMEM;
 402
 403         dev_set_drvdata(&spi->dev, ddata);
 404
 405         ddata->spi_dev = spi;
 406
 407         if (!spi->dev.of_node)
 408                 return -ENODEV;
 409
 410         r = td028ttec1_probe_of(spi);
 411         if (r)
 412                 return r;
 413
 414         ddata->vm = td028ttec1_panel_vm;
 415
 416         dssdev = &ddata->dssdev;
 417         dssdev->dev = &spi->dev;
 418         dssdev->driver = &td028ttec1_ops;
 419         dssdev->type = OMAP_DISPLAY_TYPE_DPI;
 420         dssdev->owner = THIS_MODULE;
 421         dssdev->panel.vm = ddata->vm;
 422
 423         r = omapdss_register_display(dssdev);
 424         if (r) {
 425                 dev_err(&spi->dev, "Failed to register panel\n");
 426                 goto err_reg;
 427         }
 428
 429         return 0;
 430
 431 err_reg:
 432         omap_dss_put_device(ddata->in);
 433         return r;
 434 }
 435
 436 static int td028ttec1_panel_remove(struct spi_device *spi)
 437 {
 438         struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
 439         struct omap_dss_device *dssdev = &ddata->dssdev;
 440         struct omap_dss_device *in = ddata->in;
 441
 442         dev_dbg(&ddata->spi_dev->dev, "%s\n", __func__);
 443
 444         omapdss_unregister_display(dssdev);
 445
 446         td028ttec1_panel_disable(dssdev);
 447         td028ttec1_panel_disconnect(dssdev);
 448
 449         omap_dss_put_device(in);
 450
 451         return 0;
 452 }
 453
 454 static const struct of_device_id td028ttec1_of_match[] = {
 455         { .compatible = "omapdss,tpo,td028ttec1", },
 456         /* keep to not break older DTB */
 457         { .compatible = "omapdss,toppoly,td028ttec1", },
 458         {},
 459 };
 460
 461 MODULE_DEVICE_TABLE(of, td028ttec1_of_match);
 462
 463 static const struct spi_device_id td028ttec1_ids[] = {
 464         { "toppoly,td028ttec1", 0 },
 465         { "tpo,td028ttec1", 0},
 466         { /* sentinel */ }
 467 };
 468
 469 MODULE_DEVICE_TABLE(spi, td028ttec1_ids);
 470
 471
 472 static struct spi_driver td028ttec1_spi_driver = {
 473         .probe          = td028ttec1_panel_probe,
 474         .remove         = td028ttec1_panel_remove,
 475         .id_table       = td028ttec1_ids,
 476
 477         .driver         = {
 478                 .name   = "panel-tpo-td028ttec1",
 479                 .of_match_table = td028ttec1_of_match,
 480                 .suppress_bind_attrs = true,
 481         },
 482 };
 483
 484 module_spi_driver(td028ttec1_spi_driver);
 485
 486 MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
 487 MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver");
 488 MODULE_LICENSE("GPL");