drivers/gpu/drm/omapdrm/dss/dsi.c

   1 /*
   2  * Copyright (C) 2009 Nokia Corporation
   3  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #define DSS_SUBSYS_NAME "DSI"
  19
  20 #include <linux/kernel.h>
  21 #include <linux/mfd/syscon.h>
  22 #include <linux/regmap.h>
  23 #include <linux/io.h>
  24 #include <linux/clk.h>
  25 #include <linux/device.h>
  26 #include <linux/err.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/delay.h>
  29 #include <linux/mutex.h>
  30 #include <linux/module.h>
  31 #include <linux/semaphore.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/wait.h>
  36 #include <linux/workqueue.h>
  37 #include <linux/sched.h>
  38 #include <linux/slab.h>
  39 #include <linux/debugfs.h>
  40 #include <linux/pm_runtime.h>
  41 #include <linux/of.h>
  42 #include <linux/of_graph.h>
  43 #include <linux/of_platform.h>
  44 #include <linux/component.h>
  45 #include <linux/sys_soc.h>
  46
  47 #include <video/mipi_display.h>
  48
  49 #include "omapdss.h"
  50 #include "dss.h"
  51
  52 #define DSI_CATCH_MISSING_TE
  53
  54 struct dsi_reg { u16 module; u16 idx; };
  55
  56 #define DSI_REG(mod, idx)               ((const struct dsi_reg) { mod, idx })
  57
  58 /* DSI Protocol Engine */
  59
  60 #define DSI_PROTO                       0
  61 #define DSI_PROTO_SZ                    0x200
  62
  63 #define DSI_REVISION                    DSI_REG(DSI_PROTO, 0x0000)
  64 #define DSI_SYSCONFIG                   DSI_REG(DSI_PROTO, 0x0010)
  65 #define DSI_SYSSTATUS                   DSI_REG(DSI_PROTO, 0x0014)
  66 #define DSI_IRQSTATUS                   DSI_REG(DSI_PROTO, 0x0018)
  67 #define DSI_IRQENABLE                   DSI_REG(DSI_PROTO, 0x001C)
  68 #define DSI_CTRL                        DSI_REG(DSI_PROTO, 0x0040)
  69 #define DSI_GNQ                         DSI_REG(DSI_PROTO, 0x0044)
  70 #define DSI_COMPLEXIO_CFG1              DSI_REG(DSI_PROTO, 0x0048)
  71 #define DSI_COMPLEXIO_IRQ_STATUS        DSI_REG(DSI_PROTO, 0x004C)
  72 #define DSI_COMPLEXIO_IRQ_ENABLE        DSI_REG(DSI_PROTO, 0x0050)
  73 #define DSI_CLK_CTRL                    DSI_REG(DSI_PROTO, 0x0054)
  74 #define DSI_TIMING1                     DSI_REG(DSI_PROTO, 0x0058)
  75 #define DSI_TIMING2                     DSI_REG(DSI_PROTO, 0x005C)
  76 #define DSI_VM_TIMING1                  DSI_REG(DSI_PROTO, 0x0060)
  77 #define DSI_VM_TIMING2                  DSI_REG(DSI_PROTO, 0x0064)
  78 #define DSI_VM_TIMING3                  DSI_REG(DSI_PROTO, 0x0068)
  79 #define DSI_CLK_TIMING                  DSI_REG(DSI_PROTO, 0x006C)
  80 #define DSI_TX_FIFO_VC_SIZE             DSI_REG(DSI_PROTO, 0x0070)
  81 #define DSI_RX_FIFO_VC_SIZE             DSI_REG(DSI_PROTO, 0x0074)
  82 #define DSI_COMPLEXIO_CFG2              DSI_REG(DSI_PROTO, 0x0078)
  83 #define DSI_RX_FIFO_VC_FULLNESS         DSI_REG(DSI_PROTO, 0x007C)
  84 #define DSI_VM_TIMING4                  DSI_REG(DSI_PROTO, 0x0080)
  85 #define DSI_TX_FIFO_VC_EMPTINESS        DSI_REG(DSI_PROTO, 0x0084)
  86 #define DSI_VM_TIMING5                  DSI_REG(DSI_PROTO, 0x0088)
  87 #define DSI_VM_TIMING6                  DSI_REG(DSI_PROTO, 0x008C)
  88 #define DSI_VM_TIMING7                  DSI_REG(DSI_PROTO, 0x0090)
  89 #define DSI_STOPCLK_TIMING              DSI_REG(DSI_PROTO, 0x0094)
  90 #define DSI_VC_CTRL(n)                  DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20))
  91 #define DSI_VC_TE(n)                    DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20))
  92 #define DSI_VC_LONG_PACKET_HEADER(n)    DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20))
  93 #define DSI_VC_LONG_PACKET_PAYLOAD(n)   DSI_REG(DSI_PROTO, 0x010C + (n * 0x20))
  94 #define DSI_VC_SHORT_PACKET_HEADER(n)   DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20))
  95 #define DSI_VC_IRQSTATUS(n)             DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20))
  96 #define DSI_VC_IRQENABLE(n)             DSI_REG(DSI_PROTO, 0x011C + (n * 0x20))
  97
  98 /* DSIPHY_SCP */
  99
 100 #define DSI_PHY                         1
 101 #define DSI_PHY_OFFSET                  0x200
 102 #define DSI_PHY_SZ                      0x40
 103
 104 #define DSI_DSIPHY_CFG0                 DSI_REG(DSI_PHY, 0x0000)
 105 #define DSI_DSIPHY_CFG1                 DSI_REG(DSI_PHY, 0x0004)
 106 #define DSI_DSIPHY_CFG2                 DSI_REG(DSI_PHY, 0x0008)
 107 #define DSI_DSIPHY_CFG5                 DSI_REG(DSI_PHY, 0x0014)
 108 #define DSI_DSIPHY_CFG10                DSI_REG(DSI_PHY, 0x0028)
 109
 110 /* DSI_PLL_CTRL_SCP */
 111
 112 #define DSI_PLL                         2
 113 #define DSI_PLL_OFFSET                  0x300
 114 #define DSI_PLL_SZ                      0x20
 115
 116 #define DSI_PLL_CONTROL                 DSI_REG(DSI_PLL, 0x0000)
 117 #define DSI_PLL_STATUS                  DSI_REG(DSI_PLL, 0x0004)
 118 #define DSI_PLL_GO                      DSI_REG(DSI_PLL, 0x0008)
 119 #define DSI_PLL_CONFIGURATION1          DSI_REG(DSI_PLL, 0x000C)
 120 #define DSI_PLL_CONFIGURATION2          DSI_REG(DSI_PLL, 0x0010)
 121
 122 #define REG_GET(dsidev, idx, start, end) \
 123         FLD_GET(dsi_read_reg(dsidev, idx), start, end)
 124
 125 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
 126         dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
 127
 128 /* Global interrupts */
 129 #define DSI_IRQ_VC0             (1 << 0)
 130 #define DSI_IRQ_VC1             (1 << 1)
 131 #define DSI_IRQ_VC2             (1 << 2)
 132 #define DSI_IRQ_VC3             (1 << 3)
 133 #define DSI_IRQ_WAKEUP          (1 << 4)
 134 #define DSI_IRQ_RESYNC          (1 << 5)
 135 #define DSI_IRQ_PLL_LOCK        (1 << 7)
 136 #define DSI_IRQ_PLL_UNLOCK      (1 << 8)
 137 #define DSI_IRQ_PLL_RECALL      (1 << 9)
 138 #define DSI_IRQ_COMPLEXIO_ERR   (1 << 10)
 139 #define DSI_IRQ_HS_TX_TIMEOUT   (1 << 14)
 140 #define DSI_IRQ_LP_RX_TIMEOUT   (1 << 15)
 141 #define DSI_IRQ_TE_TRIGGER      (1 << 16)
 142 #define DSI_IRQ_ACK_TRIGGER     (1 << 17)
 143 #define DSI_IRQ_SYNC_LOST       (1 << 18)
 144 #define DSI_IRQ_LDO_POWER_GOOD  (1 << 19)
 145 #define DSI_IRQ_TA_TIMEOUT      (1 << 20)
 146 #define DSI_IRQ_ERROR_MASK \
 147         (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
 148         DSI_IRQ_TA_TIMEOUT)
 149 #define DSI_IRQ_CHANNEL_MASK    0xf
 150
 151 /* Virtual channel interrupts */
 152 #define DSI_VC_IRQ_CS           (1 << 0)
 153 #define DSI_VC_IRQ_ECC_CORR     (1 << 1)
 154 #define DSI_VC_IRQ_PACKET_SENT  (1 << 2)
 155 #define DSI_VC_IRQ_FIFO_TX_OVF  (1 << 3)
 156 #define DSI_VC_IRQ_FIFO_RX_OVF  (1 << 4)
 157 #define DSI_VC_IRQ_BTA          (1 << 5)
 158 #define DSI_VC_IRQ_ECC_NO_CORR  (1 << 6)
 159 #define DSI_VC_IRQ_FIFO_TX_UDF  (1 << 7)
 160 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
 161 #define DSI_VC_IRQ_ERROR_MASK \
 162         (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
 163         DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
 164         DSI_VC_IRQ_FIFO_TX_UDF)
 165
 166 /* ComplexIO interrupts */
 167 #define DSI_CIO_IRQ_ERRSYNCESC1         (1 << 0)
 168 #define DSI_CIO_IRQ_ERRSYNCESC2         (1 << 1)
 169 #define DSI_CIO_IRQ_ERRSYNCESC3         (1 << 2)
 170 #define DSI_CIO_IRQ_ERRSYNCESC4         (1 << 3)
 171 #define DSI_CIO_IRQ_ERRSYNCESC5         (1 << 4)
 172 #define DSI_CIO_IRQ_ERRESC1             (1 << 5)
 173 #define DSI_CIO_IRQ_ERRESC2             (1 << 6)
 174 #define DSI_CIO_IRQ_ERRESC3             (1 << 7)
 175 #define DSI_CIO_IRQ_ERRESC4             (1 << 8)
 176 #define DSI_CIO_IRQ_ERRESC5             (1 << 9)
 177 #define DSI_CIO_IRQ_ERRCONTROL1         (1 << 10)
 178 #define DSI_CIO_IRQ_ERRCONTROL2         (1 << 11)
 179 #define DSI_CIO_IRQ_ERRCONTROL3         (1 << 12)
 180 #define DSI_CIO_IRQ_ERRCONTROL4         (1 << 13)
 181 #define DSI_CIO_IRQ_ERRCONTROL5         (1 << 14)
 182 #define DSI_CIO_IRQ_STATEULPS1          (1 << 15)
 183 #define DSI_CIO_IRQ_STATEULPS2          (1 << 16)
 184 #define DSI_CIO_IRQ_STATEULPS3          (1 << 17)
 185 #define DSI_CIO_IRQ_STATEULPS4          (1 << 18)
 186 #define DSI_CIO_IRQ_STATEULPS5          (1 << 19)
 187 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1  (1 << 20)
 188 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1  (1 << 21)
 189 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2  (1 << 22)
 190 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2  (1 << 23)
 191 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3  (1 << 24)
 192 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3  (1 << 25)
 193 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4  (1 << 26)
 194 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4  (1 << 27)
 195 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5  (1 << 28)
 196 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5  (1 << 29)
 197 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0  (1 << 30)
 198 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1  (1 << 31)
 199 #define DSI_CIO_IRQ_ERROR_MASK \
 200         (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
 201          DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
 202          DSI_CIO_IRQ_ERRSYNCESC5 | \
 203          DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
 204          DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
 205          DSI_CIO_IRQ_ERRESC5 | \
 206          DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
 207          DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
 208          DSI_CIO_IRQ_ERRCONTROL5 | \
 209          DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
 210          DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
 211          DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
 212          DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
 213          DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
 214
 215 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
 216
 217 static int dsi_display_init_dispc(struct platform_device *dsidev,
 218         enum omap_channel channel);
 219 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
 220         enum omap_channel channel);
 221
 222 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
 223
 224 /* DSI PLL HSDIV indices */
 225 #define HSDIV_DISPC     0
 226 #define HSDIV_DSI       1
 227
 228 #define DSI_MAX_NR_ISRS                2
 229 #define DSI_MAX_NR_LANES        5
 230
 231 enum dsi_model {
 232         DSI_MODEL_OMAP3,
 233         DSI_MODEL_OMAP4,
 234         DSI_MODEL_OMAP5,
 235 };
 236
 237 enum dsi_lane_function {
 238         DSI_LANE_UNUSED = 0,
 239         DSI_LANE_CLK,
 240         DSI_LANE_DATA1,
 241         DSI_LANE_DATA2,
 242         DSI_LANE_DATA3,
 243         DSI_LANE_DATA4,
 244 };
 245
 246 struct dsi_lane_config {
 247         enum dsi_lane_function function;
 248         u8 polarity;
 249 };
 250
 251 struct dsi_isr_data {
 252         omap_dsi_isr_t  isr;
 253         void            *arg;
 254         u32             mask;
 255 };
 256
 257 enum fifo_size {
 258         DSI_FIFO_SIZE_0         = 0,
 259         DSI_FIFO_SIZE_32        = 1,
 260         DSI_FIFO_SIZE_64        = 2,
 261         DSI_FIFO_SIZE_96        = 3,
 262         DSI_FIFO_SIZE_128       = 4,
 263 };
 264
 265 enum dsi_vc_source {
 266         DSI_VC_SOURCE_L4 = 0,
 267         DSI_VC_SOURCE_VP,
 268 };
 269
 270 struct dsi_irq_stats {
 271         unsigned long last_reset;
 272         unsigned irq_count;
 273         unsigned dsi_irqs[32];
 274         unsigned vc_irqs[4][32];
 275         unsigned cio_irqs[32];
 276 };
 277
 278 struct dsi_isr_tables {
 279         struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
 280         struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
 281         struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
 282 };
 283
 284 struct dsi_clk_calc_ctx {
 285         struct platform_device *dsidev;
 286         struct dss_pll *pll;
 287
 288         /* inputs */
 289
 290         const struct omap_dss_dsi_config *config;
 291
 292         unsigned long req_pck_min, req_pck_nom, req_pck_max;
 293
 294         /* outputs */
 295
 296         struct dss_pll_clock_info dsi_cinfo;
 297         struct dispc_clock_info dispc_cinfo;
 298
 299         struct videomode vm;
 300         struct omap_dss_dsi_videomode_timings dsi_vm;
 301 };
 302
 303 struct dsi_lp_clock_info {
 304         unsigned long lp_clk;
 305         u16 lp_clk_div;
 306 };
 307
 308 struct dsi_module_id_data {
 309         u32 address;
 310         int id;
 311 };
 312
 313 enum dsi_quirks {
 314         DSI_QUIRK_PLL_PWR_BUG = (1 << 0),       /* DSI-PLL power command 0x3 is not working */
 315         DSI_QUIRK_DCS_CMD_CONFIG_VC = (1 << 1),
 316         DSI_QUIRK_VC_OCP_WIDTH = (1 << 2),
 317         DSI_QUIRK_REVERSE_TXCLKESC = (1 << 3),
 318         DSI_QUIRK_GNQ = (1 << 4),
 319         DSI_QUIRK_PHY_DCC = (1 << 5),
 320 };
 321
 322 struct dsi_of_data {
 323         enum dsi_model model;
 324         const struct dss_pll_hw *pll_hw;
 325         const struct dsi_module_id_data *modules;
 326         unsigned int max_fck_freq;
 327         unsigned int max_pll_lpdiv;
 328         enum dsi_quirks quirks;
 329 };
 330
 331 struct dsi_data {
 332         struct platform_device *pdev;
 333         void __iomem *proto_base;
 334         void __iomem *phy_base;
 335         void __iomem *pll_base;
 336
 337         const struct dsi_of_data *data;
 338         int module_id;
 339
 340         int irq;
 341
 342         bool is_enabled;
 343
 344         struct clk *dss_clk;
 345         struct regmap *syscon;
 346
 347         struct dispc_clock_info user_dispc_cinfo;
 348         struct dss_pll_clock_info user_dsi_cinfo;
 349
 350         struct dsi_lp_clock_info user_lp_cinfo;
 351         struct dsi_lp_clock_info current_lp_cinfo;
 352
 353         struct dss_pll pll;
 354
 355         bool vdds_dsi_enabled;
 356         struct regulator *vdds_dsi_reg;
 357
 358         struct {
 359                 enum dsi_vc_source source;
 360                 struct omap_dss_device *dssdev;
 361                 enum fifo_size tx_fifo_size;
 362                 enum fifo_size rx_fifo_size;
 363                 int vc_id;
 364         } vc[4];
 365
 366         struct mutex lock;
 367         struct semaphore bus_lock;
 368
 369         spinlock_t irq_lock;
 370         struct dsi_isr_tables isr_tables;
 371         /* space for a copy used by the interrupt handler */
 372         struct dsi_isr_tables isr_tables_copy;
 373
 374         int update_channel;
 375 #ifdef DSI_PERF_MEASURE
 376         unsigned update_bytes;
 377 #endif
 378
 379         bool te_enabled;
 380         bool ulps_enabled;
 381
 382         void (*framedone_callback)(int, void *);
 383         void *framedone_data;
 384
 385         struct delayed_work framedone_timeout_work;
 386
 387 #ifdef DSI_CATCH_MISSING_TE
 388         struct timer_list te_timer;
 389 #endif
 390
 391         unsigned long cache_req_pck;
 392         unsigned long cache_clk_freq;
 393         struct dss_pll_clock_info cache_cinfo;
 394
 395         u32             errors;
 396         spinlock_t      errors_lock;
 397 #ifdef DSI_PERF_MEASURE
 398         ktime_t perf_setup_time;
 399         ktime_t perf_start_time;
 400 #endif
 401         int debug_read;
 402         int debug_write;
 403
 404 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 405         spinlock_t irq_stats_lock;
 406         struct dsi_irq_stats irq_stats;
 407 #endif
 408
 409         unsigned num_lanes_supported;
 410         unsigned line_buffer_size;
 411
 412         struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
 413         unsigned num_lanes_used;
 414
 415         unsigned scp_clk_refcount;
 416
 417         struct dss_lcd_mgr_config mgr_config;
 418         struct videomode vm;
 419         enum omap_dss_dsi_pixel_format pix_fmt;
 420         enum omap_dss_dsi_mode mode;
 421         struct omap_dss_dsi_videomode_timings vm_timings;
 422
 423         struct omap_dss_device output;
 424 };
 425
 426 struct dsi_packet_sent_handler_data {
 427         struct platform_device *dsidev;
 428         struct completion *completion;
 429 };
 430
 431 #ifdef DSI_PERF_MEASURE
 432 static bool dsi_perf;
 433 module_param(dsi_perf, bool, 0644);
 434 #endif
 435
 436 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
 437 {
 438         return dev_get_drvdata(&dsidev->dev);
 439 }
 440
 441 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
 442 {
 443         return to_platform_device(dssdev->dev);
 444 }
 445
 446 static struct platform_device *dsi_get_dsidev_from_id(int module)
 447 {
 448         struct omap_dss_device *out;
 449         enum omap_dss_output_id id;
 450
 451         switch (module) {
 452         case 0:
 453                 id = OMAP_DSS_OUTPUT_DSI1;
 454                 break;
 455         case 1:
 456                 id = OMAP_DSS_OUTPUT_DSI2;
 457                 break;
 458         default:
 459                 return NULL;
 460         }
 461
 462         out = omap_dss_get_output(id);
 463
 464         return out ? to_platform_device(out->dev) : NULL;
 465 }
 466
 467 static inline void dsi_write_reg(struct platform_device *dsidev,
 468                 const struct dsi_reg idx, u32 val)
 469 {
 470         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 471         void __iomem *base;
 472
 473         switch(idx.module) {
 474                 case DSI_PROTO: base = dsi->proto_base; break;
 475                 case DSI_PHY: base = dsi->phy_base; break;
 476                 case DSI_PLL: base = dsi->pll_base; break;
 477                 default: return;
 478         }
 479
 480         __raw_writel(val, base + idx.idx);
 481 }
 482
 483 static inline u32 dsi_read_reg(struct platform_device *dsidev,
 484                 const struct dsi_reg idx)
 485 {
 486         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 487         void __iomem *base;
 488
 489         switch(idx.module) {
 490                 case DSI_PROTO: base = dsi->proto_base; break;
 491                 case DSI_PHY: base = dsi->phy_base; break;
 492                 case DSI_PLL: base = dsi->pll_base; break;
 493                 default: return 0;
 494         }
 495
 496         return __raw_readl(base + idx.idx);
 497 }
 498
 499 static void dsi_bus_lock(struct omap_dss_device *dssdev)
 500 {
 501         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 502         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 503
 504         down(&dsi->bus_lock);
 505 }
 506
 507 static void dsi_bus_unlock(struct omap_dss_device *dssdev)
 508 {
 509         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 510         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 511
 512         up(&dsi->bus_lock);
 513 }
 514
 515 static bool dsi_bus_is_locked(struct platform_device *dsidev)
 516 {
 517         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 518
 519         return dsi->bus_lock.count == 0;
 520 }
 521
 522 static void dsi_completion_handler(void *data, u32 mask)
 523 {
 524         complete((struct completion *)data);
 525 }
 526
 527 static inline int wait_for_bit_change(struct platform_device *dsidev,
 528                 const struct dsi_reg idx, int bitnum, int value)
 529 {
 530         unsigned long timeout;
 531         ktime_t wait;
 532         int t;
 533
 534         /* first busyloop to see if the bit changes right away */
 535         t = 100;
 536         while (t-- > 0) {
 537                 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
 538                         return value;
 539         }
 540
 541         /* then loop for 500ms, sleeping for 1ms in between */
 542         timeout = jiffies + msecs_to_jiffies(500);
 543         while (time_before(jiffies, timeout)) {
 544                 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
 545                         return value;
 546
 547                 wait = ns_to_ktime(1000 * 1000);
 548                 set_current_state(TASK_UNINTERRUPTIBLE);
 549                 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
 550         }
 551
 552         return !value;
 553 }
 554
 555 static u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
 556 {
 557         switch (fmt) {
 558         case OMAP_DSS_DSI_FMT_RGB888:
 559         case OMAP_DSS_DSI_FMT_RGB666:
 560                 return 24;
 561         case OMAP_DSS_DSI_FMT_RGB666_PACKED:
 562                 return 18;
 563         case OMAP_DSS_DSI_FMT_RGB565:
 564                 return 16;
 565         default:
 566                 BUG();
 567                 return 0;
 568         }
 569 }
 570
 571 #ifdef DSI_PERF_MEASURE
 572 static void dsi_perf_mark_setup(struct platform_device *dsidev)
 573 {
 574         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 575         dsi->perf_setup_time = ktime_get();
 576 }
 577
 578 static void dsi_perf_mark_start(struct platform_device *dsidev)
 579 {
 580         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 581         dsi->perf_start_time = ktime_get();
 582 }
 583
 584 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
 585 {
 586         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 587         ktime_t t, setup_time, trans_time;
 588         u32 total_bytes;
 589         u32 setup_us, trans_us, total_us;
 590
 591         if (!dsi_perf)
 592                 return;
 593
 594         t = ktime_get();
 595
 596         setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
 597         setup_us = (u32)ktime_to_us(setup_time);
 598         if (setup_us == 0)
 599                 setup_us = 1;
 600
 601         trans_time = ktime_sub(t, dsi->perf_start_time);
 602         trans_us = (u32)ktime_to_us(trans_time);
 603         if (trans_us == 0)
 604                 trans_us = 1;
 605
 606         total_us = setup_us + trans_us;
 607
 608         total_bytes = dsi->update_bytes;
 609
 610         pr_info("DSI(%s): %u us + %u us = %u us (%uHz), %u bytes, %u kbytes/sec\n",
 611                 name,
 612                 setup_us,
 613                 trans_us,
 614                 total_us,
 615                 1000 * 1000 / total_us,
 616                 total_bytes,
 617                 total_bytes * 1000 / total_us);
 618 }
 619 #else
 620 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
 621 {
 622 }
 623
 624 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
 625 {
 626 }
 627
 628 static inline void dsi_perf_show(struct platform_device *dsidev,
 629                 const char *name)
 630 {
 631 }
 632 #endif
 633
 634 static int verbose_irq;
 635
 636 static void print_irq_status(u32 status)
 637 {
 638         if (status == 0)
 639                 return;
 640
 641         if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
 642                 return;
 643
 644 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
 645
 646         pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
 647                 status,
 648                 verbose_irq ? PIS(VC0) : "",
 649                 verbose_irq ? PIS(VC1) : "",
 650                 verbose_irq ? PIS(VC2) : "",
 651                 verbose_irq ? PIS(VC3) : "",
 652                 PIS(WAKEUP),
 653                 PIS(RESYNC),
 654                 PIS(PLL_LOCK),
 655                 PIS(PLL_UNLOCK),
 656                 PIS(PLL_RECALL),
 657                 PIS(COMPLEXIO_ERR),
 658                 PIS(HS_TX_TIMEOUT),
 659                 PIS(LP_RX_TIMEOUT),
 660                 PIS(TE_TRIGGER),
 661                 PIS(ACK_TRIGGER),
 662                 PIS(SYNC_LOST),
 663                 PIS(LDO_POWER_GOOD),
 664                 PIS(TA_TIMEOUT));
 665 #undef PIS
 666 }
 667
 668 static void print_irq_status_vc(int channel, u32 status)
 669 {
 670         if (status == 0)
 671                 return;
 672
 673         if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
 674                 return;
 675
 676 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
 677
 678         pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
 679                 channel,
 680                 status,
 681                 PIS(CS),
 682                 PIS(ECC_CORR),
 683                 PIS(ECC_NO_CORR),
 684                 verbose_irq ? PIS(PACKET_SENT) : "",
 685                 PIS(BTA),
 686                 PIS(FIFO_TX_OVF),
 687                 PIS(FIFO_RX_OVF),
 688                 PIS(FIFO_TX_UDF),
 689                 PIS(PP_BUSY_CHANGE));
 690 #undef PIS
 691 }
 692
 693 static void print_irq_status_cio(u32 status)
 694 {
 695         if (status == 0)
 696                 return;
 697
 698 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
 699
 700         pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
 701                 status,
 702                 PIS(ERRSYNCESC1),
 703                 PIS(ERRSYNCESC2),
 704                 PIS(ERRSYNCESC3),
 705                 PIS(ERRESC1),
 706                 PIS(ERRESC2),
 707                 PIS(ERRESC3),
 708                 PIS(ERRCONTROL1),
 709                 PIS(ERRCONTROL2),
 710                 PIS(ERRCONTROL3),
 711                 PIS(STATEULPS1),
 712                 PIS(STATEULPS2),
 713                 PIS(STATEULPS3),
 714                 PIS(ERRCONTENTIONLP0_1),
 715                 PIS(ERRCONTENTIONLP1_1),
 716                 PIS(ERRCONTENTIONLP0_2),
 717                 PIS(ERRCONTENTIONLP1_2),
 718                 PIS(ERRCONTENTIONLP0_3),
 719                 PIS(ERRCONTENTIONLP1_3),
 720                 PIS(ULPSACTIVENOT_ALL0),
 721                 PIS(ULPSACTIVENOT_ALL1));
 722 #undef PIS
 723 }
 724
 725 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 726 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
 727                 u32 *vcstatus, u32 ciostatus)
 728 {
 729         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 730         int i;
 731
 732         spin_lock(&dsi->irq_stats_lock);
 733
 734         dsi->irq_stats.irq_count++;
 735         dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
 736
 737         for (i = 0; i < 4; ++i)
 738                 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
 739
 740         dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
 741
 742         spin_unlock(&dsi->irq_stats_lock);
 743 }
 744 #else
 745 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
 746 #endif
 747
 748 static int debug_irq;
 749
 750 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
 751                 u32 *vcstatus, u32 ciostatus)
 752 {
 753         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 754         int i;
 755
 756         if (irqstatus & DSI_IRQ_ERROR_MASK) {
 757                 DSSERR("DSI error, irqstatus %x\n", irqstatus);
 758                 print_irq_status(irqstatus);
 759                 spin_lock(&dsi->errors_lock);
 760                 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
 761                 spin_unlock(&dsi->errors_lock);
 762         } else if (debug_irq) {
 763                 print_irq_status(irqstatus);
 764         }
 765
 766         for (i = 0; i < 4; ++i) {
 767                 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
 768                         DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
 769                                        i, vcstatus[i]);
 770                         print_irq_status_vc(i, vcstatus[i]);
 771                 } else if (debug_irq) {
 772                         print_irq_status_vc(i, vcstatus[i]);
 773                 }
 774         }
 775
 776         if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
 777                 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
 778                 print_irq_status_cio(ciostatus);
 779         } else if (debug_irq) {
 780                 print_irq_status_cio(ciostatus);
 781         }
 782 }
 783
 784 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
 785                 unsigned isr_array_size, u32 irqstatus)
 786 {
 787         struct dsi_isr_data *isr_data;
 788         int i;
 789
 790         for (i = 0; i < isr_array_size; i++) {
 791                 isr_data = &isr_array[i];
 792                 if (isr_data->isr && isr_data->mask & irqstatus)
 793                         isr_data->isr(isr_data->arg, irqstatus);
 794         }
 795 }
 796
 797 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
 798                 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
 799 {
 800         int i;
 801
 802         dsi_call_isrs(isr_tables->isr_table,
 803                         ARRAY_SIZE(isr_tables->isr_table),
 804                         irqstatus);
 805
 806         for (i = 0; i < 4; ++i) {
 807                 if (vcstatus[i] == 0)
 808                         continue;
 809                 dsi_call_isrs(isr_tables->isr_table_vc[i],
 810                                 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
 811                                 vcstatus[i]);
 812         }
 813
 814         if (ciostatus != 0)
 815                 dsi_call_isrs(isr_tables->isr_table_cio,
 816                                 ARRAY_SIZE(isr_tables->isr_table_cio),
 817                                 ciostatus);
 818 }
 819
 820 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
 821 {
 822         struct platform_device *dsidev;
 823         struct dsi_data *dsi;
 824         u32 irqstatus, vcstatus[4], ciostatus;
 825         int i;
 826
 827         dsidev = (struct platform_device *) arg;
 828         dsi = dsi_get_dsidrv_data(dsidev);
 829
 830         if (!dsi->is_enabled)
 831                 return IRQ_NONE;
 832
 833         spin_lock(&dsi->irq_lock);
 834
 835         irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
 836
 837         /* IRQ is not for us */
 838         if (!irqstatus) {
 839                 spin_unlock(&dsi->irq_lock);
 840                 return IRQ_NONE;
 841         }
 842
 843         dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
 844         /* flush posted write */
 845         dsi_read_reg(dsidev, DSI_IRQSTATUS);
 846
 847         for (i = 0; i < 4; ++i) {
 848                 if ((irqstatus & (1 << i)) == 0) {
 849                         vcstatus[i] = 0;
 850                         continue;
 851                 }
 852
 853                 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
 854
 855                 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
 856                 /* flush posted write */
 857                 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
 858         }
 859
 860         if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
 861                 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
 862
 863                 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
 864                 /* flush posted write */
 865                 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
 866         } else {
 867                 ciostatus = 0;
 868         }
 869
 870 #ifdef DSI_CATCH_MISSING_TE
 871         if (irqstatus & DSI_IRQ_TE_TRIGGER)
 872                 del_timer(&dsi->te_timer);
 873 #endif
 874
 875         /* make a copy and unlock, so that isrs can unregister
 876          * themselves */
 877         memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
 878                 sizeof(dsi->isr_tables));
 879
 880         spin_unlock(&dsi->irq_lock);
 881
 882         dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
 883
 884         dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
 885
 886         dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
 887
 888         return IRQ_HANDLED;
 889 }
 890
 891 /* dsi->irq_lock has to be locked by the caller */
 892 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
 893                 struct dsi_isr_data *isr_array,
 894                 unsigned isr_array_size, u32 default_mask,
 895                 const struct dsi_reg enable_reg,
 896                 const struct dsi_reg status_reg)
 897 {
 898         struct dsi_isr_data *isr_data;
 899         u32 mask;
 900         u32 old_mask;
 901         int i;
 902
 903         mask = default_mask;
 904
 905         for (i = 0; i < isr_array_size; i++) {
 906                 isr_data = &isr_array[i];
 907
 908                 if (isr_data->isr == NULL)
 909                         continue;
 910
 911                 mask |= isr_data->mask;
 912         }
 913
 914         old_mask = dsi_read_reg(dsidev, enable_reg);
 915         /* clear the irqstatus for newly enabled irqs */
 916         dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
 917         dsi_write_reg(dsidev, enable_reg, mask);
 918
 919         /* flush posted writes */
 920         dsi_read_reg(dsidev, enable_reg);
 921         dsi_read_reg(dsidev, status_reg);
 922 }
 923
 924 /* dsi->irq_lock has to be locked by the caller */
 925 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
 926 {
 927         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 928         u32 mask = DSI_IRQ_ERROR_MASK;
 929 #ifdef DSI_CATCH_MISSING_TE
 930         mask |= DSI_IRQ_TE_TRIGGER;
 931 #endif
 932         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
 933                         ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
 934                         DSI_IRQENABLE, DSI_IRQSTATUS);
 935 }
 936
 937 /* dsi->irq_lock has to be locked by the caller */
 938 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
 939 {
 940         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 941
 942         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
 943                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
 944                         DSI_VC_IRQ_ERROR_MASK,
 945                         DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
 946 }
 947
 948 /* dsi->irq_lock has to be locked by the caller */
 949 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
 950 {
 951         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 952
 953         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
 954                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
 955                         DSI_CIO_IRQ_ERROR_MASK,
 956                         DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
 957 }
 958
 959 static void _dsi_initialize_irq(struct platform_device *dsidev)
 960 {
 961         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 962         unsigned long flags;
 963         int vc;
 964
 965         spin_lock_irqsave(&dsi->irq_lock, flags);
 966
 967         memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
 968
 969         _omap_dsi_set_irqs(dsidev);
 970         for (vc = 0; vc < 4; ++vc)
 971                 _omap_dsi_set_irqs_vc(dsidev, vc);
 972         _omap_dsi_set_irqs_cio(dsidev);
 973
 974         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 975 }
 976
 977 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
 978                 struct dsi_isr_data *isr_array, unsigned isr_array_size)
 979 {
 980         struct dsi_isr_data *isr_data;
 981         int free_idx;
 982         int i;
 983
 984         BUG_ON(isr == NULL);
 985
 986         /* check for duplicate entry and find a free slot */
 987         free_idx = -1;
 988         for (i = 0; i < isr_array_size; i++) {
 989                 isr_data = &isr_array[i];
 990
 991                 if (isr_data->isr == isr && isr_data->arg == arg &&
 992                                 isr_data->mask == mask) {
 993                         return -EINVAL;
 994                 }
 995
 996                 if (isr_data->isr == NULL && free_idx == -1)
 997                         free_idx = i;
 998         }
 999
1000         if (free_idx == -1)
1001                 return -EBUSY;
1002
1003         isr_data = &isr_array[free_idx];
1004         isr_data->isr = isr;
1005         isr_data->arg = arg;
1006         isr_data->mask = mask;
1007
1008         return 0;
1009 }
1010
1011 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
1012                 struct dsi_isr_data *isr_array, unsigned isr_array_size)
1013 {
1014         struct dsi_isr_data *isr_data;
1015         int i;
1016
1017         for (i = 0; i < isr_array_size; i++) {
1018                 isr_data = &isr_array[i];
1019                 if (isr_data->isr != isr || isr_data->arg != arg ||
1020                                 isr_data->mask != mask)
1021                         continue;
1022
1023                 isr_data->isr = NULL;
1024                 isr_data->arg = NULL;
1025                 isr_data->mask = 0;
1026
1027                 return 0;
1028         }
1029
1030         return -EINVAL;
1031 }
1032
1033 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
1034                 void *arg, u32 mask)
1035 {
1036         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1037         unsigned long flags;
1038         int r;
1039
1040         spin_lock_irqsave(&dsi->irq_lock, flags);
1041
1042         r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1043                         ARRAY_SIZE(dsi->isr_tables.isr_table));
1044
1045         if (r == 0)
1046                 _omap_dsi_set_irqs(dsidev);
1047
1048         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1049
1050         return r;
1051 }
1052
1053 static int dsi_unregister_isr(struct platform_device *dsidev,
1054                 omap_dsi_isr_t isr, void *arg, u32 mask)
1055 {
1056         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1057         unsigned long flags;
1058         int r;
1059
1060         spin_lock_irqsave(&dsi->irq_lock, flags);
1061
1062         r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1063                         ARRAY_SIZE(dsi->isr_tables.isr_table));
1064
1065         if (r == 0)
1066                 _omap_dsi_set_irqs(dsidev);
1067
1068         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1069
1070         return r;
1071 }
1072
1073 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
1074                 omap_dsi_isr_t isr, void *arg, u32 mask)
1075 {
1076         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1077         unsigned long flags;
1078         int r;
1079
1080         spin_lock_irqsave(&dsi->irq_lock, flags);
1081
1082         r = _dsi_register_isr(isr, arg, mask,
1083                         dsi->isr_tables.isr_table_vc[channel],
1084                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1085
1086         if (r == 0)
1087                 _omap_dsi_set_irqs_vc(dsidev, channel);
1088
1089         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1090
1091         return r;
1092 }
1093
1094 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
1095                 omap_dsi_isr_t isr, void *arg, u32 mask)
1096 {
1097         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1098         unsigned long flags;
1099         int r;
1100
1101         spin_lock_irqsave(&dsi->irq_lock, flags);
1102
1103         r = _dsi_unregister_isr(isr, arg, mask,
1104                         dsi->isr_tables.isr_table_vc[channel],
1105                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1106
1107         if (r == 0)
1108                 _omap_dsi_set_irqs_vc(dsidev, channel);
1109
1110         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1111
1112         return r;
1113 }
1114
1115 static int dsi_register_isr_cio(struct platform_device *dsidev,
1116                 omap_dsi_isr_t isr, void *arg, u32 mask)
1117 {
1118         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1119         unsigned long flags;
1120         int r;
1121
1122         spin_lock_irqsave(&dsi->irq_lock, flags);
1123
1124         r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1125                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1126
1127         if (r == 0)
1128                 _omap_dsi_set_irqs_cio(dsidev);
1129
1130         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1131
1132         return r;
1133 }
1134
1135 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1136                 omap_dsi_isr_t isr, void *arg, u32 mask)
1137 {
1138         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1139         unsigned long flags;
1140         int r;
1141
1142         spin_lock_irqsave(&dsi->irq_lock, flags);
1143
1144         r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1145                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1146
1147         if (r == 0)
1148                 _omap_dsi_set_irqs_cio(dsidev);
1149
1150         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1151
1152         return r;
1153 }
1154
1155 static u32 dsi_get_errors(struct platform_device *dsidev)
1156 {
1157         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1158         unsigned long flags;
1159         u32 e;
1160         spin_lock_irqsave(&dsi->errors_lock, flags);
1161         e = dsi->errors;
1162         dsi->errors = 0;
1163         spin_unlock_irqrestore(&dsi->errors_lock, flags);
1164         return e;
1165 }
1166
1167 static int dsi_runtime_get(struct platform_device *dsidev)
1168 {
1169         int r;
1170         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1171
1172         DSSDBG("dsi_runtime_get\n");
1173
1174         r = pm_runtime_get_sync(&dsi->pdev->dev);
1175         WARN_ON(r < 0);
1176         return r < 0 ? r : 0;
1177 }
1178
1179 static void dsi_runtime_put(struct platform_device *dsidev)
1180 {
1181         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1182         int r;
1183
1184         DSSDBG("dsi_runtime_put\n");
1185
1186         r = pm_runtime_put_sync(&dsi->pdev->dev);
1187         WARN_ON(r < 0 && r != -ENOSYS);
1188 }
1189
1190 static int dsi_regulator_init(struct platform_device *dsidev)
1191 {
1192         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1193         struct regulator *vdds_dsi;
1194
1195         if (dsi->vdds_dsi_reg != NULL)
1196                 return 0;
1197
1198         vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdd");
1199
1200         if (IS_ERR(vdds_dsi)) {
1201                 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
1202                         DSSERR("can't get DSI VDD regulator\n");
1203                 return PTR_ERR(vdds_dsi);
1204         }
1205
1206         dsi->vdds_dsi_reg = vdds_dsi;
1207
1208         return 0;
1209 }
1210
1211 static void _dsi_print_reset_status(struct platform_device *dsidev)
1212 {
1213         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1214         u32 l;
1215         int b0, b1, b2;
1216
1217         /* A dummy read using the SCP interface to any DSIPHY register is
1218          * required after DSIPHY reset to complete the reset of the DSI complex
1219          * I/O. */
1220         l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1221
1222         if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) {
1223                 b0 = 28;
1224                 b1 = 27;
1225                 b2 = 26;
1226         } else {
1227                 b0 = 24;
1228                 b1 = 25;
1229                 b2 = 26;
1230         }
1231
1232 #define DSI_FLD_GET(fld, start, end)\
1233         FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end)
1234
1235         pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1236                 DSI_FLD_GET(PLL_STATUS, 0, 0),
1237                 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
1238                 DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
1239                 DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
1240                 DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
1241                 DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
1242                 DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
1243                 DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
1244
1245 #undef DSI_FLD_GET
1246 }
1247
1248 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1249 {
1250         DSSDBG("dsi_if_enable(%d)\n", enable);
1251
1252         enable = enable ? 1 : 0;
1253         REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1254
1255         if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1256                         DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1257                         return -EIO;
1258         }
1259
1260         return 0;
1261 }
1262
1263 static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1264 {
1265         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1266
1267         return dsi->pll.cinfo.clkout[HSDIV_DISPC];
1268 }
1269
1270 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1271 {
1272         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1273
1274         return dsi->pll.cinfo.clkout[HSDIV_DSI];
1275 }
1276
1277 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1278 {
1279         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1280
1281         return dsi->pll.cinfo.clkdco / 16;
1282 }
1283
1284 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1285 {
1286         unsigned long r;
1287         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1288
1289         if (dss_get_dsi_clk_source(dsi->module_id) == DSS_CLK_SRC_FCK) {
1290                 /* DSI FCLK source is DSS_CLK_FCK */
1291                 r = clk_get_rate(dsi->dss_clk);
1292         } else {
1293                 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1294                 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1295         }
1296
1297         return r;
1298 }
1299
1300 static int dsi_lp_clock_calc(unsigned long dsi_fclk,
1301                 unsigned long lp_clk_min, unsigned long lp_clk_max,
1302                 struct dsi_lp_clock_info *lp_cinfo)
1303 {
1304         unsigned lp_clk_div;
1305         unsigned long lp_clk;
1306
1307         lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2);
1308         lp_clk = dsi_fclk / 2 / lp_clk_div;
1309
1310         if (lp_clk < lp_clk_min || lp_clk > lp_clk_max)
1311                 return -EINVAL;
1312
1313         lp_cinfo->lp_clk_div = lp_clk_div;
1314         lp_cinfo->lp_clk = lp_clk;
1315
1316         return 0;
1317 }
1318
1319 static int dsi_set_lp_clk_divisor(struct platform_device *dsidev)
1320 {
1321         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1322         unsigned long dsi_fclk;
1323         unsigned lp_clk_div;
1324         unsigned long lp_clk;
1325         unsigned lpdiv_max = dsi->data->max_pll_lpdiv;
1326
1327
1328         lp_clk_div = dsi->user_lp_cinfo.lp_clk_div;
1329
1330         if (lp_clk_div == 0 || lp_clk_div > lpdiv_max)
1331                 return -EINVAL;
1332
1333         dsi_fclk = dsi_fclk_rate(dsidev);
1334
1335         lp_clk = dsi_fclk / 2 / lp_clk_div;
1336
1337         DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1338         dsi->current_lp_cinfo.lp_clk = lp_clk;
1339         dsi->current_lp_cinfo.lp_clk_div = lp_clk_div;
1340
1341         /* LP_CLK_DIVISOR */
1342         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1343
1344         /* LP_RX_SYNCHRO_ENABLE */
1345         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1346
1347         return 0;
1348 }
1349
1350 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1351 {
1352         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1353
1354         if (dsi->scp_clk_refcount++ == 0)
1355                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1356 }
1357
1358 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1359 {
1360         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1361
1362         WARN_ON(dsi->scp_clk_refcount == 0);
1363         if (--dsi->scp_clk_refcount == 0)
1364                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1365 }
1366
1367 enum dsi_pll_power_state {
1368         DSI_PLL_POWER_OFF       = 0x0,
1369         DSI_PLL_POWER_ON_HSCLK  = 0x1,
1370         DSI_PLL_POWER_ON_ALL    = 0x2,
1371         DSI_PLL_POWER_ON_DIV    = 0x3,
1372 };
1373
1374 static int dsi_pll_power(struct platform_device *dsidev,
1375                 enum dsi_pll_power_state state)
1376 {
1377         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1378         int t = 0;
1379
1380         /* DSI-PLL power command 0x3 is not working */
1381         if ((dsi->data->quirks & DSI_QUIRK_PLL_PWR_BUG) &&
1382             state == DSI_PLL_POWER_ON_DIV)
1383                 state = DSI_PLL_POWER_ON_ALL;
1384
1385         /* PLL_PWR_CMD */
1386         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1387
1388         /* PLL_PWR_STATUS */
1389         while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1390                 if (++t > 1000) {
1391                         DSSERR("Failed to set DSI PLL power mode to %d\n",
1392                                         state);
1393                         return -ENODEV;
1394                 }
1395                 udelay(1);
1396         }
1397
1398         return 0;
1399 }
1400
1401
1402 static void dsi_pll_calc_dsi_fck(struct dsi_data *dsi,
1403                                  struct dss_pll_clock_info *cinfo)
1404 {
1405         unsigned long max_dsi_fck;
1406
1407         max_dsi_fck = dsi->data->max_fck_freq;
1408
1409         cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck);
1410         cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI];
1411 }
1412
1413 static int dsi_pll_enable(struct dss_pll *pll)
1414 {
1415         struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1416         struct platform_device *dsidev = dsi->pdev;
1417         int r = 0;
1418
1419         DSSDBG("PLL init\n");
1420
1421         r = dsi_regulator_init(dsidev);
1422         if (r)
1423                 return r;
1424
1425         r = dsi_runtime_get(dsidev);
1426         if (r)
1427                 return r;
1428
1429         /*
1430          * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1431          */
1432         dsi_enable_scp_clk(dsidev);
1433
1434         if (!dsi->vdds_dsi_enabled) {
1435                 r = regulator_enable(dsi->vdds_dsi_reg);
1436                 if (r)
1437                         goto err0;
1438                 dsi->vdds_dsi_enabled = true;
1439         }
1440
1441         /* XXX PLL does not come out of reset without this... */
1442         dispc_pck_free_enable(1);
1443
1444         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1445                 DSSERR("PLL not coming out of reset.\n");
1446                 r = -ENODEV;
1447                 dispc_pck_free_enable(0);
1448                 goto err1;
1449         }
1450
1451         /* XXX ... but if left on, we get problems when planes do not
1452          * fill the whole display. No idea about this */
1453         dispc_pck_free_enable(0);
1454
1455         r = dsi_pll_power(dsidev, DSI_PLL_POWER_ON_ALL);
1456
1457         if (r)
1458                 goto err1;
1459
1460         DSSDBG("PLL init done\n");
1461
1462         return 0;
1463 err1:
1464         if (dsi->vdds_dsi_enabled) {
1465                 regulator_disable(dsi->vdds_dsi_reg);
1466                 dsi->vdds_dsi_enabled = false;
1467         }
1468 err0:
1469         dsi_disable_scp_clk(dsidev);
1470         dsi_runtime_put(dsidev);
1471         return r;
1472 }
1473
1474 static void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1475 {
1476         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1477
1478         dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1479         if (disconnect_lanes) {
1480                 WARN_ON(!dsi->vdds_dsi_enabled);
1481                 regulator_disable(dsi->vdds_dsi_reg);
1482                 dsi->vdds_dsi_enabled = false;
1483         }
1484
1485         dsi_disable_scp_clk(dsidev);
1486         dsi_runtime_put(dsidev);
1487
1488         DSSDBG("PLL uninit done\n");
1489 }
1490
1491 static void dsi_pll_disable(struct dss_pll *pll)
1492 {
1493         struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1494         struct platform_device *dsidev = dsi->pdev;
1495
1496         dsi_pll_uninit(dsidev, true);
1497 }
1498
1499 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1500                 struct seq_file *s)
1501 {
1502         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1503         struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo;
1504         enum dss_clk_source dispc_clk_src, dsi_clk_src;
1505         int dsi_module = dsi->module_id;
1506         struct dss_pll *pll = &dsi->pll;
1507
1508         dispc_clk_src = dss_get_dispc_clk_source();
1509         dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1510
1511         if (dsi_runtime_get(dsidev))
1512                 return;
1513
1514         seq_printf(s,   "- DSI%d PLL -\n", dsi_module + 1);
1515
1516         seq_printf(s,   "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin));
1517
1518         seq_printf(s,   "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n);
1519
1520         seq_printf(s,   "CLKIN4DDR\t%-16lum %u\n",
1521                         cinfo->clkdco, cinfo->m);
1522
1523         seq_printf(s,   "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n",
1524                         dss_get_clk_source_name(dsi_module == 0 ?
1525                                 DSS_CLK_SRC_PLL1_1 :
1526                                 DSS_CLK_SRC_PLL2_1),
1527                         cinfo->clkout[HSDIV_DISPC],
1528                         cinfo->mX[HSDIV_DISPC],
1529                         dispc_clk_src == DSS_CLK_SRC_FCK ?
1530                         "off" : "on");
1531
1532         seq_printf(s,   "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n",
1533                         dss_get_clk_source_name(dsi_module == 0 ?
1534                                 DSS_CLK_SRC_PLL1_2 :
1535                                 DSS_CLK_SRC_PLL2_2),
1536                         cinfo->clkout[HSDIV_DSI],
1537                         cinfo->mX[HSDIV_DSI],
1538                         dsi_clk_src == DSS_CLK_SRC_FCK ?
1539                         "off" : "on");
1540
1541         seq_printf(s,   "- DSI%d -\n", dsi_module + 1);
1542
1543         seq_printf(s,   "dsi fclk source = %s\n",
1544                         dss_get_clk_source_name(dsi_clk_src));
1545
1546         seq_printf(s,   "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1547
1548         seq_printf(s,   "DDR_CLK\t\t%lu\n",
1549                         cinfo->clkdco / 4);
1550
1551         seq_printf(s,   "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1552
1553         seq_printf(s,   "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk);
1554
1555         dsi_runtime_put(dsidev);
1556 }
1557
1558 void dsi_dump_clocks(struct seq_file *s)
1559 {
1560         struct platform_device *dsidev;
1561         int i;
1562
1563         for  (i = 0; i < MAX_NUM_DSI; i++) {
1564                 dsidev = dsi_get_dsidev_from_id(i);
1565                 if (dsidev)
1566                         dsi_dump_dsidev_clocks(dsidev, s);
1567         }
1568 }
1569
1570 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1571 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1572                 struct seq_file *s)
1573 {
1574         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1575         unsigned long flags;
1576         struct dsi_irq_stats stats;
1577
1578         spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1579
1580         stats = dsi->irq_stats;
1581         memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1582         dsi->irq_stats.last_reset = jiffies;
1583
1584         spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1585
1586         seq_printf(s, "period %u ms\n",
1587                         jiffies_to_msecs(jiffies - stats.last_reset));
1588
1589         seq_printf(s, "irqs %d\n", stats.irq_count);
1590 #define PIS(x) \
1591         seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1592
1593         seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1594         PIS(VC0);
1595         PIS(VC1);
1596         PIS(VC2);
1597         PIS(VC3);
1598         PIS(WAKEUP);
1599         PIS(RESYNC);
1600         PIS(PLL_LOCK);
1601         PIS(PLL_UNLOCK);
1602         PIS(PLL_RECALL);
1603         PIS(COMPLEXIO_ERR);
1604         PIS(HS_TX_TIMEOUT);
1605         PIS(LP_RX_TIMEOUT);
1606         PIS(TE_TRIGGER);
1607         PIS(ACK_TRIGGER);
1608         PIS(SYNC_LOST);
1609         PIS(LDO_POWER_GOOD);
1610         PIS(TA_TIMEOUT);
1611 #undef PIS
1612
1613 #define PIS(x) \
1614         seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1615                         stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1616                         stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1617                         stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1618                         stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1619
1620         seq_printf(s, "-- VC interrupts --\n");
1621         PIS(CS);
1622         PIS(ECC_CORR);
1623         PIS(PACKET_SENT);
1624         PIS(FIFO_TX_OVF);
1625         PIS(FIFO_RX_OVF);
1626         PIS(BTA);
1627         PIS(ECC_NO_CORR);
1628         PIS(FIFO_TX_UDF);
1629         PIS(PP_BUSY_CHANGE);
1630 #undef PIS
1631
1632 #define PIS(x) \
1633         seq_printf(s, "%-20s %10d\n", #x, \
1634                         stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1635
1636         seq_printf(s, "-- CIO interrupts --\n");
1637         PIS(ERRSYNCESC1);
1638         PIS(ERRSYNCESC2);
1639         PIS(ERRSYNCESC3);
1640         PIS(ERRESC1);
1641         PIS(ERRESC2);
1642         PIS(ERRESC3);
1643         PIS(ERRCONTROL1);
1644         PIS(ERRCONTROL2);
1645         PIS(ERRCONTROL3);
1646         PIS(STATEULPS1);
1647         PIS(STATEULPS2);
1648         PIS(STATEULPS3);
1649         PIS(ERRCONTENTIONLP0_1);
1650         PIS(ERRCONTENTIONLP1_1);
1651         PIS(ERRCONTENTIONLP0_2);
1652         PIS(ERRCONTENTIONLP1_2);
1653         PIS(ERRCONTENTIONLP0_3);
1654         PIS(ERRCONTENTIONLP1_3);
1655         PIS(ULPSACTIVENOT_ALL0);
1656         PIS(ULPSACTIVENOT_ALL1);
1657 #undef PIS
1658 }
1659
1660 static void dsi1_dump_irqs(struct seq_file *s)
1661 {
1662         struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1663
1664         dsi_dump_dsidev_irqs(dsidev, s);
1665 }
1666
1667 static void dsi2_dump_irqs(struct seq_file *s)
1668 {
1669         struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1670
1671         dsi_dump_dsidev_irqs(dsidev, s);
1672 }
1673 #endif
1674
1675 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1676                 struct seq_file *s)
1677 {
1678 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1679
1680         if (dsi_runtime_get(dsidev))
1681                 return;
1682         dsi_enable_scp_clk(dsidev);
1683
1684         DUMPREG(DSI_REVISION);
1685         DUMPREG(DSI_SYSCONFIG);
1686         DUMPREG(DSI_SYSSTATUS);
1687         DUMPREG(DSI_IRQSTATUS);
1688         DUMPREG(DSI_IRQENABLE);
1689         DUMPREG(DSI_CTRL);
1690         DUMPREG(DSI_COMPLEXIO_CFG1);
1691         DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1692         DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1693         DUMPREG(DSI_CLK_CTRL);
1694         DUMPREG(DSI_TIMING1);
1695         DUMPREG(DSI_TIMING2);
1696         DUMPREG(DSI_VM_TIMING1);
1697         DUMPREG(DSI_VM_TIMING2);
1698         DUMPREG(DSI_VM_TIMING3);
1699         DUMPREG(DSI_CLK_TIMING);
1700         DUMPREG(DSI_TX_FIFO_VC_SIZE);
1701         DUMPREG(DSI_RX_FIFO_VC_SIZE);
1702         DUMPREG(DSI_COMPLEXIO_CFG2);
1703         DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1704         DUMPREG(DSI_VM_TIMING4);
1705         DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1706         DUMPREG(DSI_VM_TIMING5);
1707         DUMPREG(DSI_VM_TIMING6);
1708         DUMPREG(DSI_VM_TIMING7);
1709         DUMPREG(DSI_STOPCLK_TIMING);
1710
1711         DUMPREG(DSI_VC_CTRL(0));
1712         DUMPREG(DSI_VC_TE(0));
1713         DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1714         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1715         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1716         DUMPREG(DSI_VC_IRQSTATUS(0));
1717         DUMPREG(DSI_VC_IRQENABLE(0));
1718
1719         DUMPREG(DSI_VC_CTRL(1));
1720         DUMPREG(DSI_VC_TE(1));
1721         DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1722         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1723         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1724         DUMPREG(DSI_VC_IRQSTATUS(1));
1725         DUMPREG(DSI_VC_IRQENABLE(1));
1726
1727         DUMPREG(DSI_VC_CTRL(2));
1728         DUMPREG(DSI_VC_TE(2));
1729         DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1730         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1731         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1732         DUMPREG(DSI_VC_IRQSTATUS(2));
1733         DUMPREG(DSI_VC_IRQENABLE(2));
1734
1735         DUMPREG(DSI_VC_CTRL(3));
1736         DUMPREG(DSI_VC_TE(3));
1737         DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1738         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1739         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1740         DUMPREG(DSI_VC_IRQSTATUS(3));
1741         DUMPREG(DSI_VC_IRQENABLE(3));
1742
1743         DUMPREG(DSI_DSIPHY_CFG0);
1744         DUMPREG(DSI_DSIPHY_CFG1);
1745         DUMPREG(DSI_DSIPHY_CFG2);
1746         DUMPREG(DSI_DSIPHY_CFG5);
1747
1748         DUMPREG(DSI_PLL_CONTROL);
1749         DUMPREG(DSI_PLL_STATUS);
1750         DUMPREG(DSI_PLL_GO);
1751         DUMPREG(DSI_PLL_CONFIGURATION1);
1752         DUMPREG(DSI_PLL_CONFIGURATION2);
1753
1754         dsi_disable_scp_clk(dsidev);
1755         dsi_runtime_put(dsidev);
1756 #undef DUMPREG
1757 }
1758
1759 static void dsi1_dump_regs(struct seq_file *s)
1760 {
1761         struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1762
1763         dsi_dump_dsidev_regs(dsidev, s);
1764 }
1765
1766 static void dsi2_dump_regs(struct seq_file *s)
1767 {
1768         struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1769
1770         dsi_dump_dsidev_regs(dsidev, s);
1771 }
1772
1773 enum dsi_cio_power_state {
1774         DSI_COMPLEXIO_POWER_OFF         = 0x0,
1775         DSI_COMPLEXIO_POWER_ON          = 0x1,
1776         DSI_COMPLEXIO_POWER_ULPS        = 0x2,
1777 };
1778
1779 static int dsi_cio_power(struct platform_device *dsidev,
1780                 enum dsi_cio_power_state state)
1781 {
1782         int t = 0;
1783
1784         /* PWR_CMD */
1785         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
1786
1787         /* PWR_STATUS */
1788         while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
1789                         26, 25) != state) {
1790                 if (++t > 1000) {
1791                         DSSERR("failed to set complexio power state to "
1792                                         "%d\n", state);
1793                         return -ENODEV;
1794                 }
1795                 udelay(1);
1796         }
1797
1798         return 0;
1799 }
1800
1801 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
1802 {
1803         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1804         int val;
1805
1806         /* line buffer on OMAP3 is 1024 x 24bits */
1807         /* XXX: for some reason using full buffer size causes
1808          * considerable TX slowdown with update sizes that fill the
1809          * whole buffer */
1810         if (!(dsi->data->quirks & DSI_QUIRK_GNQ))
1811                 return 1023 * 3;
1812
1813         val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
1814
1815         switch (val) {
1816         case 1:
1817                 return 512 * 3;         /* 512x24 bits */
1818         case 2:
1819                 return 682 * 3;         /* 682x24 bits */
1820         case 3:
1821                 return 853 * 3;         /* 853x24 bits */
1822         case 4:
1823                 return 1024 * 3;        /* 1024x24 bits */
1824         case 5:
1825                 return 1194 * 3;        /* 1194x24 bits */
1826         case 6:
1827                 return 1365 * 3;        /* 1365x24 bits */
1828         case 7:
1829                 return 1920 * 3;        /* 1920x24 bits */
1830         default:
1831                 BUG();
1832                 return 0;
1833         }
1834 }
1835
1836 static int dsi_set_lane_config(struct platform_device *dsidev)
1837 {
1838         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1839         static const u8 offsets[] = { 0, 4, 8, 12, 16 };
1840         static const enum dsi_lane_function functions[] = {
1841                 DSI_LANE_CLK,
1842                 DSI_LANE_DATA1,
1843                 DSI_LANE_DATA2,
1844                 DSI_LANE_DATA3,
1845                 DSI_LANE_DATA4,
1846         };
1847         u32 r;
1848         int i;
1849
1850         r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1851
1852         for (i = 0; i < dsi->num_lanes_used; ++i) {
1853                 unsigned offset = offsets[i];
1854                 unsigned polarity, lane_number;
1855                 unsigned t;
1856
1857                 for (t = 0; t < dsi->num_lanes_supported; ++t)
1858                         if (dsi->lanes[t].function == functions[i])
1859                                 break;
1860
1861                 if (t == dsi->num_lanes_supported)
1862                         return -EINVAL;
1863
1864                 lane_number = t;
1865                 polarity = dsi->lanes[t].polarity;
1866
1867                 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
1868                 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
1869         }
1870
1871         /* clear the unused lanes */
1872         for (; i < dsi->num_lanes_supported; ++i) {
1873                 unsigned offset = offsets[i];
1874
1875                 r = FLD_MOD(r, 0, offset + 2, offset);
1876                 r = FLD_MOD(r, 0, offset + 3, offset + 3);
1877         }
1878
1879         dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
1880
1881         return 0;
1882 }
1883
1884 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
1885 {
1886         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1887
1888         /* convert time in ns to ddr ticks, rounding up */
1889         unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1890         return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1891 }
1892
1893 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
1894 {
1895         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1896
1897         unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1898         return ddr * 1000 * 1000 / (ddr_clk / 1000);
1899 }
1900
1901 static void dsi_cio_timings(struct platform_device *dsidev)
1902 {
1903         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1904         u32 r;
1905         u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1906         u32 tlpx_half, tclk_trail, tclk_zero;
1907         u32 tclk_prepare;
1908
1909         /* calculate timings */
1910
1911         /* 1 * DDR_CLK = 2 * UI */
1912
1913         /* min 40ns + 4*UI      max 85ns + 6*UI */
1914         ths_prepare = ns2ddr(dsidev, 70) + 2;
1915
1916         /* min 145ns + 10*UI */
1917         ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
1918
1919         /* min max(8*UI, 60ns+4*UI) */
1920         ths_trail = ns2ddr(dsidev, 60) + 5;
1921
1922         /* min 100ns */
1923         ths_exit = ns2ddr(dsidev, 145);
1924
1925         /* tlpx min 50n */
1926         tlpx_half = ns2ddr(dsidev, 25);
1927
1928         /* min 60ns */
1929         tclk_trail = ns2ddr(dsidev, 60) + 2;
1930
1931         /* min 38ns, max 95ns */
1932         tclk_prepare = ns2ddr(dsidev, 65);
1933
1934         /* min tclk-prepare + tclk-zero = 300ns */
1935         tclk_zero = ns2ddr(dsidev, 260);
1936
1937         DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1938                 ths_prepare, ddr2ns(dsidev, ths_prepare),
1939                 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
1940         DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1941                         ths_trail, ddr2ns(dsidev, ths_trail),
1942                         ths_exit, ddr2ns(dsidev, ths_exit));
1943
1944         DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1945                         "tclk_zero %u (%uns)\n",
1946                         tlpx_half, ddr2ns(dsidev, tlpx_half),
1947                         tclk_trail, ddr2ns(dsidev, tclk_trail),
1948                         tclk_zero, ddr2ns(dsidev, tclk_zero));
1949         DSSDBG("tclk_prepare %u (%uns)\n",
1950                         tclk_prepare, ddr2ns(dsidev, tclk_prepare));
1951
1952         /* program timings */
1953
1954         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
1955         r = FLD_MOD(r, ths_prepare, 31, 24);
1956         r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1957         r = FLD_MOD(r, ths_trail, 15, 8);
1958         r = FLD_MOD(r, ths_exit, 7, 0);
1959         dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
1960
1961         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
1962         r = FLD_MOD(r, tlpx_half, 20, 16);
1963         r = FLD_MOD(r, tclk_trail, 15, 8);
1964         r = FLD_MOD(r, tclk_zero, 7, 0);
1965
1966         if (dsi->data->quirks & DSI_QUIRK_PHY_DCC) {
1967                 r = FLD_MOD(r, 0, 21, 21);      /* DCCEN = disable */
1968                 r = FLD_MOD(r, 1, 22, 22);      /* CLKINP_DIVBY2EN = enable */
1969                 r = FLD_MOD(r, 1, 23, 23);      /* CLKINP_SEL = enable */
1970         }
1971
1972         dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
1973
1974         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
1975         r = FLD_MOD(r, tclk_prepare, 7, 0);
1976         dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
1977 }
1978
1979 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
1980 static void dsi_cio_enable_lane_override(struct platform_device *dsidev,
1981                 unsigned mask_p, unsigned mask_n)
1982 {
1983         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1984         int i;
1985         u32 l;
1986         u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
1987
1988         l = 0;
1989
1990         for (i = 0; i < dsi->num_lanes_supported; ++i) {
1991                 unsigned p = dsi->lanes[i].polarity;
1992
1993                 if (mask_p & (1 << i))
1994                         l |= 1 << (i * 2 + (p ? 0 : 1));
1995
1996                 if (mask_n & (1 << i))
1997                         l |= 1 << (i * 2 + (p ? 1 : 0));
1998         }
1999
2000         /*
2001          * Bits in REGLPTXSCPDAT4TO0DXDY:
2002          * 17: DY0 18: DX0
2003          * 19: DY1 20: DX1
2004          * 21: DY2 22: DX2
2005          * 23: DY3 24: DX3
2006          * 25: DY4 26: DX4
2007          */
2008
2009         /* Set the lane override configuration */
2010
2011         /* REGLPTXSCPDAT4TO0DXDY */
2012         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2013
2014         /* Enable lane override */
2015
2016         /* ENLPTXSCPDAT */
2017         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2018 }
2019
2020 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2021 {
2022         /* Disable lane override */
2023         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2024         /* Reset the lane override configuration */
2025         /* REGLPTXSCPDAT4TO0DXDY */
2026         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2027 }
2028
2029 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev)
2030 {
2031         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2032         int t, i;
2033         bool in_use[DSI_MAX_NR_LANES];
2034         static const u8 offsets_old[] = { 28, 27, 26 };
2035         static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2036         const u8 *offsets;
2037
2038         if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC)
2039                 offsets = offsets_old;
2040         else
2041                 offsets = offsets_new;
2042
2043         for (i = 0; i < dsi->num_lanes_supported; ++i)
2044                 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2045
2046         t = 100000;
2047         while (true) {
2048                 u32 l;
2049                 int ok;
2050
2051                 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2052
2053                 ok = 0;
2054                 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2055                         if (!in_use[i] || (l & (1 << offsets[i])))
2056                                 ok++;
2057                 }
2058
2059                 if (ok == dsi->num_lanes_supported)
2060                         break;
2061
2062                 if (--t == 0) {
2063                         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2064                                 if (!in_use[i] || (l & (1 << offsets[i])))
2065                                         continue;
2066
2067                                 DSSERR("CIO TXCLKESC%d domain not coming " \
2068                                                 "out of reset\n", i);
2069                         }
2070                         return -EIO;
2071                 }
2072         }
2073
2074         return 0;
2075 }
2076
2077 /* return bitmask of enabled lanes, lane0 being the lsb */
2078 static unsigned dsi_get_lane_mask(struct platform_device *dsidev)
2079 {
2080         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2081         unsigned mask = 0;
2082         int i;
2083
2084         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2085                 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2086                         mask |= 1 << i;
2087         }
2088
2089         return mask;
2090 }
2091
2092 /* OMAP4 CONTROL_DSIPHY */
2093 #define OMAP4_DSIPHY_SYSCON_OFFSET                      0x78
2094
2095 #define OMAP4_DSI2_LANEENABLE_SHIFT                     29
2096 #define OMAP4_DSI2_LANEENABLE_MASK                      (0x7 << 29)
2097 #define OMAP4_DSI1_LANEENABLE_SHIFT                     24
2098 #define OMAP4_DSI1_LANEENABLE_MASK                      (0x1f << 24)
2099 #define OMAP4_DSI1_PIPD_SHIFT                           19
2100 #define OMAP4_DSI1_PIPD_MASK                            (0x1f << 19)
2101 #define OMAP4_DSI2_PIPD_SHIFT                           14
2102 #define OMAP4_DSI2_PIPD_MASK                            (0x1f << 14)
2103
2104 static int dsi_omap4_mux_pads(struct dsi_data *dsi, unsigned int lanes)
2105 {
2106         u32 enable_mask, enable_shift;
2107         u32 pipd_mask, pipd_shift;
2108
2109         if (dsi->module_id == 0) {
2110                 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
2111                 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
2112                 pipd_mask = OMAP4_DSI1_PIPD_MASK;
2113                 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
2114         } else if (dsi->module_id == 1) {
2115                 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
2116                 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
2117                 pipd_mask = OMAP4_DSI2_PIPD_MASK;
2118                 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
2119         } else {
2120                 return -ENODEV;
2121         }
2122
2123         return regmap_update_bits(dsi->syscon, OMAP4_DSIPHY_SYSCON_OFFSET,
2124                 enable_mask | pipd_mask,
2125                 (lanes << enable_shift) | (lanes << pipd_shift));
2126 }
2127
2128 /* OMAP5 CONTROL_DSIPHY */
2129
2130 #define OMAP5_DSIPHY_SYSCON_OFFSET      0x74
2131
2132 #define OMAP5_DSI1_LANEENABLE_SHIFT     24
2133 #define OMAP5_DSI2_LANEENABLE_SHIFT     19
2134 #define OMAP5_DSI_LANEENABLE_MASK       0x1f
2135
2136 static int dsi_omap5_mux_pads(struct dsi_data *dsi, unsigned int lanes)
2137 {
2138         u32 enable_shift;
2139
2140         if (dsi->module_id == 0)
2141                 enable_shift = OMAP5_DSI1_LANEENABLE_SHIFT;
2142         else if (dsi->module_id == 1)
2143                 enable_shift = OMAP5_DSI2_LANEENABLE_SHIFT;
2144         else
2145                 return -ENODEV;
2146
2147         return regmap_update_bits(dsi->syscon, OMAP5_DSIPHY_SYSCON_OFFSET,
2148                 OMAP5_DSI_LANEENABLE_MASK << enable_shift,
2149                 lanes << enable_shift);
2150 }
2151
2152 static int dsi_enable_pads(struct dsi_data *dsi, unsigned int lane_mask)
2153 {
2154         if (dsi->data->model == DSI_MODEL_OMAP4)
2155                 return dsi_omap4_mux_pads(dsi, lane_mask);
2156         if (dsi->data->model == DSI_MODEL_OMAP5)
2157                 return dsi_omap5_mux_pads(dsi, lane_mask);
2158         return 0;
2159 }
2160
2161 static void dsi_disable_pads(struct dsi_data *dsi)
2162 {
2163         if (dsi->data->model == DSI_MODEL_OMAP4)
2164                 dsi_omap4_mux_pads(dsi, 0);
2165         else if (dsi->data->model == DSI_MODEL_OMAP5)
2166                 dsi_omap5_mux_pads(dsi, 0);
2167 }
2168
2169 static int dsi_cio_init(struct platform_device *dsidev)
2170 {
2171         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2172         int r;
2173         u32 l;
2174
2175         DSSDBG("DSI CIO init starts");
2176
2177         r = dsi_enable_pads(dsi, dsi_get_lane_mask(dsidev));
2178         if (r)
2179                 return r;
2180
2181         dsi_enable_scp_clk(dsidev);
2182
2183         /* A dummy read using the SCP interface to any DSIPHY register is
2184          * required after DSIPHY reset to complete the reset of the DSI complex
2185          * I/O. */
2186         dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2187
2188         if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2189                 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2190                 r = -EIO;
2191                 goto err_scp_clk_dom;
2192         }
2193
2194         r = dsi_set_lane_config(dsidev);
2195         if (r)
2196                 goto err_scp_clk_dom;
2197
2198         /* set TX STOP MODE timer to maximum for this operation */
2199         l = dsi_read_reg(dsidev, DSI_TIMING1);
2200         l = FLD_MOD(l, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
2201         l = FLD_MOD(l, 1, 14, 14);      /* STOP_STATE_X16_IO */
2202         l = FLD_MOD(l, 1, 13, 13);      /* STOP_STATE_X4_IO */
2203         l = FLD_MOD(l, 0x1fff, 12, 0);  /* STOP_STATE_COUNTER_IO */
2204         dsi_write_reg(dsidev, DSI_TIMING1, l);
2205
2206         if (dsi->ulps_enabled) {
2207                 unsigned mask_p;
2208                 int i;
2209
2210                 DSSDBG("manual ulps exit\n");
2211
2212                 /* ULPS is exited by Mark-1 state for 1ms, followed by
2213                  * stop state. DSS HW cannot do this via the normal
2214                  * ULPS exit sequence, as after reset the DSS HW thinks
2215                  * that we are not in ULPS mode, and refuses to send the
2216                  * sequence. So we need to send the ULPS exit sequence
2217                  * manually by setting positive lines high and negative lines
2218                  * low for 1ms.
2219                  */
2220
2221                 mask_p = 0;
2222
2223                 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2224                         if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2225                                 continue;
2226                         mask_p |= 1 << i;
2227                 }
2228
2229                 dsi_cio_enable_lane_override(dsidev, mask_p, 0);
2230         }
2231
2232         r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2233         if (r)
2234                 goto err_cio_pwr;
2235
2236         if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2237                 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2238                 r = -ENODEV;
2239                 goto err_cio_pwr_dom;
2240         }
2241
2242         dsi_if_enable(dsidev, true);
2243         dsi_if_enable(dsidev, false);
2244         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2245
2246         r = dsi_cio_wait_tx_clk_esc_reset(dsidev);
2247         if (r)
2248                 goto err_tx_clk_esc_rst;
2249
2250         if (dsi->ulps_enabled) {
2251                 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2252                 ktime_t wait = ns_to_ktime(1000 * 1000);
2253                 set_current_state(TASK_UNINTERRUPTIBLE);
2254                 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2255
2256                 /* Disable the override. The lanes should be set to Mark-11
2257                  * state by the HW */
2258                 dsi_cio_disable_lane_override(dsidev);
2259         }
2260
2261         /* FORCE_TX_STOP_MODE_IO */
2262         REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2263
2264         dsi_cio_timings(dsidev);
2265
2266         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2267                 /* DDR_CLK_ALWAYS_ON */
2268                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2269                         dsi->vm_timings.ddr_clk_always_on, 13, 13);
2270         }
2271
2272         dsi->ulps_enabled = false;
2273
2274         DSSDBG("CIO init done\n");
2275
2276         return 0;
2277
2278 err_tx_clk_esc_rst:
2279         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2280 err_cio_pwr_dom:
2281         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2282 err_cio_pwr:
2283         if (dsi->ulps_enabled)
2284                 dsi_cio_disable_lane_override(dsidev);
2285 err_scp_clk_dom:
2286         dsi_disable_scp_clk(dsidev);
2287         dsi_disable_pads(dsi);
2288         return r;
2289 }
2290
2291 static void dsi_cio_uninit(struct platform_device *dsidev)
2292 {
2293         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2294
2295         /* DDR_CLK_ALWAYS_ON */
2296         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2297
2298         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2299         dsi_disable_scp_clk(dsidev);
2300         dsi_disable_pads(dsi);
2301 }
2302
2303 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2304                 enum fifo_size size1, enum fifo_size size2,
2305                 enum fifo_size size3, enum fifo_size size4)
2306 {
2307         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2308         u32 r = 0;
2309         int add = 0;
2310         int i;
2311
2312         dsi->vc[0].tx_fifo_size = size1;
2313         dsi->vc[1].tx_fifo_size = size2;
2314         dsi->vc[2].tx_fifo_size = size3;
2315         dsi->vc[3].tx_fifo_size = size4;
2316
2317         for (i = 0; i < 4; i++) {
2318                 u8 v;
2319                 int size = dsi->vc[i].tx_fifo_size;
2320
2321                 if (add + size > 4) {
2322                         DSSERR("Illegal FIFO configuration\n");
2323                         BUG();
2324                         return;
2325                 }
2326
2327                 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2328                 r |= v << (8 * i);
2329                 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2330                 add += size;
2331         }
2332
2333         dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2334 }
2335
2336 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2337                 enum fifo_size size1, enum fifo_size size2,
2338                 enum fifo_size size3, enum fifo_size size4)
2339 {
2340         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2341         u32 r = 0;
2342         int add = 0;
2343         int i;
2344
2345         dsi->vc[0].rx_fifo_size = size1;
2346         dsi->vc[1].rx_fifo_size = size2;
2347         dsi->vc[2].rx_fifo_size = size3;
2348         dsi->vc[3].rx_fifo_size = size4;
2349
2350         for (i = 0; i < 4; i++) {
2351                 u8 v;
2352                 int size = dsi->vc[i].rx_fifo_size;
2353
2354                 if (add + size > 4) {
2355                         DSSERR("Illegal FIFO configuration\n");
2356                         BUG();
2357                         return;
2358                 }
2359
2360                 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2361                 r |= v << (8 * i);
2362                 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2363                 add += size;
2364         }
2365
2366         dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2367 }
2368
2369 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2370 {
2371         u32 r;
2372
2373         r = dsi_read_reg(dsidev, DSI_TIMING1);
2374         r = FLD_MOD(r, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
2375         dsi_write_reg(dsidev, DSI_TIMING1, r);
2376
2377         if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2378                 DSSERR("TX_STOP bit not going down\n");
2379                 return -EIO;
2380         }
2381
2382         return 0;
2383 }
2384
2385 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2386 {
2387         return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2388 }
2389
2390 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2391 {
2392         struct dsi_packet_sent_handler_data *vp_data =
2393                 (struct dsi_packet_sent_handler_data *) data;
2394         struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2395         const int channel = dsi->update_channel;
2396         u8 bit = dsi->te_enabled ? 30 : 31;
2397
2398         if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2399                 complete(vp_data->completion);
2400 }
2401
2402 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2403 {
2404         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2405         DECLARE_COMPLETION_ONSTACK(completion);
2406         struct dsi_packet_sent_handler_data vp_data = {
2407                 .dsidev = dsidev,
2408                 .completion = &completion
2409         };
2410         int r = 0;
2411         u8 bit;
2412
2413         bit = dsi->te_enabled ? 30 : 31;
2414
2415         r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2416                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2417         if (r)
2418                 goto err0;
2419
2420         /* Wait for completion only if TE_EN/TE_START is still set */
2421         if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2422                 if (wait_for_completion_timeout(&completion,
2423                                 msecs_to_jiffies(10)) == 0) {
2424                         DSSERR("Failed to complete previous frame transfer\n");
2425                         r = -EIO;
2426                         goto err1;
2427                 }
2428         }
2429
2430         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2431                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2432
2433         return 0;
2434 err1:
2435         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2436                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2437 err0:
2438         return r;
2439 }
2440
2441 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2442 {
2443         struct dsi_packet_sent_handler_data *l4_data =
2444                 (struct dsi_packet_sent_handler_data *) data;
2445         struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2446         const int channel = dsi->update_channel;
2447
2448         if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2449                 complete(l4_data->completion);
2450 }
2451
2452 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2453 {
2454         DECLARE_COMPLETION_ONSTACK(completion);
2455         struct dsi_packet_sent_handler_data l4_data = {
2456                 .dsidev = dsidev,
2457                 .completion = &completion
2458         };
2459         int r = 0;
2460
2461         r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2462                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2463         if (r)
2464                 goto err0;
2465
2466         /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2467         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2468                 if (wait_for_completion_timeout(&completion,
2469                                 msecs_to_jiffies(10)) == 0) {
2470                         DSSERR("Failed to complete previous l4 transfer\n");
2471                         r = -EIO;
2472                         goto err1;
2473                 }
2474         }
2475
2476         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2477                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2478
2479         return 0;
2480 err1:
2481         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2482                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2483 err0:
2484         return r;
2485 }
2486
2487 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2488 {
2489         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2490
2491         WARN_ON(!dsi_bus_is_locked(dsidev));
2492
2493         WARN_ON(in_interrupt());
2494
2495         if (!dsi_vc_is_enabled(dsidev, channel))
2496                 return 0;
2497
2498         switch (dsi->vc[channel].source) {
2499         case DSI_VC_SOURCE_VP:
2500                 return dsi_sync_vc_vp(dsidev, channel);
2501         case DSI_VC_SOURCE_L4:
2502                 return dsi_sync_vc_l4(dsidev, channel);
2503         default:
2504                 BUG();
2505                 return -EINVAL;
2506         }
2507 }
2508
2509 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2510                 bool enable)
2511 {
2512         DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2513                         channel, enable);
2514
2515         enable = enable ? 1 : 0;
2516
2517         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2518
2519         if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2520                 0, enable) != enable) {
2521                         DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2522                         return -EIO;
2523         }
2524
2525         return 0;
2526 }
2527
2528 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2529 {
2530         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2531         u32 r;
2532
2533         DSSDBG("Initial config of virtual channel %d", channel);
2534
2535         r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2536
2537         if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2538                 DSSERR("VC(%d) busy when trying to configure it!\n",
2539                                 channel);
2540
2541         r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2542         r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN  */
2543         r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2544         r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2545         r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2546         r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2547         r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2548         if (dsi->data->quirks & DSI_QUIRK_VC_OCP_WIDTH)
2549                 r = FLD_MOD(r, 3, 11, 10);      /* OCP_WIDTH = 32 bit */
2550
2551         r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2552         r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2553
2554         dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2555
2556         dsi->vc[channel].source = DSI_VC_SOURCE_L4;
2557 }
2558
2559 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2560                 enum dsi_vc_source source)
2561 {
2562         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2563
2564         if (dsi->vc[channel].source == source)
2565                 return 0;
2566
2567         DSSDBG("Source config of virtual channel %d", channel);
2568
2569         dsi_sync_vc(dsidev, channel);
2570
2571         dsi_vc_enable(dsidev, channel, 0);
2572
2573         /* VC_BUSY */
2574         if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2575                 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2576                 return -EIO;
2577         }
2578
2579         /* SOURCE, 0 = L4, 1 = video port */
2580         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2581
2582         /* DCS_CMD_ENABLE */
2583         if (dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC) {
2584                 bool enable = source == DSI_VC_SOURCE_VP;
2585                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2586         }
2587
2588         dsi_vc_enable(dsidev, channel, 1);
2589
2590         dsi->vc[channel].source = source;
2591
2592         return 0;
2593 }
2594
2595 static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2596                 bool enable)
2597 {
2598         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2599         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2600
2601         DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2602
2603         WARN_ON(!dsi_bus_is_locked(dsidev));
2604
2605         dsi_vc_enable(dsidev, channel, 0);
2606         dsi_if_enable(dsidev, 0);
2607
2608         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2609
2610         dsi_vc_enable(dsidev, channel, 1);
2611         dsi_if_enable(dsidev, 1);
2612
2613         dsi_force_tx_stop_mode_io(dsidev);
2614
2615         /* start the DDR clock by sending a NULL packet */
2616         if (dsi->vm_timings.ddr_clk_always_on && enable)
2617                 dsi_vc_send_null(dssdev, channel);
2618 }
2619
2620 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2621 {
2622         while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2623                 u32 val;
2624                 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2625                 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2626                                 (val >> 0) & 0xff,
2627                                 (val >> 8) & 0xff,
2628                                 (val >> 16) & 0xff,
2629                                 (val >> 24) & 0xff);
2630         }
2631 }
2632
2633 static void dsi_show_rx_ack_with_err(u16 err)
2634 {
2635         DSSERR("\tACK with ERROR (%#x):\n", err);
2636         if (err & (1 << 0))
2637                 DSSERR("\t\tSoT Error\n");
2638         if (err & (1 << 1))
2639                 DSSERR("\t\tSoT Sync Error\n");
2640         if (err & (1 << 2))
2641                 DSSERR("\t\tEoT Sync Error\n");
2642         if (err & (1 << 3))
2643                 DSSERR("\t\tEscape Mode Entry Command Error\n");
2644         if (err & (1 << 4))
2645                 DSSERR("\t\tLP Transmit Sync Error\n");
2646         if (err & (1 << 5))
2647                 DSSERR("\t\tHS Receive Timeout Error\n");
2648         if (err & (1 << 6))
2649                 DSSERR("\t\tFalse Control Error\n");
2650         if (err & (1 << 7))
2651                 DSSERR("\t\t(reserved7)\n");
2652         if (err & (1 << 8))
2653                 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2654         if (err & (1 << 9))
2655                 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2656         if (err & (1 << 10))
2657                 DSSERR("\t\tChecksum Error\n");
2658         if (err & (1 << 11))
2659                 DSSERR("\t\tData type not recognized\n");
2660         if (err & (1 << 12))
2661                 DSSERR("\t\tInvalid VC ID\n");
2662         if (err & (1 << 13))
2663                 DSSERR("\t\tInvalid Transmission Length\n");
2664         if (err & (1 << 14))
2665                 DSSERR("\t\t(reserved14)\n");
2666         if (err & (1 << 15))
2667                 DSSERR("\t\tDSI Protocol Violation\n");
2668 }
2669
2670 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2671                 int channel)
2672 {
2673         /* RX_FIFO_NOT_EMPTY */
2674         while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2675                 u32 val;
2676                 u8 dt;
2677                 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2678                 DSSERR("\trawval %#08x\n", val);
2679                 dt = FLD_GET(val, 5, 0);
2680                 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2681                         u16 err = FLD_GET(val, 23, 8);
2682                         dsi_show_rx_ack_with_err(err);
2683                 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2684                         DSSERR("\tDCS short response, 1 byte: %#x\n",
2685                                         FLD_GET(val, 23, 8));
2686                 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2687                         DSSERR("\tDCS short response, 2 byte: %#x\n",
2688                                         FLD_GET(val, 23, 8));
2689                 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2690                         DSSERR("\tDCS long response, len %d\n",
2691                                         FLD_GET(val, 23, 8));
2692                         dsi_vc_flush_long_data(dsidev, channel);
2693                 } else {
2694                         DSSERR("\tunknown datatype 0x%02x\n", dt);
2695                 }
2696         }
2697         return 0;
2698 }
2699
2700 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2701 {
2702         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2703
2704         if (dsi->debug_write || dsi->debug_read)
2705                 DSSDBG("dsi_vc_send_bta %d\n", channel);
2706
2707         WARN_ON(!dsi_bus_is_locked(dsidev));
2708
2709         /* RX_FIFO_NOT_EMPTY */
2710         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2711                 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2712                 dsi_vc_flush_receive_data(dsidev, channel);
2713         }
2714
2715         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2716
2717         /* flush posted write */
2718         dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2719
2720         return 0;
2721 }
2722
2723 static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2724 {
2725         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2726         DECLARE_COMPLETION_ONSTACK(completion);
2727         int r = 0;
2728         u32 err;
2729
2730         r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2731                         &completion, DSI_VC_IRQ_BTA);
2732         if (r)
2733                 goto err0;
2734
2735         r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2736                         DSI_IRQ_ERROR_MASK);
2737         if (r)
2738                 goto err1;
2739
2740         r = dsi_vc_send_bta(dsidev, channel);
2741         if (r)
2742                 goto err2;
2743
2744         if (wait_for_completion_timeout(&completion,
2745                                 msecs_to_jiffies(500)) == 0) {
2746                 DSSERR("Failed to receive BTA\n");
2747                 r = -EIO;
2748                 goto err2;
2749         }
2750
2751         err = dsi_get_errors(dsidev);
2752         if (err) {
2753                 DSSERR("Error while sending BTA: %x\n", err);
2754                 r = -EIO;
2755                 goto err2;
2756         }
2757 err2:
2758         dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2759                         DSI_IRQ_ERROR_MASK);
2760 err1:
2761         dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2762                         &completion, DSI_VC_IRQ_BTA);
2763 err0:
2764         return r;
2765 }
2766
2767 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2768                 int channel, u8 data_type, u16 len, u8 ecc)
2769 {
2770         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2771         u32 val;
2772         u8 data_id;
2773
2774         WARN_ON(!dsi_bus_is_locked(dsidev));
2775
2776         data_id = data_type | dsi->vc[channel].vc_id << 6;
2777
2778         val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2779                 FLD_VAL(ecc, 31, 24);
2780
2781         dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2782 }
2783
2784 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2785                 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2786 {
2787         u32 val;
2788
2789         val = b4 << 24 | b3 << 16 | b2 << 8  | b1 << 0;
2790
2791 /*      DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2792                         b1, b2, b3, b4, val); */
2793
2794         dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2795 }
2796
2797 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2798                 u8 data_type, u8 *data, u16 len, u8 ecc)
2799 {
2800         /*u32 val; */
2801         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2802         int i;
2803         u8 *p;
2804         int r = 0;
2805         u8 b1, b2, b3, b4;
2806
2807         if (dsi->debug_write)
2808                 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2809
2810         /* len + header */
2811         if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) {
2812                 DSSERR("unable to send long packet: packet too long.\n");
2813                 return -EINVAL;
2814         }
2815
2816         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2817
2818         dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
2819
2820         p = data;
2821         for (i = 0; i < len >> 2; i++) {
2822                 if (dsi->debug_write)
2823                         DSSDBG("\tsending full packet %d\n", i);
2824
2825                 b1 = *p++;
2826                 b2 = *p++;
2827                 b3 = *p++;
2828                 b4 = *p++;
2829
2830                 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
2831         }
2832
2833         i = len % 4;
2834         if (i) {
2835                 b1 = 0; b2 = 0; b3 = 0;
2836
2837                 if (dsi->debug_write)
2838                         DSSDBG("\tsending remainder bytes %d\n", i);
2839
2840                 switch (i) {
2841                 case 3:
2842                         b1 = *p++;
2843                         b2 = *p++;
2844                         b3 = *p++;
2845                         break;
2846                 case 2:
2847                         b1 = *p++;
2848                         b2 = *p++;
2849                         break;
2850                 case 1:
2851                         b1 = *p++;
2852                         break;
2853                 }
2854
2855                 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
2856         }
2857
2858         return r;
2859 }
2860
2861 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
2862                 u8 data_type, u16 data, u8 ecc)
2863 {
2864         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2865         u32 r;
2866         u8 data_id;
2867
2868         WARN_ON(!dsi_bus_is_locked(dsidev));
2869
2870         if (dsi->debug_write)
2871                 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2872                                 channel,
2873                                 data_type, data & 0xff, (data >> 8) & 0xff);
2874
2875         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2876
2877         if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
2878                 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2879                 return -EINVAL;
2880         }
2881
2882         data_id = data_type | dsi->vc[channel].vc_id << 6;
2883
2884         r = (data_id << 0) | (data << 8) | (ecc << 24);
2885
2886         dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
2887
2888         return 0;
2889 }
2890
2891 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
2892 {
2893         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2894
2895         return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
2896                 0, 0);
2897 }
2898
2899 static int dsi_vc_write_nosync_common(struct platform_device *dsidev,
2900                 int channel, u8 *data, int len, enum dss_dsi_content_type type)
2901 {
2902         int r;
2903
2904         if (len == 0) {
2905                 BUG_ON(type == DSS_DSI_CONTENT_DCS);
2906                 r = dsi_vc_send_short(dsidev, channel,
2907                                 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
2908         } else if (len == 1) {
2909                 r = dsi_vc_send_short(dsidev, channel,
2910                                 type == DSS_DSI_CONTENT_GENERIC ?
2911                                 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
2912                                 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
2913         } else if (len == 2) {
2914                 r = dsi_vc_send_short(dsidev, channel,
2915                                 type == DSS_DSI_CONTENT_GENERIC ?
2916                                 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
2917                                 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
2918                                 data[0] | (data[1] << 8), 0);
2919         } else {
2920                 r = dsi_vc_send_long(dsidev, channel,
2921                                 type == DSS_DSI_CONTENT_GENERIC ?
2922                                 MIPI_DSI_GENERIC_LONG_WRITE :
2923                                 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
2924         }
2925
2926         return r;
2927 }
2928
2929 static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
2930                 u8 *data, int len)
2931 {
2932         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2933
2934         return dsi_vc_write_nosync_common(dsidev, channel, data, len,
2935                         DSS_DSI_CONTENT_DCS);
2936 }
2937
2938 static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
2939                 u8 *data, int len)
2940 {
2941         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2942
2943         return dsi_vc_write_nosync_common(dsidev, channel, data, len,
2944                         DSS_DSI_CONTENT_GENERIC);
2945 }
2946
2947 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
2948                 u8 *data, int len, enum dss_dsi_content_type type)
2949 {
2950         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2951         int r;
2952
2953         r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type);
2954         if (r)
2955                 goto err;
2956
2957         r = dsi_vc_send_bta_sync(dssdev, channel);
2958         if (r)
2959                 goto err;
2960
2961         /* RX_FIFO_NOT_EMPTY */
2962         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2963                 DSSERR("rx fifo not empty after write, dumping data:\n");
2964                 dsi_vc_flush_receive_data(dsidev, channel);
2965                 r = -EIO;
2966                 goto err;
2967         }
2968
2969         return 0;
2970 err:
2971         DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
2972                         channel, data[0], len);
2973         return r;
2974 }
2975
2976 static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2977                 int len)
2978 {
2979         return dsi_vc_write_common(dssdev, channel, data, len,
2980                         DSS_DSI_CONTENT_DCS);
2981 }
2982
2983 static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2984                 int len)
2985 {
2986         return dsi_vc_write_common(dssdev, channel, data, len,
2987                         DSS_DSI_CONTENT_GENERIC);
2988 }
2989
2990 static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev,
2991                 int channel, u8 dcs_cmd)
2992 {
2993         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2994         int r;
2995
2996         if (dsi->debug_read)
2997                 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
2998                         channel, dcs_cmd);
2999
3000         r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3001         if (r) {
3002                 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3003                         " failed\n", channel, dcs_cmd);
3004                 return r;
3005         }
3006
3007         return 0;
3008 }
3009
3010 static int dsi_vc_generic_send_read_request(struct platform_device *dsidev,
3011                 int channel, u8 *reqdata, int reqlen)
3012 {
3013         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3014         u16 data;
3015         u8 data_type;
3016         int r;
3017
3018         if (dsi->debug_read)
3019                 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3020                         channel, reqlen);
3021
3022         if (reqlen == 0) {
3023                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3024                 data = 0;
3025         } else if (reqlen == 1) {
3026                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3027                 data = reqdata[0];
3028         } else if (reqlen == 2) {
3029                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3030                 data = reqdata[0] | (reqdata[1] << 8);
3031         } else {
3032                 BUG();
3033                 return -EINVAL;
3034         }
3035
3036         r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3037         if (r) {
3038                 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3039                         " failed\n", channel, reqlen);
3040                 return r;
3041         }
3042
3043         return 0;
3044 }
3045
3046 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3047                 u8 *buf, int buflen, enum dss_dsi_content_type type)
3048 {
3049         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3050         u32 val;
3051         u8 dt;
3052         int r;
3053
3054         /* RX_FIFO_NOT_EMPTY */
3055         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3056                 DSSERR("RX fifo empty when trying to read.\n");
3057                 r = -EIO;
3058                 goto err;
3059         }
3060
3061         val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3062         if (dsi->debug_read)
3063                 DSSDBG("\theader: %08x\n", val);
3064         dt = FLD_GET(val, 5, 0);
3065         if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3066                 u16 err = FLD_GET(val, 23, 8);
3067                 dsi_show_rx_ack_with_err(err);
3068                 r = -EIO;
3069                 goto err;
3070
3071         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3072                         MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3073                         MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3074                 u8 data = FLD_GET(val, 15, 8);
3075                 if (dsi->debug_read)
3076                         DSSDBG("\t%s short response, 1 byte: %02x\n",
3077                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3078                                 "DCS", data);
3079
3080                 if (buflen < 1) {
3081                         r = -EIO;
3082                         goto err;
3083                 }
3084
3085                 buf[0] = data;
3086
3087                 return 1;
3088         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3089                         MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3090                         MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3091                 u16 data = FLD_GET(val, 23, 8);
3092                 if (dsi->debug_read)
3093                         DSSDBG("\t%s short response, 2 byte: %04x\n",
3094                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3095                                 "DCS", data);
3096
3097                 if (buflen < 2) {
3098                         r = -EIO;
3099                         goto err;
3100                 }
3101
3102                 buf[0] = data & 0xff;
3103                 buf[1] = (data >> 8) & 0xff;
3104
3105                 return 2;
3106         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3107                         MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3108                         MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3109                 int w;
3110                 int len = FLD_GET(val, 23, 8);
3111                 if (dsi->debug_read)
3112                         DSSDBG("\t%s long response, len %d\n",
3113                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3114                                 "DCS", len);
3115
3116                 if (len > buflen) {
3117                         r = -EIO;
3118                         goto err;
3119                 }
3120
3121                 /* two byte checksum ends the packet, not included in len */
3122                 for (w = 0; w < len + 2;) {
3123                         int b;
3124                         val = dsi_read_reg(dsidev,
3125                                 DSI_VC_SHORT_PACKET_HEADER(channel));
3126                         if (dsi->debug_read)
3127                                 DSSDBG("\t\t%02x %02x %02x %02x\n",
3128                                                 (val >> 0) & 0xff,
3129                                                 (val >> 8) & 0xff,
3130                                                 (val >> 16) & 0xff,
3131                                                 (val >> 24) & 0xff);
3132
3133                         for (b = 0; b < 4; ++b) {
3134                                 if (w < len)
3135                                         buf[w] = (val >> (b * 8)) & 0xff;
3136                                 /* we discard the 2 byte checksum */
3137                                 ++w;
3138                         }
3139                 }
3140
3141                 return len;
3142         } else {
3143                 DSSERR("\tunknown datatype 0x%02x\n", dt);
3144                 r = -EIO;
3145                 goto err;
3146         }
3147
3148 err:
3149         DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3150                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3151
3152         return r;
3153 }
3154
3155 static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3156                 u8 *buf, int buflen)
3157 {
3158         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3159         int r;
3160
3161         r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd);
3162         if (r)
3163                 goto err;
3164
3165         r = dsi_vc_send_bta_sync(dssdev, channel);
3166         if (r)
3167                 goto err;
3168
3169         r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3170                 DSS_DSI_CONTENT_DCS);
3171         if (r < 0)
3172                 goto err;
3173
3174         if (r != buflen) {
3175                 r = -EIO;
3176                 goto err;
3177         }
3178
3179         return 0;
3180 err:
3181         DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3182         return r;
3183 }
3184
3185 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3186                 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3187 {
3188         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3189         int r;
3190
3191         r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen);
3192         if (r)
3193                 return r;
3194
3195         r = dsi_vc_send_bta_sync(dssdev, channel);
3196         if (r)
3197                 return r;
3198
3199         r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3200                 DSS_DSI_CONTENT_GENERIC);
3201         if (r < 0)
3202                 return r;
3203
3204         if (r != buflen) {
3205                 r = -EIO;
3206                 return r;
3207         }
3208
3209         return 0;
3210 }
3211
3212 static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3213                 u16 len)
3214 {
3215         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3216
3217         return dsi_vc_send_short(dsidev, channel,
3218                         MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3219 }
3220
3221 static int dsi_enter_ulps(struct platform_device *dsidev)
3222 {
3223         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3224         DECLARE_COMPLETION_ONSTACK(completion);
3225         int r, i;
3226         unsigned mask;
3227
3228         DSSDBG("Entering ULPS");
3229
3230         WARN_ON(!dsi_bus_is_locked(dsidev));
3231
3232         WARN_ON(dsi->ulps_enabled);
3233
3234         if (dsi->ulps_enabled)
3235                 return 0;
3236
3237         /* DDR_CLK_ALWAYS_ON */
3238         if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3239                 dsi_if_enable(dsidev, 0);
3240                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3241                 dsi_if_enable(dsidev, 1);
3242         }
3243
3244         dsi_sync_vc(dsidev, 0);
3245         dsi_sync_vc(dsidev, 1);
3246         dsi_sync_vc(dsidev, 2);
3247         dsi_sync_vc(dsidev, 3);
3248
3249         dsi_force_tx_stop_mode_io(dsidev);
3250
3251         dsi_vc_enable(dsidev, 0, false);
3252         dsi_vc_enable(dsidev, 1, false);
3253         dsi_vc_enable(dsidev, 2, false);
3254         dsi_vc_enable(dsidev, 3, false);
3255
3256         if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) {      /* HS_BUSY */
3257                 DSSERR("HS busy when enabling ULPS\n");
3258                 return -EIO;
3259         }
3260
3261         if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) {      /* LP_BUSY */
3262                 DSSERR("LP busy when enabling ULPS\n");
3263                 return -EIO;
3264         }
3265
3266         r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3267                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3268         if (r)
3269                 return r;
3270
3271         mask = 0;
3272
3273         for (i = 0; i < dsi->num_lanes_supported; ++i) {
3274                 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3275                         continue;
3276                 mask |= 1 << i;
3277         }
3278         /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3279         /* LANEx_ULPS_SIG2 */
3280         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3281
3282         /* flush posted write and wait for SCP interface to finish the write */
3283         dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3284
3285         if (wait_for_completion_timeout(&completion,
3286                                 msecs_to_jiffies(1000)) == 0) {
3287                 DSSERR("ULPS enable timeout\n");
3288                 r = -EIO;
3289                 goto err;
3290         }
3291
3292         dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3293                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3294
3295         /* Reset LANEx_ULPS_SIG2 */
3296         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3297
3298         /* flush posted write and wait for SCP interface to finish the write */
3299         dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3300
3301         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3302
3303         dsi_if_enable(dsidev, false);
3304
3305         dsi->ulps_enabled = true;
3306
3307         return 0;
3308
3309 err:
3310         dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3311                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3312         return r;
3313 }
3314
3315 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3316                 unsigned ticks, bool x4, bool x16)
3317 {
3318         unsigned long fck;
3319         unsigned long total_ticks;
3320         u32 r;
3321
3322         BUG_ON(ticks > 0x1fff);
3323
3324         /* ticks in DSI_FCK */
3325         fck = dsi_fclk_rate(dsidev);
3326
3327         r = dsi_read_reg(dsidev, DSI_TIMING2);
3328         r = FLD_MOD(r, 1, 15, 15);      /* LP_RX_TO */
3329         r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);    /* LP_RX_TO_X16 */
3330         r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);     /* LP_RX_TO_X4 */
3331         r = FLD_MOD(r, ticks, 12, 0);   /* LP_RX_COUNTER */
3332         dsi_write_reg(dsidev, DSI_TIMING2, r);
3333
3334         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3335
3336         DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3337                         total_ticks,
3338                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3339                         (total_ticks * 1000) / (fck / 1000 / 1000));
3340 }
3341
3342 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3343                 bool x8, bool x16)
3344 {
3345         unsigned long fck;
3346         unsigned long total_ticks;
3347         u32 r;
3348
3349         BUG_ON(ticks > 0x1fff);
3350
3351         /* ticks in DSI_FCK */
3352         fck = dsi_fclk_rate(dsidev);
3353
3354         r = dsi_read_reg(dsidev, DSI_TIMING1);
3355         r = FLD_MOD(r, 1, 31, 31);      /* TA_TO */
3356         r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);    /* TA_TO_X16 */
3357         r = FLD_MOD(r, x8 ? 1 : 0, 29, 29);     /* TA_TO_X8 */
3358         r = FLD_MOD(r, ticks, 28, 16);  /* TA_TO_COUNTER */
3359         dsi_write_reg(dsidev, DSI_TIMING1, r);
3360
3361         total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3362
3363         DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3364                         total_ticks,
3365                         ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3366                         (total_ticks * 1000) / (fck / 1000 / 1000));
3367 }
3368
3369 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3370                 unsigned ticks, bool x4, bool x16)
3371 {
3372         unsigned long fck;
3373         unsigned long total_ticks;
3374         u32 r;
3375
3376         BUG_ON(ticks > 0x1fff);
3377
3378         /* ticks in DSI_FCK */
3379         fck = dsi_fclk_rate(dsidev);
3380
3381         r = dsi_read_reg(dsidev, DSI_TIMING1);
3382         r = FLD_MOD(r, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
3383         r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);    /* STOP_STATE_X16_IO */
3384         r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);     /* STOP_STATE_X4_IO */
3385         r = FLD_MOD(r, ticks, 12, 0);   /* STOP_STATE_COUNTER_IO */
3386         dsi_write_reg(dsidev, DSI_TIMING1, r);
3387
3388         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3389
3390         DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3391                         total_ticks,
3392                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3393                         (total_ticks * 1000) / (fck / 1000 / 1000));
3394 }
3395
3396 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3397                 unsigned ticks, bool x4, bool x16)
3398 {
3399         unsigned long fck;
3400         unsigned long total_ticks;
3401         u32 r;
3402
3403         BUG_ON(ticks > 0x1fff);
3404
3405         /* ticks in TxByteClkHS */
3406         fck = dsi_get_txbyteclkhs(dsidev);
3407
3408         r = dsi_read_reg(dsidev, DSI_TIMING2);
3409         r = FLD_MOD(r, 1, 31, 31);      /* HS_TX_TO */
3410         r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);    /* HS_TX_TO_X16 */
3411         r = FLD_MOD(r, x4 ? 1 : 0, 29, 29);     /* HS_TX_TO_X8 (4 really) */
3412         r = FLD_MOD(r, ticks, 28, 16);  /* HS_TX_TO_COUNTER */
3413         dsi_write_reg(dsidev, DSI_TIMING2, r);
3414
3415         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3416
3417         DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3418                         total_ticks,
3419                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3420                         (total_ticks * 1000) / (fck / 1000 / 1000));
3421 }
3422
3423 static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
3424 {
3425         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3426         int num_line_buffers;
3427
3428         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3429                 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3430                 struct videomode *vm = &dsi->vm;
3431                 /*
3432                  * Don't use line buffers if width is greater than the video
3433                  * port's line buffer size
3434                  */
3435                 if (dsi->line_buffer_size <= vm->hactive * bpp / 8)
3436                         num_line_buffers = 0;
3437                 else
3438                         num_line_buffers = 2;
3439         } else {
3440                 /* Use maximum number of line buffers in command mode */
3441                 num_line_buffers = 2;
3442         }
3443
3444         /* LINE_BUFFER */
3445         REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3446 }
3447
3448 static void dsi_config_vp_sync_events(struct platform_device *dsidev)
3449 {
3450         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3451         bool sync_end;
3452         u32 r;
3453
3454         if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE)
3455                 sync_end = true;
3456         else
3457                 sync_end = false;
3458
3459         r = dsi_read_reg(dsidev, DSI_CTRL);
3460         r = FLD_MOD(r, 1, 9, 9);                /* VP_DE_POL */
3461         r = FLD_MOD(r, 1, 10, 10);              /* VP_HSYNC_POL */
3462         r = FLD_MOD(r, 1, 11, 11);              /* VP_VSYNC_POL */
3463         r = FLD_MOD(r, 1, 15, 15);              /* VP_VSYNC_START */
3464         r = FLD_MOD(r, sync_end, 16, 16);       /* VP_VSYNC_END */
3465         r = FLD_MOD(r, 1, 17, 17);              /* VP_HSYNC_START */
3466         r = FLD_MOD(r, sync_end, 18, 18);       /* VP_HSYNC_END */
3467         dsi_write_reg(dsidev, DSI_CTRL, r);
3468 }
3469
3470 static void dsi_config_blanking_modes(struct platform_device *dsidev)
3471 {
3472         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3473         int blanking_mode = dsi->vm_timings.blanking_mode;
3474         int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3475         int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
3476         int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
3477         u32 r;
3478
3479         /*
3480          * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3481          * 1 = Long blanking packets are sent in corresponding blanking periods
3482          */
3483         r = dsi_read_reg(dsidev, DSI_CTRL);
3484         r = FLD_MOD(r, blanking_mode, 20, 20);          /* BLANKING_MODE */
3485         r = FLD_MOD(r, hfp_blanking_mode, 21, 21);      /* HFP_BLANKING */
3486         r = FLD_MOD(r, hbp_blanking_mode, 22, 22);      /* HBP_BLANKING */
3487         r = FLD_MOD(r, hsa_blanking_mode, 23, 23);      /* HSA_BLANKING */
3488         dsi_write_reg(dsidev, DSI_CTRL, r);
3489 }
3490
3491 /*
3492  * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3493  * results in maximum transition time for data and clock lanes to enter and
3494  * exit HS mode. Hence, this is the scenario where the least amount of command
3495  * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3496  * clock cycles that can be used to interleave command mode data in HS so that
3497  * all scenarios are satisfied.
3498  */
3499 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3500                 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3501 {
3502         int transition;
3503
3504         /*
3505          * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3506          * time of data lanes only, if it isn't set, we need to consider HS
3507          * transition time of both data and clock lanes. HS transition time
3508          * of Scenario 3 is considered.
3509          */
3510         if (ddr_alwon) {
3511                 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3512         } else {
3513                 int trans1, trans2;
3514                 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3515                 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3516                                 enter_hs + 1;
3517                 transition = max(trans1, trans2);
3518         }
3519
3520         return blank > transition ? blank - transition : 0;
3521 }
3522
3523 /*
3524  * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3525  * results in maximum transition time for data lanes to enter and exit LP mode.
3526  * Hence, this is the scenario where the least amount of command mode data can
3527  * be interleaved. We program the minimum amount of bytes that can be
3528  * interleaved in LP so that all scenarios are satisfied.
3529  */
3530 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3531                 int lp_clk_div, int tdsi_fclk)
3532 {
3533         int trans_lp;   /* time required for a LP transition, in TXBYTECLKHS */
3534         int tlp_avail;  /* time left for interleaving commands, in CLKIN4DDR */
3535         int ttxclkesc;  /* period of LP transmit escape clock, in CLKIN4DDR */
3536         int thsbyte_clk = 16;   /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3537         int lp_inter;   /* cmd mode data that can be interleaved, in bytes */
3538
3539         /* maximum LP transition time according to Scenario 1 */
3540         trans_lp = exit_hs + max(enter_hs, 2) + 1;
3541
3542         /* CLKIN4DDR = 16 * TXBYTECLKHS */
3543         tlp_avail = thsbyte_clk * (blank - trans_lp);
3544
3545         ttxclkesc = tdsi_fclk * lp_clk_div;
3546
3547         lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3548                         26) / 16;
3549
3550         return max(lp_inter, 0);
3551 }
3552
3553 static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
3554 {
3555         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3556         int blanking_mode;
3557         int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3558         int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3559         int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3560         int tclk_trail, ths_exit, exiths_clk;
3561         bool ddr_alwon;
3562         struct videomode *vm = &dsi->vm;
3563         int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3564         int ndl = dsi->num_lanes_used - 1;
3565         int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1;
3566         int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3567         int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3568         int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3569         int bl_interleave_hs = 0, bl_interleave_lp = 0;
3570         u32 r;
3571
3572         r = dsi_read_reg(dsidev, DSI_CTRL);
3573         blanking_mode = FLD_GET(r, 20, 20);
3574         hfp_blanking_mode = FLD_GET(r, 21, 21);
3575         hbp_blanking_mode = FLD_GET(r, 22, 22);
3576         hsa_blanking_mode = FLD_GET(r, 23, 23);
3577
3578         r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3579         hbp = FLD_GET(r, 11, 0);
3580         hfp = FLD_GET(r, 23, 12);
3581         hsa = FLD_GET(r, 31, 24);
3582
3583         r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3584         ddr_clk_post = FLD_GET(r, 7, 0);
3585         ddr_clk_pre = FLD_GET(r, 15, 8);
3586
3587         r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
3588         exit_hs_mode_lat = FLD_GET(r, 15, 0);
3589         enter_hs_mode_lat = FLD_GET(r, 31, 16);
3590
3591         r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
3592         lp_clk_div = FLD_GET(r, 12, 0);
3593         ddr_alwon = FLD_GET(r, 13, 13);
3594
3595         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3596         ths_exit = FLD_GET(r, 7, 0);
3597
3598         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3599         tclk_trail = FLD_GET(r, 15, 8);
3600
3601         exiths_clk = ths_exit + tclk_trail;
3602
3603         width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8);
3604         bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3605
3606         if (!hsa_blanking_mode) {
3607                 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3608                                         enter_hs_mode_lat, exit_hs_mode_lat,
3609                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3610                 hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3611                                         enter_hs_mode_lat, exit_hs_mode_lat,
3612                                         lp_clk_div, dsi_fclk_hsdiv);
3613         }
3614
3615         if (!hfp_blanking_mode) {
3616                 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3617                                         enter_hs_mode_lat, exit_hs_mode_lat,
3618                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3619                 hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3620                                         enter_hs_mode_lat, exit_hs_mode_lat,
3621                                         lp_clk_div, dsi_fclk_hsdiv);
3622         }
3623
3624         if (!hbp_blanking_mode) {
3625                 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3626                                         enter_hs_mode_lat, exit_hs_mode_lat,
3627                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3628
3629                 hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3630                                         enter_hs_mode_lat, exit_hs_mode_lat,
3631                                         lp_clk_div, dsi_fclk_hsdiv);
3632         }
3633
3634         if (!blanking_mode) {
3635                 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3636                                         enter_hs_mode_lat, exit_hs_mode_lat,
3637                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3638
3639                 bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3640                                         enter_hs_mode_lat, exit_hs_mode_lat,
3641                                         lp_clk_div, dsi_fclk_hsdiv);
3642         }
3643
3644         DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3645                 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3646                 bl_interleave_hs);
3647
3648         DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3649                 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3650                 bl_interleave_lp);
3651
3652         r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
3653         r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3654         r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
3655         r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
3656         dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
3657
3658         r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
3659         r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
3660         r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
3661         r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
3662         dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
3663
3664         r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
3665         r = FLD_MOD(r, bl_interleave_hs, 31, 15);
3666         r = FLD_MOD(r, bl_interleave_lp, 16, 0);
3667         dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
3668 }
3669
3670 static int dsi_proto_config(struct platform_device *dsidev)
3671 {
3672         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3673         u32 r;
3674         int buswidth = 0;
3675
3676         dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3677                         DSI_FIFO_SIZE_32,
3678                         DSI_FIFO_SIZE_32,
3679                         DSI_FIFO_SIZE_32);
3680
3681         dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3682                         DSI_FIFO_SIZE_32,
3683                         DSI_FIFO_SIZE_32,
3684                         DSI_FIFO_SIZE_32);
3685
3686         /* XXX what values for the timeouts? */
3687         dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3688         dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3689         dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3690         dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3691
3692         switch (dsi_get_pixel_size(dsi->pix_fmt)) {
3693         case 16:
3694                 buswidth = 0;
3695                 break;
3696         case 18:
3697                 buswidth = 1;
3698                 break;
3699         case 24:
3700                 buswidth = 2;
3701                 break;
3702         default:
3703                 BUG();
3704                 return -EINVAL;
3705         }
3706
3707         r = dsi_read_reg(dsidev, DSI_CTRL);
3708         r = FLD_MOD(r, 1, 1, 1);        /* CS_RX_EN */
3709         r = FLD_MOD(r, 1, 2, 2);        /* ECC_RX_EN */
3710         r = FLD_MOD(r, 1, 3, 3);        /* TX_FIFO_ARBITRATION */
3711         r = FLD_MOD(r, 1, 4, 4);        /* VP_CLK_RATIO, always 1, see errata*/
3712         r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3713         r = FLD_MOD(r, 0, 8, 8);        /* VP_CLK_POL */
3714         r = FLD_MOD(r, 1, 14, 14);      /* TRIGGER_RESET_MODE */
3715         r = FLD_MOD(r, 1, 19, 19);      /* EOT_ENABLE */
3716         if (!(dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC)) {
3717                 r = FLD_MOD(r, 1, 24, 24);      /* DCS_CMD_ENABLE */
3718                 /* DCS_CMD_CODE, 1=start, 0=continue */
3719                 r = FLD_MOD(r, 0, 25, 25);
3720         }
3721
3722         dsi_write_reg(dsidev, DSI_CTRL, r);
3723
3724         dsi_config_vp_num_line_buffers(dsidev);
3725
3726         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3727                 dsi_config_vp_sync_events(dsidev);
3728                 dsi_config_blanking_modes(dsidev);
3729                 dsi_config_cmd_mode_interleaving(dsidev);
3730         }
3731
3732         dsi_vc_initial_config(dsidev, 0);
3733         dsi_vc_initial_config(dsidev, 1);
3734         dsi_vc_initial_config(dsidev, 2);
3735         dsi_vc_initial_config(dsidev, 3);
3736
3737         return 0;
3738 }
3739
3740 static void dsi_proto_timings(struct platform_device *dsidev)
3741 {
3742         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3743         unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3744         unsigned tclk_pre, tclk_post;
3745         unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3746         unsigned ths_trail, ths_exit;
3747         unsigned ddr_clk_pre, ddr_clk_post;
3748         unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3749         unsigned ths_eot;
3750         int ndl = dsi->num_lanes_used - 1;
3751         u32 r;
3752
3753         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3754         ths_prepare = FLD_GET(r, 31, 24);
3755         ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3756         ths_zero = ths_prepare_ths_zero - ths_prepare;
3757         ths_trail = FLD_GET(r, 15, 8);
3758         ths_exit = FLD_GET(r, 7, 0);
3759
3760         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3761         tlpx = FLD_GET(r, 20, 16) * 2;
3762         tclk_trail = FLD_GET(r, 15, 8);
3763         tclk_zero = FLD_GET(r, 7, 0);
3764
3765         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3766         tclk_prepare = FLD_GET(r, 7, 0);
3767
3768         /* min 8*UI */
3769         tclk_pre = 20;
3770         /* min 60ns + 52*UI */
3771         tclk_post = ns2ddr(dsidev, 60) + 26;
3772
3773         ths_eot = DIV_ROUND_UP(4, ndl);
3774
3775         ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3776                         4);
3777         ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3778
3779         BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3780         BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3781
3782         r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3783         r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3784         r = FLD_MOD(r, ddr_clk_post, 7, 0);
3785         dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3786
3787         DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3788                         ddr_clk_pre,
3789                         ddr_clk_post);
3790
3791         enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3792                 DIV_ROUND_UP(ths_prepare, 4) +
3793                 DIV_ROUND_UP(ths_zero + 3, 4);
3794
3795         exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3796
3797         r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3798                 FLD_VAL(exit_hs_mode_lat, 15, 0);
3799         dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3800
3801         DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3802                         enter_hs_mode_lat, exit_hs_mode_lat);
3803
3804          if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3805                 /* TODO: Implement a video mode check_timings function */
3806                 int hsa = dsi->vm_timings.hsa;
3807                 int hfp = dsi->vm_timings.hfp;
3808                 int hbp = dsi->vm_timings.hbp;
3809                 int vsa = dsi->vm_timings.vsa;
3810                 int vfp = dsi->vm_timings.vfp;
3811                 int vbp = dsi->vm_timings.vbp;
3812                 int window_sync = dsi->vm_timings.window_sync;
3813                 bool hsync_end;
3814                 struct videomode *vm = &dsi->vm;
3815                 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3816                 int tl, t_he, width_bytes;
3817
3818                 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE;
3819                 t_he = hsync_end ?
3820                         ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3821
3822                 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8);
3823
3824                 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3825                 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3826                         DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3827
3828                 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3829                         hfp, hsync_end ? hsa : 0, tl);
3830                 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3831                         vsa, vm->vactive);
3832
3833                 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3834                 r = FLD_MOD(r, hbp, 11, 0);     /* HBP */
3835                 r = FLD_MOD(r, hfp, 23, 12);    /* HFP */
3836                 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24);    /* HSA */
3837                 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
3838
3839                 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
3840                 r = FLD_MOD(r, vbp, 7, 0);      /* VBP */
3841                 r = FLD_MOD(r, vfp, 15, 8);     /* VFP */
3842                 r = FLD_MOD(r, vsa, 23, 16);    /* VSA */
3843                 r = FLD_MOD(r, window_sync, 27, 24);    /* WINDOW_SYNC */
3844                 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
3845
3846                 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
3847                 r = FLD_MOD(r, vm->vactive, 14, 0);     /* VACT */
3848                 r = FLD_MOD(r, tl, 31, 16);             /* TL */
3849                 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
3850         }
3851 }
3852
3853 static int dsi_configure_pins(struct omap_dss_device *dssdev,
3854                 const struct omap_dsi_pin_config *pin_cfg)
3855 {
3856         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3857         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3858         int num_pins;
3859         const int *pins;
3860         struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
3861         int num_lanes;
3862         int i;
3863
3864         static const enum dsi_lane_function functions[] = {
3865                 DSI_LANE_CLK,
3866                 DSI_LANE_DATA1,
3867                 DSI_LANE_DATA2,
3868                 DSI_LANE_DATA3,
3869                 DSI_LANE_DATA4,
3870         };
3871
3872         num_pins = pin_cfg->num_pins;
3873         pins = pin_cfg->pins;
3874
3875         if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
3876                         || num_pins % 2 != 0)
3877                 return -EINVAL;
3878
3879         for (i = 0; i < DSI_MAX_NR_LANES; ++i)
3880                 lanes[i].function = DSI_LANE_UNUSED;
3881
3882         num_lanes = 0;
3883
3884         for (i = 0; i < num_pins; i += 2) {
3885                 u8 lane, pol;
3886                 int dx, dy;
3887
3888                 dx = pins[i];
3889                 dy = pins[i + 1];
3890
3891                 if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
3892                         return -EINVAL;
3893
3894                 if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
3895                         return -EINVAL;
3896
3897                 if (dx & 1) {
3898                         if (dy != dx - 1)
3899                                 return -EINVAL;
3900                         pol = 1;
3901                 } else {
3902                         if (dy != dx + 1)
3903                                 return -EINVAL;
3904                         pol = 0;
3905                 }
3906
3907                 lane = dx / 2;
3908
3909                 lanes[lane].function = functions[i / 2];
3910                 lanes[lane].polarity = pol;
3911                 num_lanes++;
3912         }
3913
3914         memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
3915         dsi->num_lanes_used = num_lanes;
3916
3917         return 0;
3918 }
3919
3920 static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
3921 {
3922         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3923         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3924         enum omap_channel dispc_channel = dssdev->dispc_channel;
3925         int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3926         struct omap_dss_device *out = &dsi->output;
3927         u8 data_type;
3928         u16 word_count;
3929         int r;
3930
3931         if (!out->dispc_channel_connected) {
3932                 DSSERR("failed to enable display: no output/manager\n");
3933                 return -ENODEV;
3934         }
3935
3936         r = dsi_display_init_dispc(dsidev, dispc_channel);
3937         if (r)
3938                 goto err_init_dispc;
3939
3940         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3941                 switch (dsi->pix_fmt) {
3942                 case OMAP_DSS_DSI_FMT_RGB888:
3943                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
3944                         break;
3945                 case OMAP_DSS_DSI_FMT_RGB666:
3946                         data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
3947                         break;
3948                 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
3949                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
3950                         break;
3951                 case OMAP_DSS_DSI_FMT_RGB565:
3952                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
3953                         break;
3954                 default:
3955                         r = -EINVAL;
3956                         goto err_pix_fmt;
3957                 }
3958
3959                 dsi_if_enable(dsidev, false);
3960                 dsi_vc_enable(dsidev, channel, false);
3961
3962                 /* MODE, 1 = video mode */
3963                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
3964
3965                 word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8);
3966
3967                 dsi_vc_write_long_header(dsidev, channel, data_type,
3968                                 word_count, 0);
3969
3970                 dsi_vc_enable(dsidev, channel, true);
3971                 dsi_if_enable(dsidev, true);
3972         }
3973
3974         r = dss_mgr_enable(dispc_channel);
3975         if (r)
3976                 goto err_mgr_enable;
3977
3978         return 0;
3979
3980 err_mgr_enable:
3981         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3982                 dsi_if_enable(dsidev, false);
3983                 dsi_vc_enable(dsidev, channel, false);
3984         }
3985 err_pix_fmt:
3986         dsi_display_uninit_dispc(dsidev, dispc_channel);
3987 err_init_dispc:
3988         return r;
3989 }
3990
3991 static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
3992 {
3993         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3994         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3995         enum omap_channel dispc_channel = dssdev->dispc_channel;
3996
3997         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3998                 dsi_if_enable(dsidev, false);
3999                 dsi_vc_enable(dsidev, channel, false);
4000
4001                 /* MODE, 0 = command mode */
4002                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
4003
4004                 dsi_vc_enable(dsidev, channel, true);
4005                 dsi_if_enable(dsidev, true);
4006         }
4007
4008         dss_mgr_disable(dispc_channel);
4009
4010         dsi_display_uninit_dispc(dsidev, dispc_channel);
4011 }
4012
4013 static void dsi_update_screen_dispc(struct platform_device *dsidev)
4014 {
4015         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4016         enum omap_channel dispc_channel = dsi->output.dispc_channel;
4017         unsigned bytespp;
4018         unsigned bytespl;
4019         unsigned bytespf;
4020         unsigned total_len;
4021         unsigned packet_payload;
4022         unsigned packet_len;
4023         u32 l;
4024         int r;
4025         const unsigned channel = dsi->update_channel;
4026         const unsigned line_buf_size = dsi->line_buffer_size;
4027         u16 w = dsi->vm.hactive;
4028         u16 h = dsi->vm.vactive;
4029
4030         DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
4031
4032         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4033
4034         bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8;
4035         bytespl = w * bytespp;
4036         bytespf = bytespl * h;
4037
4038         /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4039          * number of lines in a packet.  See errata about VP_CLK_RATIO */
4040
4041         if (bytespf < line_buf_size)
4042                 packet_payload = bytespf;
4043         else
4044                 packet_payload = (line_buf_size) / bytespl * bytespl;
4045
4046         packet_len = packet_payload + 1;        /* 1 byte for DCS cmd */
4047         total_len = (bytespf / packet_payload) * packet_len;
4048
4049         if (bytespf % packet_payload)
4050                 total_len += (bytespf % packet_payload) + 1;
4051
4052         l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4053         dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4054
4055         dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4056                 packet_len, 0);
4057
4058         if (dsi->te_enabled)
4059                 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4060         else
4061                 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4062         dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4063
4064         /* We put SIDLEMODE to no-idle for the duration of the transfer,
4065          * because DSS interrupts are not capable of waking up the CPU and the
4066          * framedone interrupt could be delayed for quite a long time. I think
4067          * the same goes for any DSS interrupts, but for some reason I have not
4068          * seen the problem anywhere else than here.
4069          */
4070         dispc_disable_sidle();
4071
4072         dsi_perf_mark_start(dsidev);
4073
4074         r = schedule_delayed_work(&dsi->framedone_timeout_work,
4075                 msecs_to_jiffies(250));
4076         BUG_ON(r == 0);
4077
4078         dss_mgr_set_timings(dispc_channel, &dsi->vm);
4079
4080         dss_mgr_start_update(dispc_channel);
4081
4082         if (dsi->te_enabled) {
4083                 /* disable LP_RX_TO, so that we can receive TE.  Time to wait
4084                  * for TE is longer than the timer allows */
4085                 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4086
4087                 dsi_vc_send_bta(dsidev, channel);
4088
4089 #ifdef DSI_CATCH_MISSING_TE
4090                 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4091 #endif
4092         }
4093 }
4094
4095 #ifdef DSI_CATCH_MISSING_TE
4096 static void dsi_te_timeout(struct timer_list *unused)
4097 {
4098         DSSERR("TE not received for 250ms!\n");
4099 }
4100 #endif
4101
4102 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4103 {
4104         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4105
4106         /* SIDLEMODE back to smart-idle */
4107         dispc_enable_sidle();
4108
4109         if (dsi->te_enabled) {
4110                 /* enable LP_RX_TO again after the TE */
4111                 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4112         }
4113
4114         dsi->framedone_callback(error, dsi->framedone_data);
4115
4116         if (!error)
4117                 dsi_perf_show(dsidev, "DISPC");
4118 }
4119
4120 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4121 {
4122         struct dsi_data *dsi = container_of(work, struct dsi_data,
4123                         framedone_timeout_work.work);
4124         /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4125          * 250ms which would conflict with this timeout work. What should be
4126          * done is first cancel the transfer on the HW, and then cancel the
4127          * possibly scheduled framedone work. However, cancelling the transfer
4128          * on the HW is buggy, and would probably require resetting the whole
4129          * DSI */
4130
4131         DSSERR("Framedone not received for 250ms!\n");
4132
4133         dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4134 }
4135
4136 static void dsi_framedone_irq_callback(void *data)
4137 {
4138         struct platform_device *dsidev = (struct platform_device *) data;
4139         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4140
4141         /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4142          * turns itself off. However, DSI still has the pixels in its buffers,
4143          * and is sending the data.
4144          */
4145
4146         cancel_delayed_work(&dsi->framedone_timeout_work);
4147
4148         dsi_handle_framedone(dsidev, 0);
4149 }
4150
4151 static int dsi_update(struct omap_dss_device *dssdev, int channel,
4152                 void (*callback)(int, void *), void *data)
4153 {
4154         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4155         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4156         u16 dw, dh;
4157
4158         dsi_perf_mark_setup(dsidev);
4159
4160         dsi->update_channel = channel;
4161
4162         dsi->framedone_callback = callback;
4163         dsi->framedone_data = data;
4164
4165         dw = dsi->vm.hactive;
4166         dh = dsi->vm.vactive;
4167
4168 #ifdef DSI_PERF_MEASURE
4169         dsi->update_bytes = dw * dh *
4170                 dsi_get_pixel_size(dsi->pix_fmt) / 8;
4171 #endif
4172         dsi_update_screen_dispc(dsidev);
4173
4174         return 0;
4175 }
4176
4177 /* Display funcs */
4178
4179 static int dsi_configure_dispc_clocks(struct platform_device *dsidev)
4180 {
4181         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4182         struct dispc_clock_info dispc_cinfo;
4183         int r;
4184         unsigned long fck;
4185
4186         fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4187
4188         dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
4189         dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
4190
4191         r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4192         if (r) {
4193                 DSSERR("Failed to calc dispc clocks\n");
4194                 return r;
4195         }
4196
4197         dsi->mgr_config.clock_info = dispc_cinfo;
4198
4199         return 0;
4200 }
4201
4202 static int dsi_display_init_dispc(struct platform_device *dsidev,
4203                 enum omap_channel channel)
4204 {
4205         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4206         int r;
4207
4208         dss_select_lcd_clk_source(channel, dsi->module_id == 0 ?
4209                         DSS_CLK_SRC_PLL1_1 :
4210                         DSS_CLK_SRC_PLL2_1);
4211
4212         if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4213                 r = dss_mgr_register_framedone_handler(channel,
4214                                 dsi_framedone_irq_callback, dsidev);
4215                 if (r) {
4216                         DSSERR("can't register FRAMEDONE handler\n");
4217                         goto err;
4218                 }
4219
4220                 dsi->mgr_config.stallmode = true;
4221                 dsi->mgr_config.fifohandcheck = true;
4222         } else {
4223                 dsi->mgr_config.stallmode = false;
4224                 dsi->mgr_config.fifohandcheck = false;
4225         }
4226
4227         /*
4228          * override interlace, logic level and edge related parameters in
4229          * videomode with default values
4230          */
4231         dsi->vm.flags &= ~DISPLAY_FLAGS_INTERLACED;
4232         dsi->vm.flags &= ~DISPLAY_FLAGS_HSYNC_LOW;
4233         dsi->vm.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
4234         dsi->vm.flags &= ~DISPLAY_FLAGS_VSYNC_LOW;
4235         dsi->vm.flags |= DISPLAY_FLAGS_VSYNC_HIGH;
4236         dsi->vm.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE;
4237         dsi->vm.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE;
4238         dsi->vm.flags &= ~DISPLAY_FLAGS_DE_LOW;
4239         dsi->vm.flags |= DISPLAY_FLAGS_DE_HIGH;
4240         dsi->vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE;
4241         dsi->vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE;
4242
4243         dss_mgr_set_timings(channel, &dsi->vm);
4244
4245         r = dsi_configure_dispc_clocks(dsidev);
4246         if (r)
4247                 goto err1;
4248
4249         dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4250         dsi->mgr_config.video_port_width =
4251                         dsi_get_pixel_size(dsi->pix_fmt);
4252         dsi->mgr_config.lcden_sig_polarity = 0;
4253
4254         dss_mgr_set_lcd_config(channel, &dsi->mgr_config);
4255
4256         return 0;
4257 err1:
4258         if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4259                 dss_mgr_unregister_framedone_handler(channel,
4260                                 dsi_framedone_irq_callback, dsidev);
4261 err:
4262         dss_select_lcd_clk_source(channel, DSS_CLK_SRC_FCK);
4263         return r;
4264 }
4265
4266 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
4267                 enum omap_channel channel)
4268 {
4269         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4270
4271         if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4272                 dss_mgr_unregister_framedone_handler(channel,
4273                                 dsi_framedone_irq_callback, dsidev);
4274
4275         dss_select_lcd_clk_source(channel, DSS_CLK_SRC_FCK);
4276 }
4277
4278 static int dsi_configure_dsi_clocks(struct platform_device *dsidev)
4279 {
4280         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4281         struct dss_pll_clock_info cinfo;
4282         int r;
4283
4284         cinfo = dsi->user_dsi_cinfo;
4285
4286         r = dss_pll_set_config(&dsi->pll, &cinfo);
4287         if (r) {
4288                 DSSERR("Failed to set dsi clocks\n");
4289                 return r;
4290         }
4291
4292         return 0;
4293 }
4294
4295 static int dsi_display_init_dsi(struct platform_device *dsidev)
4296 {
4297         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4298         int r;
4299
4300         r = dss_pll_enable(&dsi->pll);
4301         if (r)
4302                 goto err0;
4303
4304         r = dsi_configure_dsi_clocks(dsidev);
4305         if (r)
4306                 goto err1;
4307
4308         dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ?
4309                         DSS_CLK_SRC_PLL1_2 :
4310                         DSS_CLK_SRC_PLL2_2);
4311
4312         DSSDBG("PLL OK\n");
4313
4314         r = dsi_cio_init(dsidev);
4315         if (r)
4316                 goto err2;
4317
4318         _dsi_print_reset_status(dsidev);
4319
4320         dsi_proto_timings(dsidev);
4321         dsi_set_lp_clk_divisor(dsidev);
4322
4323         if (1)
4324                 _dsi_print_reset_status(dsidev);
4325
4326         r = dsi_proto_config(dsidev);
4327         if (r)
4328                 goto err3;
4329
4330         /* enable interface */
4331         dsi_vc_enable(dsidev, 0, 1);
4332         dsi_vc_enable(dsidev, 1, 1);
4333         dsi_vc_enable(dsidev, 2, 1);
4334         dsi_vc_enable(dsidev, 3, 1);
4335         dsi_if_enable(dsidev, 1);
4336         dsi_force_tx_stop_mode_io(dsidev);
4337
4338         return 0;
4339 err3:
4340         dsi_cio_uninit(dsidev);
4341 err2:
4342         dss_select_dsi_clk_source(dsi->module_id, DSS_CLK_SRC_FCK);
4343 err1:
4344         dss_pll_disable(&dsi->pll);
4345 err0:
4346         return r;
4347 }
4348
4349 static void dsi_display_uninit_dsi(struct platform_device *dsidev,
4350                 bool disconnect_lanes, bool enter_ulps)
4351 {
4352         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4353
4354         if (enter_ulps && !dsi->ulps_enabled)
4355                 dsi_enter_ulps(dsidev);
4356
4357         /* disable interface */
4358         dsi_if_enable(dsidev, 0);
4359         dsi_vc_enable(dsidev, 0, 0);
4360         dsi_vc_enable(dsidev, 1, 0);
4361         dsi_vc_enable(dsidev, 2, 0);
4362         dsi_vc_enable(dsidev, 3, 0);
4363
4364         dss_select_dsi_clk_source(dsi->module_id, DSS_CLK_SRC_FCK);
4365         dsi_cio_uninit(dsidev);
4366         dsi_pll_uninit(dsidev, disconnect_lanes);
4367 }
4368
4369 static int dsi_display_enable(struct omap_dss_device *dssdev)
4370 {
4371         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4372         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4373         int r = 0;
4374
4375         DSSDBG("dsi_display_enable\n");
4376
4377         WARN_ON(!dsi_bus_is_locked(dsidev));
4378
4379         mutex_lock(&dsi->lock);
4380
4381         r = dsi_runtime_get(dsidev);
4382         if (r)
4383                 goto err_get_dsi;
4384
4385         _dsi_initialize_irq(dsidev);
4386
4387         r = dsi_display_init_dsi(dsidev);
4388         if (r)
4389                 goto err_init_dsi;
4390
4391         mutex_unlock(&dsi->lock);
4392
4393         return 0;
4394
4395 err_init_dsi:
4396         dsi_runtime_put(dsidev);
4397 err_get_dsi:
4398         mutex_unlock(&dsi->lock);
4399         DSSDBG("dsi_display_enable FAILED\n");
4400         return r;
4401 }
4402
4403 static void dsi_display_disable(struct omap_dss_device *dssdev,
4404                 bool disconnect_lanes, bool enter_ulps)
4405 {
4406         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4407         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4408
4409         DSSDBG("dsi_display_disable\n");
4410
4411         WARN_ON(!dsi_bus_is_locked(dsidev));
4412
4413         mutex_lock(&dsi->lock);
4414
4415         dsi_sync_vc(dsidev, 0);
4416         dsi_sync_vc(dsidev, 1);
4417         dsi_sync_vc(dsidev, 2);
4418         dsi_sync_vc(dsidev, 3);
4419
4420         dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps);
4421
4422         dsi_runtime_put(dsidev);
4423
4424         mutex_unlock(&dsi->lock);
4425 }
4426
4427 static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4428 {
4429         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4430         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4431
4432         dsi->te_enabled = enable;
4433         return 0;
4434 }
4435
4436 #ifdef PRINT_VERBOSE_VM_TIMINGS
4437 static void print_dsi_vm(const char *str,
4438                 const struct omap_dss_dsi_videomode_timings *t)
4439 {
4440         unsigned long byteclk = t->hsclk / 4;
4441         int bl, wc, pps, tot;
4442
4443         wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
4444         pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */
4445         bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp;
4446         tot = bl + pps;
4447
4448 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
4449
4450         pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, "
4451                         "%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
4452                         str,
4453                         byteclk,
4454                         t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,
4455                         bl, pps, tot,
4456                         TO_DSI_T(t->hss),
4457                         TO_DSI_T(t->hsa),
4458                         TO_DSI_T(t->hse),
4459                         TO_DSI_T(t->hbp),
4460                         TO_DSI_T(pps),
4461                         TO_DSI_T(t->hfp),
4462
4463                         TO_DSI_T(bl),
4464                         TO_DSI_T(pps),
4465
4466                         TO_DSI_T(tot));
4467 #undef TO_DSI_T
4468 }
4469
4470 static void print_dispc_vm(const char *str, const struct videomode *vm)
4471 {
4472         unsigned long pck = vm->pixelclock;
4473         int hact, bl, tot;
4474
4475         hact = vm->hactive;
4476         bl = vm->hsync_len + vm->hback_porch + vm->hfront_porch;
4477         tot = hact + bl;
4478
4479 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
4480
4481         pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, "
4482                         "%u/%u/%u/%u = %u + %u = %u\n",
4483                         str,
4484                         pck,
4485                         vm->hsync_len, vm->hback_porch, hact, vm->hfront_porch,
4486                         bl, hact, tot,
4487                         TO_DISPC_T(vm->hsync_len),
4488                         TO_DISPC_T(vm->hback_porch),
4489                         TO_DISPC_T(hact),
4490                         TO_DISPC_T(vm->hfront_porch),
4491                         TO_DISPC_T(bl),
4492                         TO_DISPC_T(hact),
4493                         TO_DISPC_T(tot));
4494 #undef TO_DISPC_T
4495 }
4496
4497 /* note: this is not quite accurate */
4498 static void print_dsi_dispc_vm(const char *str,
4499                 const struct omap_dss_dsi_videomode_timings *t)
4500 {
4501         struct videomode vm = { 0 };
4502         unsigned long byteclk = t->hsclk / 4;
4503         unsigned long pck;
4504         u64 dsi_tput;
4505         int dsi_hact, dsi_htot;
4506
4507         dsi_tput = (u64)byteclk * t->ndl * 8;
4508         pck = (u32)div64_u64(dsi_tput, t->bitspp);
4509         dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
4510         dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
4511
4512         vm.pixelclock = pck;
4513         vm.hsync_len = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
4514         vm.hback_porch = div64_u64((u64)t->hbp * pck, byteclk);
4515         vm.hfront_porch = div64_u64((u64)t->hfp * pck, byteclk);
4516         vm.hactive = t->hact;
4517
4518         print_dispc_vm(str, &vm);
4519 }
4520 #endif /* PRINT_VERBOSE_VM_TIMINGS */
4521
4522 static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4523                 unsigned long pck, void *data)
4524 {
4525         struct dsi_clk_calc_ctx *ctx = data;
4526         struct videomode *vm = &ctx->vm;
4527
4528         ctx->dispc_cinfo.lck_div = lckd;
4529         ctx->dispc_cinfo.pck_div = pckd;
4530         ctx->dispc_cinfo.lck = lck;
4531         ctx->dispc_cinfo.pck = pck;
4532
4533         *vm = *ctx->config->vm;
4534         vm->pixelclock = pck;
4535         vm->hactive = ctx->config->vm->hactive;
4536         vm->vactive = ctx->config->vm->vactive;
4537         vm->hsync_len = vm->hfront_porch = vm->hback_porch = vm->vsync_len = 1;
4538         vm->vfront_porch = vm->vback_porch = 0;
4539
4540         return true;
4541 }
4542
4543 static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4544                 void *data)
4545 {
4546         struct dsi_clk_calc_ctx *ctx = data;
4547
4548         ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4549         ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4550
4551         return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max,
4552                         dsi_cm_calc_dispc_cb, ctx);
4553 }
4554
4555 static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint,
4556                 unsigned long clkdco, void *data)
4557 {
4558         struct dsi_clk_calc_ctx *ctx = data;
4559         struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev);
4560
4561         ctx->dsi_cinfo.n = n;
4562         ctx->dsi_cinfo.m = m;
4563         ctx->dsi_cinfo.fint = fint;
4564         ctx->dsi_cinfo.clkdco = clkdco;
4565
4566         return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min,
4567                         dsi->data->max_fck_freq,
4568                         dsi_cm_calc_hsdiv_cb, ctx);
4569 }
4570
4571 static bool dsi_cm_calc(struct dsi_data *dsi,
4572                 const struct omap_dss_dsi_config *cfg,
4573                 struct dsi_clk_calc_ctx *ctx)
4574 {
4575         unsigned long clkin;
4576         int bitspp, ndl;
4577         unsigned long pll_min, pll_max;
4578         unsigned long pck, txbyteclk;
4579
4580         clkin = clk_get_rate(dsi->pll.clkin);
4581         bitspp = dsi_get_pixel_size(cfg->pixel_format);
4582         ndl = dsi->num_lanes_used - 1;
4583
4584         /*
4585          * Here we should calculate minimum txbyteclk to be able to send the
4586          * frame in time, and also to handle TE. That's not very simple, though,
4587          * especially as we go to LP between each pixel packet due to HW
4588          * "feature". So let's just estimate very roughly and multiply by 1.5.
4589          */
4590         pck = cfg->vm->pixelclock;
4591         pck = pck * 3 / 2;
4592         txbyteclk = pck * bitspp / 8 / ndl;
4593
4594         memset(ctx, 0, sizeof(*ctx));
4595         ctx->dsidev = dsi->pdev;
4596         ctx->pll = &dsi->pll;
4597         ctx->config = cfg;
4598         ctx->req_pck_min = pck;
4599         ctx->req_pck_nom = pck;
4600         ctx->req_pck_max = pck * 3 / 2;
4601
4602         pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4);
4603         pll_max = cfg->hs_clk_max * 4;
4604
4605         return dss_pll_calc_a(ctx->pll, clkin,
4606                         pll_min, pll_max,
4607                         dsi_cm_calc_pll_cb, ctx);
4608 }
4609
4610 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4611 {
4612         struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev);
4613         const struct omap_dss_dsi_config *cfg = ctx->config;
4614         int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4615         int ndl = dsi->num_lanes_used - 1;
4616         unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4;
4617         unsigned long byteclk = hsclk / 4;
4618
4619         unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max;
4620         int xres;
4621         int panel_htot, panel_hbl; /* pixels */
4622         int dispc_htot, dispc_hbl; /* pixels */
4623         int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */
4624         int hfp, hsa, hbp;
4625         const struct videomode *req_vm;
4626         struct videomode *dispc_vm;
4627         struct omap_dss_dsi_videomode_timings *dsi_vm;
4628         u64 dsi_tput, dispc_tput;
4629
4630         dsi_tput = (u64)byteclk * ndl * 8;
4631
4632         req_vm = cfg->vm;
4633         req_pck_min = ctx->req_pck_min;
4634         req_pck_max = ctx->req_pck_max;
4635         req_pck_nom = ctx->req_pck_nom;
4636
4637         dispc_pck = ctx->dispc_cinfo.pck;
4638         dispc_tput = (u64)dispc_pck * bitspp;
4639
4640         xres = req_vm->hactive;
4641
4642         panel_hbl = req_vm->hfront_porch + req_vm->hback_porch +
4643                     req_vm->hsync_len;
4644         panel_htot = xres + panel_hbl;
4645
4646         dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
4647
4648         /*
4649          * When there are no line buffers, DISPC and DSI must have the
4650          * same tput. Otherwise DISPC tput needs to be higher than DSI's.
4651          */
4652         if (dsi->line_buffer_size < xres * bitspp / 8) {
4653                 if (dispc_tput != dsi_tput)
4654                         return false;
4655         } else {
4656                 if (dispc_tput < dsi_tput)
4657                         return false;
4658         }
4659
4660         /* DSI tput must be over the min requirement */
4661         if (dsi_tput < (u64)bitspp * req_pck_min)
4662                 return false;
4663
4664         /* When non-burst mode, DSI tput must be below max requirement. */
4665         if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) {
4666                 if (dsi_tput > (u64)bitspp * req_pck_max)
4667                         return false;
4668         }
4669
4670         hss = DIV_ROUND_UP(4, ndl);
4671
4672         if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4673                 if (ndl == 3 && req_vm->hsync_len == 0)
4674                         hse = 1;
4675                 else
4676                         hse = DIV_ROUND_UP(4, ndl);
4677         } else {
4678                 hse = 0;
4679         }
4680
4681         /* DSI htot to match the panel's nominal pck */
4682         dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom);
4683
4684         /* fail if there would be no time for blanking */
4685         if (dsi_htot < hss + hse + dsi_hact)
4686                 return false;
4687
4688         /* total DSI blanking needed to achieve panel's TL */
4689         dsi_hbl = dsi_htot - dsi_hact;
4690
4691         /* DISPC htot to match the DSI TL */
4692         dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk);
4693
4694         /* verify that the DSI and DISPC TLs are the same */
4695         if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk)
4696                 return false;
4697
4698         dispc_hbl = dispc_htot - xres;
4699
4700         /* setup DSI videomode */
4701
4702         dsi_vm = &ctx->dsi_vm;
4703         memset(dsi_vm, 0, sizeof(*dsi_vm));
4704
4705         dsi_vm->hsclk = hsclk;
4706
4707         dsi_vm->ndl = ndl;
4708         dsi_vm->bitspp = bitspp;
4709
4710         if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
4711                 hsa = 0;
4712         } else if (ndl == 3 && req_vm->hsync_len == 0) {
4713                 hsa = 0;
4714         } else {
4715                 hsa = div64_u64((u64)req_vm->hsync_len * byteclk, req_pck_nom);
4716                 hsa = max(hsa - hse, 1);
4717         }
4718
4719         hbp = div64_u64((u64)req_vm->hback_porch * byteclk, req_pck_nom);
4720         hbp = max(hbp, 1);
4721
4722         hfp = dsi_hbl - (hss + hsa + hse + hbp);
4723         if (hfp < 1) {
4724                 int t;
4725                 /* we need to take cycles from hbp */
4726
4727                 t = 1 - hfp;
4728                 hbp = max(hbp - t, 1);
4729                 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4730
4731                 if (hfp < 1 && hsa > 0) {
4732                         /* we need to take cycles from hsa */
4733                         t = 1 - hfp;
4734                         hsa = max(hsa - t, 1);
4735                         hfp = dsi_hbl - (hss + hsa + hse + hbp);
4736                 }
4737         }
4738
4739         if (hfp < 1)
4740                 return false;
4741
4742         dsi_vm->hss = hss;
4743         dsi_vm->hsa = hsa;
4744         dsi_vm->hse = hse;
4745         dsi_vm->hbp = hbp;
4746         dsi_vm->hact = xres;
4747         dsi_vm->hfp = hfp;
4748
4749         dsi_vm->vsa = req_vm->vsync_len;
4750         dsi_vm->vbp = req_vm->vback_porch;
4751         dsi_vm->vact = req_vm->vactive;
4752         dsi_vm->vfp = req_vm->vfront_porch;
4753
4754         dsi_vm->trans_mode = cfg->trans_mode;
4755
4756         dsi_vm->blanking_mode = 0;
4757         dsi_vm->hsa_blanking_mode = 1;
4758         dsi_vm->hfp_blanking_mode = 1;
4759         dsi_vm->hbp_blanking_mode = 1;
4760
4761         dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on;
4762         dsi_vm->window_sync = 4;
4763
4764         /* setup DISPC videomode */
4765
4766         dispc_vm = &ctx->vm;
4767         *dispc_vm = *req_vm;
4768         dispc_vm->pixelclock = dispc_pck;
4769
4770         if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4771                 hsa = div64_u64((u64)req_vm->hsync_len * dispc_pck,
4772                                 req_pck_nom);
4773                 hsa = max(hsa, 1);
4774         } else {
4775                 hsa = 1;
4776         }
4777
4778         hbp = div64_u64((u64)req_vm->hback_porch * dispc_pck, req_pck_nom);
4779         hbp = max(hbp, 1);
4780
4781         hfp = dispc_hbl - hsa - hbp;
4782         if (hfp < 1) {
4783                 int t;
4784                 /* we need to take cycles from hbp */
4785
4786                 t = 1 - hfp;
4787                 hbp = max(hbp - t, 1);
4788                 hfp = dispc_hbl - hsa - hbp;
4789
4790                 if (hfp < 1) {
4791                         /* we need to take cycles from hsa */
4792                         t = 1 - hfp;
4793                         hsa = max(hsa - t, 1);
4794                         hfp = dispc_hbl - hsa - hbp;
4795                 }
4796         }
4797
4798         if (hfp < 1)
4799                 return false;
4800
4801         dispc_vm->hfront_porch = hfp;
4802         dispc_vm->hsync_len = hsa;
4803         dispc_vm->hback_porch = hbp;
4804
4805         return true;
4806 }
4807
4808
4809 static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4810                 unsigned long pck, void *data)
4811 {
4812         struct dsi_clk_calc_ctx *ctx = data;
4813
4814         ctx->dispc_cinfo.lck_div = lckd;
4815         ctx->dispc_cinfo.pck_div = pckd;
4816         ctx->dispc_cinfo.lck = lck;
4817         ctx->dispc_cinfo.pck = pck;
4818
4819         if (dsi_vm_calc_blanking(ctx) == false)
4820                 return false;
4821
4822 #ifdef PRINT_VERBOSE_VM_TIMINGS
4823         print_dispc_vm("dispc", &ctx->vm);
4824         print_dsi_vm("dsi  ", &ctx->dsi_vm);
4825         print_dispc_vm("req  ", ctx->config->vm);
4826         print_dsi_dispc_vm("act  ", &ctx->dsi_vm);
4827 #endif
4828
4829         return true;
4830 }
4831
4832 static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4833                 void *data)
4834 {
4835         struct dsi_clk_calc_ctx *ctx = data;
4836         unsigned long pck_max;
4837
4838         ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4839         ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4840
4841         /*
4842          * In burst mode we can let the dispc pck be arbitrarily high, but it
4843          * limits our scaling abilities. So for now, don't aim too high.
4844          */
4845
4846         if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE)
4847                 pck_max = ctx->req_pck_max + 10000000;
4848         else
4849                 pck_max = ctx->req_pck_max;
4850
4851         return dispc_div_calc(dispc, ctx->req_pck_min, pck_max,
4852                         dsi_vm_calc_dispc_cb, ctx);
4853 }
4854
4855 static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint,
4856                 unsigned long clkdco, void *data)
4857 {
4858         struct dsi_clk_calc_ctx *ctx = data;
4859         struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev);
4860
4861         ctx->dsi_cinfo.n = n;
4862         ctx->dsi_cinfo.m = m;
4863         ctx->dsi_cinfo.fint = fint;
4864         ctx->dsi_cinfo.clkdco = clkdco;
4865
4866         return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min,
4867                         dsi->data->max_fck_freq,
4868                         dsi_vm_calc_hsdiv_cb, ctx);
4869 }
4870
4871 static bool dsi_vm_calc(struct dsi_data *dsi,
4872                 const struct omap_dss_dsi_config *cfg,
4873                 struct dsi_clk_calc_ctx *ctx)
4874 {
4875         const struct videomode *vm = cfg->vm;
4876         unsigned long clkin;
4877         unsigned long pll_min;
4878         unsigned long pll_max;
4879         int ndl = dsi->num_lanes_used - 1;
4880         int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4881         unsigned long byteclk_min;
4882
4883         clkin = clk_get_rate(dsi->pll.clkin);
4884
4885         memset(ctx, 0, sizeof(*ctx));
4886         ctx->dsidev = dsi->pdev;
4887         ctx->pll = &dsi->pll;
4888         ctx->config = cfg;
4889
4890         /* these limits should come from the panel driver */
4891         ctx->req_pck_min = vm->pixelclock - 1000;
4892         ctx->req_pck_nom = vm->pixelclock;
4893         ctx->req_pck_max = vm->pixelclock + 1000;
4894
4895         byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
4896         pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
4897
4898         if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) {
4899                 pll_max = cfg->hs_clk_max * 4;
4900         } else {
4901                 unsigned long byteclk_max;
4902                 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp,
4903                                 ndl * 8);
4904
4905                 pll_max = byteclk_max * 4 * 4;
4906         }
4907
4908         return dss_pll_calc_a(ctx->pll, clkin,
4909                         pll_min, pll_max,
4910                         dsi_vm_calc_pll_cb, ctx);
4911 }
4912
4913 static int dsi_set_config(struct omap_dss_device *dssdev,
4914                 const struct omap_dss_dsi_config *config)
4915 {
4916         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4917         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4918         struct dsi_clk_calc_ctx ctx;
4919         bool ok;
4920         int r;
4921
4922         mutex_lock(&dsi->lock);
4923
4924         dsi->pix_fmt = config->pixel_format;
4925         dsi->mode = config->mode;
4926
4927         if (config->mode == OMAP_DSS_DSI_VIDEO_MODE)
4928                 ok = dsi_vm_calc(dsi, config, &ctx);
4929         else
4930                 ok = dsi_cm_calc(dsi, config, &ctx);
4931
4932         if (!ok) {
4933                 DSSERR("failed to find suitable DSI clock settings\n");
4934                 r = -EINVAL;
4935                 goto err;
4936         }
4937
4938         dsi_pll_calc_dsi_fck(dsi, &ctx.dsi_cinfo);
4939
4940         r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI],
4941                 config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo);
4942         if (r) {
4943                 DSSERR("failed to find suitable DSI LP clock settings\n");
4944                 goto err;
4945         }
4946
4947         dsi->user_dsi_cinfo = ctx.dsi_cinfo;
4948         dsi->user_dispc_cinfo = ctx.dispc_cinfo;
4949
4950         dsi->vm = ctx.vm;
4951         dsi->vm_timings = ctx.dsi_vm;
4952
4953         mutex_unlock(&dsi->lock);
4954
4955         return 0;
4956 err:
4957         mutex_unlock(&dsi->lock);
4958
4959         return r;
4960 }
4961
4962 /*
4963  * Return a hardcoded channel for the DSI output. This should work for
4964  * current use cases, but this can be later expanded to either resolve
4965  * the channel in some more dynamic manner, or get the channel as a user
4966  * parameter.
4967  */
4968 static enum omap_channel dsi_get_channel(struct dsi_data *dsi)
4969 {
4970         switch (dsi->data->model) {
4971         case DSI_MODEL_OMAP3:
4972                 return OMAP_DSS_CHANNEL_LCD;
4973
4974         case DSI_MODEL_OMAP4:
4975                 switch (dsi->module_id) {
4976                 case 0:
4977                         return OMAP_DSS_CHANNEL_LCD;
4978                 case 1:
4979                         return OMAP_DSS_CHANNEL_LCD2;
4980                 default:
4981                         DSSWARN("unsupported module id\n");
4982                         return OMAP_DSS_CHANNEL_LCD;
4983                 }
4984
4985         case DSI_MODEL_OMAP5:
4986                 switch (dsi->module_id) {
4987                 case 0:
4988                         return OMAP_DSS_CHANNEL_LCD;
4989                 case 1:
4990                         return OMAP_DSS_CHANNEL_LCD3;
4991                 default:
4992                         DSSWARN("unsupported module id\n");
4993                         return OMAP_DSS_CHANNEL_LCD;
4994                 }
4995
4996         default:
4997                 DSSWARN("unsupported DSS version\n");
4998                 return OMAP_DSS_CHANNEL_LCD;
4999         }
5000 }
5001
5002 static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
5003 {
5004         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5005         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5006         int i;
5007
5008         for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5009                 if (!dsi->vc[i].dssdev) {
5010                         dsi->vc[i].dssdev = dssdev;
5011                         *channel = i;
5012                         return 0;
5013                 }
5014         }
5015
5016         DSSERR("cannot get VC for display %s", dssdev->name);
5017         return -ENOSPC;
5018 }
5019
5020 static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
5021 {
5022         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5023         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5024
5025         if (vc_id < 0 || vc_id > 3) {
5026                 DSSERR("VC ID out of range\n");
5027                 return -EINVAL;
5028         }
5029
5030         if (channel < 0 || channel > 3) {
5031                 DSSERR("Virtual Channel out of range\n");
5032                 return -EINVAL;
5033         }
5034
5035         if (dsi->vc[channel].dssdev != dssdev) {
5036                 DSSERR("Virtual Channel not allocated to display %s\n",
5037                         dssdev->name);
5038                 return -EINVAL;
5039         }
5040
5041         dsi->vc[channel].vc_id = vc_id;
5042
5043         return 0;
5044 }
5045
5046 static void dsi_release_vc(struct omap_dss_device *dssdev, int channel)
5047 {
5048         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5049         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5050
5051         if ((channel >= 0 && channel <= 3) &&
5052                 dsi->vc[channel].dssdev == dssdev) {
5053                 dsi->vc[channel].dssdev = NULL;
5054                 dsi->vc[channel].vc_id = 0;
5055         }
5056 }
5057
5058
5059 static int dsi_get_clocks(struct platform_device *dsidev)
5060 {
5061         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5062         struct clk *clk;
5063
5064         clk = devm_clk_get(&dsidev->dev, "fck");
5065         if (IS_ERR(clk)) {
5066                 DSSERR("can't get fck\n");
5067                 return PTR_ERR(clk);
5068         }
5069
5070         dsi->dss_clk = clk;
5071
5072         return 0;
5073 }
5074
5075 static int dsi_connect(struct omap_dss_device *dssdev,
5076                 struct omap_dss_device *dst)
5077 {
5078         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5079         enum omap_channel dispc_channel = dssdev->dispc_channel;
5080         int r;
5081
5082         r = dsi_regulator_init(dsidev);
5083         if (r)
5084                 return r;
5085
5086         r = dss_mgr_connect(dispc_channel, dssdev);
5087         if (r)
5088                 return r;
5089
5090         r = omapdss_output_set_device(dssdev, dst);
5091         if (r) {
5092                 DSSERR("failed to connect output to new device: %s\n",
5093                                 dssdev->name);
5094                 dss_mgr_disconnect(dispc_channel, dssdev);
5095                 return r;
5096         }
5097
5098         return 0;
5099 }
5100
5101 static void dsi_disconnect(struct omap_dss_device *dssdev,
5102                 struct omap_dss_device *dst)
5103 {
5104         enum omap_channel dispc_channel = dssdev->dispc_channel;
5105
5106         WARN_ON(dst != dssdev->dst);
5107
5108         if (dst != dssdev->dst)
5109                 return;
5110
5111         omapdss_output_unset_device(dssdev);
5112
5113         dss_mgr_disconnect(dispc_channel, dssdev);
5114 }
5115
5116 static const struct omapdss_dsi_ops dsi_ops = {
5117         .connect = dsi_connect,
5118         .disconnect = dsi_disconnect,
5119
5120         .bus_lock = dsi_bus_lock,
5121         .bus_unlock = dsi_bus_unlock,
5122
5123         .enable = dsi_display_enable,
5124         .disable = dsi_display_disable,
5125
5126         .enable_hs = dsi_vc_enable_hs,
5127
5128         .configure_pins = dsi_configure_pins,
5129         .set_config = dsi_set_config,
5130
5131         .enable_video_output = dsi_enable_video_output,
5132         .disable_video_output = dsi_disable_video_output,
5133
5134         .update = dsi_update,
5135
5136         .enable_te = dsi_enable_te,
5137
5138         .request_vc = dsi_request_vc,
5139         .set_vc_id = dsi_set_vc_id,
5140         .release_vc = dsi_release_vc,
5141
5142         .dcs_write = dsi_vc_dcs_write,
5143         .dcs_write_nosync = dsi_vc_dcs_write_nosync,
5144         .dcs_read = dsi_vc_dcs_read,
5145
5146         .gen_write = dsi_vc_generic_write,
5147         .gen_write_nosync = dsi_vc_generic_write_nosync,
5148         .gen_read = dsi_vc_generic_read,
5149
5150         .bta_sync = dsi_vc_send_bta_sync,
5151
5152         .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size,
5153 };
5154
5155 static void dsi_init_output(struct platform_device *dsidev)
5156 {
5157         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5158         struct omap_dss_device *out = &dsi->output;
5159
5160         out->dev = &dsidev->dev;
5161         out->id = dsi->module_id == 0 ?
5162                         OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5163
5164         out->output_type = OMAP_DISPLAY_TYPE_DSI;
5165         out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
5166         out->dispc_channel = dsi_get_channel(dsi);
5167         out->ops.dsi = &dsi_ops;
5168         out->owner = THIS_MODULE;
5169
5170         omapdss_register_output(out);
5171 }
5172
5173 static void dsi_uninit_output(struct platform_device *dsidev)
5174 {
5175         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5176         struct omap_dss_device *out = &dsi->output;
5177
5178         omapdss_unregister_output(out);
5179 }
5180
5181 static int dsi_probe_of(struct platform_device *pdev)
5182 {
5183         struct device_node *node = pdev->dev.of_node;
5184         struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5185         struct property *prop;
5186         u32 lane_arr[10];
5187         int len, num_pins;
5188         int r, i;
5189         struct device_node *ep;
5190         struct omap_dsi_pin_config pin_cfg;
5191
5192         ep = of_graph_get_endpoint_by_regs(node, 0, 0);
5193         if (!ep)
5194                 return 0;
5195
5196         prop = of_find_property(ep, "lanes", &len);
5197         if (prop == NULL) {
5198                 dev_err(&pdev->dev, "failed to find lane data\n");
5199                 r = -EINVAL;
5200                 goto err;
5201         }
5202
5203         num_pins = len / sizeof(u32);
5204
5205         if (num_pins < 4 || num_pins % 2 != 0 ||
5206                 num_pins > dsi->num_lanes_supported * 2) {
5207                 dev_err(&pdev->dev, "bad number of lanes\n");
5208                 r = -EINVAL;
5209                 goto err;
5210         }
5211
5212         r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins);
5213         if (r) {
5214                 dev_err(&pdev->dev, "failed to read lane data\n");
5215                 goto err;
5216         }
5217
5218         pin_cfg.num_pins = num_pins;
5219         for (i = 0; i < num_pins; ++i)
5220                 pin_cfg.pins[i] = (int)lane_arr[i];
5221
5222         r = dsi_configure_pins(&dsi->output, &pin_cfg);
5223         if (r) {
5224                 dev_err(&pdev->dev, "failed to configure pins");
5225                 goto err;
5226         }
5227
5228         of_node_put(ep);
5229
5230         return 0;
5231
5232 err:
5233         of_node_put(ep);
5234         return r;
5235 }
5236
5237 static const struct dss_pll_ops dsi_pll_ops = {
5238         .enable = dsi_pll_enable,
5239         .disable = dsi_pll_disable,
5240         .set_config = dss_pll_write_config_type_a,
5241 };
5242
5243 static const struct dss_pll_hw dss_omap3_dsi_pll_hw = {
5244         .type = DSS_PLL_TYPE_A,
5245
5246         .n_max = (1 << 7) - 1,
5247         .m_max = (1 << 11) - 1,
5248         .mX_max = (1 << 4) - 1,
5249         .fint_min = 750000,
5250         .fint_max = 2100000,
5251         .clkdco_low = 1000000000,
5252         .clkdco_max = 1800000000,
5253
5254         .n_msb = 7,
5255         .n_lsb = 1,
5256         .m_msb = 18,
5257         .m_lsb = 8,
5258
5259         .mX_msb[0] = 22,
5260         .mX_lsb[0] = 19,
5261         .mX_msb[1] = 26,
5262         .mX_lsb[1] = 23,
5263
5264         .has_stopmode = true,
5265         .has_freqsel = true,
5266         .has_selfreqdco = false,
5267         .has_refsel = false,
5268 };
5269
5270 static const struct dss_pll_hw dss_omap4_dsi_pll_hw = {
5271         .type = DSS_PLL_TYPE_A,
5272
5273         .n_max = (1 << 8) - 1,
5274         .m_max = (1 << 12) - 1,
5275         .mX_max = (1 << 5) - 1,
5276         .fint_min = 500000,
5277         .fint_max = 2500000,
5278         .clkdco_low = 1000000000,
5279         .clkdco_max = 1800000000,
5280
5281         .n_msb = 8,
5282         .n_lsb = 1,
5283         .m_msb = 20,
5284         .m_lsb = 9,
5285
5286         .mX_msb[0] = 25,
5287         .mX_lsb[0] = 21,
5288         .mX_msb[1] = 30,
5289         .mX_lsb[1] = 26,
5290
5291         .has_stopmode = true,
5292         .has_freqsel = false,
5293         .has_selfreqdco = false,
5294         .has_refsel = false,
5295 };
5296
5297 static const struct dss_pll_hw dss_omap5_dsi_pll_hw = {
5298         .type = DSS_PLL_TYPE_A,
5299
5300         .n_max = (1 << 8) - 1,
5301         .m_max = (1 << 12) - 1,
5302         .mX_max = (1 << 5) - 1,
5303         .fint_min = 150000,
5304         .fint_max = 52000000,
5305         .clkdco_low = 1000000000,
5306         .clkdco_max = 1800000000,
5307
5308         .n_msb = 8,
5309         .n_lsb = 1,
5310         .m_msb = 20,
5311         .m_lsb = 9,
5312
5313         .mX_msb[0] = 25,
5314         .mX_lsb[0] = 21,
5315         .mX_msb[1] = 30,
5316         .mX_lsb[1] = 26,
5317
5318         .has_stopmode = true,
5319         .has_freqsel = false,
5320         .has_selfreqdco = true,
5321         .has_refsel = true,
5322 };
5323
5324 static int dsi_init_pll_data(struct platform_device *dsidev)
5325 {
5326         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5327         struct dss_pll *pll = &dsi->pll;
5328         struct clk *clk;
5329         int r;
5330
5331         clk = devm_clk_get(&dsidev->dev, "sys_clk");
5332         if (IS_ERR(clk)) {
5333                 DSSERR("can't get sys_clk\n");
5334                 return PTR_ERR(clk);
5335         }
5336
5337         pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1";
5338         pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2;
5339         pll->clkin = clk;
5340         pll->base = dsi->pll_base;
5341         pll->hw = dsi->data->pll_hw;
5342         pll->ops = &dsi_pll_ops;
5343
5344         r = dss_pll_register(pll);
5345         if (r)
5346                 return r;
5347
5348         return 0;
5349 }
5350
5351 /* DSI1 HW IP initialisation */
5352 static const struct dsi_of_data dsi_of_data_omap34xx = {
5353         .model = DSI_MODEL_OMAP3,
5354         .pll_hw = &dss_omap3_dsi_pll_hw,
5355         .modules = (const struct dsi_module_id_data[]) {
5356                 { .address = 0x4804fc00, .id = 0, },
5357                 { },
5358         },
5359         .max_fck_freq = 173000000,
5360         .max_pll_lpdiv = (1 << 13) - 1,
5361         .quirks = DSI_QUIRK_REVERSE_TXCLKESC,
5362 };
5363
5364 static const struct dsi_of_data dsi_of_data_omap36xx = {
5365         .model = DSI_MODEL_OMAP3,
5366         .pll_hw = &dss_omap3_dsi_pll_hw,
5367         .modules = (const struct dsi_module_id_data[]) {
5368                 { .address = 0x4804fc00, .id = 0, },
5369                 { },
5370         },
5371         .max_fck_freq = 173000000,
5372         .max_pll_lpdiv = (1 << 13) - 1,
5373         .quirks = DSI_QUIRK_PLL_PWR_BUG,
5374 };
5375
5376 static const struct dsi_of_data dsi_of_data_omap4 = {
5377         .model = DSI_MODEL_OMAP4,
5378         .pll_hw = &dss_omap4_dsi_pll_hw,
5379         .modules = (const struct dsi_module_id_data[]) {
5380                 { .address = 0x58004000, .id = 0, },
5381                 { .address = 0x58005000, .id = 1, },
5382                 { },
5383         },
5384         .max_fck_freq = 170000000,
5385         .max_pll_lpdiv = (1 << 13) - 1,
5386         .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH
5387                 | DSI_QUIRK_GNQ,
5388 };
5389
5390 static const struct dsi_of_data dsi_of_data_omap5 = {
5391         .model = DSI_MODEL_OMAP5,
5392         .pll_hw = &dss_omap5_dsi_pll_hw,
5393         .modules = (const struct dsi_module_id_data[]) {
5394                 { .address = 0x58004000, .id = 0, },
5395                 { .address = 0x58009000, .id = 1, },
5396                 { },
5397         },
5398         .max_fck_freq = 209250000,
5399         .max_pll_lpdiv = (1 << 13) - 1,
5400         .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH
5401                 | DSI_QUIRK_GNQ | DSI_QUIRK_PHY_DCC,
5402 };
5403
5404 static const struct of_device_id dsi_of_match[] = {
5405         { .compatible = "ti,omap3-dsi", .data = &dsi_of_data_omap36xx, },
5406         { .compatible = "ti,omap4-dsi", .data = &dsi_of_data_omap4, },
5407         { .compatible = "ti,omap5-dsi", .data = &dsi_of_data_omap5, },
5408         {},
5409 };
5410
5411 static const struct soc_device_attribute dsi_soc_devices[] = {
5412         { .machine = "OMAP3[45]*",      .data = &dsi_of_data_omap34xx },
5413         { .machine = "AM35*",           .data = &dsi_of_data_omap34xx },
5414         { /* sentinel */ }
5415 };
5416 static int dsi_bind(struct device *dev, struct device *master, void *data)
5417 {
5418         struct platform_device *dsidev = to_platform_device(dev);
5419         const struct soc_device_attribute *soc;
5420         const struct dsi_module_id_data *d;
5421         u32 rev;
5422         int r, i;
5423         struct dsi_data *dsi;
5424         struct resource *dsi_mem;
5425         struct resource *res;
5426
5427         dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
5428         if (!dsi)
5429                 return -ENOMEM;
5430
5431         dsi->pdev = dsidev;
5432         dev_set_drvdata(&dsidev->dev, dsi);
5433
5434         spin_lock_init(&dsi->irq_lock);
5435         spin_lock_init(&dsi->errors_lock);
5436         dsi->errors = 0;
5437
5438 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5439         spin_lock_init(&dsi->irq_stats_lock);
5440         dsi->irq_stats.last_reset = jiffies;
5441 #endif
5442
5443         mutex_init(&dsi->lock);
5444         sema_init(&dsi->bus_lock, 1);
5445
5446         INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
5447                              dsi_framedone_timeout_work_callback);
5448
5449 #ifdef DSI_CATCH_MISSING_TE
5450         timer_setup(&dsi->te_timer, dsi_te_timeout, 0);
5451 #endif
5452
5453         dsi_mem = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto");
5454         dsi->proto_base = devm_ioremap_resource(&dsidev->dev, dsi_mem);
5455         if (IS_ERR(dsi->proto_base))
5456                 return PTR_ERR(dsi->proto_base);
5457
5458         res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy");
5459         dsi->phy_base = devm_ioremap_resource(&dsidev->dev, res);
5460         if (IS_ERR(dsi->phy_base))
5461                 return PTR_ERR(dsi->phy_base);
5462
5463         res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll");
5464         dsi->pll_base = devm_ioremap_resource(&dsidev->dev, res);
5465         if (IS_ERR(dsi->pll_base))
5466                 return PTR_ERR(dsi->pll_base);
5467
5468         dsi->irq = platform_get_irq(dsi->pdev, 0);
5469         if (dsi->irq < 0) {
5470                 DSSERR("platform_get_irq failed\n");
5471                 return -ENODEV;
5472         }
5473
5474         r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
5475                              IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
5476         if (r < 0) {
5477                 DSSERR("request_irq failed\n");
5478                 return r;
5479         }
5480
5481         soc = soc_device_match(dsi_soc_devices);
5482         if (soc)
5483                 dsi->data = soc->data;
5484         else
5485                 dsi->data = of_match_node(dsi_of_match, dev->of_node)->data;
5486
5487         d = dsi->data->modules;
5488         while (d->address != 0 && d->address != dsi_mem->start)
5489                 d++;
5490
5491         if (d->address == 0) {
5492                 DSSERR("unsupported DSI module\n");
5493                 return -ENODEV;
5494         }
5495
5496         dsi->module_id = d->id;
5497
5498         if (dsi->data->model == DSI_MODEL_OMAP4 ||
5499             dsi->data->model == DSI_MODEL_OMAP5) {
5500                 struct device_node *np;
5501
5502                 /*
5503                  * The OMAP4/5 display DT bindings don't reference the padconf
5504                  * syscon. Our only option to retrieve it is to find it by name.
5505                  */
5506                 np = of_find_node_by_name(NULL,
5507                         dsi->data->model == DSI_MODEL_OMAP4 ?
5508                         "omap4_padconf_global" : "omap5_padconf_global");
5509                 if (!np)
5510                         return -ENODEV;
5511
5512                 dsi->syscon = syscon_node_to_regmap(np);
5513                 of_node_put(np);
5514         }
5515
5516         /* DSI VCs initialization */
5517         for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5518                 dsi->vc[i].source = DSI_VC_SOURCE_L4;
5519                 dsi->vc[i].dssdev = NULL;
5520                 dsi->vc[i].vc_id = 0;
5521         }
5522
5523         r = dsi_get_clocks(dsidev);
5524         if (r)
5525                 return r;
5526
5527         dsi_init_pll_data(dsidev);
5528
5529         pm_runtime_enable(&dsidev->dev);
5530
5531         r = dsi_runtime_get(dsidev);
5532         if (r)
5533                 goto err_runtime_get;
5534
5535         rev = dsi_read_reg(dsidev, DSI_REVISION);
5536         dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
5537                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5538
5539         /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5540          * of data to 3 by default */
5541         if (dsi->data->quirks & DSI_QUIRK_GNQ)
5542                 /* NB_DATA_LANES */
5543                 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
5544         else
5545                 dsi->num_lanes_supported = 3;
5546
5547         dsi->line_buffer_size = dsi_get_line_buf_size(dsidev);
5548
5549         dsi_init_output(dsidev);
5550
5551         r = dsi_probe_of(dsidev);
5552         if (r) {
5553                 DSSERR("Invalid DSI DT data\n");
5554                 goto err_probe_of;
5555         }
5556
5557         r = of_platform_populate(dsidev->dev.of_node, NULL, NULL, &dsidev->dev);
5558         if (r)
5559                 DSSERR("Failed to populate DSI child devices: %d\n", r);
5560
5561         dsi_runtime_put(dsidev);
5562
5563         if (dsi->module_id == 0)
5564                 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
5565         else if (dsi->module_id == 1)
5566                 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
5567
5568 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5569         if (dsi->module_id == 0)
5570                 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
5571         else if (dsi->module_id == 1)
5572                 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
5573 #endif
5574
5575         return 0;
5576
5577 err_probe_of:
5578         dsi_uninit_output(dsidev);
5579         dsi_runtime_put(dsidev);
5580
5581 err_runtime_get:
5582         pm_runtime_disable(&dsidev->dev);
5583         return r;
5584 }
5585
5586 static void dsi_unbind(struct device *dev, struct device *master, void *data)
5587 {
5588         struct platform_device *dsidev = to_platform_device(dev);
5589         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5590
5591         of_platform_depopulate(&dsidev->dev);
5592
5593         WARN_ON(dsi->scp_clk_refcount > 0);
5594
5595         dss_pll_unregister(&dsi->pll);
5596
5597         dsi_uninit_output(dsidev);
5598
5599         pm_runtime_disable(&dsidev->dev);
5600
5601         if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) {
5602                 regulator_disable(dsi->vdds_dsi_reg);
5603                 dsi->vdds_dsi_enabled = false;
5604         }
5605 }
5606
5607 static const struct component_ops dsi_component_ops = {
5608         .bind   = dsi_bind,
5609         .unbind = dsi_unbind,
5610 };
5611
5612 static int dsi_probe(struct platform_device *pdev)
5613 {
5614         return component_add(&pdev->dev, &dsi_component_ops);
5615 }
5616
5617 static int dsi_remove(struct platform_device *pdev)
5618 {
5619         component_del(&pdev->dev, &dsi_component_ops);
5620         return 0;
5621 }
5622
5623 static int dsi_runtime_suspend(struct device *dev)
5624 {
5625         struct platform_device *pdev = to_platform_device(dev);
5626         struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5627
5628         dsi->is_enabled = false;
5629         /* ensure the irq handler sees the is_enabled value */
5630         smp_wmb();
5631         /* wait for current handler to finish before turning the DSI off */
5632         synchronize_irq(dsi->irq);
5633
5634         dispc_runtime_put();
5635
5636         return 0;
5637 }
5638
5639 static int dsi_runtime_resume(struct device *dev)
5640 {
5641         struct platform_device *pdev = to_platform_device(dev);
5642         struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5643         int r;
5644
5645         r = dispc_runtime_get();
5646         if (r)
5647                 return r;
5648
5649         dsi->is_enabled = true;
5650         /* ensure the irq handler sees the is_enabled value */
5651         smp_wmb();
5652
5653         return 0;
5654 }
5655
5656 static const struct dev_pm_ops dsi_pm_ops = {
5657         .runtime_suspend = dsi_runtime_suspend,
5658         .runtime_resume = dsi_runtime_resume,
5659 };
5660
5661 struct platform_driver omap_dsihw_driver = {
5662         .probe          = dsi_probe,
5663         .remove         = dsi_remove,
5664         .driver         = {
5665                 .name   = "omapdss_dsi",
5666                 .pm     = &dsi_pm_ops,
5667                 .of_match_table = dsi_of_match,
5668                 .suppress_bind_attrs = true,
5669         },
5670 };