drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

   1 /*
   2  * HDMI wrapper
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #define DSS_SUBSYS_NAME "HDMIWP"
  12
  13 #include <linux/kernel.h>
  14 #include <linux/err.h>
  15 #include <linux/io.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/seq_file.h>
  18
  19 #include "omapdss.h"
  20 #include "dss.h"
  21 #include "hdmi.h"
  22
  23 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s)
  24 {
  25 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r))
  26
  27         DUMPREG(HDMI_WP_REVISION);
  28         DUMPREG(HDMI_WP_SYSCONFIG);
  29         DUMPREG(HDMI_WP_IRQSTATUS_RAW);
  30         DUMPREG(HDMI_WP_IRQSTATUS);
  31         DUMPREG(HDMI_WP_IRQENABLE_SET);
  32         DUMPREG(HDMI_WP_IRQENABLE_CLR);
  33         DUMPREG(HDMI_WP_IRQWAKEEN);
  34         DUMPREG(HDMI_WP_PWR_CTRL);
  35         DUMPREG(HDMI_WP_DEBOUNCE);
  36         DUMPREG(HDMI_WP_VIDEO_CFG);
  37         DUMPREG(HDMI_WP_VIDEO_SIZE);
  38         DUMPREG(HDMI_WP_VIDEO_TIMING_H);
  39         DUMPREG(HDMI_WP_VIDEO_TIMING_V);
  40         DUMPREG(HDMI_WP_CLK);
  41         DUMPREG(HDMI_WP_AUDIO_CFG);
  42         DUMPREG(HDMI_WP_AUDIO_CFG2);
  43         DUMPREG(HDMI_WP_AUDIO_CTRL);
  44         DUMPREG(HDMI_WP_AUDIO_DATA);
  45 }
  46
  47 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp)
  48 {
  49         return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
  50 }
  51
  52 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus)
  53 {
  54         hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus);
  55         /* flush posted write */
  56         hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
  57 }
  58
  59 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask)
  60 {
  61         hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask);
  62 }
  63
  64 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask)
  65 {
  66         hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask);
  67 }
  68
  69 /* PHY_PWR_CMD */
  70 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val)
  71 {
  72         /* Return if already the state */
  73         if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val)
  74                 return 0;
  75
  76         /* Command for power control of HDMI PHY */
  77         REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6);
  78
  79         /* Status of the power control of HDMI PHY */
  80         if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val)
  81                         != val) {
  82                 DSSERR("Failed to set PHY power mode to %d\n", val);
  83                 return -ETIMEDOUT;
  84         }
  85
  86         return 0;
  87 }
  88
  89 /* PLL_PWR_CMD */
  90 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val)
  91 {
  92         /* Command for power control of HDMI PLL */
  93         REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2);
  94
  95         /* wait till PHY_PWR_STATUS is set */
  96         if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val)
  97                         != val) {
  98                 DSSERR("Failed to set PLL_PWR_STATUS\n");
  99                 return -ETIMEDOUT;
 100         }
 101
 102         return 0;
 103 }
 104
 105 int hdmi_wp_video_start(struct hdmi_wp_data *wp)
 106 {
 107         REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31);
 108
 109         return 0;
 110 }
 111
 112 void hdmi_wp_video_stop(struct hdmi_wp_data *wp)
 113 {
 114         int i;
 115
 116         hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_FRAME_DONE);
 117
 118         REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31);
 119
 120         for (i = 0; i < 50; ++i) {
 121                 u32 v;
 122
 123                 msleep(20);
 124
 125                 v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW);
 126                 if (v & HDMI_IRQ_VIDEO_FRAME_DONE)
 127                         return;
 128         }
 129
 130         DSSERR("no HDMI FRAMEDONE when disabling output\n");
 131 }
 132
 133 void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
 134                 struct hdmi_video_format *video_fmt)
 135 {
 136         u32 l = 0;
 137
 138         REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode,
 139                 10, 8);
 140
 141         l |= FLD_VAL(video_fmt->y_res, 31, 16);
 142         l |= FLD_VAL(video_fmt->x_res, 15, 0);
 143         hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l);
 144 }
 145
 146 void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
 147                                     struct videomode *vm)
 148 {
 149         u32 r;
 150         bool vsync_inv, hsync_inv;
 151         DSSDBG("Enter hdmi_wp_video_config_interface\n");
 152
 153         vsync_inv = !!(vm->flags & DISPLAY_FLAGS_VSYNC_LOW);
 154         hsync_inv = !!(vm->flags & DISPLAY_FLAGS_HSYNC_LOW);
 155
 156         r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);
 157         r = FLD_MOD(r, 1, 7, 7);        /* VSYNC_POL to dispc active high */
 158         r = FLD_MOD(r, 1, 6, 6);        /* HSYNC_POL to dispc active high */
 159         r = FLD_MOD(r, vsync_inv, 5, 5);        /* CORE_VSYNC_INV */
 160         r = FLD_MOD(r, hsync_inv, 4, 4);        /* CORE_HSYNC_INV */
 161         r = FLD_MOD(r, !!(vm->flags & DISPLAY_FLAGS_INTERLACED), 3, 3);
 162         r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
 163         hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);
 164 }
 165
 166 void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
 167                                  struct videomode *vm)
 168 {
 169         u32 timing_h = 0;
 170         u32 timing_v = 0;
 171         unsigned hsync_len_offset = 1;
 172
 173         DSSDBG("Enter hdmi_wp_video_config_timing\n");
 174
 175         /*
 176          * On OMAP4 and OMAP5 ES1 the HSW field is programmed as is. On OMAP5
 177          * ES2+ (including DRA7/AM5 SoCs) HSW field is programmed to hsync_len-1.
 178          * However, we don't support OMAP5 ES1 at all, so we can just check for
 179          * OMAP4 here.
 180          */
 181         if (wp->version == 4)
 182                 hsync_len_offset = 0;
 183
 184         timing_h |= FLD_VAL(vm->hback_porch, 31, 20);
 185         timing_h |= FLD_VAL(vm->hfront_porch, 19, 8);
 186         timing_h |= FLD_VAL(vm->hsync_len - hsync_len_offset, 7, 0);
 187         hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);
 188
 189         timing_v |= FLD_VAL(vm->vback_porch, 31, 20);
 190         timing_v |= FLD_VAL(vm->vfront_porch, 19, 8);
 191         timing_v |= FLD_VAL(vm->vsync_len, 7, 0);
 192         hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);
 193 }
 194
 195 void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
 196                 struct videomode *vm, struct hdmi_config *param)
 197 {
 198         DSSDBG("Enter hdmi_wp_video_init_format\n");
 199
 200         video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
 201         video_fmt->y_res = param->vm.vactive;
 202         video_fmt->x_res = param->vm.hactive;
 203
 204         vm->hback_porch = param->vm.hback_porch;
 205         vm->hfront_porch = param->vm.hfront_porch;
 206         vm->hsync_len = param->vm.hsync_len;
 207         vm->vback_porch = param->vm.vback_porch;
 208         vm->vfront_porch = param->vm.vfront_porch;
 209         vm->vsync_len = param->vm.vsync_len;
 210
 211         vm->flags = param->vm.flags;
 212
 213         if (param->vm.flags & DISPLAY_FLAGS_INTERLACED) {
 214                 video_fmt->y_res /= 2;
 215                 vm->vback_porch /= 2;
 216                 vm->vfront_porch /= 2;
 217                 vm->vsync_len /= 2;
 218         }
 219
 220         if (param->vm.flags & DISPLAY_FLAGS_DOUBLECLK) {
 221                 video_fmt->x_res *= 2;
 222                 vm->hfront_porch *= 2;
 223                 vm->hsync_len *= 2;
 224                 vm->hback_porch *= 2;
 225         }
 226 }
 227
 228 void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
 229                 struct hdmi_audio_format *aud_fmt)
 230 {
 231         u32 r;
 232
 233         DSSDBG("Enter hdmi_wp_audio_config_format\n");
 234
 235         r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG);
 236         if (wp->version == 4) {
 237                 r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
 238                 r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
 239         }
 240         r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
 241         r = FLD_MOD(r, aud_fmt->type, 4, 4);
 242         r = FLD_MOD(r, aud_fmt->justification, 3, 3);
 243         r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
 244         r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
 245         r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
 246         hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r);
 247 }
 248
 249 void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
 250                 struct hdmi_audio_dma *aud_dma)
 251 {
 252         u32 r;
 253
 254         DSSDBG("Enter hdmi_wp_audio_config_dma\n");
 255
 256         r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2);
 257         r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
 258         r = FLD_MOD(r, aud_dma->block_size, 7, 0);
 259         hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r);
 260
 261         r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL);
 262         r = FLD_MOD(r, aud_dma->mode, 9, 9);
 263         r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
 264         hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r);
 265 }
 266
 267 int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable)
 268 {
 269         REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31);
 270
 271         return 0;
 272 }
 273
 274 int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable)
 275 {
 276         REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30);
 277
 278         return 0;
 279 }
 280
 281 int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp,
 282                  unsigned int version)
 283 {
 284         struct resource *res;
 285
 286         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wp");
 287         wp->base = devm_ioremap_resource(&pdev->dev, res);
 288         if (IS_ERR(wp->base))
 289                 return PTR_ERR(wp->base);
 290
 291         wp->phys_base = res->start;
 292         wp->version = version;
 293
 294         return 0;
 295 }
 296
 297 phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp)
 298 {
 299         return wp->phys_base + HDMI_WP_AUDIO_DATA;
 300 }