drivers/gpu/drm/omapdrm/dss/sdi.c

   1 /*
   2  * Copyright (C) 2009 Nokia Corporation
   3  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #define DSS_SUBSYS_NAME "SDI"
  19
  20 #include <linux/kernel.h>
  21 #include <linux/delay.h>
  22 #include <linux/err.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/export.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/string.h>
  27 #include <linux/of.h>
  28
  29 #include "omapdss.h"
  30 #include "dss.h"
  31
  32 static struct {
  33         struct platform_device *pdev;
  34
  35         bool update_enabled;
  36         struct regulator *vdds_sdi_reg;
  37
  38         struct dss_lcd_mgr_config mgr_config;
  39         struct videomode vm;
  40         int datapairs;
  41
  42         struct omap_dss_device output;
  43
  44         bool port_initialized;
  45 } sdi;
  46
  47 struct sdi_clk_calc_ctx {
  48         unsigned long pck_min, pck_max;
  49
  50         unsigned long fck;
  51         struct dispc_clock_info dispc_cinfo;
  52 };
  53
  54 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
  55                 unsigned long pck, void *data)
  56 {
  57         struct sdi_clk_calc_ctx *ctx = data;
  58
  59         ctx->dispc_cinfo.lck_div = lckd;
  60         ctx->dispc_cinfo.pck_div = pckd;
  61         ctx->dispc_cinfo.lck = lck;
  62         ctx->dispc_cinfo.pck = pck;
  63
  64         return true;
  65 }
  66
  67 static bool dpi_calc_dss_cb(unsigned long fck, void *data)
  68 {
  69         struct sdi_clk_calc_ctx *ctx = data;
  70
  71         ctx->fck = fck;
  72
  73         return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
  74                         dpi_calc_dispc_cb, ctx);
  75 }
  76
  77 static int sdi_calc_clock_div(unsigned long pclk,
  78                 unsigned long *fck,
  79                 struct dispc_clock_info *dispc_cinfo)
  80 {
  81         int i;
  82         struct sdi_clk_calc_ctx ctx;
  83
  84         /*
  85          * DSS fclk gives us very few possibilities, so finding a good pixel
  86          * clock may not be possible. We try multiple times to find the clock,
  87          * each time widening the pixel clock range we look for, up to
  88          * +/- 1MHz.
  89          */
  90
  91         for (i = 0; i < 10; ++i) {
  92                 bool ok;
  93
  94                 memset(&ctx, 0, sizeof(ctx));
  95                 if (pclk > 1000 * i * i * i)
  96                         ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu);
  97                 else
  98                         ctx.pck_min = 0;
  99                 ctx.pck_max = pclk + 1000 * i * i * i;
 100
 101                 ok = dss_div_calc(pclk, ctx.pck_min, dpi_calc_dss_cb, &ctx);
 102                 if (ok) {
 103                         *fck = ctx.fck;
 104                         *dispc_cinfo = ctx.dispc_cinfo;
 105                         return 0;
 106                 }
 107         }
 108
 109         return -EINVAL;
 110 }
 111
 112 static void sdi_config_lcd_manager(struct omap_dss_device *dssdev)
 113 {
 114         enum omap_channel channel = dssdev->dispc_channel;
 115
 116         sdi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
 117
 118         sdi.mgr_config.stallmode = false;
 119         sdi.mgr_config.fifohandcheck = false;
 120
 121         sdi.mgr_config.video_port_width = 24;
 122         sdi.mgr_config.lcden_sig_polarity = 1;
 123
 124         dss_mgr_set_lcd_config(channel, &sdi.mgr_config);
 125 }
 126
 127 static int sdi_display_enable(struct omap_dss_device *dssdev)
 128 {
 129         struct omap_dss_device *out = &sdi.output;
 130         enum omap_channel channel = dssdev->dispc_channel;
 131         struct videomode *vm = &sdi.vm;
 132         unsigned long fck;
 133         struct dispc_clock_info dispc_cinfo;
 134         unsigned long pck;
 135         int r;
 136
 137         if (!out->dispc_channel_connected) {
 138                 DSSERR("failed to enable display: no output/manager\n");
 139                 return -ENODEV;
 140         }
 141
 142         r = regulator_enable(sdi.vdds_sdi_reg);
 143         if (r)
 144                 goto err_reg_enable;
 145
 146         r = dispc_runtime_get();
 147         if (r)
 148                 goto err_get_dispc;
 149
 150         /* 15.5.9.1.2 */
 151         vm->flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_SYNC_POSEDGE;
 152
 153         r = sdi_calc_clock_div(vm->pixelclock, &fck, &dispc_cinfo);
 154         if (r)
 155                 goto err_calc_clock_div;
 156
 157         sdi.mgr_config.clock_info = dispc_cinfo;
 158
 159         pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div;
 160
 161         if (pck != vm->pixelclock) {
 162                 DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n",
 163                         vm->pixelclock, pck);
 164
 165                 vm->pixelclock = pck;
 166         }
 167
 168
 169         dss_mgr_set_timings(channel, vm);
 170
 171         r = dss_set_fck_rate(fck);
 172         if (r)
 173                 goto err_set_dss_clock_div;
 174
 175         sdi_config_lcd_manager(dssdev);
 176
 177         /*
 178          * LCLK and PCLK divisors are located in shadow registers, and we
 179          * normally write them to DISPC registers when enabling the output.
 180          * However, SDI uses pck-free as source clock for its PLL, and pck-free
 181          * is affected by the divisors. And as we need the PLL before enabling
 182          * the output, we need to write the divisors early.
 183          *
 184          * It seems just writing to the DISPC register is enough, and we don't
 185          * need to care about the shadow register mechanism for pck-free. The
 186          * exact reason for this is unknown.
 187          */
 188         dispc_mgr_set_clock_div(channel, &sdi.mgr_config.clock_info);
 189
 190         dss_sdi_init(sdi.datapairs);
 191         r = dss_sdi_enable();
 192         if (r)
 193                 goto err_sdi_enable;
 194         mdelay(2);
 195
 196         r = dss_mgr_enable(channel);
 197         if (r)
 198                 goto err_mgr_enable;
 199
 200         return 0;
 201
 202 err_mgr_enable:
 203         dss_sdi_disable();
 204 err_sdi_enable:
 205 err_set_dss_clock_div:
 206 err_calc_clock_div:
 207         dispc_runtime_put();
 208 err_get_dispc:
 209         regulator_disable(sdi.vdds_sdi_reg);
 210 err_reg_enable:
 211         return r;
 212 }
 213
 214 static void sdi_display_disable(struct omap_dss_device *dssdev)
 215 {
 216         enum omap_channel channel = dssdev->dispc_channel;
 217
 218         dss_mgr_disable(channel);
 219
 220         dss_sdi_disable();
 221
 222         dispc_runtime_put();
 223
 224         regulator_disable(sdi.vdds_sdi_reg);
 225 }
 226
 227 static void sdi_set_timings(struct omap_dss_device *dssdev,
 228                             struct videomode *vm)
 229 {
 230         sdi.vm = *vm;
 231 }
 232
 233 static void sdi_get_timings(struct omap_dss_device *dssdev,
 234                             struct videomode *vm)
 235 {
 236         *vm = sdi.vm;
 237 }
 238
 239 static int sdi_check_timings(struct omap_dss_device *dssdev,
 240                              struct videomode *vm)
 241 {
 242         enum omap_channel channel = dssdev->dispc_channel;
 243
 244         if (!dispc_mgr_timings_ok(channel, vm))
 245                 return -EINVAL;
 246
 247         if (vm->pixelclock == 0)
 248                 return -EINVAL;
 249
 250         return 0;
 251 }
 252
 253 static int sdi_init_regulator(void)
 254 {
 255         struct regulator *vdds_sdi;
 256
 257         if (sdi.vdds_sdi_reg)
 258                 return 0;
 259
 260         vdds_sdi = devm_regulator_get(&sdi.pdev->dev, "vdds_sdi");
 261         if (IS_ERR(vdds_sdi)) {
 262                 if (PTR_ERR(vdds_sdi) != -EPROBE_DEFER)
 263                         DSSERR("can't get VDDS_SDI regulator\n");
 264                 return PTR_ERR(vdds_sdi);
 265         }
 266
 267         sdi.vdds_sdi_reg = vdds_sdi;
 268
 269         return 0;
 270 }
 271
 272 static int sdi_connect(struct omap_dss_device *dssdev,
 273                 struct omap_dss_device *dst)
 274 {
 275         enum omap_channel channel = dssdev->dispc_channel;
 276         int r;
 277
 278         r = sdi_init_regulator();
 279         if (r)
 280                 return r;
 281
 282         r = dss_mgr_connect(channel, dssdev);
 283         if (r)
 284                 return r;
 285
 286         r = omapdss_output_set_device(dssdev, dst);
 287         if (r) {
 288                 DSSERR("failed to connect output to new device: %s\n",
 289                                 dst->name);
 290                 dss_mgr_disconnect(channel, dssdev);
 291                 return r;
 292         }
 293
 294         return 0;
 295 }
 296
 297 static void sdi_disconnect(struct omap_dss_device *dssdev,
 298                 struct omap_dss_device *dst)
 299 {
 300         enum omap_channel channel = dssdev->dispc_channel;
 301
 302         WARN_ON(dst != dssdev->dst);
 303
 304         if (dst != dssdev->dst)
 305                 return;
 306
 307         omapdss_output_unset_device(dssdev);
 308
 309         dss_mgr_disconnect(channel, dssdev);
 310 }
 311
 312 static const struct omapdss_sdi_ops sdi_ops = {
 313         .connect = sdi_connect,
 314         .disconnect = sdi_disconnect,
 315
 316         .enable = sdi_display_enable,
 317         .disable = sdi_display_disable,
 318
 319         .check_timings = sdi_check_timings,
 320         .set_timings = sdi_set_timings,
 321         .get_timings = sdi_get_timings,
 322 };
 323
 324 static void sdi_init_output(struct platform_device *pdev)
 325 {
 326         struct omap_dss_device *out = &sdi.output;
 327
 328         out->dev = &pdev->dev;
 329         out->id = OMAP_DSS_OUTPUT_SDI;
 330         out->output_type = OMAP_DISPLAY_TYPE_SDI;
 331         out->name = "sdi.0";
 332         out->dispc_channel = OMAP_DSS_CHANNEL_LCD;
 333         /* We have SDI only on OMAP3, where it's on port 1 */
 334         out->port_num = 1;
 335         out->ops.sdi = &sdi_ops;
 336         out->owner = THIS_MODULE;
 337
 338         omapdss_register_output(out);
 339 }
 340
 341 static void sdi_uninit_output(struct platform_device *pdev)
 342 {
 343         struct omap_dss_device *out = &sdi.output;
 344
 345         omapdss_unregister_output(out);
 346 }
 347
 348 int sdi_init_port(struct platform_device *pdev, struct device_node *port)
 349 {
 350         struct device_node *ep;
 351         u32 datapairs;
 352         int r;
 353
 354         ep = of_get_next_child(port, NULL);
 355         if (!ep)
 356                 return 0;
 357
 358         r = of_property_read_u32(ep, "datapairs", &datapairs);
 359         if (r) {
 360                 DSSERR("failed to parse datapairs\n");
 361                 goto err_datapairs;
 362         }
 363
 364         sdi.datapairs = datapairs;
 365
 366         of_node_put(ep);
 367
 368         sdi.pdev = pdev;
 369
 370         sdi_init_output(pdev);
 371
 372         sdi.port_initialized = true;
 373
 374         return 0;
 375
 376 err_datapairs:
 377         of_node_put(ep);
 378
 379         return r;
 380 }
 381
 382 void sdi_uninit_port(struct device_node *port)
 383 {
 384         if (!sdi.port_initialized)
 385                 return;
 386
 387         sdi_uninit_output(sdi.pdev);
 388 }