drivers/gpu/drm/pl111/pl111_drm.h

   1 /*
   2  *
   3  * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
   4  *
   5  *
   6  * Parts of this file were based on sources as follows:
   7  *
   8  * Copyright (c) 2006-2008 Intel Corporation
   9  * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
  10  * Copyright (C) 2011 Texas Instruments
  11  *
  12  * This program is free software and is provided to you under the terms of the
  13  * GNU General Public License version 2 as published by the Free Software
  14  * Foundation, and any use by you of this program is subject to the terms of
  15  * such GNU licence.
  16  *
  17  */
  18
  19 #ifndef _PL111_DRM_H_
  20 #define _PL111_DRM_H_
  21
  22 #include <drm/drm_gem.h>
  23 #include <drm/drm_simple_kms_helper.h>
  24 #include <drm/drm_connector.h>
  25 #include <drm/drm_encoder.h>
  26 #include <drm/drm_panel.h>
  27 #include <drm/drm_bridge.h>
  28 #include <linux/clk-provider.h>
  29 #include <linux/interrupt.h>
  30
  31 #define CLCD_IRQ_NEXTBASE_UPDATE BIT(2)
  32
  33 struct drm_minor;
  34
  35 /**
  36  * struct pl111_variant_data - encodes IP differences
  37  * @name: the name of this variant
  38  * @is_pl110: this is the early PL110 variant
  39  * @formats: array of supported pixel formats on this variant
  40  * @nformats: the length of the array of supported pixel formats
  41  */
  42 struct pl111_variant_data {
  43         const char *name;
  44         bool is_pl110;
  45         const u32 *formats;
  46         unsigned int nformats;
  47 };
  48
  49 struct pl111_drm_dev_private {
  50         struct drm_device *drm;
  51
  52         struct drm_connector *connector;
  53         struct drm_panel *panel;
  54         struct drm_bridge *bridge;
  55         struct drm_simple_display_pipe pipe;
  56
  57         void *regs;
  58         u32 ienb;
  59         u32 ctrl;
  60         /* The pixel clock (a reference to our clock divider off of CLCDCLK). */
  61         struct clk *clk;
  62         /* pl111's internal clock divider. */
  63         struct clk_hw clk_div;
  64         /* Lock to sync access to CLCD_TIM2 between the common clock
  65          * subsystem and pl111_display_enable().
  66          */
  67         spinlock_t tim2_lock;
  68         const struct pl111_variant_data *variant;
  69         void (*variant_display_enable) (struct drm_device *drm, u32 format);
  70         void (*variant_display_disable) (struct drm_device *drm);
  71 };
  72
  73 int pl111_display_init(struct drm_device *dev);
  74 int pl111_enable_vblank(struct drm_device *drm, unsigned int crtc);
  75 void pl111_disable_vblank(struct drm_device *drm, unsigned int crtc);
  76 irqreturn_t pl111_irq(int irq, void *data);
  77 int pl111_debugfs_init(struct drm_minor *minor);
  78
  79 #endif /* _PL111_DRM_H_ */