drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c

   1 /*
   2  * rcar_du_lvdsenc.c  --  R-Car Display Unit LVDS Encoder
   3  *
   4  * Copyright (C) 2013-2014 Renesas Electronics Corporation
   5  *
   6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/io.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/slab.h>
  19
  20 #include "rcar_du_drv.h"
  21 #include "rcar_du_encoder.h"
  22 #include "rcar_du_lvdsenc.h"
  23 #include "rcar_lvds_regs.h"
  24
  25 struct rcar_du_lvdsenc {
  26         struct rcar_du_device *dev;
  27
  28         unsigned int index;
  29         void __iomem *mmio;
  30         struct clk *clock;
  31         bool enabled;
  32
  33         enum rcar_lvds_input input;
  34         enum rcar_lvds_mode mode;
  35 };
  36
  37 static void rcar_lvds_write(struct rcar_du_lvdsenc *lvds, u32 reg, u32 data)
  38 {
  39         iowrite32(data, lvds->mmio + reg);
  40 }
  41
  42 static void rcar_du_lvdsenc_start_gen2(struct rcar_du_lvdsenc *lvds,
  43                                        struct rcar_du_crtc *rcrtc)
  44 {
  45         const struct drm_display_mode *mode = &rcrtc->crtc.mode;
  46         unsigned int freq = mode->clock;
  47         u32 lvdcr0;
  48         u32 pllcr;
  49
  50         /* PLL clock configuration */
  51         if (freq < 39000)
  52                 pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
  53         else if (freq < 61000)
  54                 pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
  55         else if (freq < 121000)
  56                 pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
  57         else
  58                 pllcr = LVDPLLCR_PLLDLYCNT_150M;
  59
  60         rcar_lvds_write(lvds, LVDPLLCR, pllcr);
  61
  62         /*
  63          * Select the input, hardcode mode 0, enable LVDS operation and turn
  64          * bias circuitry on.
  65          */
  66         lvdcr0 = (lvds->mode << LVDCR0_LVMD_SHIFT) | LVDCR0_BEN | LVDCR0_LVEN;
  67         if (rcrtc->index == 2)
  68                 lvdcr0 |= LVDCR0_DUSEL;
  69         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
  70
  71         /* Turn all the channels on. */
  72         rcar_lvds_write(lvds, LVDCR1,
  73                         LVDCR1_CHSTBY_GEN2(3) | LVDCR1_CHSTBY_GEN2(2) |
  74                         LVDCR1_CHSTBY_GEN2(1) | LVDCR1_CHSTBY_GEN2(0) |
  75                         LVDCR1_CLKSTBY_GEN2);
  76
  77         /*
  78          * Turn the PLL on, wait for the startup delay, and turn the output
  79          * on.
  80          */
  81         lvdcr0 |= LVDCR0_PLLON;
  82         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
  83
  84         usleep_range(100, 150);
  85
  86         lvdcr0 |= LVDCR0_LVRES;
  87         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
  88 }
  89
  90 static void rcar_du_lvdsenc_start_gen3(struct rcar_du_lvdsenc *lvds,
  91                                        struct rcar_du_crtc *rcrtc)
  92 {
  93         const struct drm_display_mode *mode = &rcrtc->crtc.mode;
  94         unsigned int freq = mode->clock;
  95         u32 lvdcr0;
  96         u32 pllcr;
  97
  98         /* PLL clock configuration */
  99         if (freq < 42000)
 100                 pllcr = LVDPLLCR_PLLDIVCNT_42M;
 101         else if (freq < 85000)
 102                 pllcr = LVDPLLCR_PLLDIVCNT_85M;
 103         else if (freq < 128000)
 104                 pllcr = LVDPLLCR_PLLDIVCNT_128M;
 105         else
 106                 pllcr = LVDPLLCR_PLLDIVCNT_148M;
 107
 108         rcar_lvds_write(lvds, LVDPLLCR, pllcr);
 109
 110         /* Turn all the channels on. */
 111         rcar_lvds_write(lvds, LVDCR1,
 112                         LVDCR1_CHSTBY_GEN3(3) | LVDCR1_CHSTBY_GEN3(2) |
 113                         LVDCR1_CHSTBY_GEN3(1) | LVDCR1_CHSTBY_GEN3(0) |
 114                         LVDCR1_CLKSTBY_GEN3);
 115
 116         /*
 117          * Turn the PLL on, set it to LVDS normal mode, wait for the startup
 118          * delay and turn the output on.
 119          */
 120         lvdcr0 = (lvds->mode << LVDCR0_LVMD_SHIFT) | LVDCR0_PLLON;
 121         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 122
 123         lvdcr0 |= LVDCR0_PWD;
 124         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 125
 126         usleep_range(100, 150);
 127
 128         lvdcr0 |= LVDCR0_LVRES;
 129         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 130 }
 131
 132 static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,
 133                                  struct rcar_du_crtc *rcrtc)
 134 {
 135         u32 lvdhcr;
 136         int ret;
 137
 138         if (lvds->enabled)
 139                 return 0;
 140
 141         ret = clk_prepare_enable(lvds->clock);
 142         if (ret < 0)
 143                 return ret;
 144
 145         /*
 146          * Hardcode the channels and control signals routing for now.
 147          *
 148          * HSYNC -> CTRL0
 149          * VSYNC -> CTRL1
 150          * DISP  -> CTRL2
 151          * 0     -> CTRL3
 152          */
 153         rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
 154                         LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC |
 155                         LVDCTRCR_CTR0SEL_HSYNC);
 156
 157         if (rcar_du_needs(lvds->dev, RCAR_DU_QUIRK_LVDS_LANES))
 158                 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3)
 159                        | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1);
 160         else
 161                 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 1)
 162                        | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 3);
 163
 164         rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
 165
 166         /* Perform generation-specific initialization. */
 167         if (lvds->dev->info->gen < 3)
 168                 rcar_du_lvdsenc_start_gen2(lvds, rcrtc);
 169         else
 170                 rcar_du_lvdsenc_start_gen3(lvds, rcrtc);
 171
 172         lvds->enabled = true;
 173
 174         return 0;
 175 }
 176
 177 static void rcar_du_lvdsenc_stop(struct rcar_du_lvdsenc *lvds)
 178 {
 179         if (!lvds->enabled)
 180                 return;
 181
 182         rcar_lvds_write(lvds, LVDCR0, 0);
 183         rcar_lvds_write(lvds, LVDCR1, 0);
 184
 185         clk_disable_unprepare(lvds->clock);
 186
 187         lvds->enabled = false;
 188 }
 189
 190 int rcar_du_lvdsenc_enable(struct rcar_du_lvdsenc *lvds, struct drm_crtc *crtc,
 191                            bool enable)
 192 {
 193         if (!enable) {
 194                 rcar_du_lvdsenc_stop(lvds);
 195                 return 0;
 196         } else if (crtc) {
 197                 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 198                 return rcar_du_lvdsenc_start(lvds, rcrtc);
 199         } else
 200                 return -EINVAL;
 201 }
 202
 203 void rcar_du_lvdsenc_atomic_check(struct rcar_du_lvdsenc *lvds,
 204                                   struct drm_display_mode *mode)
 205 {
 206         struct rcar_du_device *rcdu = lvds->dev;
 207
 208         /*
 209          * The internal LVDS encoder has a restricted clock frequency operating
 210          * range (30MHz to 150MHz on Gen2, 25.175MHz to 148.5MHz on Gen3). Clamp
 211          * the clock accordingly.
 212          */
 213         if (rcdu->info->gen < 3)
 214                 mode->clock = clamp(mode->clock, 30000, 150000);
 215         else
 216                 mode->clock = clamp(mode->clock, 25175, 148500);
 217 }
 218
 219 void rcar_du_lvdsenc_set_mode(struct rcar_du_lvdsenc *lvds,
 220                               enum rcar_lvds_mode mode)
 221 {
 222         lvds->mode = mode;
 223 }
 224
 225 static int rcar_du_lvdsenc_get_resources(struct rcar_du_lvdsenc *lvds,
 226                                          struct platform_device *pdev)
 227 {
 228         struct resource *mem;
 229         char name[7];
 230
 231         sprintf(name, "lvds.%u", lvds->index);
 232
 233         mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
 234         lvds->mmio = devm_ioremap_resource(&pdev->dev, mem);
 235         if (IS_ERR(lvds->mmio))
 236                 return PTR_ERR(lvds->mmio);
 237
 238         lvds->clock = devm_clk_get(&pdev->dev, name);
 239         if (IS_ERR(lvds->clock)) {
 240                 dev_err(&pdev->dev, "failed to get clock for %s\n", name);
 241                 return PTR_ERR(lvds->clock);
 242         }
 243
 244         return 0;
 245 }
 246
 247 int rcar_du_lvdsenc_init(struct rcar_du_device *rcdu)
 248 {
 249         struct platform_device *pdev = to_platform_device(rcdu->dev);
 250         struct rcar_du_lvdsenc *lvds;
 251         unsigned int i;
 252         int ret;
 253
 254         for (i = 0; i < rcdu->info->num_lvds; ++i) {
 255                 lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
 256                 if (lvds == NULL)
 257                         return -ENOMEM;
 258
 259                 lvds->dev = rcdu;
 260                 lvds->index = i;
 261                 lvds->input = i ? RCAR_LVDS_INPUT_DU1 : RCAR_LVDS_INPUT_DU0;
 262                 lvds->enabled = false;
 263
 264                 ret = rcar_du_lvdsenc_get_resources(lvds, pdev);
 265                 if (ret < 0)
 266                         return ret;
 267
 268                 rcdu->lvds[i] = lvds;
 269         }
 270
 271         return 0;
 272 }