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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[cris-mirror.git] / drivers / mtd / spi-nor / cadence-quadspi.c
blob4b8e9183489aa444edfa193d20fd004581470544
1 /*
2 * Driver for Cadence QSPI Controller
3 *
4 * Copyright Altera Corporation (C) 2012-2014. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18 #include <linux/clk.h>
19 #include <linux/completion.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22 #include <linux/errno.h>
23 #include <linux/interrupt.h>
24 #include <linux/io.h>
25 #include <linux/jiffies.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/partitions.h>
30 #include <linux/mtd/spi-nor.h>
31 #include <linux/of_device.h>
32 #include <linux/of.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/sched.h>
36 #include <linux/spi/spi.h>
37 #include <linux/timer.h>
38
39 #define CQSPI_NAME "cadence-qspi"
40 #define CQSPI_MAX_CHIPSELECT 16
41
42 /* Quirks */
43 #define CQSPI_NEEDS_WR_DELAY BIT(0)
44
45 struct cqspi_st;
46
47 struct cqspi_flash_pdata {
48 struct spi_nor nor;
49 struct cqspi_st *cqspi;
50 u32 clk_rate;
51 u32 read_delay;
52 u32 tshsl_ns;
53 u32 tsd2d_ns;
54 u32 tchsh_ns;
55 u32 tslch_ns;
56 u8 inst_width;
57 u8 addr_width;
58 u8 data_width;
59 u8 cs;
60 bool registered;
61 bool use_direct_mode;
62 };
63
64 struct cqspi_st {
65 struct platform_device *pdev;
66
67 struct clk *clk;
68 unsigned int sclk;
69
70 void __iomem *iobase;
71 void __iomem *ahb_base;
72 resource_size_t ahb_size;
73 struct completion transfer_complete;
74 struct mutex bus_mutex;
75
76 int current_cs;
77 int current_page_size;
78 int current_erase_size;
79 int current_addr_width;
80 unsigned long master_ref_clk_hz;
81 bool is_decoded_cs;
82 u32 fifo_depth;
83 u32 fifo_width;
84 bool rclk_en;
85 u32 trigger_address;
86 u32 wr_delay;
87 struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
88 };
89
90 /* Operation timeout value */
91 #define CQSPI_TIMEOUT_MS 500
92 #define CQSPI_READ_TIMEOUT_MS 10
93
94 /* Instruction type */
95 #define CQSPI_INST_TYPE_SINGLE 0
96 #define CQSPI_INST_TYPE_DUAL 1
97 #define CQSPI_INST_TYPE_QUAD 2
98
99 #define CQSPI_DUMMY_CLKS_PER_BYTE 8
100 #define CQSPI_DUMMY_BYTES_MAX 4
101 #define CQSPI_DUMMY_CLKS_MAX 31
102
103 #define CQSPI_STIG_DATA_LEN_MAX 8
104
105 /* Register map */
106 #define CQSPI_REG_CONFIG 0x00
107 #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0)
108 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7)
109 #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9)
110 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
111 #define CQSPI_REG_CONFIG_DMA_MASK BIT(15)
112 #define CQSPI_REG_CONFIG_BAUD_LSB 19
113 #define CQSPI_REG_CONFIG_IDLE_LSB 31
114 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
115 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
116
117 #define CQSPI_REG_RD_INSTR 0x04
118 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
119 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
120 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
121 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
122 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
123 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
124 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
125 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
126 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
127 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
128
129 #define CQSPI_REG_WR_INSTR 0x08
130 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
131 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12
132 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
133
134 #define CQSPI_REG_DELAY 0x0C
135 #define CQSPI_REG_DELAY_TSLCH_LSB 0
136 #define CQSPI_REG_DELAY_TCHSH_LSB 8
137 #define CQSPI_REG_DELAY_TSD2D_LSB 16
138 #define CQSPI_REG_DELAY_TSHSL_LSB 24
139 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
140 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
141 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
142 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
143
144 #define CQSPI_REG_READCAPTURE 0x10
145 #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0
146 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1
147 #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF
148
149 #define CQSPI_REG_SIZE 0x14
150 #define CQSPI_REG_SIZE_ADDRESS_LSB 0
151 #define CQSPI_REG_SIZE_PAGE_LSB 4
152 #define CQSPI_REG_SIZE_BLOCK_LSB 16
153 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
154 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
155 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
156
157 #define CQSPI_REG_SRAMPARTITION 0x18
158 #define CQSPI_REG_INDIRECTTRIGGER 0x1C
159
160 #define CQSPI_REG_DMA 0x20
161 #define CQSPI_REG_DMA_SINGLE_LSB 0
162 #define CQSPI_REG_DMA_BURST_LSB 8
163 #define CQSPI_REG_DMA_SINGLE_MASK 0xFF
164 #define CQSPI_REG_DMA_BURST_MASK 0xFF
165
166 #define CQSPI_REG_REMAP 0x24
167 #define CQSPI_REG_MODE_BIT 0x28
168
169 #define CQSPI_REG_SDRAMLEVEL 0x2C
170 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
171 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
172 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
173 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
174
175 #define CQSPI_REG_IRQSTATUS 0x40
176 #define CQSPI_REG_IRQMASK 0x44
177
178 #define CQSPI_REG_INDIRECTRD 0x60
179 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0)
180 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1)
181 #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5)
182
183 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
184 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
185 #define CQSPI_REG_INDIRECTRDBYTES 0x6C
186
187 #define CQSPI_REG_CMDCTRL 0x90
188 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0)
189 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1)
190 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
191 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
192 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
193 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
194 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
195 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
196 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
197 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
198 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
199 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
200
201 #define CQSPI_REG_INDIRECTWR 0x70
202 #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0)
203 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1)
204 #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5)
205
206 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
207 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
208 #define CQSPI_REG_INDIRECTWRBYTES 0x7C
209
210 #define CQSPI_REG_CMDADDRESS 0x94
211 #define CQSPI_REG_CMDREADDATALOWER 0xA0
212 #define CQSPI_REG_CMDREADDATAUPPER 0xA4
213 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
214 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
215
216 /* Interrupt status bits */
217 #define CQSPI_REG_IRQ_MODE_ERR BIT(0)
218 #define CQSPI_REG_IRQ_UNDERFLOW BIT(1)
219 #define CQSPI_REG_IRQ_IND_COMP BIT(2)
220 #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3)
221 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4)
222 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5)
223 #define CQSPI_REG_IRQ_WATERMARK BIT(6)
224 #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12)
225
226 #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \
227 CQSPI_REG_IRQ_IND_SRAM_FULL | \
228 CQSPI_REG_IRQ_IND_COMP)
229
230 #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \
231 CQSPI_REG_IRQ_WATERMARK | \
232 CQSPI_REG_IRQ_UNDERFLOW)
233
234 #define CQSPI_IRQ_STATUS_MASK 0x1FFFF
235
236 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clear)
237 {
238 unsigned long end = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
239 u32 val;
240
241 while (1) {
242 val = readl(reg);
243 if (clear)
244 val = ~val;
245 val &= mask;
246
247 if (val == mask)
248 return 0;
249
250 if (time_after(jiffies, end))
251 return -ETIMEDOUT;
252 }
253 }
254
255 static bool cqspi_is_idle(struct cqspi_st *cqspi)
256 {
257 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
258
259 return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
260 }
261
262 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
263 {
264 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
265
266 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
267 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
268 }
269
270 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
271 {
272 struct cqspi_st *cqspi = dev;
273 unsigned int irq_status;
274
275 /* Read interrupt status */
276 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
277
278 /* Clear interrupt */
279 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
280
281 irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
282
283 if (irq_status)
284 complete(&cqspi->transfer_complete);
285
286 return IRQ_HANDLED;
287 }
288
289 static unsigned int cqspi_calc_rdreg(struct spi_nor *nor, const u8 opcode)
290 {
291 struct cqspi_flash_pdata *f_pdata = nor->priv;
292 u32 rdreg = 0;
293
294 rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
295 rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
296 rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
297
298 return rdreg;
299 }
300
301 static int cqspi_wait_idle(struct cqspi_st *cqspi)
302 {
303 const unsigned int poll_idle_retry = 3;
304 unsigned int count = 0;
305 unsigned long timeout;
306
307 timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
308 while (1) {
309 /*
310 * Read few times in succession to ensure the controller
311 * is indeed idle, that is, the bit does not transition
312 * low again.
313 */
314 if (cqspi_is_idle(cqspi))
315 count++;
316 else
317 count = 0;
318
319 if (count >= poll_idle_retry)
320 return 0;
321
322 if (time_after(jiffies, timeout)) {
323 /* Timeout, in busy mode. */
324 dev_err(&cqspi->pdev->dev,
325 "QSPI is still busy after %dms timeout.\n",
326 CQSPI_TIMEOUT_MS);
327 return -ETIMEDOUT;
328 }
329
330 cpu_relax();
331 }
332 }
333
334 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
335 {
336 void __iomem *reg_base = cqspi->iobase;
337 int ret;
338
339 /* Write the CMDCTRL without start execution. */
340 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
341 /* Start execute */
342 reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
343 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
344
345 /* Polling for completion. */
346 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
347 CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
348 if (ret) {
349 dev_err(&cqspi->pdev->dev,
350 "Flash command execution timed out.\n");
351 return ret;
352 }
353
354 /* Polling QSPI idle status. */
355 return cqspi_wait_idle(cqspi);
356 }
357
358 static int cqspi_command_read(struct spi_nor *nor,
359 const u8 *txbuf, const unsigned n_tx,
360 u8 *rxbuf, const unsigned n_rx)
361 {
362 struct cqspi_flash_pdata *f_pdata = nor->priv;
363 struct cqspi_st *cqspi = f_pdata->cqspi;
364 void __iomem *reg_base = cqspi->iobase;
365 unsigned int rdreg;
366 unsigned int reg;
367 unsigned int read_len;
368 int status;
369
370 if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
371 dev_err(nor->dev, "Invalid input argument, len %d rxbuf 0x%p\n",
372 n_rx, rxbuf);
373 return -EINVAL;
374 }
375
376 reg = txbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
377
378 rdreg = cqspi_calc_rdreg(nor, txbuf[0]);
379 writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
380
381 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
382
383 /* 0 means 1 byte. */
384 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
385 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
386 status = cqspi_exec_flash_cmd(cqspi, reg);
387 if (status)
388 return status;
389
390 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
391
392 /* Put the read value into rx_buf */
393 read_len = (n_rx > 4) ? 4 : n_rx;
394 memcpy(rxbuf, &reg, read_len);
395 rxbuf += read_len;
396
397 if (n_rx > 4) {
398 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
399
400 read_len = n_rx - read_len;
401 memcpy(rxbuf, &reg, read_len);
402 }
403
404 return 0;
405 }
406
407 static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
408 const u8 *txbuf, const unsigned n_tx)
409 {
410 struct cqspi_flash_pdata *f_pdata = nor->priv;
411 struct cqspi_st *cqspi = f_pdata->cqspi;
412 void __iomem *reg_base = cqspi->iobase;
413 unsigned int reg;
414 unsigned int data;
415 int ret;
416
417 if (n_tx > 4 || (n_tx && !txbuf)) {
418 dev_err(nor->dev,
419 "Invalid input argument, cmdlen %d txbuf 0x%p\n",
420 n_tx, txbuf);
421 return -EINVAL;
422 }
423
424 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
425 if (n_tx) {
426 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
427 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
428 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
429 data = 0;
430 memcpy(&data, txbuf, n_tx);
431 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
432 }
433
434 ret = cqspi_exec_flash_cmd(cqspi, reg);
435 return ret;
436 }
437
438 static int cqspi_command_write_addr(struct spi_nor *nor,
439 const u8 opcode, const unsigned int addr)
440 {
441 struct cqspi_flash_pdata *f_pdata = nor->priv;
442 struct cqspi_st *cqspi = f_pdata->cqspi;
443 void __iomem *reg_base = cqspi->iobase;
444 unsigned int reg;
445
446 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
447 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
448 reg |= ((nor->addr_width - 1) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
449 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
450
451 writel(addr, reg_base + CQSPI_REG_CMDADDRESS);
452
453 return cqspi_exec_flash_cmd(cqspi, reg);
454 }
455
456 static int cqspi_read_setup(struct spi_nor *nor)
457 {
458 struct cqspi_flash_pdata *f_pdata = nor->priv;
459 struct cqspi_st *cqspi = f_pdata->cqspi;
460 void __iomem *reg_base = cqspi->iobase;
461 unsigned int dummy_clk = 0;
462 unsigned int reg;
463
464 reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
465 reg |= cqspi_calc_rdreg(nor, nor->read_opcode);
466
467 /* Setup dummy clock cycles */
468 dummy_clk = nor->read_dummy;
469 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
470 dummy_clk = CQSPI_DUMMY_CLKS_MAX;
471
472 if (dummy_clk / 8) {
473 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
474 /* Set mode bits high to ensure chip doesn't enter XIP */
475 writel(0xFF, reg_base + CQSPI_REG_MODE_BIT);
476
477 /* Need to subtract the mode byte (8 clocks). */
478 if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD)
479 dummy_clk -= 8;
480
481 if (dummy_clk)
482 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
483 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
484 }
485
486 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
487
488 /* Set address width */
489 reg = readl(reg_base + CQSPI_REG_SIZE);
490 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
491 reg |= (nor->addr_width - 1);
492 writel(reg, reg_base + CQSPI_REG_SIZE);
493 return 0;
494 }
495
496 static int cqspi_indirect_read_execute(struct spi_nor *nor, u8 *rxbuf,
497 loff_t from_addr, const size_t n_rx)
498 {
499 struct cqspi_flash_pdata *f_pdata = nor->priv;
500 struct cqspi_st *cqspi = f_pdata->cqspi;
501 void __iomem *reg_base = cqspi->iobase;
502 void __iomem *ahb_base = cqspi->ahb_base;
503 unsigned int remaining = n_rx;
504 unsigned int bytes_to_read = 0;
505 int ret = 0;
506
507 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
508 writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
509
510 /* Clear all interrupts. */
511 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
512
513 writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
514
515 reinit_completion(&cqspi->transfer_complete);
516 writel(CQSPI_REG_INDIRECTRD_START_MASK,
517 reg_base + CQSPI_REG_INDIRECTRD);
518
519 while (remaining > 0) {
520 ret = wait_for_completion_timeout(&cqspi->transfer_complete,
521 msecs_to_jiffies
522 (CQSPI_READ_TIMEOUT_MS));
523
524 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
525
526 if (!ret && bytes_to_read == 0) {
527 dev_err(nor->dev, "Indirect read timeout, no bytes\n");
528 ret = -ETIMEDOUT;
529 goto failrd;
530 }
531
532 while (bytes_to_read != 0) {
533 bytes_to_read *= cqspi->fifo_width;
534 bytes_to_read = bytes_to_read > remaining ?
535 remaining : bytes_to_read;
536 ioread32_rep(ahb_base, rxbuf,
537 DIV_ROUND_UP(bytes_to_read, 4));
538 rxbuf += bytes_to_read;
539 remaining -= bytes_to_read;
540 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
541 }
542
543 if (remaining > 0)
544 reinit_completion(&cqspi->transfer_complete);
545 }
546
547 /* Check indirect done status */
548 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
549 CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
550 if (ret) {
551 dev_err(nor->dev,
552 "Indirect read completion error (%i)\n", ret);
553 goto failrd;
554 }
555
556 /* Disable interrupt */
557 writel(0, reg_base + CQSPI_REG_IRQMASK);
558
559 /* Clear indirect completion status */
560 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
561
562 return 0;
563
564 failrd:
565 /* Disable interrupt */
566 writel(0, reg_base + CQSPI_REG_IRQMASK);
567
568 /* Cancel the indirect read */
569 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
570 reg_base + CQSPI_REG_INDIRECTRD);
571 return ret;
572 }
573
574 static int cqspi_write_setup(struct spi_nor *nor)
575 {
576 unsigned int reg;
577 struct cqspi_flash_pdata *f_pdata = nor->priv;
578 struct cqspi_st *cqspi = f_pdata->cqspi;
579 void __iomem *reg_base = cqspi->iobase;
580
581 /* Set opcode. */
582 reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
583 writel(reg, reg_base + CQSPI_REG_WR_INSTR);
584 reg = cqspi_calc_rdreg(nor, nor->program_opcode);
585 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
586
587 reg = readl(reg_base + CQSPI_REG_SIZE);
588 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
589 reg |= (nor->addr_width - 1);
590 writel(reg, reg_base + CQSPI_REG_SIZE);
591 return 0;
592 }
593
594 static int cqspi_indirect_write_execute(struct spi_nor *nor, loff_t to_addr,
595 const u8 *txbuf, const size_t n_tx)
596 {
597 const unsigned int page_size = nor->page_size;
598 struct cqspi_flash_pdata *f_pdata = nor->priv;
599 struct cqspi_st *cqspi = f_pdata->cqspi;
600 void __iomem *reg_base = cqspi->iobase;
601 unsigned int remaining = n_tx;
602 unsigned int write_bytes;
603 int ret;
604
605 writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
606 writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
607
608 /* Clear all interrupts. */
609 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
610
611 writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
612
613 reinit_completion(&cqspi->transfer_complete);
614 writel(CQSPI_REG_INDIRECTWR_START_MASK,
615 reg_base + CQSPI_REG_INDIRECTWR);
616 /*
617 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
618 * Controller programming sequence, couple of cycles of
619 * QSPI_REF_CLK delay is required for the above bit to
620 * be internally synchronized by the QSPI module. Provide 5
621 * cycles of delay.
622 */
623 if (cqspi->wr_delay)
624 ndelay(cqspi->wr_delay);
625
626 while (remaining > 0) {
627 write_bytes = remaining > page_size ? page_size : remaining;
628 iowrite32_rep(cqspi->ahb_base, txbuf,
629 DIV_ROUND_UP(write_bytes, 4));
630
631 ret = wait_for_completion_timeout(&cqspi->transfer_complete,
632 msecs_to_jiffies
633 (CQSPI_TIMEOUT_MS));
634 if (!ret) {
635 dev_err(nor->dev, "Indirect write timeout\n");
636 ret = -ETIMEDOUT;
637 goto failwr;
638 }
639
640 txbuf += write_bytes;
641 remaining -= write_bytes;
642
643 if (remaining > 0)
644 reinit_completion(&cqspi->transfer_complete);
645 }
646
647 /* Check indirect done status */
648 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
649 CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
650 if (ret) {
651 dev_err(nor->dev,
652 "Indirect write completion error (%i)\n", ret);
653 goto failwr;
654 }
655
656 /* Disable interrupt. */
657 writel(0, reg_base + CQSPI_REG_IRQMASK);
658
659 /* Clear indirect completion status */
660 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
661
662 cqspi_wait_idle(cqspi);
663
664 return 0;
665
666 failwr:
667 /* Disable interrupt. */
668 writel(0, reg_base + CQSPI_REG_IRQMASK);
669
670 /* Cancel the indirect write */
671 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
672 reg_base + CQSPI_REG_INDIRECTWR);
673 return ret;
674 }
675
676 static void cqspi_chipselect(struct spi_nor *nor)
677 {
678 struct cqspi_flash_pdata *f_pdata = nor->priv;
679 struct cqspi_st *cqspi = f_pdata->cqspi;
680 void __iomem *reg_base = cqspi->iobase;
681 unsigned int chip_select = f_pdata->cs;
682 unsigned int reg;
683
684 reg = readl(reg_base + CQSPI_REG_CONFIG);
685 if (cqspi->is_decoded_cs) {
686 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
687 } else {
688 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
689
690 /* Convert CS if without decoder.
691 * CS0 to 4b'1110
692 * CS1 to 4b'1101
693 * CS2 to 4b'1011
694 * CS3 to 4b'0111
695 */
696 chip_select = 0xF & ~(1 << chip_select);
697 }
698
699 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
700 << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
701 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
702 << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
703 writel(reg, reg_base + CQSPI_REG_CONFIG);
704 }
705
706 static void cqspi_configure_cs_and_sizes(struct spi_nor *nor)
707 {
708 struct cqspi_flash_pdata *f_pdata = nor->priv;
709 struct cqspi_st *cqspi = f_pdata->cqspi;
710 void __iomem *iobase = cqspi->iobase;
711 unsigned int reg;
712
713 /* configure page size and block size. */
714 reg = readl(iobase + CQSPI_REG_SIZE);
715 reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
716 reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
717 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
718 reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB);
719 reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB);
720 reg |= (nor->addr_width - 1);
721 writel(reg, iobase + CQSPI_REG_SIZE);
722
723 /* configure the chip select */
724 cqspi_chipselect(nor);
725
726 /* Store the new configuration of the controller */
727 cqspi->current_page_size = nor->page_size;
728 cqspi->current_erase_size = nor->mtd.erasesize;
729 cqspi->current_addr_width = nor->addr_width;
730 }
731
732 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
733 const unsigned int ns_val)
734 {
735 unsigned int ticks;
736
737 ticks = ref_clk_hz / 1000; /* kHz */
738 ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
739
740 return ticks;
741 }
742
743 static void cqspi_delay(struct spi_nor *nor)
744 {
745 struct cqspi_flash_pdata *f_pdata = nor->priv;
746 struct cqspi_st *cqspi = f_pdata->cqspi;
747 void __iomem *iobase = cqspi->iobase;
748 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
749 unsigned int tshsl, tchsh, tslch, tsd2d;
750 unsigned int reg;
751 unsigned int tsclk;
752
753 /* calculate the number of ref ticks for one sclk tick */
754 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
755
756 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
757 /* this particular value must be at least one sclk */
758 if (tshsl < tsclk)
759 tshsl = tsclk;
760
761 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
762 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
763 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
764
765 reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
766 << CQSPI_REG_DELAY_TSHSL_LSB;
767 reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
768 << CQSPI_REG_DELAY_TCHSH_LSB;
769 reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
770 << CQSPI_REG_DELAY_TSLCH_LSB;
771 reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
772 << CQSPI_REG_DELAY_TSD2D_LSB;
773 writel(reg, iobase + CQSPI_REG_DELAY);
774 }
775
776 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
777 {
778 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
779 void __iomem *reg_base = cqspi->iobase;
780 u32 reg, div;
781
782 /* Recalculate the baudrate divisor based on QSPI specification. */
783 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
784
785 reg = readl(reg_base + CQSPI_REG_CONFIG);
786 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
787 reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
788 writel(reg, reg_base + CQSPI_REG_CONFIG);
789 }
790
791 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
792 const bool bypass,
793 const unsigned int delay)
794 {
795 void __iomem *reg_base = cqspi->iobase;
796 unsigned int reg;
797
798 reg = readl(reg_base + CQSPI_REG_READCAPTURE);
799
800 if (bypass)
801 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
802 else
803 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
804
805 reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
806 << CQSPI_REG_READCAPTURE_DELAY_LSB);
807
808 reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
809 << CQSPI_REG_READCAPTURE_DELAY_LSB;
810
811 writel(reg, reg_base + CQSPI_REG_READCAPTURE);
812 }
813
814 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
815 {
816 void __iomem *reg_base = cqspi->iobase;
817 unsigned int reg;
818
819 reg = readl(reg_base + CQSPI_REG_CONFIG);
820
821 if (enable)
822 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
823 else
824 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
825
826 writel(reg, reg_base + CQSPI_REG_CONFIG);
827 }
828
829 static void cqspi_configure(struct spi_nor *nor)
830 {
831 struct cqspi_flash_pdata *f_pdata = nor->priv;
832 struct cqspi_st *cqspi = f_pdata->cqspi;
833 const unsigned int sclk = f_pdata->clk_rate;
834 int switch_cs = (cqspi->current_cs != f_pdata->cs);
835 int switch_ck = (cqspi->sclk != sclk);
836
837 if ((cqspi->current_page_size != nor->page_size) ||
838 (cqspi->current_erase_size != nor->mtd.erasesize) ||
839 (cqspi->current_addr_width != nor->addr_width))
840 switch_cs = 1;
841
842 if (switch_cs || switch_ck)
843 cqspi_controller_enable(cqspi, 0);
844
845 /* Switch chip select. */
846 if (switch_cs) {
847 cqspi->current_cs = f_pdata->cs;
848 cqspi_configure_cs_and_sizes(nor);
849 }
850
851 /* Setup baudrate divisor and delays */
852 if (switch_ck) {
853 cqspi->sclk = sclk;
854 cqspi_config_baudrate_div(cqspi);
855 cqspi_delay(nor);
856 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
857 f_pdata->read_delay);
858 }
859
860 if (switch_cs || switch_ck)
861 cqspi_controller_enable(cqspi, 1);
862 }
863
864 static int cqspi_set_protocol(struct spi_nor *nor, const int read)
865 {
866 struct cqspi_flash_pdata *f_pdata = nor->priv;
867
868 f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
869 f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
870 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
871
872 if (read) {
873 switch (nor->read_proto) {
874 case SNOR_PROTO_1_1_1:
875 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
876 break;
877 case SNOR_PROTO_1_1_2:
878 f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
879 break;
880 case SNOR_PROTO_1_1_4:
881 f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
882 break;
883 default:
884 return -EINVAL;
885 }
886 }
887
888 cqspi_configure(nor);
889
890 return 0;
891 }
892
893 static ssize_t cqspi_write(struct spi_nor *nor, loff_t to,
894 size_t len, const u_char *buf)
895 {
896 struct cqspi_flash_pdata *f_pdata = nor->priv;
897 struct cqspi_st *cqspi = f_pdata->cqspi;
898 int ret;
899
900 ret = cqspi_set_protocol(nor, 0);
901 if (ret)
902 return ret;
903
904 ret = cqspi_write_setup(nor);
905 if (ret)
906 return ret;
907
908 if (f_pdata->use_direct_mode)
909 memcpy_toio(cqspi->ahb_base + to, buf, len);
910 else
911 ret = cqspi_indirect_write_execute(nor, to, buf, len);
912 if (ret)
913 return ret;
914
915 return len;
916 }
917
918 static ssize_t cqspi_read(struct spi_nor *nor, loff_t from,
919 size_t len, u_char *buf)
920 {
921 struct cqspi_flash_pdata *f_pdata = nor->priv;
922 struct cqspi_st *cqspi = f_pdata->cqspi;
923 int ret;
924
925 ret = cqspi_set_protocol(nor, 1);
926 if (ret)
927 return ret;
928
929 ret = cqspi_read_setup(nor);
930 if (ret)
931 return ret;
932
933 if (f_pdata->use_direct_mode)
934 memcpy_fromio(buf, cqspi->ahb_base + from, len);
935 else
936 ret = cqspi_indirect_read_execute(nor, buf, from, len);
937 if (ret)
938 return ret;
939
940 return len;
941 }
942
943 static int cqspi_erase(struct spi_nor *nor, loff_t offs)
944 {
945 int ret;
946
947 ret = cqspi_set_protocol(nor, 0);
948 if (ret)
949 return ret;
950
951 /* Send write enable, then erase commands. */
952 ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
953 if (ret)
954 return ret;
955
956 /* Set up command buffer. */
957 ret = cqspi_command_write_addr(nor, nor->erase_opcode, offs);
958 if (ret)
959 return ret;
960
961 return 0;
962 }
963
964 static int cqspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
965 {
966 struct cqspi_flash_pdata *f_pdata = nor->priv;
967 struct cqspi_st *cqspi = f_pdata->cqspi;
968
969 mutex_lock(&cqspi->bus_mutex);
970
971 return 0;
972 }
973
974 static void cqspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
975 {
976 struct cqspi_flash_pdata *f_pdata = nor->priv;
977 struct cqspi_st *cqspi = f_pdata->cqspi;
978
979 mutex_unlock(&cqspi->bus_mutex);
980 }
981
982 static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
983 {
984 int ret;
985
986 ret = cqspi_set_protocol(nor, 0);
987 if (!ret)
988 ret = cqspi_command_read(nor, &opcode, 1, buf, len);
989
990 return ret;
991 }
992
993 static int cqspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
994 {
995 int ret;
996
997 ret = cqspi_set_protocol(nor, 0);
998 if (!ret)
999 ret = cqspi_command_write(nor, opcode, buf, len);
1000
1001 return ret;
1002 }
1003
1004 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1005 struct cqspi_flash_pdata *f_pdata,
1006 struct device_node *np)
1007 {
1008 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1009 dev_err(&pdev->dev, "couldn't determine read-delay\n");
1010 return -ENXIO;
1011 }
1012
1013 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1014 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1015 return -ENXIO;
1016 }
1017
1018 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1019 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1020 return -ENXIO;
1021 }
1022
1023 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1024 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1025 return -ENXIO;
1026 }
1027
1028 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1029 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1030 return -ENXIO;
1031 }
1032
1033 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1034 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1035 return -ENXIO;
1036 }
1037
1038 return 0;
1039 }
1040
1041 static int cqspi_of_get_pdata(struct platform_device *pdev)
1042 {
1043 struct device_node *np = pdev->dev.of_node;
1044 struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1045
1046 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1047
1048 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1049 dev_err(&pdev->dev, "couldn't determine fifo-depth\n");
1050 return -ENXIO;
1051 }
1052
1053 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1054 dev_err(&pdev->dev, "couldn't determine fifo-width\n");
1055 return -ENXIO;
1056 }
1057
1058 if (of_property_read_u32(np, "cdns,trigger-address",
1059 &cqspi->trigger_address)) {
1060 dev_err(&pdev->dev, "couldn't determine trigger-address\n");
1061 return -ENXIO;
1062 }
1063
1064 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1065
1066 return 0;
1067 }
1068
1069 static void cqspi_controller_init(struct cqspi_st *cqspi)
1070 {
1071 u32 reg;
1072
1073 cqspi_controller_enable(cqspi, 0);
1074
1075 /* Configure the remap address register, no remap */
1076 writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1077
1078 /* Disable all interrupts. */
1079 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1080
1081 /* Configure the SRAM split to 1:1 . */
1082 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1083
1084 /* Load indirect trigger address. */
1085 writel(cqspi->trigger_address,
1086 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1087
1088 /* Program read watermark -- 1/2 of the FIFO. */
1089 writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1090 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1091 /* Program write watermark -- 1/8 of the FIFO. */
1092 writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1093 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1094
1095 /* Enable Direct Access Controller */
1096 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1097 reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1098 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1099
1100 cqspi_controller_enable(cqspi, 1);
1101 }
1102
1103 static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
1104 {
1105 const struct spi_nor_hwcaps hwcaps = {
1106 .mask = SNOR_HWCAPS_READ |
1107 SNOR_HWCAPS_READ_FAST |
1108 SNOR_HWCAPS_READ_1_1_2 |
1109 SNOR_HWCAPS_READ_1_1_4 |
1110 SNOR_HWCAPS_PP,
1111 };
1112 struct platform_device *pdev = cqspi->pdev;
1113 struct device *dev = &pdev->dev;
1114 struct cqspi_flash_pdata *f_pdata;
1115 struct spi_nor *nor;
1116 struct mtd_info *mtd;
1117 unsigned int cs;
1118 int i, ret;
1119
1120 /* Get flash device data */
1121 for_each_available_child_of_node(dev->of_node, np) {
1122 ret = of_property_read_u32(np, "reg", &cs);
1123 if (ret) {
1124 dev_err(dev, "Couldn't determine chip select.\n");
1125 goto err;
1126 }
1127
1128 if (cs >= CQSPI_MAX_CHIPSELECT) {
1129 ret = -EINVAL;
1130 dev_err(dev, "Chip select %d out of range.\n", cs);
1131 goto err;
1132 }
1133
1134 f_pdata = &cqspi->f_pdata[cs];
1135 f_pdata->cqspi = cqspi;
1136 f_pdata->cs = cs;
1137
1138 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1139 if (ret)
1140 goto err;
1141
1142 nor = &f_pdata->nor;
1143 mtd = &nor->mtd;
1144
1145 mtd->priv = nor;
1146
1147 nor->dev = dev;
1148 spi_nor_set_flash_node(nor, np);
1149 nor->priv = f_pdata;
1150
1151 nor->read_reg = cqspi_read_reg;
1152 nor->write_reg = cqspi_write_reg;
1153 nor->read = cqspi_read;
1154 nor->write = cqspi_write;
1155 nor->erase = cqspi_erase;
1156 nor->prepare = cqspi_prep;
1157 nor->unprepare = cqspi_unprep;
1158
1159 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d",
1160 dev_name(dev), cs);
1161 if (!mtd->name) {
1162 ret = -ENOMEM;
1163 goto err;
1164 }
1165
1166 ret = spi_nor_scan(nor, NULL, &hwcaps);
1167 if (ret)
1168 goto err;
1169
1170 ret = mtd_device_register(mtd, NULL, 0);
1171 if (ret)
1172 goto err;
1173
1174 f_pdata->registered = true;
1175
1176 if (mtd->size <= cqspi->ahb_size) {
1177 f_pdata->use_direct_mode = true;
1178 dev_dbg(nor->dev, "using direct mode for %s\n",
1179 mtd->name);
1180 }
1181 }
1182
1183 return 0;
1184
1185 err:
1186 for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1187 if (cqspi->f_pdata[i].registered)
1188 mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1189 return ret;
1190 }
1191
1192 static int cqspi_probe(struct platform_device *pdev)
1193 {
1194 struct device_node *np = pdev->dev.of_node;
1195 struct device *dev = &pdev->dev;
1196 struct cqspi_st *cqspi;
1197 struct resource *res;
1198 struct resource *res_ahb;
1199 unsigned long data;
1200 int ret;
1201 int irq;
1202
1203 cqspi = devm_kzalloc(dev, sizeof(*cqspi), GFP_KERNEL);
1204 if (!cqspi)
1205 return -ENOMEM;
1206
1207 mutex_init(&cqspi->bus_mutex);
1208 cqspi->pdev = pdev;
1209 platform_set_drvdata(pdev, cqspi);
1210
1211 /* Obtain configuration from OF. */
1212 ret = cqspi_of_get_pdata(pdev);
1213 if (ret) {
1214 dev_err(dev, "Cannot get mandatory OF data.\n");
1215 return -ENODEV;
1216 }
1217
1218 /* Obtain QSPI clock. */
1219 cqspi->clk = devm_clk_get(dev, NULL);
1220 if (IS_ERR(cqspi->clk)) {
1221 dev_err(dev, "Cannot claim QSPI clock.\n");
1222 return PTR_ERR(cqspi->clk);
1223 }
1224
1225 /* Obtain and remap controller address. */
1226 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1227 cqspi->iobase = devm_ioremap_resource(dev, res);
1228 if (IS_ERR(cqspi->iobase)) {
1229 dev_err(dev, "Cannot remap controller address.\n");
1230 return PTR_ERR(cqspi->iobase);
1231 }
1232
1233 /* Obtain and remap AHB address. */
1234 res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1235 cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1236 if (IS_ERR(cqspi->ahb_base)) {
1237 dev_err(dev, "Cannot remap AHB address.\n");
1238 return PTR_ERR(cqspi->ahb_base);
1239 }
1240 cqspi->ahb_size = resource_size(res_ahb);
1241
1242 init_completion(&cqspi->transfer_complete);
1243
1244 /* Obtain IRQ line. */
1245 irq = platform_get_irq(pdev, 0);
1246 if (irq < 0) {
1247 dev_err(dev, "Cannot obtain IRQ.\n");
1248 return -ENXIO;
1249 }
1250
1251 pm_runtime_enable(dev);
1252 ret = pm_runtime_get_sync(dev);
1253 if (ret < 0) {
1254 pm_runtime_put_noidle(dev);
1255 return ret;
1256 }
1257
1258 ret = clk_prepare_enable(cqspi->clk);
1259 if (ret) {
1260 dev_err(dev, "Cannot enable QSPI clock.\n");
1261 goto probe_clk_failed;
1262 }
1263
1264 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1265 data = (unsigned long)of_device_get_match_data(dev);
1266 if (data & CQSPI_NEEDS_WR_DELAY)
1267 cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
1268 cqspi->master_ref_clk_hz);
1269
1270 ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1271 pdev->name, cqspi);
1272 if (ret) {
1273 dev_err(dev, "Cannot request IRQ.\n");
1274 goto probe_irq_failed;
1275 }
1276
1277 cqspi_wait_idle(cqspi);
1278 cqspi_controller_init(cqspi);
1279 cqspi->current_cs = -1;
1280 cqspi->sclk = 0;
1281
1282 ret = cqspi_setup_flash(cqspi, np);
1283 if (ret) {
1284 dev_err(dev, "Cadence QSPI NOR probe failed %d\n", ret);
1285 goto probe_setup_failed;
1286 }
1287
1288 return ret;
1289 probe_setup_failed:
1290 cqspi_controller_enable(cqspi, 0);
1291 probe_irq_failed:
1292 clk_disable_unprepare(cqspi->clk);
1293 probe_clk_failed:
1294 pm_runtime_put_sync(dev);
1295 pm_runtime_disable(dev);
1296 return ret;
1297 }
1298
1299 static int cqspi_remove(struct platform_device *pdev)
1300 {
1301 struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1302 int i;
1303
1304 for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1305 if (cqspi->f_pdata[i].registered)
1306 mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1307
1308 cqspi_controller_enable(cqspi, 0);
1309
1310 clk_disable_unprepare(cqspi->clk);
1311
1312 pm_runtime_put_sync(&pdev->dev);
1313 pm_runtime_disable(&pdev->dev);
1314
1315 return 0;
1316 }
1317
1318 #ifdef CONFIG_PM_SLEEP
1319 static int cqspi_suspend(struct device *dev)
1320 {
1321 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1322
1323 cqspi_controller_enable(cqspi, 0);
1324 return 0;
1325 }
1326
1327 static int cqspi_resume(struct device *dev)
1328 {
1329 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1330
1331 cqspi_controller_enable(cqspi, 1);
1332 return 0;
1333 }
1334
1335 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1336 .suspend = cqspi_suspend,
1337 .resume = cqspi_resume,
1338 };
1339
1340 #define CQSPI_DEV_PM_OPS (&cqspi__dev_pm_ops)
1341 #else
1342 #define CQSPI_DEV_PM_OPS NULL
1343 #endif
1344
1345 static const struct of_device_id cqspi_dt_ids[] = {
1346 {
1347 .compatible = "cdns,qspi-nor",
1348 .data = (void *)0,
1349 },
1350 {
1351 .compatible = "ti,k2g-qspi",
1352 .data = (void *)CQSPI_NEEDS_WR_DELAY,
1353 },
1354 { /* end of table */ }
1355 };
1356
1357 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1358
1359 static struct platform_driver cqspi_platform_driver = {
1360 .probe = cqspi_probe,
1361 .remove = cqspi_remove,
1362 .driver = {
1363 .name = CQSPI_NAME,
1364 .pm = CQSPI_DEV_PM_OPS,
1365 .of_match_table = cqspi_dt_ids,
1366 },
1367 };
1368
1369 module_platform_driver(cqspi_platform_driver);
1370
1371 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1372 MODULE_LICENSE("GPL v2");
1373 MODULE_ALIAS("platform:" CQSPI_NAME);
1374 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1375 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");
CRIS linux kernel tree