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1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* $Id: cassini.h,v 1.16 2004/08/17 21:15:16 zaumen Exp $
3 * cassini.h: Definitions for Sun Microsystems Cassini(+) ethernet driver.
4 *
5 * Copyright (C) 2004 Sun Microsystems Inc.
6 * Copyright (c) 2003 Adrian Sun (asun@darksunrising.com)
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 *
21 * vendor id: 0x108E (Sun Microsystems, Inc.)
22 * device id: 0xabba (Cassini)
23 * revision ids: 0x01 = Cassini
24 * 0x02 = Cassini rev 2
25 * 0x10 = Cassini+
26 * 0x11 = Cassini+ 0.2u
27 *
28 * vendor id: 0x100b (National Semiconductor)
29 * device id: 0x0035 (DP83065/Saturn)
30 * revision ids: 0x30 = Saturn B2
31 *
32 * rings are all offset from 0.
33 *
34 * there are two clock domains:
35 * PCI: 33/66MHz clock
36 * chip: 125MHz clock
37 */
39 #ifndef _CASSINI_H
40 #define _CASSINI_H
42 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
43 * 32-bit words. there is no i/o port access. REG_ addresses are
44 * shared between cassini and cassini+. REG_PLUS_ addresses only
45 * appear in cassini+. REG_MINUS_ addresses only appear in cassini.
46 */
47 #define CAS_ID_REV2 0x02
48 #define CAS_ID_REVPLUS 0x10
49 #define CAS_ID_REVPLUS02u 0x11
50 #define CAS_ID_REVSATURNB2 0x30
52 /** global resources **/
54 /* this register sets the weights for the weighted round robin arbiter. e.g.,
55 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
56 * for its next turn to access the pci bus.
57 * map: 0x0 = x1, 0x1 = x2, 0x2 = x4, 0x3 = x8
58 * DEFAULT: 0x0, SIZE: 5 bits
59 */
61 #define CAWR_RX_DMA_WEIGHT_SHIFT 0
63 #define CAWR_TX_DMA_WEIGHT_SHIFT 2
67 /* if enabled, BIM can send bursts across PCI bus > cacheline size. burst
68 * sizes determined by length of packet or descriptor transfer and the
69 * max length allowed by the target.
70 * DEFAULT: 0x0, SIZE: 1 bit
71 */
75 /* top level interrupts [0-9] are auto-cleared to 0 when the status
76 * register is read. second level interrupts [13 - 18] are cleared at
77 * the source. tx completion register 3 is replicated in [19 - 31]
78 * DEFAULT: 0x00000000, SIZE: 29 bits
79 */
82 xferred from host queue to
83 TX FIFO */
85 TX FIFO. i.e.,
86 TX Kick == TX complete. if
87 PACED_MODE set, then TX FIFO
88 also empty */
90 FIFO */
92 corrupted. FATAL ERROR */
94 from RX FIFO to host mem.
95 RX completion reg updated.
96 may be delayed by recv
97 intr blanking. */
99 RX Kick == RX complete */
101 corrupted. FATAL ERROR */
103 ring to post descriptors.
104 RX complete head incr to
105 almost reach RX complete
106 tail */
108 programmable threshold #
109 of free descr avail for
110 hw use */
112 programmable threshold #
113 of descr spaces for hw
114 use in completion descr
115 ring */
117 len of non-reassembly pkt
118 from fifo during DMA or
119 header parser provides TCP
120 header and payload size >
121 MAC packet size.
122 FATAL ERROR */
124 bit will be set if an interrupt
125 generated on the pci bus. useful
126 when driver is polling for
127 interrupts */
130 least 1 unmasked interrupt set */
132 least 1 unmasked interrupt set */
134 at least 1 unmasked interrupt
135 set */
137 1 unmasked interrupt set */
139 BIF has at least 1 unmasked
140 interrupt set */
142 3 reg data */
143 #define INTR_TX_COMP_3_SHIFT 19
144 #define INTR_ERROR_MASK (INTR_MIF_STATUS | INTR_PCI_ERROR_STATUS | \
145 INTR_PCS_STATUS | INTR_RX_LEN_MISMATCH | \
146 INTR_TX_MAC_STATUS | INTR_RX_MAC_STATUS | \
147 INTR_TX_TAG_ERROR | INTR_RX_TAG_ERROR | \
148 INTR_MAC_CTRL_STATUS)
150 /* determines which status events will cause an interrupt. layout same
151 * as REG_INTR_STATUS.
152 * DEFAULT: 0xFFFFFFFF, SIZE: 16 bits
153 */
156 /* top level interrupt bits that are cleared during read of REG_INTR_STATUS_ALIAS.
157 * useful when driver is polling for interrupts. layout same as REG_INTR_MASK.
158 * DEFAULT: 0x00000000, SIZE: 12 bits
159 */
161 (used w/ status alias) */
162 /* same as REG_INTR_STATUS except that only bits cleared are those selected by
163 * REG_ALIAS_CLEAR
164 * DEFAULT: 0x00000000, SIZE: 29 bits
165 */
167 (selective clear) */
169 /* DEFAULT: 0x0, SIZE: 3 bits */
172 set if no ACK64# during ABS64 cycle
173 in Cassini. */
175 no read retry after 2^15 clocks */
178 unused in Cassini. */
180 unused in Cassini. */
182 DMA. unused in cassini. */
184 /* mask for PCI status events that will set PCI_ERR_STATUS. if cleared, event
185 * causes an interrupt to be generated.
186 * DEFAULT: 0x7, SIZE: 3 bits
187 */
190 /* used to configure PCI related parameters that are not in PCI config space.
191 * DEFAULT: 0bxx000, SIZE: 5 bits
192 */
204 reset. reserved in Cassini. */
206 reserved in Cassini. */
208 reserved in Cassini. */
210 /* DEFAULT: 0x00000000, SIZE: 32 bits */
213 machine bits [21:0] */
215 machine bits [6:0] */
217 /* writing to SW_RESET_TX and SW_RESET_RX will issue a global
218 * reset. poll until TX and RX read back as 0's for completion.
219 */
222 cleared to 0. */
224 cleared to 0. */
226 resets PHY and anything else
227 connected to RSTOUT#. RSTOUT#
228 is also activated by local PCI
229 reset when hot-swap is being
230 done. */
232 this bit set, PCS and SLINK
233 modules won't be reset.
234 i.e., link won't drop. */
237 0b000: ARB_IDLE1
238 0b001: ARB_IDLE2
239 0b010: ARB_WB_ACK
240 0b011: ARB_WB_WAT
241 0b100: ARB_RB_ACK
242 0b101: ARB_RB_WAT
243 0b110: ARB_RB_END
244 0b111: ARB_WB_END */
246 0b00: RD_PCI_WAT
247 0b01: RD_PCI_RDY
248 0b11: RD_PCI_ACK */
250 0b00: AD_IDL_RX
251 0b01: AD_ACK_RX
252 0b10: AD_ACK_TX
253 0b11: AD_IDL_TX */
255 0b00: WR_PCI_WAT
256 0b01: WR_PCI_RDY
257 0b11: WR_PCI_ACK */
259 0b000: ARB_IDLE1
260 0b001: ARB_IDLE2
261 0b010: ARB_TX_ACK
262 0b011: ARB_TX_WAT
263 0b100: ARB_RX_ACK
264 0b110: ARB_RX_WAT */
266 /* Cassini only. 64-bit register used to check PCI datapath. when read,
267 * value written has both lower and upper 32-bit halves rotated to the right
268 * one bit position. e.g., FFFFFFFF FFFFFFFF -> 7FFFFFFF 7FFFFFFF
269 */
271 Cassini+: reserved */
273 /* output enables are provided for each device's chip select and for the rest
274 * of the outputs from cassini to its local bus devices. two sw programmable
275 * bits are connected to general purpus control/status bits.
276 * DEFAULT: 0x7
277 */
279 output EN. default: 0x7 */
281 OE signal output enable on the
282 local bus interface. these
283 are shared between both local
284 bus devices. tristate when 0. */
287 select output enable */
292 /* access 24 entry BIM read and write buffers. put address in REG_BIM_BUFFER_ADDR
293 * and read/write from/to it REG_BIM_BUFFER_DATA_LOW and _DATA_HI.
294 * _DATA_HI should be the last access of the sequence.
295 * DEFAULT: undefined
296 */
298 purposes. */
301 read buffer access = 0 */
302 /* DEFAULT: undefined */
306 /* set BIM_RAM_BIST_START to start built-in self test for BIM read buffer.
307 * bit auto-clears when done with status read from _SUMMARY and _PASS bits.
308 */
310 control/status */
313 Cassini only. reserved in
314 Cassini+. */
316 buffer. */
318 buffer. Cassini only. reserved
319 in Cassini+. */
323 Cassini only. reserved in
324 Cassini+. */
326 Cassini only. reserved in
327 Cassini+. */
329 /* ASUN: i'm not sure what this does as it's not in the spec.
330 * DEFAULT: 0xFC
331 */
333 select register */
335 /* enable probe monitoring mode and select data appearing on the P_A* bus. bit
336 * values for _SEL_HI_MASK and _SEL_LOW_MASK:
337 * 0x0: internal probe[7:0] (pci arb state, wtc empty w, wtc full w, wtc empty w,
338 * wtc empty r, post pci)
339 * 0x1: internal probe[15:8] (pci wbuf comp, pci wpkt comp, pci rbuf comp,
340 * pci rpkt comp, txdma wr req, txdma wr ack,
341 * txdma wr rdy, txdma wr xfr done)
342 * 0x2: internal probe[23:16] (txdma rd req, txdma rd ack, txdma rd rdy, rxdma rd,
343 * rd arb state, rd pci state)
344 * 0x3: internal probe[31:24] (rxdma req, rxdma ack, rxdma rdy, wrarb state,
345 * wrpci state)
346 * 0x4: pci io probe[7:0] 0x5: pci io probe[15:8]
347 * 0x6: pci io probe[23:16] 0x7: pci io probe[31:24]
348 * 0x8: pci io probe[39:32] 0x9: pci io probe[47:40]
349 * 0xa: pci io probe[55:48] 0xb: pci io probe[63:56]
350 * the following are not available in Cassini:
351 * 0xc: rx probe[7:0] 0xd: tx probe[7:0]
352 * 0xe: hp probe[7:0] 0xf: mac probe[7:0]
353 */
356 driven on local bus P_A[15:0]
357 for debugging */
359 0x03 = mac[1:0]
360 0x0C = rx[1:0]
361 0x30 = tx[1:0]
362 0xC0 = hp[1:0] */
364 on P_A[15:8]. see above for
365 values. */
367 on P_A[7:0]. see above for
368 values. */
370 /* values mean the same thing as REG_INTR_MASK excep that it's for INTB.
371 DEFAULT: 0x1F */
373 register 2 for INTB */
374 #define REG_PLUS_INTRN_MASK(x) (REG_PLUS_INTR_MASK_1 + ((x) - 1)*16)
375 /* bits correspond to both _MASK and _STATUS registers. _ALT corresponds to
376 * all of the alternate (2-4) INTR registers while _1 corresponds to only
377 * _MASK_1 and _STATUS_1 registers.
378 * DEFAULT: 0x7 for MASK registers, 0x0 for ALIAS_CLEAR registers
379 */
380 #define INTR_RX_DONE_ALT 0x01
381 #define INTR_RX_COMP_FULL_ALT 0x02
382 #define INTR_RX_COMP_AF_ALT 0x04
383 #define INTR_RX_BUF_UNAVAIL_1 0x08
385 #define INTRN_MASK_RX_EN 0x80
386 #define INTRN_MASK_CLEAR_ALL (INTR_RX_DONE_ALT | \
387 INTR_RX_COMP_FULL_ALT | \
388 INTR_RX_COMP_AF_ALT | \
389 INTR_RX_BUF_UNAVAIL_1 | \
390 INTR_RX_BUF_AE_1)
392 register 2 for INTB. default: 0x1F */
393 #define REG_PLUS_INTRN_STATUS(x) (REG_PLUS_INTR_STATUS_1 + ((x) - 1)*16)
395 flags are set. enables desc ring. */
398 register 2 for INTB */
399 #define REG_PLUS_ALIASN_CLEAR(x) (REG_PLUS_ALIAS_CLEAR_1 + ((x) - 1)*16)
402 register alias 2 for INTB */
403 #define REG_PLUS_INTRN_STATUS_ALIAS(x) (REG_PLUS_INTR_STATUS_ALIAS_1 + ((x) - 1)*16)
406 integrated macphy */
414 0 = normal */
417 GMII on SERDES pins for
418 monitoring. */
420 pins configed as outputs.
421 for power saving when using
422 internal phy. */
424 polarity from strapping
425 value.
426 1 = mac core led ctrl
427 polarity active low. */
430 /** transmit dma registers **/
431 #define MAX_TX_RINGS_SHIFT 2
432 #define MAX_TX_RINGS (1 << MAX_TX_RINGS_SHIFT)
433 #define MAX_TX_RINGS_MASK (MAX_TX_RINGS - 1)
435 /* TX configuration.
436 * descr ring sizes size = 32 * (1 << n), n < 9. e.g., 0x8 = 8k. default: 0x8
437 * DEFAULT: 0x3F000001
438 */
441 will stop after xfer of current
442 buffer has been completed. */
444 accessed w/ FIFO addr
445 and data registers.
446 TX DMA should be
447 disabled. */
449 ring 1. */
450 #define TX_CFG_DESC_RING0_SHIFT 2
451 #define TX_CFG_DESC_RINGN_MASK(a) (TX_CFG_DESC_RING0_MASK << (a)*4)
452 #define TX_CFG_DESC_RINGN_SHIFT(a) (TX_CFG_DESC_RING0_SHIFT + (a)*4)
454 TX FIFO becomes empty.
455 if 0, TX_ALL set
456 if descr queue empty. */
459 the end of every packet kicked
460 through Q1. */
462 the end of every packet kicked
463 through Q2. */
465 the end of every packet kicked
466 through Q3 */
468 the end of every packet kicked
469 through Q4 */
471 writeback */
473 connection
474 0b00: tx mac req,
475 tx mac retry req,
476 tx ack and tx tag.
477 0b01: txdma rd req,
478 txdma rd ack,
479 txdma rd rdy,
480 txdma rd type0
481 0b11: txdma wr req,
482 txdma wr ack,
483 txdma wr rdy,
484 txdma wr xfr done. */
485 #define TX_CFG_CTX_SEL_SHIFT 30
487 /* 11-bit counters that point to next location in FIFO to be loaded/retrieved.
488 * used for diagnostics only.
489 */
492 pointer. temp hold reg.
493 diagnostics only. */
496 pointer */
498 /* (ro) 11-bit up/down counter w/ # of frames currently in TX FIFO */
501 /* current state of all state machines in TX */
506 = 0x01 when TX disabled. */
509 state machine */
517 /* 64-bit pointer to the transmit data buffer. only the 50 LSB are incremented
518 * while the upper 23 bits are taken from the TX descriptor
519 */
523 /* 13 bit registers written by driver w/ descriptor value that follows
524 * last valid xmit descriptor. kick # and complete # values are used by
525 * the xmit dma engine to control tx descr fetching. if > 1 valid
526 * tx descr is available within the cache line being read, cassini will
527 * internally cache up to 4 of them. 0 on reset. _KICK = rw, _COMP = ro.
528 */
530 #define REG_TX_KICKN(x) (REG_TX_KICK0 + (x)*4)
532 #define REG_TX_COMPN(x) (REG_TX_COMP0 + (x)*4)
534 /* values of TX_COMPLETE_1-4 are written. each completion register
535 * is 2bytes in size and contiguous. 8B allocation w/ 8B alignment.
536 * NOTE: completion reg values are only written back prior to TX_INTME and
537 * TX_ALL interrupts. at all other times, the most up-to-date index values
538 * should be obtained from the REG_TX_COMPLETE_# registers.
539 * here's the layout:
540 * offset from base addr completion # byte
541 * 0 TX_COMPLETE_1_MSB
542 * 1 TX_COMPLETE_1_LSB
543 * 2 TX_COMPLETE_2_MSB
544 * 3 TX_COMPLETE_2_LSB
545 * 4 TX_COMPLETE_3_MSB
546 * 5 TX_COMPLETE_3_LSB
547 * 6 TX_COMPLETE_4_MSB
548 * 7 TX_COMPLETE_4_LSB
549 */
550 #define TX_COMPWB_SIZE 8
552 base low */
554 base high */
555 #define TX_COMPWB_MSB_MASK 0x00000000000000FFULL
556 #define TX_COMPWB_MSB_SHIFT 0
557 #define TX_COMPWB_LSB_MASK 0x000000000000FF00ULL
558 #define TX_COMPWB_LSB_SHIFT 8
559 #define TX_COMPWB_NEXT(x) ((x) >> 16)
561 /* 53 MSB used as base address. 11 LSB assumed to be 0. TX desc pointer must
562 * be 2KB-aligned. */
565 #define REG_TX_DBN_LOW(x) (REG_TX_DB0_LOW + (x)*8)
566 #define REG_TX_DBN_HI(x) (REG_TX_DB0_HI + (x)*8)
568 /* 16-bit registers hold weights for the weighted round-robin of the
569 * four CBQ TX descr rings. weights correspond to # bytes xferred from
570 * host to TXFIFO in a round of WRR arbitration. can be set
571 * dynamically with new weights set upon completion of the current
572 * packet transfer from host memory to TXFIFO. a dummy write to any of
573 * these registers causes a queue1 pre-emption with all historical bw
574 * deficit data reset to 0 (useful when congestion requires a
575 * pre-emption/re-allocation of network bandwidth
576 */
582 /* diagnostics access to any TX FIFO location. every access is 65
583 * bits. _DATA_LOW = 32 LSB, _DATA_HI_T1/T0 = 32 MSB. _TAG = tag bit.
584 * writing _DATA_HI_T0 sets tag bit low, writing _DATA_HI_T1 sets tag
585 * bit high. TX_FIFO_PIO_SEL must be set for TX FIFO PIO access. if
586 * TX FIFO data integrity is desired, TX DMA should be
587 * disabled. _DATA_HI_Tx should be the last access of the sequence.
588 */
596 /* 9-bit register controls BIST of TX FIFO. bit set indicates that the BIST
597 * passed for the specified memory
598 */
601 controller state machine */
608 clears on completion. */
610 /** receive dma registers **/
611 #define MAX_RX_DESC_RINGS 2
612 #define MAX_RX_COMP_RINGS 4
614 /* receive DMA channel configuration. default: 0x80910
615 * free ring size = (1 << n)*32 -> [32 - 8k]
616 * completion ring size = (1 << n)*128 -> [128 - 32k], n < 9
617 * DEFAULT: 0x80910
618 */
621 channel as soon as current
622 frame xfer has completed.
623 driver should disable MAC
624 for 200ms before disabling
625 RX */
627 free desc ring.
628 def: 0x8 = 8k */
629 #define RX_CFG_DESC_RING_SHIFT 1
631 ring. def: 0x8 = 32k */
632 #define RX_CFG_COMP_RING_SHIFT 5
634 batching. def: 0x0 =
635 enabled */
637 data byte of the packet
638 w/in 8 byte boundares.
639 this swivels the data
640 DMA'ed to header
641 buffers, jumbo buffers
642 when header split is not
643 requested and MTU sized
644 buffers. def: 0x2 */
645 #define RX_CFG_SWIVEL_SHIFT 10
647 /* cassini+ only */
649 RX free desc ring 2.
650 def: 0x8 = 8k */
651 #define RX_CFG_DESC_RING1_SHIFT 16
654 /* the page size register allows cassini chips to do the following with
655 * received data:
656 * [--------------------------------------------------------------] page
657 * [off][buf1][pad][off][buf2][pad][off][buf3][pad][off][buf4][pad]
658 * |--------------| = PAGE_SIZE_BUFFER_STRIDE
659 * page = PAGE_SIZE
660 * offset = PAGE_SIZE_MTU_OFF
661 * for the above example, MTU_BUFFER_COUNT = 4.
662 * NOTE: as is apparent, you need to ensure that the following holds:
663 * MTU_BUFFER_COUNT <= PAGE_SIZE/PAGE_SIZE_BUFFER_STRIDE
664 * DEFAULT: 0x48002002 (8k pages)
665 */
668 by receive descriptors.
669 if jumbo buffers are
670 supported the page size
671 should not be < 8k.
672 0b00 = 2k, 0b01 = 4k
673 0b10 = 8k, 0b11 = 16k
674 DEFAULT: 8k */
675 #define RX_PAGE_SIZE_SHIFT 0
677 packs into a page.
678 DEFAULT: 4 */
679 #define RX_PAGE_SIZE_MTU_COUNT_SHIFT 11
681 each MTU buffer +
682 offset from each
683 other.
684 0b00 = 1k, 0b01 = 2k
685 0b10 = 4k, 0b11 = 8k
686 DEFAULT: 0x1 */
687 #define RX_PAGE_SIZE_MTU_STRIDE_SHIFT 27
689 hw writes the MTU buffer
690 into.
691 0b00 = 0,
692 0b01 = 64 bytes
693 0b10 = 96, 0b11 = 128
694 DEFAULT: 0x1 */
695 #define RX_PAGE_SIZE_MTU_OFF_SHIFT 30
697 /* 11-bit counter points to next location in RX FIFO to be loaded/read.
698 * shadow write pointers enable retries in case of early receive aborts.
699 * DEFAULT: 0x0. generated on 64-bit boundaries.
700 */
704 pointer */
706 pointer */
708 pointer. (8-bit counter) */
710 /* current state of RX DMA state engines + other info
711 * DEFAULT: 0x0
712 */
715 0x0 = idle, 0x1 = load_bop
716 0x2 = load 1, 0x3 = load 2
717 0x4 = load 3, 0x5 = load 4
718 0x6 = last detect
719 0x7 = wait req
720 0x8 = wait req statuss 1st
721 0x9 = load st
722 0xa = bubble mac
723 0xb = error */
725 RX FIFO:
726 0x0 = idle, 0x1 = hp xfr
727 0x2 = wait hp ready
728 0x3 = wait flow code
729 0x4 = fifo xfer
730 0x5 = make status
731 0x6 = csum ready
732 0x7 = error */
734 w/ MAC:
735 0x0 = idle
736 0x1 = wait xoff ack
737 0x2 = wait xon
738 0x3 = wait xon ack */
740 states:
741 0x0 = idle data
742 0x1 = header begin
743 0x2 = xfer header
744 0x3 = xfer header ld
745 0x4 = mtu begin
746 0x5 = xfer mtu
747 0x6 = xfer mtu ld
748 0x7 = jumbo begin
749 0x8 = xfer jumbo
750 0x9 = xfer jumbo ld
751 0xa = reas begin
752 0xb = xfer reas
753 0xc = flush tag
754 0xd = xfer reas ld
755 0xe = error
756 0xf = bubble idle */
758 states:
759 0x0 = idle desc
760 0x1 = wait ack
761 0x9 = wait ack 2
762 0x2 = fetch desc 1
763 0xa = fetch desc 2
764 0x3 = load ptrs
765 0x4 = wait dma
766 0x5 = wait ack batch
767 0x6 = post batch
768 0x7 = xfr done */
770 interrupt queue */
772 of the interrupt queue */
774 /* flow control frames are emitted using two PAUSE thresholds:
775 * XOFF PAUSE uses pause time value pre-programmed in the Send PAUSE MAC reg
776 * XON PAUSE uses a pause time of 0. granularity of threshold is 64bytes.
777 * PAUSE thresholds defined in terms of FIFO occupancy and may be translated
778 * into FIFO vacancy using RX_FIFO_SIZE. setting ON will trigger XON frames
779 * when FIFO reaches 0. OFF threshold should not be > size of RX FIFO. max
780 * value is is 0x6F.
781 * DEFAULT: 0x00078
782 */
784 #define RX_PAUSE_THRESH_QUANTUM 64
786 RX FIFO occupancy >
787 value*64B */
788 #define RX_PAUSE_THRESH_OFF_SHIFT 0
790 emitting XOFF PAUSE when RX
791 FIFO occupancy falls below
792 this value*64B. must be
793 < XOFF threshold. if =
794 RX_FIFO_SIZE< XON frames are
795 never emitted. */
796 #define RX_PAUSE_THRESH_ON_SHIFT 12
798 /* 13-bit register used to control RX desc fetching and intr generation. if 4+
799 * valid RX descriptors are available, Cassini will read 4 at a time.
800 * writing N means that all desc up to *but* excluding N are available. N must
801 * be a multiple of 4 (N % 4 = 0). first desc should be cache-line aligned.
802 * DEFAULT: 0 on reset
803 */
806 /* 8KB aligned 64-bit pointer to the base of the RX free/completion rings.
807 * lower 13 bits of the low register are hard-wired to 0.
808 */
810 base low */
812 base hi */
814 base low */
816 base hi */
817 /* 13-bit register indicate desc used by cassini for receive frames. used
818 * for diagnostic purposes.
819 * DEFAULT: 0 on reset
820 */
823 /* HEAD and TAIL are used to control RX desc posting and interrupt
824 * generation. hw moves the head register to pass ownership to sw. sw
825 * moves the tail register to pass ownership back to hw. to give all
826 * entries to hw, set TAIL = HEAD. if HEAD and TAIL indicate that no
827 * more entries are available, DMA will pause and an interrupt will be
828 * generated to indicate no more entries are available. sw can use
829 * this interrupt to reduce the # of times it must update the
830 * completion tail register.
831 * DEFAULT: 0 on reset
832 */
836 /* values used for receive interrupt blanking. loaded each time the ISR is read
837 * DEFAULT: 0x00000000
838 */
840 for ISR read */
842 this many sets of completion
843 writebacks (up to 2 packets)
844 occur since the last time
845 the ISR was read. 0 = no
846 packet blanking */
847 #define RX_BLANK_INTR_PKT_SHIFT 0
849 if that many clocks were
850 counted since last time the
851 ISR was read.
852 each count is 512 core
853 clocks (125MHz). 0 = no
854 time blanking */
855 #define RX_BLANK_INTR_TIME_SHIFT 12
857 /* values used for interrupt generation based on threshold values of how
858 * many free desc and completion entries are available for hw use.
859 * DEFAULT: 0x00000000
860 */
862 thresholds */
864 generated if # desc
865 avail for hw use <=
866 # */
867 #define RX_AE_THRESH_FREE_SHIFT 0
869 generated if # of
870 completion entries
871 avail for hw use <=
872 # */
873 #define RX_AE_THRESH_COMP_SHIFT 13
875 /* probabilities for random early drop (RED) thresholds on a FIFO threshold
876 * basis. probability should increase when the FIFO level increases. control
877 * packets are never dropped and not counted in stats. probability programmed
878 * on a 12.5% granularity. e.g., 0x1 = 1/8 packets dropped.
879 * DEFAULT: 0x00000000
880 */
887 /* FIFO fullness levels for RX FIFO, RX control FIFO, and RX IPP FIFO.
888 * RX control FIFO = # of packets in RX FIFO.
889 * DEFAULT: 0x0
890 */
898 high */
900 /* BIST testing ro RX FIFO, RX control FIFO, and RX IPP FIFO. only RX BIST
901 * START/COMPLETE is writeable. START will clear when the BIST has completed
902 * checking all 17 RAMS.
903 * DEFAULT: 0bxxxx xxxxx xxxx xxxx xxxx x000 0000 0000 00x0
904 */
925 summary pass bit
926 contains AND of BIST
927 results of all 16
928 RAMS */
930 BIST. self clears
931 on completion. */
933 /* next location in RX CTRL FIFO that will be loaded w/ data from RX IPP/read
934 * from to retrieve packet control info.
935 * DEFAULT: 0
936 */
938 write ptr */
940 ptr */
942 /* receive interrupt blanking. loaded each time interrupt alias register is
943 * read.
944 * DEFAULT: 0x0
945 */
947 alias read */
949 completion writebacks
950 > # since last ISR
951 read. 0 = no
952 blanking. up to 2
953 packets per
954 completion wb. */
956 clocks > # since last
957 ISR read. each count
958 is 512 core clocks
959 (125MHz). 0 = no
960 blanking. */
962 /* diagnostic access to RX FIFO. 32 LSB accessed via DATA_LOW. 32 MSB accessed
963 * via DATA_HI_T0 or DATA_HI_T1. TAG reads the tag bit. writing HI_T0
964 * will unset the tag bit while writing HI_T1 will set the tag bit. to reset
965 * to normal operation after diagnostics, write to address location 0x0.
966 * RX_DMA_EN bit must be set to 0x0 for RX FIFO PIO access. DATA_HI should
967 * be the last write access of a write sequence.
968 * DEFAULT: undefined
969 */
976 /* diagnostic assess to RX CTRL FIFO. 8-bit FIFO_ADDR holds address of
977 * 81 bit control entry and 6 bit flow id. LOW and MID are both 32-bit
978 * accesses. HI is 7-bits with 6-bit flow id and 1 bit control
979 * word. RX_DMA_EN must be 0 for RX CTRL FIFO PIO access. DATA_HI
980 * should be last write access of the write sequence.
981 * DEFAULT: undefined
982 */
984 Batching FIFO addr */
986 low */
988 mid */
990 hi and flow id */
994 /* diagnostic access to RX IPP FIFO. same semantics as RX_FIFO.
995 * DEFAULT: undefined
996 */
1001 T0 */
1003 T1 */
1005 /* 64-bit pointer to receive data buffer in host memory used for headers and
1006 * small packets. MSB in high register. loaded by DMA state machine and
1007 * increments as DMA writes receive data. only 50 LSB are incremented. top
1008 * 13 bits taken from RX descriptor.
1009 * DEFAULT: undefined
1010 */
1012 low */
1014 high */
1016 low */
1018 high */
1020 /* PIO diagnostic access to RX reassembly DMA Table RAM. 6-bit register holds
1021 * one of 64 79-bit locations in the RX Reassembly DMA table and the addr of
1022 * one of the 64 byte locations in the Batching table. LOW holds 32 LSB.
1023 * MID holds the next 32 LSB. HIGH holds the 15 MSB. RX_DMA_EN must be set
1024 * to 0 for PIO access. DATA_HIGH should be last write of write sequence.
1025 * layout:
1026 * reassmbl ptr [78:15] | reassmbl index [14:1] | reassmbl entry valid [0]
1027 * DEFAULT: undefined
1028 */
1030 address */
1034 data low */
1036 data mid */
1038 data high */
1040 /* cassini+ only */
1041 /* 8KB aligned 64-bit pointer to base of RX rings. lower 13 bits hardwired to
1042 * 0. same semantics as primary desc/complete rings.
1043 */
1045 2 base low */
1047 2 base high */
1049 2 base low. 4 total */
1051 2 base high. 4 total */
1052 #define REG_PLUS_RX_CBN_LOW(x) (REG_PLUS_RX_CB1_LOW + 8*((x) - 1))
1053 #define REG_PLUS_RX_CBN_HI(x) (REG_PLUS_RX_CB1_HI + 8*((x) - 1))
1056 reg */
1058 head reg. 4 total. */
1060 tail reg. 4 total. */
1061 #define REG_PLUS_RX_COMPN_HEAD(x) (REG_PLUS_RX_COMP1_HEAD + 8*((x) - 1))
1062 #define REG_PLUS_RX_COMPN_TAIL(x) (REG_PLUS_RX_COMP1_TAIL + 8*((x) - 1))
1064 thresholds */
1065 #define RX_AE1_THRESH_FREE_MASK RX_AE_THRESH_FREE_MASK
1066 #define RX_AE1_THRESH_FREE_SHIFT RX_AE_THRESH_FREE_SHIFT
1068 /** header parser registers **/
1070 /* RX parser configuration register.
1071 * DEFAULT: 0x1651004
1072 */
1074 configuration reg */
1077 0 = 64. 0x3f = 63 */
1078 #define HP_CFG_NUM_CPU_SHIFT 2
1080 TCP seq # by one when
1081 stored in FDBM */
1083 needed to be considered
1084 for reassembly */
1085 #define HP_CFG_TCP_THRESH_SHIFT 9
1087 /* access to RX Instruction RAM. 5-bit register/counter holds addr
1088 * of 39 bit entry to be read/written. 32 LSB in _DATA_LOW. 7 MSB in _DATA_HI.
1089 * RX_DMA_EN must be 0 for RX instr PIO access. DATA_HI should be last access
1090 * of sequence.
1091 * DEFAULT: undefined
1092 */
1094 address */
1097 data low */
1098 #define HP_INSTR_RAM_LOW_OUTMASK_MASK 0x0000FFFF
1099 #define HP_INSTR_RAM_LOW_OUTMASK_SHIFT 0
1100 #define HP_INSTR_RAM_LOW_OUTSHIFT_MASK 0x000F0000
1101 #define HP_INSTR_RAM_LOW_OUTSHIFT_SHIFT 16
1102 #define HP_INSTR_RAM_LOW_OUTEN_MASK 0x00300000
1103 #define HP_INSTR_RAM_LOW_OUTEN_SHIFT 20
1104 #define HP_INSTR_RAM_LOW_OUTARG_MASK 0xFFC00000
1105 #define HP_INSTR_RAM_LOW_OUTARG_SHIFT 22
1107 data mid */
1108 #define HP_INSTR_RAM_MID_OUTARG_MASK 0x00000003
1109 #define HP_INSTR_RAM_MID_OUTARG_SHIFT 0
1110 #define HP_INSTR_RAM_MID_OUTOP_MASK 0x0000003C
1111 #define HP_INSTR_RAM_MID_OUTOP_SHIFT 2
1112 #define HP_INSTR_RAM_MID_FNEXT_MASK 0x000007C0
1113 #define HP_INSTR_RAM_MID_FNEXT_SHIFT 6
1114 #define HP_INSTR_RAM_MID_FOFF_MASK 0x0003F800
1115 #define HP_INSTR_RAM_MID_FOFF_SHIFT 11
1116 #define HP_INSTR_RAM_MID_SNEXT_MASK 0x007C0000
1117 #define HP_INSTR_RAM_MID_SNEXT_SHIFT 18
1118 #define HP_INSTR_RAM_MID_SOFF_MASK 0x3F800000
1119 #define HP_INSTR_RAM_MID_SOFF_SHIFT 23
1120 #define HP_INSTR_RAM_MID_OP_MASK 0xC0000000
1121 #define HP_INSTR_RAM_MID_OP_SHIFT 30
1123 data high */
1124 #define HP_INSTR_RAM_HI_VAL_MASK 0x0000FFFF
1125 #define HP_INSTR_RAM_HI_VAL_SHIFT 0
1126 #define HP_INSTR_RAM_HI_MASK_MASK 0xFFFF0000
1127 #define HP_INSTR_RAM_HI_MASK_SHIFT 16
1129 /* PIO access into RX Header parser data RAM and flow database.
1130 * 11-bit register. Data fills the LSB portion of bus if less than 32 bits.
1131 * DATA_RAM: write RAM_FDB_DATA with index to access DATA_RAM.
1132 * RAM bytes = 4*(x - 1) + [3:0]. e.g., 0 -> [3:0], 31 -> [123:120]
1133 * FLOWDB: write DATA_RAM_FDB register and then read/write FDB1-12 to access
1134 * flow database.
1135 * RX_DMA_EN must be 0 for RX parser RAM PIO access. RX Parser RAM data reg
1136 * should be the last write access of the write sequence.
1137 * DEFAULT: undefined
1138 */
1140 RAM address */
1142 locations in header
1143 parser data ram to
1144 read/write */
1146 in the flow database */
1149 /* HP flow database registers: 1 - 12, 0x415C - 0x4188, 4 8-bit bytes
1150 * FLOW_DB(1) = IP_SA[127:96], FLOW_DB(2) = IP_SA[95:64]
1151 * FLOW_DB(3) = IP_SA[63:32], FLOW_DB(4) = IP_SA[31:0]
1152 * FLOW_DB(5) = IP_DA[127:96], FLOW_DB(6) = IP_DA[95:64]
1153 * FLOW_DB(7) = IP_DA[63:32], FLOW_DB(8) = IP_DA[31:0]
1154 * FLOW_DB(9) = {TCP_SP[15:0],TCP_DP[15:0]}
1155 * FLOW_DB(10) = bit 0 has value for flow valid
1156 * FLOW_DB(11) = TCP_SEQ[63:32], FLOW_DB(12) = TCP_SEQ[31:0]
1157 */
1159 #define REG_HP_FLOW_DBN(x) (REG_HP_FLOW_DB0 + (x)*4)
1161 /* diagnostics for RX Header Parser block.
1162 * ASUN: the header parser state machine register is used for diagnostics
1163 * purposes. however, the spec doesn't have any details on it.
1164 */
1170 number */
1182 start offset */
1186 reassembly */
1188 enable */
1190 check */
1192 equal to zero */
1194 chk */
1196 threshold */
1204 /* BIST for header parser(HP) and flow database memories (FDBM). set _START
1205 * to start BIST. controller clears _START on completion. _START can also
1206 * be cleared to force termination of BIST. a bit set indicates that that
1207 * memory passed its BIST.
1208 */
1217 bank 0 */
1219 bank 0 */
1221 bank 0 */
1223 bank 0 */
1225 bank 1 */
1227 bank 2 */
1229 bank 1 */
1231 bank 1 */
1233 RAM */
1238 /** MAC registers. **/
1239 /* reset bits are set using a PIO write and self-cleared after the command
1240 * execution has completed.
1241 */
1243 command (default: 0x0) */
1245 command (default: 0x0) */
1246 /* execute a pause flow control frame transmission
1247 DEFAULT: 0x0XXXX */
1250 to be sent on network
1251 in units of slot
1252 times */
1254 frame on network */
1256 /* bit set indicates that event occurred. auto-cleared when status register
1257 * is read and have corresponding mask bits in mask register. events will
1258 * trigger an interrupt if the corresponding mask bit is 0.
1259 * status register default: 0x00000000
1260 * mask register default = 0xFFFFFFFF on reset
1261 */
1264 transmision */
1266 transmission due to
1267 data starvation in the
1268 xmit data path */
1270 length passed to TX MAC
1271 by the DMA engine */
1273 collision counter */
1275 collision counter */
1277 collision counter */
1279 collision counter */
1281 timer */
1283 attempts counter */
1287 a frame */
1289 RX FIFO overflow */
1291 counter */
1293 error counter */
1295 counter */
1297 error counter */
1299 violation error */
1301 /* DEFAULT: 0xXXXX0000 on reset */
1304 reception of a
1305 pause control
1306 frame */
1308 transition from
1309 "not paused" to
1310 "paused" */
1312 transition from
1313 "paused" to "not
1314 paused" */
1316 operand that was
1317 received in the last
1318 pause flow control
1319 frame */
1321 /* layout identical to TX MAC[8:0] */
1323 /* layout identical to RX MAC[6:0] */
1325 /* layout identical to CTRL MAC[2:0] */
1328 /* to ensure proper operation, CFG_EN must be cleared to 0 and a delay
1329 * imposed before writes to other bits in the TX_MAC_CFG register or any of
1330 * the MAC parameters is performed. delay dependent upon time required to
1331 * transmit a maximum size frame (= MAC_FRAMESIZE_MAX*8/Mbps). e.g.,
1332 * the delay for a 1518-byte frame on a 100Mbps network is 125us.
1333 * alternatively, just poll TX_CFG_EN until it reads back as 0.
1334 * NOTE: on half-duplex 1Gbps, TX_CFG_CARRIER_EXTEND and
1335 * RX_CFG_CARRIER_EXTEND should be set and the SLOT_TIME register should
1336 * be 0x200 (slot time of 512 bytes)
1337 */
1340 force TXMAC state
1341 machine to remain in
1342 idle state or to
1343 transition to idle state
1344 on completion of an
1345 ongoing packet. */
1347 process. set to 1 when
1348 full duplex and 0 when
1349 half duplex */
1351 algorithm. set to 1 when
1352 full duplex and 0 when
1353 half duplex */
1355 Rx-to-TX IPG. after
1356 receiving a frame, TX
1357 MAC will reset its
1358 deferral process to
1359 carrier sense for the
1360 amount of time = IPG0 +
1361 IPG1 and commit to
1362 transmission for time
1363 specified in IPG2. when
1364 0 or when xmitting frames
1365 back-to-pack (Tx-to-Tx
1366 IPG), TX MAC ignores
1367 IPG0 and will only use
1368 IPG1 for deferral time.
1369 IPG2 still used. */
1371 give up on frame
1372 xmission. if backoff
1373 algorithm reaches the
1374 ATTEMPT_LIMIT, it will
1375 clear attempts counter
1376 and continue trying to
1377 send the frame as
1378 specified by
1379 GIVE_UP_LIM. when 0,
1380 TX MAC will execute
1381 standard CSMA/CD prot. */
1383 continue to try to xmit
1384 until successful. when
1385 0, TX MAC will continue
1386 to try xmitting until
1387 successful or backoff
1388 algorithm reaches
1389 ATTEMPT_LIMIT*16 */
1391 backoff algorithm. TX
1392 MAC will not back off
1393 after a xmission attempt
1394 that resulted in a
1395 collision. */
1397 deferral process is reset
1398 in response to carrier
1399 sense during the entire
1400 duration of IPG. TX MAC
1401 will only commit to frame
1402 xmission after frame
1403 xmission has actually
1404 begun. */
1406 CRC for all xmitted
1407 packets. when clear, CRC
1408 generation is dependent
1409 upon NO_CRC bit in the
1410 xmit control word from
1411 TX DMA */
1413 carrier extension
1414 feature. this allows for
1415 longer collision domains
1416 by extending the carrier
1417 and collision window
1418 from the end of FCS until
1419 the end of the slot time
1420 if necessary. Required
1421 for half-duplex at 1Gbps,
1422 clear otherwise. */
1424 /* when CRC is not stripped, reassembly packets will not contain the CRC.
1425 * these will be stripped by HRP because it reassembles layer 4 data, and the
1426 * CRC is layer 2. however, non-reassembly packets will still contain the CRC
1427 * when passed to the host. to ensure proper operation, need to wait 3.2ms
1428 * after clearing RX_CFG_EN before writing to any other RX MAC registers
1429 * or other MAC parameters. alternatively, poll RX_CFG_EN until it clears
1430 * to 0. similary, HASH_FILTER_EN and ADDR_FILTER_EN have the same
1431 * restrictions as CFG_EN.
1432 */
1436 feature not supported */
1438 last 4 bytes of a
1439 received frame. */
1442 multicast frames (group
1443 bit in DA field set) */
1445 multicast addresses */
1447 address filtering regs
1448 to filter both unicast
1449 and multicast
1450 addresses */
1452 RX DMA by setting BAD
1453 bit but not Abort bit
1454 in the status. CRC,
1455 framing, and length errs
1456 will not increment
1457 error counters. frames
1458 which don't match dest
1459 addr will be passed up
1460 w/ BAD bit set. */
1462 packet bursts generated
1463 by carrier extension
1464 with packet bursting
1465 senders. only applies
1466 to half-duplex 1Gbps */
1468 /* DEFAULT: 0x0 */
1471 sending pause flow ctrl
1472 frames */
1474 pause flow ctrl frames */
1476 packets to RX DMA */
1478 /* to ensure proper operation, a global initialization sequence should be
1479 * performed when a loopback config is entered or exited. if programmed after
1480 * a hw or global sw reset, RX/TX MAC software reset and initialization
1481 * should be done to ensure stable clocking.
1482 * DEFAULT: 0x0
1483 */
1486 on MII xmit bus */
1488 path to GMII recv data
1489 path. phy mode register
1490 clock selection must be
1491 set to GMII mode and
1492 GMII_MODE should be set
1493 to 1. in loopback mode,
1494 REFCLK will drive the
1495 entire mac core. 0 for
1496 normal operation. */
1498 path during packet
1499 xmission. clear to 0
1500 in any full duplex mode,
1501 in any loopback mode,
1502 or in half-duplex SERDES
1503 or SLINK modes. set when
1504 in half-duplex when
1505 using external phy. */
1507 clocks and datapath */
1509 external tristate buffer
1510 on the MII receive
1511 bus. */
1516 recommended: 0x00 */
1518 recommended: 0x08 */
1520 recommended: 0x04 */
1522 recommended: 0x40 */
1524 recommended: 0x40 */
1526 /* FRAMESIZE_MAX holds both the max frame size as well as the max burst size.
1527 * recommended value: 0x2000.05EE
1528 */
1531 #define MAC_FRAMESIZE_MAX_BURST_SHIFT 16
1533 #define MAC_FRAMESIZE_MAX_FRAME_SHIFT 0
1535 preamble bytes that the
1536 TX MAC will xmit at the
1537 beginning of each frame
1538 value should be 2 or
1539 greater. recommended
1540 value: 0x07 */
1542 of jam in units of media
1543 byte time. recommended
1544 value: 0x04 */
1546 of attempts TX MAC will
1547 make to xmit a frame
1548 before it resets its
1549 attempts counter. after
1550 the limit has been
1551 reached, TX MAC may or
1552 may not drop the frame
1553 dependent upon value
1554 in TX_MAC_CFG.
1555 recommended
1556 value: 0x10 */
1558 type field of a MAC
1559 ctrl frame. recommended
1560 value: 0x8808 */
1562 /* mac address registers: 0 - 44, 0x6080 - 0x6130, 4 8-bit bytes.
1563 * register contains comparison
1564 * 0 16 MSB of primary MAC addr [47:32] of DA field
1565 * 1 16 middle bits "" [31:16] of DA field
1566 * 2 16 LSB "" [15:0] of DA field
1567 * 3*x 16MSB of alt MAC addr 1-15 [47:32] of DA field
1568 * 4*x 16 middle bits "" [31:16]
1569 * 5*x 16 LSB "" [15:0]
1570 * 42 16 MSB of MAC CTRL addr [47:32] of DA.
1571 * 43 16 middle bits "" [31:16]
1572 * 44 16 LSB "" [15:0]
1573 * MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames.
1574 * if there is a match, MAC will set the bit for alternative address
1575 * filter pass [15]
1577 * here is the map of registers given MAC address notation: a:b:c:d:e:f
1578 * ab cd ef
1579 * primary addr reg 2 reg 1 reg 0
1580 * alt addr 1 reg 5 reg 4 reg 3
1581 * alt addr x reg 5*x reg 4*x reg 3*x
1582 * ctrl addr reg 44 reg 43 reg 42
1583 */
1585 #define REG_MAC_ADDRN(x) (REG_MAC_ADDR0 + (x)*4)
1587 [47:32] */
1589 [31:16] */
1591 [15:0] */
1593 mask reg. 8-bit reg
1594 contains nibble mask for
1595 reg 2 and 1. */
1597 reg */
1599 /* hash table registers: 0 - 15, 0x6160 - 0x619C, 4 8-bit bytes
1600 * 16-bit registers contain bits of the hash table.
1601 * reg x -> [16*(15 - x) + 15 : 16*(15 - x)].
1602 * e.g., 15 -> [15:0], 0 -> [255:240]
1603 */
1605 #define REG_MAC_HASH_TABLEN(x) (REG_MAC_HASH_TABLE0 + (x)*4)
1607 /* statistics registers. these registers generate an interrupt on
1608 * overflow. recommended initialization: 0x0000. most are 16-bits except
1609 * for PEAK_ATTEMPTS register which is 8 bits.
1610 */
1612 counter. */
1614 successful collision
1615 counter */
1617 counter */
1620 is the media byte
1621 clock/256 */
1628 error counter */
1630 /* misc registers */
1632 10-bit register used as a
1633 seed for the random number
1634 generator for the CSMA/CD
1635 backoff algorithm. only
1636 programmed after power-on
1637 reset and should be a
1638 random value which has a
1639 high likelihood of being
1640 unique for each MAC
1641 attached to a network
1642 segment (e.g., 10 LSB of
1643 MAC address) */
1645 /* ASUN: there's a PAUSE_TIMER (ro) described, but it's not in the address
1646 * map
1647 */
1649 /* 27-bit register has the current state for key state machines in the MAC */
1651 #define MAC_SM_RLM_MASK 0x07800000
1652 #define MAC_SM_RLM_SHIFT 23
1653 #define MAC_SM_RX_FC_MASK 0x00700000
1654 #define MAC_SM_RX_FC_SHIFT 20
1655 #define MAC_SM_TLM_MASK 0x000F0000
1656 #define MAC_SM_TLM_SHIFT 16
1657 #define MAC_SM_ENCAP_SM_MASK 0x0000F000
1658 #define MAC_SM_ENCAP_SM_SHIFT 12
1659 #define MAC_SM_TX_REQ_MASK 0x00000C00
1660 #define MAC_SM_TX_REQ_SHIFT 10
1661 #define MAC_SM_TX_FC_MASK 0x000003C0
1662 #define MAC_SM_TX_FC_SHIFT 6
1663 #define MAC_SM_FIFO_WRITE_SEL_MASK 0x00000038
1664 #define MAC_SM_FIFO_WRITE_SEL_SHIFT 3
1665 #define MAC_SM_TX_FIFO_EMPTY_MASK 0x00000007
1666 #define MAC_SM_TX_FIFO_EMPTY_SHIFT 0
1668 /** MIF registers. the MIF can be programmed in either bit-bang or
1669 * frame mode.
1670 **/
1672 1 -> 0 will generate a
1673 rising edge. 0 -> 1 will
1674 generate a falling edge. */
1676 register generates data */
1678 enable. enable when
1679 xmitting data from MIF to
1680 transceiver. */
1682 /* 32-bit register serves as an instruction register when the MIF is
1683 * programmed in frame mode. load this register w/ a valid instruction
1684 * (as per IEEE 802.3u MII spec). poll this register to check for instruction
1685 * execution completion. during a read operation, this register will also
1686 * contain the 16-bit data returned by the tranceiver. unless specified
1687 * otherwise, fields are considered "don't care" when polling for
1688 * completion.
1689 */
1692 load w/ 01 when
1693 issuing an instr */
1696 write. 10 for a
1697 read */
1701 issuing an instr,
1702 this field should be
1703 loaded w/ the XCVR
1704 addr */
1705 #define MIF_FRAME_PHY_ADDR_SHIFT 23
1707 when issuing an instr,
1708 addr of register
1709 to be read/written */
1710 #define MIF_FRAME_REG_ADDR_SHIFT 18
1712 when issuing an instr,
1713 set this bit to 1 */
1715 when issuing an instr,
1716 set this bit to 0.
1717 when polling for
1718 completion, 1 means
1719 that instr execution
1720 has been completed */
1722 load with 16-bit data
1723 to be written in
1724 transceiver reg for a
1725 write. doesn't matter
1726 in a read. when
1727 polling for
1728 completion, field is
1729 "don't care" for write
1730 and 16-bit data
1731 returned by the
1732 transceiver for a
1733 read (if valid bit
1734 is set) */
1737 0 -> select MDIO_0 */
1739 mechanism. if set,
1740 BB_MODE should be 0 */
1742 0 -> frame mode */
1744 used by polling mode.
1745 only meaningful if POLL_EN
1746 is set to 1 */
1747 #define MIF_CFG_POLL_REG_SHIFT 3
1749 when MDIO_0 is idle,
1750 1 -> tranceiver is
1751 connected to MDIO_0.
1752 when MIF is communicating
1753 w/ MDIO_0 in bit-bang
1754 mode, this bit indicates
1755 the incoming bit stream
1756 during a read op */
1758 when MDIO_1 is idle,
1759 1 -> transceiver is
1760 connected to MDIO_1.
1761 when MIF is communicating
1762 w/ MDIO_1 in bit-bang
1763 mode, this bit indicates
1764 the incoming bit stream
1765 during a read op */
1767 be polled */
1768 #define MIF_CFG_POLL_PHY_SHIFT 10
1770 /* 16-bit register used to determine which bits in the POLL_STATUS portion of
1771 * the MIF_STATUS register will cause an interrupt. if a mask bit is 0,
1772 * corresponding bit of the POLL_STATUS will generate a MIF interrupt when
1773 * set. DEFAULT: 0xFFFF
1774 */
1777 /* 32-bit register used when in poll mode. auto-cleared after being read */
1780 the "latest image"
1781 update of the XCVR
1782 reg being read */
1783 #define MIF_STATUS_POLL_DATA_SHIFT 16
1785 which bits in the
1786 POLL_DATA field have
1787 changed since the
1788 MIF_STATUS reg was
1789 last read */
1790 #define MIF_STATUS_POLL_STATUS_SHIFT 0
1792 /* 7-bit register has current state for all state machines in the MIF */
1795 state */
1797 state */
1799 /** PCS/Serialink. the following registers are equivalent to the standard
1800 * MII management registers except that they're directly mapped in
1801 * Cassini's register space.
1802 **/
1804 /* the auto-negotiation enable bit should be programmed the same at
1805 * the link partner as in the local device to enable auto-negotiation to
1806 * complete. when that bit is reprogrammed, auto-neg/manual config is
1807 * restarted automatically.
1808 * DEFAULT: 0x1040
1809 */
1812 writes */
1814 to MAC interface is
1815 activated regardless
1816 of activity */
1818 behaviour same for
1819 half and full dplx */
1821 restart auto-
1822 negotiation */
1824 on writes */
1826 on writes */
1828 through automatic
1829 link config before it
1830 can be used. when 0,
1831 link can be used
1832 w/out any link config
1833 phase */
1835 writes */
1837 when done */
1839 /* DEFAULT: 0x0108 */
1844 0 -> link down. 0 is
1845 latched so that 0 is
1846 kept until read. read
1847 2x to determine if the
1848 link has gone up again */
1850 auto-neg) */
1852 from received link code
1853 word. only valid after
1854 auto-neg completed */
1856 completed
1857 0 -> auto-negotiation not
1858 completed */
1860 indication that this is
1861 a 1000 Base-X PHY. writes
1862 to it are ignored */
1864 /* used during auto-negotiation.
1865 * DEFAULT: 0x00E0
1866 */
1868 reg */
1870 1000 Base-X */
1872 1000 Base-X */
1874 symmetric capability */
1876 asymmetric capability */
1878 to optionally indicate to
1879 link partner that chip is
1880 going off-line. bit12 will
1881 get set when signal
1882 detect == FAIL and will
1883 remain set until
1884 successful negotiation */
1888 /* contents updated as a result of autonegotiation. layout and definitions
1889 * identical to PCS_MII_ADVERT
1890 */
1892 ability reg */
1893 #define PCS_MII_LPA_FD PCS_MII_ADVERT_FD
1894 #define PCS_MII_LPA_HD PCS_MII_ADVERT_HD
1895 #define PCS_MII_LPA_SYM_PAUSE PCS_MII_ADVERT_SYM_PAUSE
1896 #define PCS_MII_LPA_ASYM_PAUSE PCS_MII_ADVERT_ASYM_PAUSE
1897 #define PCS_MII_LPA_RF_MASK PCS_MII_ADVERT_RF_MASK
1898 #define PCS_MII_LPA_ACK PCS_MII_ADVERT_ACK
1899 #define PCS_MII_LPA_NEXT_PAGE PCS_MII_ADVERT_NEXT_PAGE
1901 /* DEFAULT: 0x0 */
1904 0 when modifying
1905 PCS_MII_ADVERT */
1907 OK. bit is
1908 non-resettable */
1910 of optical signal to make
1911 signal detect okay when
1912 signal is low */
1914 measurements. a single
1915 code group is xmitted
1916 regularly.
1917 0x0 = normal operation
1918 0x1 = high freq test
1919 pattern, D21.5
1920 0x2 = low freq test
1921 pattern, K28.7
1922 0x3 = reserved */
1924 negotiation timer to
1925 a few cycles for test
1926 purposes */
1928 /* used for diagnostic purposes. bits 20-22 autoclear on read */
1930 and diagnostic reg */
1932 xmission of idle.
1933 otherwise, xmission of
1934 a packet */
1936 of idle. otherwise,
1937 reception of packet */
1939 sync */
1941 indicates reception of
1942 Config codes. cycling
1943 through 0-1 indicates
1944 reception of idles */
1945 #define PCS_SM_LINK_STATE_MASK 0x0001E000
1949 recept of Config
1950 codes */
1952 loss of sync */
1954 from OK to FAIL. bit29
1955 will also be set if
1956 this is set */
1958 receipt of breaklink
1959 C codes from partner.
1960 C codes w/ 0 content
1961 received triggering
1962 start/restart of
1963 autonegotiation.
1964 should be sent for
1965 no longer than 20ms */
1967 initialized. see serdes
1968 state reg */
1970 not received */
1972 achieved */
1974 w/ ack bit set */
1976 to send C codes
1977 instead of idle
1978 symbols or pkt data */
1980 /* this register indicates interrupt changes in specific PCS MII status bits.
1981 * PCS_INT may be masked at the ISR level. only a single bit is implemented
1982 * for link status change.
1983 */
1986 since last read */
1988 /* control which network interface is used. no more than one bit should
1989 * be set.
1990 * DEFAULT: none
1991 */
1994 MII/GMII is selected.
1995 selection between MII and
1996 GMII is controlled by
1997 XIF_CFG */
1999 10-bit interface */
2001 /* input to serdes chip or serialink block */
2004 serdes interface */
2006 detection. should be
2007 0x0 for normal
2008 operation */
2010 to REFCLK when set.
2011 when clear, receiver
2012 clock locks to incoming
2013 serial data */
2015 /* multiplex test outputs into the PROM address (PA_3 through PA_0) pins.
2016 * should be 0x0 for normal operations.
2017 * 0b000 normal operation, PROM address[3:0] selected
2018 * 0b001 rxdma req, rxdma ack, rxdma ready, rxdma read
2019 * 0b010 rxmac req, rx ack, rx tag, rx clk shared
2020 * 0b011 txmac req, tx ack, tx tag, tx retry req
2021 * 0b100 tx tp3, tx tp2, tx tp1, tx tp0
2022 * 0b101 R period RX, R period TX, R period HP, R period BIM
2023 * DEFAULT: 0x0
2024 */
2026 #define PCS_SOS_PROM_ADDR_MASK 0x0007
2028 /* used for diagnostics. this register indicates progress of the SERDES
2029 * boot up.
2030 * 0b00 undergoing reset
2031 * 0b01 waiting 500us while lockrefn is asserted
2032 * 0b10 waiting for comma detect
2033 * 0b11 receive data is synchronized
2034 * DEFAULT: 0x0
2035 */
2037 #define PCS_SERDES_STATE_MASK 0x03
2039 /* used for diagnostics. indicates number of packets transmitted or received.
2040 * counters rollover w/out generating an interrupt.
2041 * DEFAULT: 0x0
2042 */
2046 whether they
2047 encountered an error
2048 or not */
2050 /** LocalBus Devices. the following provides run-time access to the
2051 * Cassini's PROM
2052 ***/
2054 access */
2055 #define REG_EXPANSION_ROM_RUN_END 0x17FFFF
2058 device */
2059 #define REG_SECOND_LOCALBUS_END 0x1FFFFF
2061 /* entropy device */
2062 #define REG_ENTROPY_START REG_SECOND_LOCALBUS_START
2063 #define REG_ENTROPY_DATA (REG_ENTROPY_START + 0x00)
2064 #define REG_ENTROPY_STATUS (REG_ENTROPY_START + 0x04)
2065 #define ENTROPY_STATUS_DRDY 0x01
2066 #define ENTROPY_STATUS_BUSY 0x02
2067 #define ENTROPY_STATUS_CIPHER 0x04
2068 #define ENTROPY_STATUS_BYPASS_MASK 0x18
2069 #define REG_ENTROPY_MODE (REG_ENTROPY_START + 0x05)
2070 #define ENTROPY_MODE_KEY_MASK 0x07
2071 #define ENTROPY_MODE_ENCRYPT 0x40
2072 #define REG_ENTROPY_RAND_REG (REG_ENTROPY_START + 0x06)
2073 #define REG_ENTROPY_RESET (REG_ENTROPY_START + 0x07)
2074 #define ENTROPY_RESET_DES_IO 0x01
2075 #define ENTROPY_RESET_STC_MODE 0x02
2076 #define ENTROPY_RESET_KEY_CACHE 0x04
2077 #define ENTROPY_RESET_IV 0x08
2078 #define REG_ENTROPY_IV (REG_ENTROPY_START + 0x08)
2079 #define REG_ENTROPY_KEY0 (REG_ENTROPY_START + 0x10)
2080 #define REG_ENTROPY_KEYN(x) (REG_ENTROPY_KEY0 + 4*(x))
2082 /* phys of interest w/ their special mii registers */
2083 #define PHY_LUCENT_B0 0x00437421
2084 #define LUCENT_MII_REG 0x1F
2086 #define PHY_NS_DP83065 0x20005c78
2087 #define DP83065_MII_MEM 0x16
2088 #define DP83065_MII_REGD 0x1D
2089 #define DP83065_MII_REGE 0x1E
2091 #define PHY_BROADCOM_5411 0x00206071
2092 #define PHY_BROADCOM_B0 0x00206050
2093 #define BROADCOM_MII_REG4 0x14
2094 #define BROADCOM_MII_REG5 0x15
2095 #define BROADCOM_MII_REG7 0x17
2096 #define BROADCOM_MII_REG8 0x18
2098 #define CAS_MII_ANNPTR 0x07
2099 #define CAS_MII_ANNPRR 0x08
2100 #define CAS_MII_1000_CTRL 0x09
2101 #define CAS_MII_1000_STATUS 0x0A
2102 #define CAS_MII_1000_EXTEND 0x0F
2105 /*
2106 * if autoneg is disabled, here's the table:
2107 * BMCR_SPEED100 = 100Mbps
2108 * BMCR_SPEED1000 = 1000Mbps
2109 * ~(BMCR_SPEED100 | BMCR_SPEED1000) = 10Mbps
2110 */
2113 #define CAS_ADVERTISE_1000HALF 0x0100
2114 #define CAS_ADVERTISE_1000FULL 0x0200
2115 #define CAS_ADVERTISE_PAUSE 0x0400
2116 #define CAS_ADVERTISE_ASYM_PAUSE 0x0800
2118 /* regular lpa register */
2119 #define CAS_LPA_PAUSE CAS_ADVERTISE_PAUSE
2120 #define CAS_LPA_ASYM_PAUSE CAS_ADVERTISE_ASYM_PAUSE
2122 /* 1000_STATUS register */
2123 #define CAS_LPA_1000HALF 0x0400
2124 #define CAS_LPA_1000FULL 0x0800
2126 #define CAS_EXTEND_1000XFULL 0x8000
2127 #define CAS_EXTEND_1000XHALF 0x4000
2128 #define CAS_EXTEND_1000TFULL 0x2000
2129 #define CAS_EXTEND_1000THALF 0x1000
2131 /* cassini header parser firmware */
2137 u8 op;
2140 /* output info */
2145 2 = if !match, 3 = always */
2147 u16 outmask;
2150 /* comparison */
2156 /* output opcodes */
2157 #define CL_REG 0
2158 #define LD_FID 1
2159 #define LD_SEQ 2
2160 #define LD_CTL 3
2161 #define LD_SAP 4
2162 #define LD_R1 5
2163 #define LD_L3 6
2164 #define LD_SUM 7
2165 #define LD_HDR 8
2166 #define IM_FID 9
2167 #define IM_SEQ 10
2168 #define IM_SAP 11
2169 #define IM_R1 12
2170 #define IM_CTL 13
2171 #define LD_LEN 14
2172 #define ST_FLG 15
2174 /* match setp #s for IP4TCP4 */
2175 #define S1_PCKT 0
2176 #define S1_VLAN 1
2177 #define S1_CFI 2
2178 #define S1_8023 3
2179 #define S1_LLC 4
2180 #define S1_LLCc 5
2181 #define S1_IPV4 6
2182 #define S1_IPV4c 7
2183 #define S1_IPV4F 8
2184 #define S1_TCP44 9
2185 #define S1_IPV6 10
2186 #define S1_IPV6L 11
2187 #define S1_IPV6c 12
2188 #define S1_TCP64 13
2189 #define S1_TCPSQ 14
2190 #define S1_TCPFG 15
2191 #define S1_TCPHL 16
2192 #define S1_TCPHc 17
2193 #define S1_CLNP 18
2194 #define S1_CLNP2 19
2195 #define S1_DROP 20
2196 #define S2_HTTP 21
2197 #define S1_ESP4 22
2198 #define S1_AH4 23
2199 #define S1_ESP6 24
2200 #define S1_AH6 25
2202 #define CAS_PROG_IP46TCP4_PREAMBLE \
2204 CL_REG, 0x3ff, 1, 0x0, 0x0000}, \
2206 IM_CTL, 0x00a, 3, 0x0, 0xffff}, \
2208 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2210 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2212 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2214 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2216 LD_SAP, 0x100, 3, 0x0, 0xffff}, \
2218 LD_SUM, 0x00a, 1, 0x0, 0x0000}, \
2220 LD_LEN, 0x03e, 1, 0x0, 0xffff}, \
2224 LD_SUM, 0x015, 1, 0x0, 0x0000}, \
2226 IM_R1, 0x128, 1, 0x0, 0xffff}, \
2230 LD_LEN, 0x03f, 1, 0x0, 0xffff}
2232 #ifdef USE_HP_IP46TCP4
2234 CAS_PROG_IP46TCP4_PREAMBLE,
2251 };
2252 #ifdef HP_IP46TCP4_DEFAULT
2253 #define CAS_HP_FIRMWARE cas_prog_ip46tcp4tab
2254 #endif
2255 #endif
2257 /*
2258 * Alternate table load which excludes HTTP server traffic from reassembly.
2259 * It is substantially similar to the basic table, with one extra state
2260 * and a few extra compares. */
2261 #ifdef USE_HP_IP46TCP4NOHTTP
2263 CAS_PROG_IP46TCP4_PREAMBLE,
2282 };
2283 #ifdef HP_IP46TCP4NOHTTP_DEFAULT
2284 #define CAS_HP_FIRMWARE cas_prog_ip46tcp4nohttptab
2285 #endif
2286 #endif
2288 /* match step #s for IP4FRAG */
2289 #define S3_IPV6c 11
2290 #define S3_TCP64 12
2291 #define S3_TCPSQ 13
2292 #define S3_TCPFG 14
2293 #define S3_TCPHL 15
2294 #define S3_TCPHc 16
2295 #define S3_FRAG 17
2296 #define S3_FOFF 18
2297 #define S3_CLNP 19
2299 #ifdef USE_HP_IP4FRAG
2343 };
2344 #ifdef HP_IP4FRAG_DEFAULT
2345 #define CAS_HP_FIRMWARE cas_prog_ip4fragtab
2346 #endif
2347 #endif
2349 /*
2350 * Alternate table which does batching without reassembly
2351 */
2352 #ifdef USE_HP_IP46TCP4BATCH
2354 CAS_PROG_IP46TCP4_PREAMBLE,
2369 };
2370 #ifdef HP_IP46TCP4BATCH_DEFAULT
2371 #define CAS_HP_FIRMWARE cas_prog_ip46tcp4batchtab
2372 #endif
2373 #endif
2375 /* Workaround for Cassini rev2 descriptor corruption problem.
2376 * Does batching without reassembly, and sets the SAP to a known
2377 * data pattern for all packets.
2378 */
2379 #ifdef USE_HP_WORKAROUND
2423 };
2424 #ifdef HP_WORKAROUND_DEFAULT
2425 #define CAS_HP_FIRMWARE cas_prog_workaroundtab
2426 #endif
2427 #endif
2429 #ifdef USE_HP_ENCRYPT
2435 #if 0
2436 //"CFI?", /* 02 FIND CFI and If FIND go to S1_DROP */
2437 //0x1000, 0x1000, OP_EQ, 0, S1_DROP, 1, S1_8023, CL_REG, 0x000, 0, 0x0, 0x00
2439 #endif
2464 #if 0
2465 //@@@0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_ESP6, LD_LEN, 0x03f, 1, 0x0, 0xffff,
2466 #endif
2493 #if 0
2494 //@@@0x00ff, 0x0032, OP_EQ, 0, S1_CLNP2, 0, S1_AH6, IM_CTL, 0x021, 1, 0x0, 0xffff,
2495 #endif
2499 #if 0
2500 //@@@0x00ff, 0x0033, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL, 0x021, 1, 0x0, 0xffff,
2501 #endif
2505 };
2506 #ifdef HP_ENCRYPT_DEFAULT
2507 #define CAS_HP_FIRMWARE cas_prog_encryptiontab
2508 #endif
2509 #endif
2512 #ifdef HP_NULL_DEFAULT
2513 #define CAS_HP_FIRMWARE cas_prog_null
2514 #endif
2516 /* phy types */
2517 #define CAS_PHY_UNKNOWN 0x00
2518 #define CAS_PHY_SERDES 0x01
2519 #define CAS_PHY_MII_MDIO0 0x02
2520 #define CAS_PHY_MII_MDIO1 0x04
2521 #define CAS_PHY_MII(x) ((x) & (CAS_PHY_MII_MDIO0 | CAS_PHY_MII_MDIO1))
2523 /* _RING_INDEX is the index for the ring sizes to be used. _RING_SIZE
2524 * is the actual size. the default index for the various rings is
2525 * 8. NOTE: there a bunch of alignment constraints for the rings. to
2526 * deal with that, i just allocate rings to create the desired
2527 * alignment. here are the constraints:
2528 * RX DESC and COMP rings must be 8KB aligned
2529 * TX DESC must be 2KB aligned.
2530 * if you change the numbers, be cognizant of how the alignment will change
2531 * in INIT_BLOCK as well.
2532 */
2534 #define DESC_RING_I_TO_S(x) (32*(1 << (x)))
2535 #define COMP_RING_I_TO_S(x) (128*(1 << (x)))
2540 #if (TX_DESC_RING_INDEX > 8) || (TX_DESC_RING_INDEX < 0)
2541 #error TX_DESC_RING_INDEX must be between 0 and 8
2542 #endif
2544 #if (RX_DESC_RING_INDEX > 8) || (RX_DESC_RING_INDEX < 0)
2545 #error RX_DESC_RING_INDEX must be between 0 and 8
2546 #endif
2548 #if (RX_COMP_RING_INDEX > 8) || (RX_COMP_RING_INDEX < 0)
2549 #error RX_COMP_RING_INDEX must be between 0 and 8
2550 #endif
2553 #define N_TX_RINGS_MASK MAX_TX_RINGS_MASK
2557 /* number of flows that can go through re-assembly */
2558 #define N_RX_FLOWS 64
2560 #define TX_DESC_RING_SIZE DESC_RING_I_TO_S(TX_DESC_RING_INDEX)
2561 #define RX_DESC_RING_SIZE DESC_RING_I_TO_S(RX_DESC_RING_INDEX)
2562 #define RX_COMP_RING_SIZE COMP_RING_I_TO_S(RX_COMP_RING_INDEX)
2563 #define TX_DESC_RINGN_INDEX(x) TX_DESC_RING_INDEX
2564 #define RX_DESC_RINGN_INDEX(x) RX_DESC_RING_INDEX
2565 #define RX_COMP_RINGN_INDEX(x) RX_COMP_RING_INDEX
2566 #define TX_DESC_RINGN_SIZE(x) TX_DESC_RING_SIZE
2567 #define RX_DESC_RINGN_SIZE(x) RX_DESC_RING_SIZE
2568 #define RX_COMP_RINGN_SIZE(x) RX_COMP_RING_SIZE
2570 /* convert values */
2571 #define CAS_BASE(x, y) (((y) << (x ## _SHIFT)) & (x ## _MASK))
2572 #define CAS_VAL(x, y) (((y) & (x ## _MASK)) >> (x ## _SHIFT))
2573 #define CAS_TX_RINGN_BASE(y) ((TX_DESC_RINGN_INDEX(y) << \
2574 TX_CFG_DESC_RINGN_SHIFT(y)) & \
2575 TX_CFG_DESC_RINGN_MASK(y))
2577 /* min is 2k, but we can't do jumbo frames unless it's at least 8k */
2583 bytes. 0 - 9256 */
2584 #define TX_DESC_BUFLEN_SHIFT 0
2586 of bytes to be
2587 skipped before
2588 csum calc begins.
2589 value must be
2590 even */
2591 #define TX_DESC_CSUM_START_SHIFT 15
2593 byte offset w/in
2594 the pkt for the
2595 1st csum byte.
2596 must be > 8 */
2597 #define TX_DESC_CSUM_STUFF_SHIFT 21
2603 CRC will not be
2604 inserted into
2605 outgoing frame. */
2607 __le64 control;
2608 __le64 buffer;
2609 };
2611 /* descriptor ring for free buffers contains page-sized buffers. the index
2612 * value is not used by the hw in any way. it's just stored and returned in
2613 * the completion ring.
2614 */
2616 __le64 index;
2617 __le64 buffer;
2618 };
2620 /* received packets are put on the completion ring. */
2621 /* word 1 */
2622 #define RX_COMP1_DATA_SIZE_MASK 0x0000000007FFE000ULL
2623 #define RX_COMP1_DATA_SIZE_SHIFT 13
2624 #define RX_COMP1_DATA_OFF_MASK 0x000001FFF8000000ULL
2625 #define RX_COMP1_DATA_OFF_SHIFT 27
2626 #define RX_COMP1_DATA_INDEX_MASK 0x007FFE0000000000ULL
2627 #define RX_COMP1_DATA_INDEX_SHIFT 41
2628 #define RX_COMP1_SKIP_MASK 0x0180000000000000ULL
2629 #define RX_COMP1_SKIP_SHIFT 55
2630 #define RX_COMP1_RELEASE_NEXT 0x0200000000000000ULL
2631 #define RX_COMP1_SPLIT_PKT 0x0400000000000000ULL
2632 #define RX_COMP1_RELEASE_FLOW 0x0800000000000000ULL
2633 #define RX_COMP1_RELEASE_DATA 0x1000000000000000ULL
2634 #define RX_COMP1_RELEASE_HDR 0x2000000000000000ULL
2635 #define RX_COMP1_TYPE_MASK 0xC000000000000000ULL
2636 #define RX_COMP1_TYPE_SHIFT 62
2638 /* word 2 */
2639 #define RX_COMP2_NEXT_INDEX_MASK 0x00000007FFE00000ULL
2640 #define RX_COMP2_NEXT_INDEX_SHIFT 21
2641 #define RX_COMP2_HDR_SIZE_MASK 0x00000FF800000000ULL
2642 #define RX_COMP2_HDR_SIZE_SHIFT 35
2643 #define RX_COMP2_HDR_OFF_MASK 0x0003F00000000000ULL
2644 #define RX_COMP2_HDR_OFF_SHIFT 44
2645 #define RX_COMP2_HDR_INDEX_MASK 0xFFFC000000000000ULL
2646 #define RX_COMP2_HDR_INDEX_SHIFT 50
2648 /* word 3 */
2649 #define RX_COMP3_SMALL_PKT 0x0000000000000001ULL
2650 #define RX_COMP3_JUMBO_PKT 0x0000000000000002ULL
2651 #define RX_COMP3_JUMBO_HDR_SPLIT_EN 0x0000000000000004ULL
2652 #define RX_COMP3_CSUM_START_MASK 0x000000000007F000ULL
2653 #define RX_COMP3_CSUM_START_SHIFT 12
2654 #define RX_COMP3_FLOWID_MASK 0x0000000001F80000ULL
2655 #define RX_COMP3_FLOWID_SHIFT 19
2656 #define RX_COMP3_OPCODE_MASK 0x000000000E000000ULL
2657 #define RX_COMP3_OPCODE_SHIFT 25
2658 #define RX_COMP3_FORCE_FLAG 0x0000000010000000ULL
2659 #define RX_COMP3_NO_ASSIST 0x0000000020000000ULL
2660 #define RX_COMP3_LOAD_BAL_MASK 0x000001F800000000ULL
2661 #define RX_COMP3_LOAD_BAL_SHIFT 35
2664 #define RX_COMP3_L3_HEAD_OFF_SHIFT 41
2666 #define RX_PLUS_COMP_L3_HEAD_OFF_SHIFT 42
2667 #define RX_COMP3_SAP_MASK 0xFFFF000000000000ULL
2668 #define RX_COMP3_SAP_SHIFT 48
2670 /* word 4 */
2671 #define RX_COMP4_TCP_CSUM_MASK 0x000000000000FFFFULL
2672 #define RX_COMP4_TCP_CSUM_SHIFT 0
2673 #define RX_COMP4_PKT_LEN_MASK 0x000000003FFF0000ULL
2674 #define RX_COMP4_PKT_LEN_SHIFT 16
2675 #define RX_COMP4_PERFECT_MATCH_MASK 0x00000003C0000000ULL
2676 #define RX_COMP4_PERFECT_MATCH_SHIFT 30
2677 #define RX_COMP4_ZERO 0x0000080000000000ULL
2678 #define RX_COMP4_HASH_VAL_MASK 0x0FFFF00000000000ULL
2679 #define RX_COMP4_HASH_VAL_SHIFT 44
2680 #define RX_COMP4_HASH_PASS 0x1000000000000000ULL
2681 #define RX_COMP4_BAD 0x4000000000000000ULL
2682 #define RX_COMP4_LEN_MISMATCH 0x8000000000000000ULL
2684 /* we encode the following: ring/index/release. only 14 bits
2685 * are usable.
2686 * NOTE: the encoding is dependent upon RX_DESC_RING_SIZE and
2687 * MAX_RX_DESC_RINGS. */
2688 #define RX_INDEX_NUM_MASK 0x0000000000000FFFULL
2689 #define RX_INDEX_NUM_SHIFT 0
2690 #define RX_INDEX_RING_MASK 0x0000000000001000ULL
2691 #define RX_INDEX_RING_SHIFT 12
2692 #define RX_INDEX_RELEASE 0x0000000000002000ULL
2695 __le64 word1;
2696 __le64 word2;
2697 __le64 word3;
2698 __le64 word4;
2699 };
2707 link_up /* Link is up */
2708 };
2713 dma_addr_t dma_addr;
2718 /* some alignment constraints:
2719 * TX DESC, RX DESC, and RX COMP must each be 8K aligned.
2720 * TX COMPWB must be 8-byte aligned.
2721 * to accomplish this, here's what we do:
2722 *
2723 * INIT_BLOCK_RX_COMP = 64k (already aligned)
2724 * INIT_BLOCK_RX_DESC = 8k
2725 * INIT_BLOCK_TX = 8k
2726 * INIT_BLOCK_RX1_DESC = 8k
2727 * TX COMPWB
2728 */
2729 #define INIT_BLOCK_TX (TX_DESC_RING_SIZE)
2730 #define INIT_BLOCK_RX_DESC (RX_DESC_RING_SIZE)
2731 #define INIT_BLOCK_RX_COMP (RX_COMP_RING_SIZE)
2737 __le64 tx_compwb;
2738 };
2740 /* tiny buffers to deal with target abort issue. we allocate a bit
2741 * over so that we don't have target abort issues with these buffers
2742 * as well.
2743 */
2744 #define TX_TINY_BUF_LEN 0x100
2745 #define TX_TINY_BUF_BLOCK ((INIT_BLOCK_TX + 1)*TX_TINY_BUF_LEN)
2750 };
2767 /* Set when chip is actually in operational state
2768 * (ie. not power managed) */
2778 /* we use sk_buffs for tx and pages for rx. the rx skbuffs
2779 * are there for flow re-assembly. */
2786 /* for small packets when copying would be quicker than
2787 mapping */
2791 u32 msg_enable;
2793 /* N_TX_RINGS must be >= N_RX_DESC_RINGS */
2797 u8 pci_revision;
2801 u32 phy_id;
2802 #define CAS_FLAG_1000MB_CAP 0x00000001
2803 #define CAS_FLAG_REG_PLUS 0x00000002
2804 #define CAS_FLAG_TARGET_ABORT 0x00000004
2805 #define CAS_FLAG_SATURN 0x00000008
2806 #define CAS_FLAG_RXD_POST_MASK 0x000000F0
2807 #define CAS_FLAG_RXD_POST_SHIFT 4
2808 #define CAS_FLAG_RXD_POST(x) ((1 << (CAS_FLAG_RXD_POST_SHIFT + (x))) & \
2809 CAS_FLAG_RXD_POST_MASK)
2810 #define CAS_FLAG_ENTROPY_DEV 0x00000100
2811 #define CAS_FLAG_NO_HW_CSUM 0x00000200
2812 u32 cas_flags;
2823 /* page size allocation */
2828 u32 mac_rx_cfg;
2830 /* Autoneg & PHY control */
2837 #if 0
2838 atomic_t reset_task_pending;
2839 #else
2840 atomic_t reset_task_pending;
2841 atomic_t reset_task_pending_mtu;
2842 atomic_t reset_task_pending_spare;
2843 atomic_t reset_task_pending_all;
2844 #endif
2846 /* Link-down problem workaround */
2847 #define LINK_TRANSITION_UNKNOWN 0
2848 #define LINK_TRANSITION_ON_FAILURE 1
2849 #define LINK_TRANSITION_STILL_FAILED 2
2850 #define LINK_TRANSITION_LINK_UP 3
2851 #define LINK_TRANSITION_LINK_CONFIG 4
2852 #define LINK_TRANSITION_LINK_DOWN 5
2853 #define LINK_TRANSITION_REQUESTED_RESET 6
2858 /* Tuning */
2862 /* Diagnostic counters and state. */
2864 u64 pause_entered;
2865 u16 pause_last_time_recvd;
2870 #if defined(CONFIG_OF)
2872 #endif
2874 /* Firmware Info */
2875 u16 fw_load_addr;
2876 u32 fw_size;
2878 };
2880 #define TX_DESC_NEXT(r, x) (((x) + 1) & (TX_DESC_RINGN_SIZE(r) - 1))
2881 #define RX_DESC_ENTRY(r, x) ((x) & (RX_DESC_RINGN_SIZE(r) - 1))
2882 #define RX_COMP_ENTRY(r, x) ((x) & (RX_COMP_RINGN_SIZE(r) - 1))
2884 #define TX_BUFF_COUNT(r, x, y) ((x) <= (y) ? ((y) - (x)) : \
2885 (TX_DESC_RINGN_SIZE(r) - (x) + (y)))
2887 #define TX_BUFFS_AVAIL(cp, i) ((cp)->tx_old[(i)] <= (cp)->tx_new[(i)] ? \
2888 (cp)->tx_old[(i)] + (TX_DESC_RINGN_SIZE(i) - 1) - (cp)->tx_new[(i)] : \
2889 (cp)->tx_old[(i)] - (cp)->tx_new[(i)] - 1)
2891 #define CAS_ALIGN(addr, align) \
2892 (((unsigned long) (addr) + ((align) - 1UL)) & ~((align) - 1))
2894 #define RX_FIFO_SIZE 16384
2895 #define EXPANSION_ROM_SIZE 65536
2897 #define CAS_MC_EXACT_MATCH_SIZE 15
2898 #define CAS_MC_HASH_SIZE 256
2899 #define CAS_MC_HASH_MAX (CAS_MC_EXACT_MATCH_SIZE + \
2900 CAS_MC_HASH_SIZE)
2902 #define TX_TARGET_ABORT_LEN 0x20
2903 #define RX_SWIVEL_OFF_VAL 0x2
2904 #define RX_AE_FREEN_VAL(x) (RX_DESC_RINGN_SIZE(x) >> 1)
2905 #define RX_AE_COMP_VAL (RX_COMP_RING_SIZE >> 1)
2906 #define RX_BLANK_INTR_PKT_VAL 0x05
2907 #define RX_BLANK_INTR_TIME_VAL 0x0F
2910 #define RX_SPARE_COUNT (RX_DESC_RING_SIZE >> 1)
2911 #define RX_SPARE_RECOVER_VAL (RX_SPARE_COUNT >> 2)