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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[cris-mirror.git] / drivers / net / ethernet / sun / niu.c
blob8dd545fed30d2aa62f2dd6940ac44f8b33a951f3
1 // SPDX-License-Identifier: GPL-2.0
2 /* niu.c: Neptune ethernet driver.
3 *
4 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
5 */
6
7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/pci.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/netdevice.h>
15 #include <linux/ethtool.h>
16 #include <linux/etherdevice.h>
17 #include <linux/platform_device.h>
18 #include <linux/delay.h>
19 #include <linux/bitops.h>
20 #include <linux/mii.h>
21 #include <linux/if.h>
22 #include <linux/if_ether.h>
23 #include <linux/if_vlan.h>
24 #include <linux/ip.h>
25 #include <linux/in.h>
26 #include <linux/ipv6.h>
27 #include <linux/log2.h>
28 #include <linux/jiffies.h>
29 #include <linux/crc32.h>
30 #include <linux/list.h>
31 #include <linux/slab.h>
32
33 #include <linux/io.h>
34 #include <linux/of_device.h>
35
36 #include "niu.h"
37
38 #define DRV_MODULE_NAME "niu"
39 #define DRV_MODULE_VERSION "1.1"
40 #define DRV_MODULE_RELDATE "Apr 22, 2010"
41
42 static char version[] =
43 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
44
45 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
46 MODULE_DESCRIPTION("NIU ethernet driver");
47 MODULE_LICENSE("GPL");
48 MODULE_VERSION(DRV_MODULE_VERSION);
49
50 #ifndef readq
51 static u64 readq(void __iomem *reg)
52 {
53 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
54 }
55
56 static void writeq(u64 val, void __iomem *reg)
57 {
58 writel(val & 0xffffffff, reg);
59 writel(val >> 32, reg + 0x4UL);
60 }
61 #endif
62
63 static const struct pci_device_id niu_pci_tbl[] = {
64 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
65 {}
66 };
67
68 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
69
70 #define NIU_TX_TIMEOUT (5 * HZ)
71
72 #define nr64(reg) readq(np->regs + (reg))
73 #define nw64(reg, val) writeq((val), np->regs + (reg))
74
75 #define nr64_mac(reg) readq(np->mac_regs + (reg))
76 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
77
78 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
79 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
80
81 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
82 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
83
84 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
85 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
86
87 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
88
89 static int niu_debug;
90 static int debug = -1;
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "NIU debug level");
93
94 #define niu_lock_parent(np, flags) \
95 spin_lock_irqsave(&np->parent->lock, flags)
96 #define niu_unlock_parent(np, flags) \
97 spin_unlock_irqrestore(&np->parent->lock, flags)
98
99 static int serdes_init_10g_serdes(struct niu *np);
100
101 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
102 u64 bits, int limit, int delay)
103 {
104 while (--limit >= 0) {
105 u64 val = nr64_mac(reg);
106
107 if (!(val & bits))
108 break;
109 udelay(delay);
110 }
111 if (limit < 0)
112 return -ENODEV;
113 return 0;
114 }
115
116 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
117 u64 bits, int limit, int delay,
118 const char *reg_name)
119 {
120 int err;
121
122 nw64_mac(reg, bits);
123 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
124 if (err)
125 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
126 (unsigned long long)bits, reg_name,
127 (unsigned long long)nr64_mac(reg));
128 return err;
129 }
130
131 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
132 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
133 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
134 })
135
136 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
137 u64 bits, int limit, int delay)
138 {
139 while (--limit >= 0) {
140 u64 val = nr64_ipp(reg);
141
142 if (!(val & bits))
143 break;
144 udelay(delay);
145 }
146 if (limit < 0)
147 return -ENODEV;
148 return 0;
149 }
150
151 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
152 u64 bits, int limit, int delay,
153 const char *reg_name)
154 {
155 int err;
156 u64 val;
157
158 val = nr64_ipp(reg);
159 val |= bits;
160 nw64_ipp(reg, val);
161
162 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
163 if (err)
164 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
165 (unsigned long long)bits, reg_name,
166 (unsigned long long)nr64_ipp(reg));
167 return err;
168 }
169
170 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
171 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
172 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
173 })
174
175 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
176 u64 bits, int limit, int delay)
177 {
178 while (--limit >= 0) {
179 u64 val = nr64(reg);
180
181 if (!(val & bits))
182 break;
183 udelay(delay);
184 }
185 if (limit < 0)
186 return -ENODEV;
187 return 0;
188 }
189
190 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
191 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
192 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
193 })
194
195 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
196 u64 bits, int limit, int delay,
197 const char *reg_name)
198 {
199 int err;
200
201 nw64(reg, bits);
202 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
203 if (err)
204 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
205 (unsigned long long)bits, reg_name,
206 (unsigned long long)nr64(reg));
207 return err;
208 }
209
210 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
211 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
212 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
213 })
214
215 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
216 {
217 u64 val = (u64) lp->timer;
218
219 if (on)
220 val |= LDG_IMGMT_ARM;
221
222 nw64(LDG_IMGMT(lp->ldg_num), val);
223 }
224
225 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
226 {
227 unsigned long mask_reg, bits;
228 u64 val;
229
230 if (ldn < 0 || ldn > LDN_MAX)
231 return -EINVAL;
232
233 if (ldn < 64) {
234 mask_reg = LD_IM0(ldn);
235 bits = LD_IM0_MASK;
236 } else {
237 mask_reg = LD_IM1(ldn - 64);
238 bits = LD_IM1_MASK;
239 }
240
241 val = nr64(mask_reg);
242 if (on)
243 val &= ~bits;
244 else
245 val |= bits;
246 nw64(mask_reg, val);
247
248 return 0;
249 }
250
251 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
252 {
253 struct niu_parent *parent = np->parent;
254 int i;
255
256 for (i = 0; i <= LDN_MAX; i++) {
257 int err;
258
259 if (parent->ldg_map[i] != lp->ldg_num)
260 continue;
261
262 err = niu_ldn_irq_enable(np, i, on);
263 if (err)
264 return err;
265 }
266 return 0;
267 }
268
269 static int niu_enable_interrupts(struct niu *np, int on)
270 {
271 int i;
272
273 for (i = 0; i < np->num_ldg; i++) {
274 struct niu_ldg *lp = &np->ldg[i];
275 int err;
276
277 err = niu_enable_ldn_in_ldg(np, lp, on);
278 if (err)
279 return err;
280 }
281 for (i = 0; i < np->num_ldg; i++)
282 niu_ldg_rearm(np, &np->ldg[i], on);
283
284 return 0;
285 }
286
287 static u32 phy_encode(u32 type, int port)
288 {
289 return type << (port * 2);
290 }
291
292 static u32 phy_decode(u32 val, int port)
293 {
294 return (val >> (port * 2)) & PORT_TYPE_MASK;
295 }
296
297 static int mdio_wait(struct niu *np)
298 {
299 int limit = 1000;
300 u64 val;
301
302 while (--limit > 0) {
303 val = nr64(MIF_FRAME_OUTPUT);
304 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
305 return val & MIF_FRAME_OUTPUT_DATA;
306
307 udelay(10);
308 }
309
310 return -ENODEV;
311 }
312
313 static int mdio_read(struct niu *np, int port, int dev, int reg)
314 {
315 int err;
316
317 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
318 err = mdio_wait(np);
319 if (err < 0)
320 return err;
321
322 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
323 return mdio_wait(np);
324 }
325
326 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
327 {
328 int err;
329
330 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
331 err = mdio_wait(np);
332 if (err < 0)
333 return err;
334
335 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
336 err = mdio_wait(np);
337 if (err < 0)
338 return err;
339
340 return 0;
341 }
342
343 static int mii_read(struct niu *np, int port, int reg)
344 {
345 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
346 return mdio_wait(np);
347 }
348
349 static int mii_write(struct niu *np, int port, int reg, int data)
350 {
351 int err;
352
353 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
354 err = mdio_wait(np);
355 if (err < 0)
356 return err;
357
358 return 0;
359 }
360
361 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
362 {
363 int err;
364
365 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
366 ESR2_TI_PLL_TX_CFG_L(channel),
367 val & 0xffff);
368 if (!err)
369 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
370 ESR2_TI_PLL_TX_CFG_H(channel),
371 val >> 16);
372 return err;
373 }
374
375 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
376 {
377 int err;
378
379 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
380 ESR2_TI_PLL_RX_CFG_L(channel),
381 val & 0xffff);
382 if (!err)
383 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
384 ESR2_TI_PLL_RX_CFG_H(channel),
385 val >> 16);
386 return err;
387 }
388
389 /* Mode is always 10G fiber. */
390 static int serdes_init_niu_10g_fiber(struct niu *np)
391 {
392 struct niu_link_config *lp = &np->link_config;
393 u32 tx_cfg, rx_cfg;
394 unsigned long i;
395
396 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
397 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
398 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
399 PLL_RX_CFG_EQ_LP_ADAPTIVE);
400
401 if (lp->loopback_mode == LOOPBACK_PHY) {
402 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
403
404 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
405 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
406
407 tx_cfg |= PLL_TX_CFG_ENTEST;
408 rx_cfg |= PLL_RX_CFG_ENTEST;
409 }
410
411 /* Initialize all 4 lanes of the SERDES. */
412 for (i = 0; i < 4; i++) {
413 int err = esr2_set_tx_cfg(np, i, tx_cfg);
414 if (err)
415 return err;
416 }
417
418 for (i = 0; i < 4; i++) {
419 int err = esr2_set_rx_cfg(np, i, rx_cfg);
420 if (err)
421 return err;
422 }
423
424 return 0;
425 }
426
427 static int serdes_init_niu_1g_serdes(struct niu *np)
428 {
429 struct niu_link_config *lp = &np->link_config;
430 u16 pll_cfg, pll_sts;
431 int max_retry = 100;
432 u64 uninitialized_var(sig), mask, val;
433 u32 tx_cfg, rx_cfg;
434 unsigned long i;
435 int err;
436
437 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
438 PLL_TX_CFG_RATE_HALF);
439 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
440 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
441 PLL_RX_CFG_RATE_HALF);
442
443 if (np->port == 0)
444 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
445
446 if (lp->loopback_mode == LOOPBACK_PHY) {
447 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
448
449 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
450 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
451
452 tx_cfg |= PLL_TX_CFG_ENTEST;
453 rx_cfg |= PLL_RX_CFG_ENTEST;
454 }
455
456 /* Initialize PLL for 1G */
457 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
458
459 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
460 ESR2_TI_PLL_CFG_L, pll_cfg);
461 if (err) {
462 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
463 np->port, __func__);
464 return err;
465 }
466
467 pll_sts = PLL_CFG_ENPLL;
468
469 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
470 ESR2_TI_PLL_STS_L, pll_sts);
471 if (err) {
472 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
473 np->port, __func__);
474 return err;
475 }
476
477 udelay(200);
478
479 /* Initialize all 4 lanes of the SERDES. */
480 for (i = 0; i < 4; i++) {
481 err = esr2_set_tx_cfg(np, i, tx_cfg);
482 if (err)
483 return err;
484 }
485
486 for (i = 0; i < 4; i++) {
487 err = esr2_set_rx_cfg(np, i, rx_cfg);
488 if (err)
489 return err;
490 }
491
492 switch (np->port) {
493 case 0:
494 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
495 mask = val;
496 break;
497
498 case 1:
499 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
500 mask = val;
501 break;
502
503 default:
504 return -EINVAL;
505 }
506
507 while (max_retry--) {
508 sig = nr64(ESR_INT_SIGNALS);
509 if ((sig & mask) == val)
510 break;
511
512 mdelay(500);
513 }
514
515 if ((sig & mask) != val) {
516 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
517 np->port, (int)(sig & mask), (int)val);
518 return -ENODEV;
519 }
520
521 return 0;
522 }
523
524 static int serdes_init_niu_10g_serdes(struct niu *np)
525 {
526 struct niu_link_config *lp = &np->link_config;
527 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
528 int max_retry = 100;
529 u64 uninitialized_var(sig), mask, val;
530 unsigned long i;
531 int err;
532
533 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
534 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
535 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
536 PLL_RX_CFG_EQ_LP_ADAPTIVE);
537
538 if (lp->loopback_mode == LOOPBACK_PHY) {
539 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
540
541 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
542 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
543
544 tx_cfg |= PLL_TX_CFG_ENTEST;
545 rx_cfg |= PLL_RX_CFG_ENTEST;
546 }
547
548 /* Initialize PLL for 10G */
549 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
550
551 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
552 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
553 if (err) {
554 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
555 np->port, __func__);
556 return err;
557 }
558
559 pll_sts = PLL_CFG_ENPLL;
560
561 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
562 ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
563 if (err) {
564 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
565 np->port, __func__);
566 return err;
567 }
568
569 udelay(200);
570
571 /* Initialize all 4 lanes of the SERDES. */
572 for (i = 0; i < 4; i++) {
573 err = esr2_set_tx_cfg(np, i, tx_cfg);
574 if (err)
575 return err;
576 }
577
578 for (i = 0; i < 4; i++) {
579 err = esr2_set_rx_cfg(np, i, rx_cfg);
580 if (err)
581 return err;
582 }
583
584 /* check if serdes is ready */
585
586 switch (np->port) {
587 case 0:
588 mask = ESR_INT_SIGNALS_P0_BITS;
589 val = (ESR_INT_SRDY0_P0 |
590 ESR_INT_DET0_P0 |
591 ESR_INT_XSRDY_P0 |
592 ESR_INT_XDP_P0_CH3 |
593 ESR_INT_XDP_P0_CH2 |
594 ESR_INT_XDP_P0_CH1 |
595 ESR_INT_XDP_P0_CH0);
596 break;
597
598 case 1:
599 mask = ESR_INT_SIGNALS_P1_BITS;
600 val = (ESR_INT_SRDY0_P1 |
601 ESR_INT_DET0_P1 |
602 ESR_INT_XSRDY_P1 |
603 ESR_INT_XDP_P1_CH3 |
604 ESR_INT_XDP_P1_CH2 |
605 ESR_INT_XDP_P1_CH1 |
606 ESR_INT_XDP_P1_CH0);
607 break;
608
609 default:
610 return -EINVAL;
611 }
612
613 while (max_retry--) {
614 sig = nr64(ESR_INT_SIGNALS);
615 if ((sig & mask) == val)
616 break;
617
618 mdelay(500);
619 }
620
621 if ((sig & mask) != val) {
622 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
623 np->port, (int)(sig & mask), (int)val);
624
625 /* 10G failed, try initializing at 1G */
626 err = serdes_init_niu_1g_serdes(np);
627 if (!err) {
628 np->flags &= ~NIU_FLAGS_10G;
629 np->mac_xcvr = MAC_XCVR_PCS;
630 } else {
631 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
632 np->port);
633 return -ENODEV;
634 }
635 }
636 return 0;
637 }
638
639 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
640 {
641 int err;
642
643 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
644 if (err >= 0) {
645 *val = (err & 0xffff);
646 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
647 ESR_RXTX_CTRL_H(chan));
648 if (err >= 0)
649 *val |= ((err & 0xffff) << 16);
650 err = 0;
651 }
652 return err;
653 }
654
655 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
656 {
657 int err;
658
659 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
660 ESR_GLUE_CTRL0_L(chan));
661 if (err >= 0) {
662 *val = (err & 0xffff);
663 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
664 ESR_GLUE_CTRL0_H(chan));
665 if (err >= 0) {
666 *val |= ((err & 0xffff) << 16);
667 err = 0;
668 }
669 }
670 return err;
671 }
672
673 static int esr_read_reset(struct niu *np, u32 *val)
674 {
675 int err;
676
677 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
678 ESR_RXTX_RESET_CTRL_L);
679 if (err >= 0) {
680 *val = (err & 0xffff);
681 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
682 ESR_RXTX_RESET_CTRL_H);
683 if (err >= 0) {
684 *val |= ((err & 0xffff) << 16);
685 err = 0;
686 }
687 }
688 return err;
689 }
690
691 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
692 {
693 int err;
694
695 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
696 ESR_RXTX_CTRL_L(chan), val & 0xffff);
697 if (!err)
698 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
699 ESR_RXTX_CTRL_H(chan), (val >> 16));
700 return err;
701 }
702
703 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
704 {
705 int err;
706
707 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
708 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
709 if (!err)
710 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
711 ESR_GLUE_CTRL0_H(chan), (val >> 16));
712 return err;
713 }
714
715 static int esr_reset(struct niu *np)
716 {
717 u32 uninitialized_var(reset);
718 int err;
719
720 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
721 ESR_RXTX_RESET_CTRL_L, 0x0000);
722 if (err)
723 return err;
724 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
725 ESR_RXTX_RESET_CTRL_H, 0xffff);
726 if (err)
727 return err;
728 udelay(200);
729
730 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
731 ESR_RXTX_RESET_CTRL_L, 0xffff);
732 if (err)
733 return err;
734 udelay(200);
735
736 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
737 ESR_RXTX_RESET_CTRL_H, 0x0000);
738 if (err)
739 return err;
740 udelay(200);
741
742 err = esr_read_reset(np, &reset);
743 if (err)
744 return err;
745 if (reset != 0) {
746 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
747 np->port, reset);
748 return -ENODEV;
749 }
750
751 return 0;
752 }
753
754 static int serdes_init_10g(struct niu *np)
755 {
756 struct niu_link_config *lp = &np->link_config;
757 unsigned long ctrl_reg, test_cfg_reg, i;
758 u64 ctrl_val, test_cfg_val, sig, mask, val;
759 int err;
760
761 switch (np->port) {
762 case 0:
763 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
764 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
765 break;
766 case 1:
767 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
768 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
769 break;
770
771 default:
772 return -EINVAL;
773 }
774 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
775 ENET_SERDES_CTRL_SDET_1 |
776 ENET_SERDES_CTRL_SDET_2 |
777 ENET_SERDES_CTRL_SDET_3 |
778 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
779 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
780 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
781 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
782 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
783 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
784 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
785 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
786 test_cfg_val = 0;
787
788 if (lp->loopback_mode == LOOPBACK_PHY) {
789 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
790 ENET_SERDES_TEST_MD_0_SHIFT) |
791 (ENET_TEST_MD_PAD_LOOPBACK <<
792 ENET_SERDES_TEST_MD_1_SHIFT) |
793 (ENET_TEST_MD_PAD_LOOPBACK <<
794 ENET_SERDES_TEST_MD_2_SHIFT) |
795 (ENET_TEST_MD_PAD_LOOPBACK <<
796 ENET_SERDES_TEST_MD_3_SHIFT));
797 }
798
799 nw64(ctrl_reg, ctrl_val);
800 nw64(test_cfg_reg, test_cfg_val);
801
802 /* Initialize all 4 lanes of the SERDES. */
803 for (i = 0; i < 4; i++) {
804 u32 rxtx_ctrl, glue0;
805
806 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
807 if (err)
808 return err;
809 err = esr_read_glue0(np, i, &glue0);
810 if (err)
811 return err;
812
813 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
814 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
815 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
816
817 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
818 ESR_GLUE_CTRL0_THCNT |
819 ESR_GLUE_CTRL0_BLTIME);
820 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
821 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
822 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
823 (BLTIME_300_CYCLES <<
824 ESR_GLUE_CTRL0_BLTIME_SHIFT));
825
826 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
827 if (err)
828 return err;
829 err = esr_write_glue0(np, i, glue0);
830 if (err)
831 return err;
832 }
833
834 err = esr_reset(np);
835 if (err)
836 return err;
837
838 sig = nr64(ESR_INT_SIGNALS);
839 switch (np->port) {
840 case 0:
841 mask = ESR_INT_SIGNALS_P0_BITS;
842 val = (ESR_INT_SRDY0_P0 |
843 ESR_INT_DET0_P0 |
844 ESR_INT_XSRDY_P0 |
845 ESR_INT_XDP_P0_CH3 |
846 ESR_INT_XDP_P0_CH2 |
847 ESR_INT_XDP_P0_CH1 |
848 ESR_INT_XDP_P0_CH0);
849 break;
850
851 case 1:
852 mask = ESR_INT_SIGNALS_P1_BITS;
853 val = (ESR_INT_SRDY0_P1 |
854 ESR_INT_DET0_P1 |
855 ESR_INT_XSRDY_P1 |
856 ESR_INT_XDP_P1_CH3 |
857 ESR_INT_XDP_P1_CH2 |
858 ESR_INT_XDP_P1_CH1 |
859 ESR_INT_XDP_P1_CH0);
860 break;
861
862 default:
863 return -EINVAL;
864 }
865
866 if ((sig & mask) != val) {
867 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
868 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
869 return 0;
870 }
871 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
872 np->port, (int)(sig & mask), (int)val);
873 return -ENODEV;
874 }
875 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
876 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
877 return 0;
878 }
879
880 static int serdes_init_1g(struct niu *np)
881 {
882 u64 val;
883
884 val = nr64(ENET_SERDES_1_PLL_CFG);
885 val &= ~ENET_SERDES_PLL_FBDIV2;
886 switch (np->port) {
887 case 0:
888 val |= ENET_SERDES_PLL_HRATE0;
889 break;
890 case 1:
891 val |= ENET_SERDES_PLL_HRATE1;
892 break;
893 case 2:
894 val |= ENET_SERDES_PLL_HRATE2;
895 break;
896 case 3:
897 val |= ENET_SERDES_PLL_HRATE3;
898 break;
899 default:
900 return -EINVAL;
901 }
902 nw64(ENET_SERDES_1_PLL_CFG, val);
903
904 return 0;
905 }
906
907 static int serdes_init_1g_serdes(struct niu *np)
908 {
909 struct niu_link_config *lp = &np->link_config;
910 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
911 u64 ctrl_val, test_cfg_val, sig, mask, val;
912 int err;
913 u64 reset_val, val_rd;
914
915 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
916 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
917 ENET_SERDES_PLL_FBDIV0;
918 switch (np->port) {
919 case 0:
920 reset_val = ENET_SERDES_RESET_0;
921 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
922 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
923 pll_cfg = ENET_SERDES_0_PLL_CFG;
924 break;
925 case 1:
926 reset_val = ENET_SERDES_RESET_1;
927 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
928 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
929 pll_cfg = ENET_SERDES_1_PLL_CFG;
930 break;
931
932 default:
933 return -EINVAL;
934 }
935 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
936 ENET_SERDES_CTRL_SDET_1 |
937 ENET_SERDES_CTRL_SDET_2 |
938 ENET_SERDES_CTRL_SDET_3 |
939 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
940 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
941 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
942 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
943 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
944 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
945 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
946 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
947 test_cfg_val = 0;
948
949 if (lp->loopback_mode == LOOPBACK_PHY) {
950 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
951 ENET_SERDES_TEST_MD_0_SHIFT) |
952 (ENET_TEST_MD_PAD_LOOPBACK <<
953 ENET_SERDES_TEST_MD_1_SHIFT) |
954 (ENET_TEST_MD_PAD_LOOPBACK <<
955 ENET_SERDES_TEST_MD_2_SHIFT) |
956 (ENET_TEST_MD_PAD_LOOPBACK <<
957 ENET_SERDES_TEST_MD_3_SHIFT));
958 }
959
960 nw64(ENET_SERDES_RESET, reset_val);
961 mdelay(20);
962 val_rd = nr64(ENET_SERDES_RESET);
963 val_rd &= ~reset_val;
964 nw64(pll_cfg, val);
965 nw64(ctrl_reg, ctrl_val);
966 nw64(test_cfg_reg, test_cfg_val);
967 nw64(ENET_SERDES_RESET, val_rd);
968 mdelay(2000);
969
970 /* Initialize all 4 lanes of the SERDES. */
971 for (i = 0; i < 4; i++) {
972 u32 rxtx_ctrl, glue0;
973
974 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
975 if (err)
976 return err;
977 err = esr_read_glue0(np, i, &glue0);
978 if (err)
979 return err;
980
981 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
982 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
983 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
984
985 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
986 ESR_GLUE_CTRL0_THCNT |
987 ESR_GLUE_CTRL0_BLTIME);
988 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
989 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
990 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
991 (BLTIME_300_CYCLES <<
992 ESR_GLUE_CTRL0_BLTIME_SHIFT));
993
994 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
995 if (err)
996 return err;
997 err = esr_write_glue0(np, i, glue0);
998 if (err)
999 return err;
1000 }
1001
1002
1003 sig = nr64(ESR_INT_SIGNALS);
1004 switch (np->port) {
1005 case 0:
1006 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1007 mask = val;
1008 break;
1009
1010 case 1:
1011 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1012 mask = val;
1013 break;
1014
1015 default:
1016 return -EINVAL;
1017 }
1018
1019 if ((sig & mask) != val) {
1020 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1021 np->port, (int)(sig & mask), (int)val);
1022 return -ENODEV;
1023 }
1024
1025 return 0;
1026 }
1027
1028 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1029 {
1030 struct niu_link_config *lp = &np->link_config;
1031 int link_up;
1032 u64 val;
1033 u16 current_speed;
1034 unsigned long flags;
1035 u8 current_duplex;
1036
1037 link_up = 0;
1038 current_speed = SPEED_INVALID;
1039 current_duplex = DUPLEX_INVALID;
1040
1041 spin_lock_irqsave(&np->lock, flags);
1042
1043 val = nr64_pcs(PCS_MII_STAT);
1044
1045 if (val & PCS_MII_STAT_LINK_STATUS) {
1046 link_up = 1;
1047 current_speed = SPEED_1000;
1048 current_duplex = DUPLEX_FULL;
1049 }
1050
1051 lp->active_speed = current_speed;
1052 lp->active_duplex = current_duplex;
1053 spin_unlock_irqrestore(&np->lock, flags);
1054
1055 *link_up_p = link_up;
1056 return 0;
1057 }
1058
1059 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1060 {
1061 unsigned long flags;
1062 struct niu_link_config *lp = &np->link_config;
1063 int link_up = 0;
1064 int link_ok = 1;
1065 u64 val, val2;
1066 u16 current_speed;
1067 u8 current_duplex;
1068
1069 if (!(np->flags & NIU_FLAGS_10G))
1070 return link_status_1g_serdes(np, link_up_p);
1071
1072 current_speed = SPEED_INVALID;
1073 current_duplex = DUPLEX_INVALID;
1074 spin_lock_irqsave(&np->lock, flags);
1075
1076 val = nr64_xpcs(XPCS_STATUS(0));
1077 val2 = nr64_mac(XMAC_INTER2);
1078 if (val2 & 0x01000000)
1079 link_ok = 0;
1080
1081 if ((val & 0x1000ULL) && link_ok) {
1082 link_up = 1;
1083 current_speed = SPEED_10000;
1084 current_duplex = DUPLEX_FULL;
1085 }
1086 lp->active_speed = current_speed;
1087 lp->active_duplex = current_duplex;
1088 spin_unlock_irqrestore(&np->lock, flags);
1089 *link_up_p = link_up;
1090 return 0;
1091 }
1092
1093 static int link_status_mii(struct niu *np, int *link_up_p)
1094 {
1095 struct niu_link_config *lp = &np->link_config;
1096 int err;
1097 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1098 int supported, advertising, active_speed, active_duplex;
1099
1100 err = mii_read(np, np->phy_addr, MII_BMCR);
1101 if (unlikely(err < 0))
1102 return err;
1103 bmcr = err;
1104
1105 err = mii_read(np, np->phy_addr, MII_BMSR);
1106 if (unlikely(err < 0))
1107 return err;
1108 bmsr = err;
1109
1110 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1111 if (unlikely(err < 0))
1112 return err;
1113 advert = err;
1114
1115 err = mii_read(np, np->phy_addr, MII_LPA);
1116 if (unlikely(err < 0))
1117 return err;
1118 lpa = err;
1119
1120 if (likely(bmsr & BMSR_ESTATEN)) {
1121 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1122 if (unlikely(err < 0))
1123 return err;
1124 estatus = err;
1125
1126 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1127 if (unlikely(err < 0))
1128 return err;
1129 ctrl1000 = err;
1130
1131 err = mii_read(np, np->phy_addr, MII_STAT1000);
1132 if (unlikely(err < 0))
1133 return err;
1134 stat1000 = err;
1135 } else
1136 estatus = ctrl1000 = stat1000 = 0;
1137
1138 supported = 0;
1139 if (bmsr & BMSR_ANEGCAPABLE)
1140 supported |= SUPPORTED_Autoneg;
1141 if (bmsr & BMSR_10HALF)
1142 supported |= SUPPORTED_10baseT_Half;
1143 if (bmsr & BMSR_10FULL)
1144 supported |= SUPPORTED_10baseT_Full;
1145 if (bmsr & BMSR_100HALF)
1146 supported |= SUPPORTED_100baseT_Half;
1147 if (bmsr & BMSR_100FULL)
1148 supported |= SUPPORTED_100baseT_Full;
1149 if (estatus & ESTATUS_1000_THALF)
1150 supported |= SUPPORTED_1000baseT_Half;
1151 if (estatus & ESTATUS_1000_TFULL)
1152 supported |= SUPPORTED_1000baseT_Full;
1153 lp->supported = supported;
1154
1155 advertising = mii_adv_to_ethtool_adv_t(advert);
1156 advertising |= mii_ctrl1000_to_ethtool_adv_t(ctrl1000);
1157
1158 if (bmcr & BMCR_ANENABLE) {
1159 int neg, neg1000;
1160
1161 lp->active_autoneg = 1;
1162 advertising |= ADVERTISED_Autoneg;
1163
1164 neg = advert & lpa;
1165 neg1000 = (ctrl1000 << 2) & stat1000;
1166
1167 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1168 active_speed = SPEED_1000;
1169 else if (neg & LPA_100)
1170 active_speed = SPEED_100;
1171 else if (neg & (LPA_10HALF | LPA_10FULL))
1172 active_speed = SPEED_10;
1173 else
1174 active_speed = SPEED_INVALID;
1175
1176 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1177 active_duplex = DUPLEX_FULL;
1178 else if (active_speed != SPEED_INVALID)
1179 active_duplex = DUPLEX_HALF;
1180 else
1181 active_duplex = DUPLEX_INVALID;
1182 } else {
1183 lp->active_autoneg = 0;
1184
1185 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1186 active_speed = SPEED_1000;
1187 else if (bmcr & BMCR_SPEED100)
1188 active_speed = SPEED_100;
1189 else
1190 active_speed = SPEED_10;
1191
1192 if (bmcr & BMCR_FULLDPLX)
1193 active_duplex = DUPLEX_FULL;
1194 else
1195 active_duplex = DUPLEX_HALF;
1196 }
1197
1198 lp->active_advertising = advertising;
1199 lp->active_speed = active_speed;
1200 lp->active_duplex = active_duplex;
1201 *link_up_p = !!(bmsr & BMSR_LSTATUS);
1202
1203 return 0;
1204 }
1205
1206 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1207 {
1208 struct niu_link_config *lp = &np->link_config;
1209 u16 current_speed, bmsr;
1210 unsigned long flags;
1211 u8 current_duplex;
1212 int err, link_up;
1213
1214 link_up = 0;
1215 current_speed = SPEED_INVALID;
1216 current_duplex = DUPLEX_INVALID;
1217
1218 spin_lock_irqsave(&np->lock, flags);
1219
1220 err = -EINVAL;
1221
1222 err = mii_read(np, np->phy_addr, MII_BMSR);
1223 if (err < 0)
1224 goto out;
1225
1226 bmsr = err;
1227 if (bmsr & BMSR_LSTATUS) {
1228 u16 adv, lpa;
1229
1230 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1231 if (err < 0)
1232 goto out;
1233 adv = err;
1234
1235 err = mii_read(np, np->phy_addr, MII_LPA);
1236 if (err < 0)
1237 goto out;
1238 lpa = err;
1239
1240 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1241 if (err < 0)
1242 goto out;
1243 link_up = 1;
1244 current_speed = SPEED_1000;
1245 current_duplex = DUPLEX_FULL;
1246
1247 }
1248 lp->active_speed = current_speed;
1249 lp->active_duplex = current_duplex;
1250 err = 0;
1251
1252 out:
1253 spin_unlock_irqrestore(&np->lock, flags);
1254
1255 *link_up_p = link_up;
1256 return err;
1257 }
1258
1259 static int link_status_1g(struct niu *np, int *link_up_p)
1260 {
1261 struct niu_link_config *lp = &np->link_config;
1262 unsigned long flags;
1263 int err;
1264
1265 spin_lock_irqsave(&np->lock, flags);
1266
1267 err = link_status_mii(np, link_up_p);
1268 lp->supported |= SUPPORTED_TP;
1269 lp->active_advertising |= ADVERTISED_TP;
1270
1271 spin_unlock_irqrestore(&np->lock, flags);
1272 return err;
1273 }
1274
1275 static int bcm8704_reset(struct niu *np)
1276 {
1277 int err, limit;
1278
1279 err = mdio_read(np, np->phy_addr,
1280 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1281 if (err < 0 || err == 0xffff)
1282 return err;
1283 err |= BMCR_RESET;
1284 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1285 MII_BMCR, err);
1286 if (err)
1287 return err;
1288
1289 limit = 1000;
1290 while (--limit >= 0) {
1291 err = mdio_read(np, np->phy_addr,
1292 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1293 if (err < 0)
1294 return err;
1295 if (!(err & BMCR_RESET))
1296 break;
1297 }
1298 if (limit < 0) {
1299 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1300 np->port, (err & 0xffff));
1301 return -ENODEV;
1302 }
1303 return 0;
1304 }
1305
1306 /* When written, certain PHY registers need to be read back twice
1307 * in order for the bits to settle properly.
1308 */
1309 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1310 {
1311 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1312 if (err < 0)
1313 return err;
1314 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1315 if (err < 0)
1316 return err;
1317 return 0;
1318 }
1319
1320 static int bcm8706_init_user_dev3(struct niu *np)
1321 {
1322 int err;
1323
1324
1325 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1326 BCM8704_USER_OPT_DIGITAL_CTRL);
1327 if (err < 0)
1328 return err;
1329 err &= ~USER_ODIG_CTRL_GPIOS;
1330 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1331 err |= USER_ODIG_CTRL_RESV2;
1332 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1333 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1334 if (err)
1335 return err;
1336
1337 mdelay(1000);
1338
1339 return 0;
1340 }
1341
1342 static int bcm8704_init_user_dev3(struct niu *np)
1343 {
1344 int err;
1345
1346 err = mdio_write(np, np->phy_addr,
1347 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1348 (USER_CONTROL_OPTXRST_LVL |
1349 USER_CONTROL_OPBIASFLT_LVL |
1350 USER_CONTROL_OBTMPFLT_LVL |
1351 USER_CONTROL_OPPRFLT_LVL |
1352 USER_CONTROL_OPTXFLT_LVL |
1353 USER_CONTROL_OPRXLOS_LVL |
1354 USER_CONTROL_OPRXFLT_LVL |
1355 USER_CONTROL_OPTXON_LVL |
1356 (0x3f << USER_CONTROL_RES1_SHIFT)));
1357 if (err)
1358 return err;
1359
1360 err = mdio_write(np, np->phy_addr,
1361 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1362 (USER_PMD_TX_CTL_XFP_CLKEN |
1363 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1364 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1365 USER_PMD_TX_CTL_TSCK_LPWREN));
1366 if (err)
1367 return err;
1368
1369 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1370 if (err)
1371 return err;
1372 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1373 if (err)
1374 return err;
1375
1376 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1377 BCM8704_USER_OPT_DIGITAL_CTRL);
1378 if (err < 0)
1379 return err;
1380 err &= ~USER_ODIG_CTRL_GPIOS;
1381 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1382 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1383 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1384 if (err)
1385 return err;
1386
1387 mdelay(1000);
1388
1389 return 0;
1390 }
1391
1392 static int mrvl88x2011_act_led(struct niu *np, int val)
1393 {
1394 int err;
1395
1396 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1397 MRVL88X2011_LED_8_TO_11_CTL);
1398 if (err < 0)
1399 return err;
1400
1401 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1402 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1403
1404 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1405 MRVL88X2011_LED_8_TO_11_CTL, err);
1406 }
1407
1408 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1409 {
1410 int err;
1411
1412 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1413 MRVL88X2011_LED_BLINK_CTL);
1414 if (err >= 0) {
1415 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1416 err |= (rate << 4);
1417
1418 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1419 MRVL88X2011_LED_BLINK_CTL, err);
1420 }
1421
1422 return err;
1423 }
1424
1425 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1426 {
1427 int err;
1428
1429 /* Set LED functions */
1430 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1431 if (err)
1432 return err;
1433
1434 /* led activity */
1435 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1436 if (err)
1437 return err;
1438
1439 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1440 MRVL88X2011_GENERAL_CTL);
1441 if (err < 0)
1442 return err;
1443
1444 err |= MRVL88X2011_ENA_XFPREFCLK;
1445
1446 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1447 MRVL88X2011_GENERAL_CTL, err);
1448 if (err < 0)
1449 return err;
1450
1451 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1452 MRVL88X2011_PMA_PMD_CTL_1);
1453 if (err < 0)
1454 return err;
1455
1456 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1457 err |= MRVL88X2011_LOOPBACK;
1458 else
1459 err &= ~MRVL88X2011_LOOPBACK;
1460
1461 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1462 MRVL88X2011_PMA_PMD_CTL_1, err);
1463 if (err < 0)
1464 return err;
1465
1466 /* Enable PMD */
1467 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1468 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1469 }
1470
1471
1472 static int xcvr_diag_bcm870x(struct niu *np)
1473 {
1474 u16 analog_stat0, tx_alarm_status;
1475 int err = 0;
1476
1477 #if 1
1478 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1479 MII_STAT1000);
1480 if (err < 0)
1481 return err;
1482 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
1483
1484 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1485 if (err < 0)
1486 return err;
1487 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
1488
1489 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1490 MII_NWAYTEST);
1491 if (err < 0)
1492 return err;
1493 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
1494 #endif
1495
1496 /* XXX dig this out it might not be so useful XXX */
1497 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1498 BCM8704_USER_ANALOG_STATUS0);
1499 if (err < 0)
1500 return err;
1501 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1502 BCM8704_USER_ANALOG_STATUS0);
1503 if (err < 0)
1504 return err;
1505 analog_stat0 = err;
1506
1507 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1508 BCM8704_USER_TX_ALARM_STATUS);
1509 if (err < 0)
1510 return err;
1511 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1512 BCM8704_USER_TX_ALARM_STATUS);
1513 if (err < 0)
1514 return err;
1515 tx_alarm_status = err;
1516
1517 if (analog_stat0 != 0x03fc) {
1518 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1519 pr_info("Port %u cable not connected or bad cable\n",
1520 np->port);
1521 } else if (analog_stat0 == 0x639c) {
1522 pr_info("Port %u optical module is bad or missing\n",
1523 np->port);
1524 }
1525 }
1526
1527 return 0;
1528 }
1529
1530 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1531 {
1532 struct niu_link_config *lp = &np->link_config;
1533 int err;
1534
1535 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1536 MII_BMCR);
1537 if (err < 0)
1538 return err;
1539
1540 err &= ~BMCR_LOOPBACK;
1541
1542 if (lp->loopback_mode == LOOPBACK_MAC)
1543 err |= BMCR_LOOPBACK;
1544
1545 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1546 MII_BMCR, err);
1547 if (err)
1548 return err;
1549
1550 return 0;
1551 }
1552
1553 static int xcvr_init_10g_bcm8706(struct niu *np)
1554 {
1555 int err = 0;
1556 u64 val;
1557
1558 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1559 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1560 return err;
1561
1562 val = nr64_mac(XMAC_CONFIG);
1563 val &= ~XMAC_CONFIG_LED_POLARITY;
1564 val |= XMAC_CONFIG_FORCE_LED_ON;
1565 nw64_mac(XMAC_CONFIG, val);
1566
1567 val = nr64(MIF_CONFIG);
1568 val |= MIF_CONFIG_INDIRECT_MODE;
1569 nw64(MIF_CONFIG, val);
1570
1571 err = bcm8704_reset(np);
1572 if (err)
1573 return err;
1574
1575 err = xcvr_10g_set_lb_bcm870x(np);
1576 if (err)
1577 return err;
1578
1579 err = bcm8706_init_user_dev3(np);
1580 if (err)
1581 return err;
1582
1583 err = xcvr_diag_bcm870x(np);
1584 if (err)
1585 return err;
1586
1587 return 0;
1588 }
1589
1590 static int xcvr_init_10g_bcm8704(struct niu *np)
1591 {
1592 int err;
1593
1594 err = bcm8704_reset(np);
1595 if (err)
1596 return err;
1597
1598 err = bcm8704_init_user_dev3(np);
1599 if (err)
1600 return err;
1601
1602 err = xcvr_10g_set_lb_bcm870x(np);
1603 if (err)
1604 return err;
1605
1606 err = xcvr_diag_bcm870x(np);
1607 if (err)
1608 return err;
1609
1610 return 0;
1611 }
1612
1613 static int xcvr_init_10g(struct niu *np)
1614 {
1615 int phy_id, err;
1616 u64 val;
1617
1618 val = nr64_mac(XMAC_CONFIG);
1619 val &= ~XMAC_CONFIG_LED_POLARITY;
1620 val |= XMAC_CONFIG_FORCE_LED_ON;
1621 nw64_mac(XMAC_CONFIG, val);
1622
1623 /* XXX shared resource, lock parent XXX */
1624 val = nr64(MIF_CONFIG);
1625 val |= MIF_CONFIG_INDIRECT_MODE;
1626 nw64(MIF_CONFIG, val);
1627
1628 phy_id = phy_decode(np->parent->port_phy, np->port);
1629 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1630
1631 /* handle different phy types */
1632 switch (phy_id & NIU_PHY_ID_MASK) {
1633 case NIU_PHY_ID_MRVL88X2011:
1634 err = xcvr_init_10g_mrvl88x2011(np);
1635 break;
1636
1637 default: /* bcom 8704 */
1638 err = xcvr_init_10g_bcm8704(np);
1639 break;
1640 }
1641
1642 return err;
1643 }
1644
1645 static int mii_reset(struct niu *np)
1646 {
1647 int limit, err;
1648
1649 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1650 if (err)
1651 return err;
1652
1653 limit = 1000;
1654 while (--limit >= 0) {
1655 udelay(500);
1656 err = mii_read(np, np->phy_addr, MII_BMCR);
1657 if (err < 0)
1658 return err;
1659 if (!(err & BMCR_RESET))
1660 break;
1661 }
1662 if (limit < 0) {
1663 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1664 np->port, err);
1665 return -ENODEV;
1666 }
1667
1668 return 0;
1669 }
1670
1671 static int xcvr_init_1g_rgmii(struct niu *np)
1672 {
1673 int err;
1674 u64 val;
1675 u16 bmcr, bmsr, estat;
1676
1677 val = nr64(MIF_CONFIG);
1678 val &= ~MIF_CONFIG_INDIRECT_MODE;
1679 nw64(MIF_CONFIG, val);
1680
1681 err = mii_reset(np);
1682 if (err)
1683 return err;
1684
1685 err = mii_read(np, np->phy_addr, MII_BMSR);
1686 if (err < 0)
1687 return err;
1688 bmsr = err;
1689
1690 estat = 0;
1691 if (bmsr & BMSR_ESTATEN) {
1692 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1693 if (err < 0)
1694 return err;
1695 estat = err;
1696 }
1697
1698 bmcr = 0;
1699 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1700 if (err)
1701 return err;
1702
1703 if (bmsr & BMSR_ESTATEN) {
1704 u16 ctrl1000 = 0;
1705
1706 if (estat & ESTATUS_1000_TFULL)
1707 ctrl1000 |= ADVERTISE_1000FULL;
1708 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1709 if (err)
1710 return err;
1711 }
1712
1713 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1714
1715 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1716 if (err)
1717 return err;
1718
1719 err = mii_read(np, np->phy_addr, MII_BMCR);
1720 if (err < 0)
1721 return err;
1722 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1723
1724 err = mii_read(np, np->phy_addr, MII_BMSR);
1725 if (err < 0)
1726 return err;
1727
1728 return 0;
1729 }
1730
1731 static int mii_init_common(struct niu *np)
1732 {
1733 struct niu_link_config *lp = &np->link_config;
1734 u16 bmcr, bmsr, adv, estat;
1735 int err;
1736
1737 err = mii_reset(np);
1738 if (err)
1739 return err;
1740
1741 err = mii_read(np, np->phy_addr, MII_BMSR);
1742 if (err < 0)
1743 return err;
1744 bmsr = err;
1745
1746 estat = 0;
1747 if (bmsr & BMSR_ESTATEN) {
1748 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1749 if (err < 0)
1750 return err;
1751 estat = err;
1752 }
1753
1754 bmcr = 0;
1755 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1756 if (err)
1757 return err;
1758
1759 if (lp->loopback_mode == LOOPBACK_MAC) {
1760 bmcr |= BMCR_LOOPBACK;
1761 if (lp->active_speed == SPEED_1000)
1762 bmcr |= BMCR_SPEED1000;
1763 if (lp->active_duplex == DUPLEX_FULL)
1764 bmcr |= BMCR_FULLDPLX;
1765 }
1766
1767 if (lp->loopback_mode == LOOPBACK_PHY) {
1768 u16 aux;
1769
1770 aux = (BCM5464R_AUX_CTL_EXT_LB |
1771 BCM5464R_AUX_CTL_WRITE_1);
1772 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1773 if (err)
1774 return err;
1775 }
1776
1777 if (lp->autoneg) {
1778 u16 ctrl1000;
1779
1780 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1781 if ((bmsr & BMSR_10HALF) &&
1782 (lp->advertising & ADVERTISED_10baseT_Half))
1783 adv |= ADVERTISE_10HALF;
1784 if ((bmsr & BMSR_10FULL) &&
1785 (lp->advertising & ADVERTISED_10baseT_Full))
1786 adv |= ADVERTISE_10FULL;
1787 if ((bmsr & BMSR_100HALF) &&
1788 (lp->advertising & ADVERTISED_100baseT_Half))
1789 adv |= ADVERTISE_100HALF;
1790 if ((bmsr & BMSR_100FULL) &&
1791 (lp->advertising & ADVERTISED_100baseT_Full))
1792 adv |= ADVERTISE_100FULL;
1793 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1794 if (err)
1795 return err;
1796
1797 if (likely(bmsr & BMSR_ESTATEN)) {
1798 ctrl1000 = 0;
1799 if ((estat & ESTATUS_1000_THALF) &&
1800 (lp->advertising & ADVERTISED_1000baseT_Half))
1801 ctrl1000 |= ADVERTISE_1000HALF;
1802 if ((estat & ESTATUS_1000_TFULL) &&
1803 (lp->advertising & ADVERTISED_1000baseT_Full))
1804 ctrl1000 |= ADVERTISE_1000FULL;
1805 err = mii_write(np, np->phy_addr,
1806 MII_CTRL1000, ctrl1000);
1807 if (err)
1808 return err;
1809 }
1810
1811 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1812 } else {
1813 /* !lp->autoneg */
1814 int fulldpx;
1815
1816 if (lp->duplex == DUPLEX_FULL) {
1817 bmcr |= BMCR_FULLDPLX;
1818 fulldpx = 1;
1819 } else if (lp->duplex == DUPLEX_HALF)
1820 fulldpx = 0;
1821 else
1822 return -EINVAL;
1823
1824 if (lp->speed == SPEED_1000) {
1825 /* if X-full requested while not supported, or
1826 X-half requested while not supported... */
1827 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1828 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1829 return -EINVAL;
1830 bmcr |= BMCR_SPEED1000;
1831 } else if (lp->speed == SPEED_100) {
1832 if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1833 (!fulldpx && !(bmsr & BMSR_100HALF)))
1834 return -EINVAL;
1835 bmcr |= BMCR_SPEED100;
1836 } else if (lp->speed == SPEED_10) {
1837 if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1838 (!fulldpx && !(bmsr & BMSR_10HALF)))
1839 return -EINVAL;
1840 } else
1841 return -EINVAL;
1842 }
1843
1844 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1845 if (err)
1846 return err;
1847
1848 #if 0
1849 err = mii_read(np, np->phy_addr, MII_BMCR);
1850 if (err < 0)
1851 return err;
1852 bmcr = err;
1853
1854 err = mii_read(np, np->phy_addr, MII_BMSR);
1855 if (err < 0)
1856 return err;
1857 bmsr = err;
1858
1859 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1860 np->port, bmcr, bmsr);
1861 #endif
1862
1863 return 0;
1864 }
1865
1866 static int xcvr_init_1g(struct niu *np)
1867 {
1868 u64 val;
1869
1870 /* XXX shared resource, lock parent XXX */
1871 val = nr64(MIF_CONFIG);
1872 val &= ~MIF_CONFIG_INDIRECT_MODE;
1873 nw64(MIF_CONFIG, val);
1874
1875 return mii_init_common(np);
1876 }
1877
1878 static int niu_xcvr_init(struct niu *np)
1879 {
1880 const struct niu_phy_ops *ops = np->phy_ops;
1881 int err;
1882
1883 err = 0;
1884 if (ops->xcvr_init)
1885 err = ops->xcvr_init(np);
1886
1887 return err;
1888 }
1889
1890 static int niu_serdes_init(struct niu *np)
1891 {
1892 const struct niu_phy_ops *ops = np->phy_ops;
1893 int err;
1894
1895 err = 0;
1896 if (ops->serdes_init)
1897 err = ops->serdes_init(np);
1898
1899 return err;
1900 }
1901
1902 static void niu_init_xif(struct niu *);
1903 static void niu_handle_led(struct niu *, int status);
1904
1905 static int niu_link_status_common(struct niu *np, int link_up)
1906 {
1907 struct niu_link_config *lp = &np->link_config;
1908 struct net_device *dev = np->dev;
1909 unsigned long flags;
1910
1911 if (!netif_carrier_ok(dev) && link_up) {
1912 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1913 lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1914 lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1915 lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1916 "10Mbit/sec",
1917 lp->active_duplex == DUPLEX_FULL ? "full" : "half");
1918
1919 spin_lock_irqsave(&np->lock, flags);
1920 niu_init_xif(np);
1921 niu_handle_led(np, 1);
1922 spin_unlock_irqrestore(&np->lock, flags);
1923
1924 netif_carrier_on(dev);
1925 } else if (netif_carrier_ok(dev) && !link_up) {
1926 netif_warn(np, link, dev, "Link is down\n");
1927 spin_lock_irqsave(&np->lock, flags);
1928 niu_handle_led(np, 0);
1929 spin_unlock_irqrestore(&np->lock, flags);
1930 netif_carrier_off(dev);
1931 }
1932
1933 return 0;
1934 }
1935
1936 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1937 {
1938 int err, link_up, pma_status, pcs_status;
1939
1940 link_up = 0;
1941
1942 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1943 MRVL88X2011_10G_PMD_STATUS_2);
1944 if (err < 0)
1945 goto out;
1946
1947 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1948 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1949 MRVL88X2011_PMA_PMD_STATUS_1);
1950 if (err < 0)
1951 goto out;
1952
1953 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1954
1955 /* Check PMC Register : 3.0001.2 == 1: read twice */
1956 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1957 MRVL88X2011_PMA_PMD_STATUS_1);
1958 if (err < 0)
1959 goto out;
1960
1961 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1962 MRVL88X2011_PMA_PMD_STATUS_1);
1963 if (err < 0)
1964 goto out;
1965
1966 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1967
1968 /* Check XGXS Register : 4.0018.[0-3,12] */
1969 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1970 MRVL88X2011_10G_XGXS_LANE_STAT);
1971 if (err < 0)
1972 goto out;
1973
1974 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1975 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1976 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1977 0x800))
1978 link_up = (pma_status && pcs_status) ? 1 : 0;
1979
1980 np->link_config.active_speed = SPEED_10000;
1981 np->link_config.active_duplex = DUPLEX_FULL;
1982 err = 0;
1983 out:
1984 mrvl88x2011_act_led(np, (link_up ?
1985 MRVL88X2011_LED_CTL_PCS_ACT :
1986 MRVL88X2011_LED_CTL_OFF));
1987
1988 *link_up_p = link_up;
1989 return err;
1990 }
1991
1992 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
1993 {
1994 int err, link_up;
1995 link_up = 0;
1996
1997 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1998 BCM8704_PMD_RCV_SIGDET);
1999 if (err < 0 || err == 0xffff)
2000 goto out;
2001 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2002 err = 0;
2003 goto out;
2004 }
2005
2006 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2007 BCM8704_PCS_10G_R_STATUS);
2008 if (err < 0)
2009 goto out;
2010
2011 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2012 err = 0;
2013 goto out;
2014 }
2015
2016 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2017 BCM8704_PHYXS_XGXS_LANE_STAT);
2018 if (err < 0)
2019 goto out;
2020 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2021 PHYXS_XGXS_LANE_STAT_MAGIC |
2022 PHYXS_XGXS_LANE_STAT_PATTEST |
2023 PHYXS_XGXS_LANE_STAT_LANE3 |
2024 PHYXS_XGXS_LANE_STAT_LANE2 |
2025 PHYXS_XGXS_LANE_STAT_LANE1 |
2026 PHYXS_XGXS_LANE_STAT_LANE0)) {
2027 err = 0;
2028 np->link_config.active_speed = SPEED_INVALID;
2029 np->link_config.active_duplex = DUPLEX_INVALID;
2030 goto out;
2031 }
2032
2033 link_up = 1;
2034 np->link_config.active_speed = SPEED_10000;
2035 np->link_config.active_duplex = DUPLEX_FULL;
2036 err = 0;
2037
2038 out:
2039 *link_up_p = link_up;
2040 return err;
2041 }
2042
2043 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2044 {
2045 int err, link_up;
2046
2047 link_up = 0;
2048
2049 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2050 BCM8704_PMD_RCV_SIGDET);
2051 if (err < 0)
2052 goto out;
2053 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2054 err = 0;
2055 goto out;
2056 }
2057
2058 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2059 BCM8704_PCS_10G_R_STATUS);
2060 if (err < 0)
2061 goto out;
2062 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2063 err = 0;
2064 goto out;
2065 }
2066
2067 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2068 BCM8704_PHYXS_XGXS_LANE_STAT);
2069 if (err < 0)
2070 goto out;
2071
2072 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2073 PHYXS_XGXS_LANE_STAT_MAGIC |
2074 PHYXS_XGXS_LANE_STAT_LANE3 |
2075 PHYXS_XGXS_LANE_STAT_LANE2 |
2076 PHYXS_XGXS_LANE_STAT_LANE1 |
2077 PHYXS_XGXS_LANE_STAT_LANE0)) {
2078 err = 0;
2079 goto out;
2080 }
2081
2082 link_up = 1;
2083 np->link_config.active_speed = SPEED_10000;
2084 np->link_config.active_duplex = DUPLEX_FULL;
2085 err = 0;
2086
2087 out:
2088 *link_up_p = link_up;
2089 return err;
2090 }
2091
2092 static int link_status_10g(struct niu *np, int *link_up_p)
2093 {
2094 unsigned long flags;
2095 int err = -EINVAL;
2096
2097 spin_lock_irqsave(&np->lock, flags);
2098
2099 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2100 int phy_id;
2101
2102 phy_id = phy_decode(np->parent->port_phy, np->port);
2103 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2104
2105 /* handle different phy types */
2106 switch (phy_id & NIU_PHY_ID_MASK) {
2107 case NIU_PHY_ID_MRVL88X2011:
2108 err = link_status_10g_mrvl(np, link_up_p);
2109 break;
2110
2111 default: /* bcom 8704 */
2112 err = link_status_10g_bcom(np, link_up_p);
2113 break;
2114 }
2115 }
2116
2117 spin_unlock_irqrestore(&np->lock, flags);
2118
2119 return err;
2120 }
2121
2122 static int niu_10g_phy_present(struct niu *np)
2123 {
2124 u64 sig, mask, val;
2125
2126 sig = nr64(ESR_INT_SIGNALS);
2127 switch (np->port) {
2128 case 0:
2129 mask = ESR_INT_SIGNALS_P0_BITS;
2130 val = (ESR_INT_SRDY0_P0 |
2131 ESR_INT_DET0_P0 |
2132 ESR_INT_XSRDY_P0 |
2133 ESR_INT_XDP_P0_CH3 |
2134 ESR_INT_XDP_P0_CH2 |
2135 ESR_INT_XDP_P0_CH1 |
2136 ESR_INT_XDP_P0_CH0);
2137 break;
2138
2139 case 1:
2140 mask = ESR_INT_SIGNALS_P1_BITS;
2141 val = (ESR_INT_SRDY0_P1 |
2142 ESR_INT_DET0_P1 |
2143 ESR_INT_XSRDY_P1 |
2144 ESR_INT_XDP_P1_CH3 |
2145 ESR_INT_XDP_P1_CH2 |
2146 ESR_INT_XDP_P1_CH1 |
2147 ESR_INT_XDP_P1_CH0);
2148 break;
2149
2150 default:
2151 return 0;
2152 }
2153
2154 if ((sig & mask) != val)
2155 return 0;
2156 return 1;
2157 }
2158
2159 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2160 {
2161 unsigned long flags;
2162 int err = 0;
2163 int phy_present;
2164 int phy_present_prev;
2165
2166 spin_lock_irqsave(&np->lock, flags);
2167
2168 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2169 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2170 1 : 0;
2171 phy_present = niu_10g_phy_present(np);
2172 if (phy_present != phy_present_prev) {
2173 /* state change */
2174 if (phy_present) {
2175 /* A NEM was just plugged in */
2176 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2177 if (np->phy_ops->xcvr_init)
2178 err = np->phy_ops->xcvr_init(np);
2179 if (err) {
2180 err = mdio_read(np, np->phy_addr,
2181 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2182 if (err == 0xffff) {
2183 /* No mdio, back-to-back XAUI */
2184 goto out;
2185 }
2186 /* debounce */
2187 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2188 }
2189 } else {
2190 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2191 *link_up_p = 0;
2192 netif_warn(np, link, np->dev,
2193 "Hotplug PHY Removed\n");
2194 }
2195 }
2196 out:
2197 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
2198 err = link_status_10g_bcm8706(np, link_up_p);
2199 if (err == 0xffff) {
2200 /* No mdio, back-to-back XAUI: it is C10NEM */
2201 *link_up_p = 1;
2202 np->link_config.active_speed = SPEED_10000;
2203 np->link_config.active_duplex = DUPLEX_FULL;
2204 }
2205 }
2206 }
2207
2208 spin_unlock_irqrestore(&np->lock, flags);
2209
2210 return 0;
2211 }
2212
2213 static int niu_link_status(struct niu *np, int *link_up_p)
2214 {
2215 const struct niu_phy_ops *ops = np->phy_ops;
2216 int err;
2217
2218 err = 0;
2219 if (ops->link_status)
2220 err = ops->link_status(np, link_up_p);
2221
2222 return err;
2223 }
2224
2225 static void niu_timer(struct timer_list *t)
2226 {
2227 struct niu *np = from_timer(np, t, timer);
2228 unsigned long off;
2229 int err, link_up;
2230
2231 err = niu_link_status(np, &link_up);
2232 if (!err)
2233 niu_link_status_common(np, link_up);
2234
2235 if (netif_carrier_ok(np->dev))
2236 off = 5 * HZ;
2237 else
2238 off = 1 * HZ;
2239 np->timer.expires = jiffies + off;
2240
2241 add_timer(&np->timer);
2242 }
2243
2244 static const struct niu_phy_ops phy_ops_10g_serdes = {
2245 .serdes_init = serdes_init_10g_serdes,
2246 .link_status = link_status_10g_serdes,
2247 };
2248
2249 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2250 .serdes_init = serdes_init_niu_10g_serdes,
2251 .link_status = link_status_10g_serdes,
2252 };
2253
2254 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2255 .serdes_init = serdes_init_niu_1g_serdes,
2256 .link_status = link_status_1g_serdes,
2257 };
2258
2259 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2260 .xcvr_init = xcvr_init_1g_rgmii,
2261 .link_status = link_status_1g_rgmii,
2262 };
2263
2264 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2265 .serdes_init = serdes_init_niu_10g_fiber,
2266 .xcvr_init = xcvr_init_10g,
2267 .link_status = link_status_10g,
2268 };
2269
2270 static const struct niu_phy_ops phy_ops_10g_fiber = {
2271 .serdes_init = serdes_init_10g,
2272 .xcvr_init = xcvr_init_10g,
2273 .link_status = link_status_10g,
2274 };
2275
2276 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2277 .serdes_init = serdes_init_10g,
2278 .xcvr_init = xcvr_init_10g_bcm8706,
2279 .link_status = link_status_10g_hotplug,
2280 };
2281
2282 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2283 .serdes_init = serdes_init_niu_10g_fiber,
2284 .xcvr_init = xcvr_init_10g_bcm8706,
2285 .link_status = link_status_10g_hotplug,
2286 };
2287
2288 static const struct niu_phy_ops phy_ops_10g_copper = {
2289 .serdes_init = serdes_init_10g,
2290 .link_status = link_status_10g, /* XXX */
2291 };
2292
2293 static const struct niu_phy_ops phy_ops_1g_fiber = {
2294 .serdes_init = serdes_init_1g,
2295 .xcvr_init = xcvr_init_1g,
2296 .link_status = link_status_1g,
2297 };
2298
2299 static const struct niu_phy_ops phy_ops_1g_copper = {
2300 .xcvr_init = xcvr_init_1g,
2301 .link_status = link_status_1g,
2302 };
2303
2304 struct niu_phy_template {
2305 const struct niu_phy_ops *ops;
2306 u32 phy_addr_base;
2307 };
2308
2309 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2310 .ops = &phy_ops_10g_fiber_niu,
2311 .phy_addr_base = 16,
2312 };
2313
2314 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2315 .ops = &phy_ops_10g_serdes_niu,
2316 .phy_addr_base = 0,
2317 };
2318
2319 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2320 .ops = &phy_ops_1g_serdes_niu,
2321 .phy_addr_base = 0,
2322 };
2323
2324 static const struct niu_phy_template phy_template_10g_fiber = {
2325 .ops = &phy_ops_10g_fiber,
2326 .phy_addr_base = 8,
2327 };
2328
2329 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2330 .ops = &phy_ops_10g_fiber_hotplug,
2331 .phy_addr_base = 8,
2332 };
2333
2334 static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2335 .ops = &phy_ops_niu_10g_hotplug,
2336 .phy_addr_base = 8,
2337 };
2338
2339 static const struct niu_phy_template phy_template_10g_copper = {
2340 .ops = &phy_ops_10g_copper,
2341 .phy_addr_base = 10,
2342 };
2343
2344 static const struct niu_phy_template phy_template_1g_fiber = {
2345 .ops = &phy_ops_1g_fiber,
2346 .phy_addr_base = 0,
2347 };
2348
2349 static const struct niu_phy_template phy_template_1g_copper = {
2350 .ops = &phy_ops_1g_copper,
2351 .phy_addr_base = 0,
2352 };
2353
2354 static const struct niu_phy_template phy_template_1g_rgmii = {
2355 .ops = &phy_ops_1g_rgmii,
2356 .phy_addr_base = 0,
2357 };
2358
2359 static const struct niu_phy_template phy_template_10g_serdes = {
2360 .ops = &phy_ops_10g_serdes,
2361 .phy_addr_base = 0,
2362 };
2363
2364 static int niu_atca_port_num[4] = {
2365 0, 0, 11, 10
2366 };
2367
2368 static int serdes_init_10g_serdes(struct niu *np)
2369 {
2370 struct niu_link_config *lp = &np->link_config;
2371 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2372 u64 ctrl_val, test_cfg_val, sig, mask, val;
2373
2374 switch (np->port) {
2375 case 0:
2376 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2377 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2378 pll_cfg = ENET_SERDES_0_PLL_CFG;
2379 break;
2380 case 1:
2381 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2382 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2383 pll_cfg = ENET_SERDES_1_PLL_CFG;
2384 break;
2385
2386 default:
2387 return -EINVAL;
2388 }
2389 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2390 ENET_SERDES_CTRL_SDET_1 |
2391 ENET_SERDES_CTRL_SDET_2 |
2392 ENET_SERDES_CTRL_SDET_3 |
2393 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2394 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2395 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2396 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2397 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2398 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2399 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2400 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2401 test_cfg_val = 0;
2402
2403 if (lp->loopback_mode == LOOPBACK_PHY) {
2404 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2405 ENET_SERDES_TEST_MD_0_SHIFT) |
2406 (ENET_TEST_MD_PAD_LOOPBACK <<
2407 ENET_SERDES_TEST_MD_1_SHIFT) |
2408 (ENET_TEST_MD_PAD_LOOPBACK <<
2409 ENET_SERDES_TEST_MD_2_SHIFT) |
2410 (ENET_TEST_MD_PAD_LOOPBACK <<
2411 ENET_SERDES_TEST_MD_3_SHIFT));
2412 }
2413
2414 esr_reset(np);
2415 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2416 nw64(ctrl_reg, ctrl_val);
2417 nw64(test_cfg_reg, test_cfg_val);
2418
2419 /* Initialize all 4 lanes of the SERDES. */
2420 for (i = 0; i < 4; i++) {
2421 u32 rxtx_ctrl, glue0;
2422 int err;
2423
2424 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2425 if (err)
2426 return err;
2427 err = esr_read_glue0(np, i, &glue0);
2428 if (err)
2429 return err;
2430
2431 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2432 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2433 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2434
2435 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2436 ESR_GLUE_CTRL0_THCNT |
2437 ESR_GLUE_CTRL0_BLTIME);
2438 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2439 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2440 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2441 (BLTIME_300_CYCLES <<
2442 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2443
2444 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2445 if (err)
2446 return err;
2447 err = esr_write_glue0(np, i, glue0);
2448 if (err)
2449 return err;
2450 }
2451
2452
2453 sig = nr64(ESR_INT_SIGNALS);
2454 switch (np->port) {
2455 case 0:
2456 mask = ESR_INT_SIGNALS_P0_BITS;
2457 val = (ESR_INT_SRDY0_P0 |
2458 ESR_INT_DET0_P0 |
2459 ESR_INT_XSRDY_P0 |
2460 ESR_INT_XDP_P0_CH3 |
2461 ESR_INT_XDP_P0_CH2 |
2462 ESR_INT_XDP_P0_CH1 |
2463 ESR_INT_XDP_P0_CH0);
2464 break;
2465
2466 case 1:
2467 mask = ESR_INT_SIGNALS_P1_BITS;
2468 val = (ESR_INT_SRDY0_P1 |
2469 ESR_INT_DET0_P1 |
2470 ESR_INT_XSRDY_P1 |
2471 ESR_INT_XDP_P1_CH3 |
2472 ESR_INT_XDP_P1_CH2 |
2473 ESR_INT_XDP_P1_CH1 |
2474 ESR_INT_XDP_P1_CH0);
2475 break;
2476
2477 default:
2478 return -EINVAL;
2479 }
2480
2481 if ((sig & mask) != val) {
2482 int err;
2483 err = serdes_init_1g_serdes(np);
2484 if (!err) {
2485 np->flags &= ~NIU_FLAGS_10G;
2486 np->mac_xcvr = MAC_XCVR_PCS;
2487 } else {
2488 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2489 np->port);
2490 return -ENODEV;
2491 }
2492 }
2493
2494 return 0;
2495 }
2496
2497 static int niu_determine_phy_disposition(struct niu *np)
2498 {
2499 struct niu_parent *parent = np->parent;
2500 u8 plat_type = parent->plat_type;
2501 const struct niu_phy_template *tp;
2502 u32 phy_addr_off = 0;
2503
2504 if (plat_type == PLAT_TYPE_NIU) {
2505 switch (np->flags &
2506 (NIU_FLAGS_10G |
2507 NIU_FLAGS_FIBER |
2508 NIU_FLAGS_XCVR_SERDES)) {
2509 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2510 /* 10G Serdes */
2511 tp = &phy_template_niu_10g_serdes;
2512 break;
2513 case NIU_FLAGS_XCVR_SERDES:
2514 /* 1G Serdes */
2515 tp = &phy_template_niu_1g_serdes;
2516 break;
2517 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2518 /* 10G Fiber */
2519 default:
2520 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2521 tp = &phy_template_niu_10g_hotplug;
2522 if (np->port == 0)
2523 phy_addr_off = 8;
2524 if (np->port == 1)
2525 phy_addr_off = 12;
2526 } else {
2527 tp = &phy_template_niu_10g_fiber;
2528 phy_addr_off += np->port;
2529 }
2530 break;
2531 }
2532 } else {
2533 switch (np->flags &
2534 (NIU_FLAGS_10G |
2535 NIU_FLAGS_FIBER |
2536 NIU_FLAGS_XCVR_SERDES)) {
2537 case 0:
2538 /* 1G copper */
2539 tp = &phy_template_1g_copper;
2540 if (plat_type == PLAT_TYPE_VF_P0)
2541 phy_addr_off = 10;
2542 else if (plat_type == PLAT_TYPE_VF_P1)
2543 phy_addr_off = 26;
2544
2545 phy_addr_off += (np->port ^ 0x3);
2546 break;
2547
2548 case NIU_FLAGS_10G:
2549 /* 10G copper */
2550 tp = &phy_template_10g_copper;
2551 break;
2552
2553 case NIU_FLAGS_FIBER:
2554 /* 1G fiber */
2555 tp = &phy_template_1g_fiber;
2556 break;
2557
2558 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2559 /* 10G fiber */
2560 tp = &phy_template_10g_fiber;
2561 if (plat_type == PLAT_TYPE_VF_P0 ||
2562 plat_type == PLAT_TYPE_VF_P1)
2563 phy_addr_off = 8;
2564 phy_addr_off += np->port;
2565 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2566 tp = &phy_template_10g_fiber_hotplug;
2567 if (np->port == 0)
2568 phy_addr_off = 8;
2569 if (np->port == 1)
2570 phy_addr_off = 12;
2571 }
2572 break;
2573
2574 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2575 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2576 case NIU_FLAGS_XCVR_SERDES:
2577 switch(np->port) {
2578 case 0:
2579 case 1:
2580 tp = &phy_template_10g_serdes;
2581 break;
2582 case 2:
2583 case 3:
2584 tp = &phy_template_1g_rgmii;
2585 break;
2586 default:
2587 return -EINVAL;
2588 }
2589 phy_addr_off = niu_atca_port_num[np->port];
2590 break;
2591
2592 default:
2593 return -EINVAL;
2594 }
2595 }
2596
2597 np->phy_ops = tp->ops;
2598 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2599
2600 return 0;
2601 }
2602
2603 static int niu_init_link(struct niu *np)
2604 {
2605 struct niu_parent *parent = np->parent;
2606 int err, ignore;
2607
2608 if (parent->plat_type == PLAT_TYPE_NIU) {
2609 err = niu_xcvr_init(np);
2610 if (err)
2611 return err;
2612 msleep(200);
2613 }
2614 err = niu_serdes_init(np);
2615 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
2616 return err;
2617 msleep(200);
2618 err = niu_xcvr_init(np);
2619 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
2620 niu_link_status(np, &ignore);
2621 return 0;
2622 }
2623
2624 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2625 {
2626 u16 reg0 = addr[4] << 8 | addr[5];
2627 u16 reg1 = addr[2] << 8 | addr[3];
2628 u16 reg2 = addr[0] << 8 | addr[1];
2629
2630 if (np->flags & NIU_FLAGS_XMAC) {
2631 nw64_mac(XMAC_ADDR0, reg0);
2632 nw64_mac(XMAC_ADDR1, reg1);
2633 nw64_mac(XMAC_ADDR2, reg2);
2634 } else {
2635 nw64_mac(BMAC_ADDR0, reg0);
2636 nw64_mac(BMAC_ADDR1, reg1);
2637 nw64_mac(BMAC_ADDR2, reg2);
2638 }
2639 }
2640
2641 static int niu_num_alt_addr(struct niu *np)
2642 {
2643 if (np->flags & NIU_FLAGS_XMAC)
2644 return XMAC_NUM_ALT_ADDR;
2645 else
2646 return BMAC_NUM_ALT_ADDR;
2647 }
2648
2649 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2650 {
2651 u16 reg0 = addr[4] << 8 | addr[5];
2652 u16 reg1 = addr[2] << 8 | addr[3];
2653 u16 reg2 = addr[0] << 8 | addr[1];
2654
2655 if (index >= niu_num_alt_addr(np))
2656 return -EINVAL;
2657
2658 if (np->flags & NIU_FLAGS_XMAC) {
2659 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2660 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2661 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2662 } else {
2663 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2664 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2665 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2666 }
2667
2668 return 0;
2669 }
2670
2671 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2672 {
2673 unsigned long reg;
2674 u64 val, mask;
2675
2676 if (index >= niu_num_alt_addr(np))
2677 return -EINVAL;
2678
2679 if (np->flags & NIU_FLAGS_XMAC) {
2680 reg = XMAC_ADDR_CMPEN;
2681 mask = 1 << index;
2682 } else {
2683 reg = BMAC_ADDR_CMPEN;
2684 mask = 1 << (index + 1);
2685 }
2686
2687 val = nr64_mac(reg);
2688 if (on)
2689 val |= mask;
2690 else
2691 val &= ~mask;
2692 nw64_mac(reg, val);
2693
2694 return 0;
2695 }
2696
2697 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2698 int num, int mac_pref)
2699 {
2700 u64 val = nr64_mac(reg);
2701 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2702 val |= num;
2703 if (mac_pref)
2704 val |= HOST_INFO_MPR;
2705 nw64_mac(reg, val);
2706 }
2707
2708 static int __set_rdc_table_num(struct niu *np,
2709 int xmac_index, int bmac_index,
2710 int rdc_table_num, int mac_pref)
2711 {
2712 unsigned long reg;
2713
2714 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2715 return -EINVAL;
2716 if (np->flags & NIU_FLAGS_XMAC)
2717 reg = XMAC_HOST_INFO(xmac_index);
2718 else
2719 reg = BMAC_HOST_INFO(bmac_index);
2720 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2721 return 0;
2722 }
2723
2724 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2725 int mac_pref)
2726 {
2727 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2728 }
2729
2730 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2731 int mac_pref)
2732 {
2733 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2734 }
2735
2736 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2737 int table_num, int mac_pref)
2738 {
2739 if (idx >= niu_num_alt_addr(np))
2740 return -EINVAL;
2741 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2742 }
2743
2744 static u64 vlan_entry_set_parity(u64 reg_val)
2745 {
2746 u64 port01_mask;
2747 u64 port23_mask;
2748
2749 port01_mask = 0x00ff;
2750 port23_mask = 0xff00;
2751
2752 if (hweight64(reg_val & port01_mask) & 1)
2753 reg_val |= ENET_VLAN_TBL_PARITY0;
2754 else
2755 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2756
2757 if (hweight64(reg_val & port23_mask) & 1)
2758 reg_val |= ENET_VLAN_TBL_PARITY1;
2759 else
2760 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2761
2762 return reg_val;
2763 }
2764
2765 static void vlan_tbl_write(struct niu *np, unsigned long index,
2766 int port, int vpr, int rdc_table)
2767 {
2768 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2769
2770 reg_val &= ~((ENET_VLAN_TBL_VPR |
2771 ENET_VLAN_TBL_VLANRDCTBLN) <<
2772 ENET_VLAN_TBL_SHIFT(port));
2773 if (vpr)
2774 reg_val |= (ENET_VLAN_TBL_VPR <<
2775 ENET_VLAN_TBL_SHIFT(port));
2776 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2777
2778 reg_val = vlan_entry_set_parity(reg_val);
2779
2780 nw64(ENET_VLAN_TBL(index), reg_val);
2781 }
2782
2783 static void vlan_tbl_clear(struct niu *np)
2784 {
2785 int i;
2786
2787 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2788 nw64(ENET_VLAN_TBL(i), 0);
2789 }
2790
2791 static int tcam_wait_bit(struct niu *np, u64 bit)
2792 {
2793 int limit = 1000;
2794
2795 while (--limit > 0) {
2796 if (nr64(TCAM_CTL) & bit)
2797 break;
2798 udelay(1);
2799 }
2800 if (limit <= 0)
2801 return -ENODEV;
2802
2803 return 0;
2804 }
2805
2806 static int tcam_flush(struct niu *np, int index)
2807 {
2808 nw64(TCAM_KEY_0, 0x00);
2809 nw64(TCAM_KEY_MASK_0, 0xff);
2810 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2811
2812 return tcam_wait_bit(np, TCAM_CTL_STAT);
2813 }
2814
2815 #if 0
2816 static int tcam_read(struct niu *np, int index,
2817 u64 *key, u64 *mask)
2818 {
2819 int err;
2820
2821 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2822 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2823 if (!err) {
2824 key[0] = nr64(TCAM_KEY_0);
2825 key[1] = nr64(TCAM_KEY_1);
2826 key[2] = nr64(TCAM_KEY_2);
2827 key[3] = nr64(TCAM_KEY_3);
2828 mask[0] = nr64(TCAM_KEY_MASK_0);
2829 mask[1] = nr64(TCAM_KEY_MASK_1);
2830 mask[2] = nr64(TCAM_KEY_MASK_2);
2831 mask[3] = nr64(TCAM_KEY_MASK_3);
2832 }
2833 return err;
2834 }
2835 #endif
2836
2837 static int tcam_write(struct niu *np, int index,
2838 u64 *key, u64 *mask)
2839 {
2840 nw64(TCAM_KEY_0, key[0]);
2841 nw64(TCAM_KEY_1, key[1]);
2842 nw64(TCAM_KEY_2, key[2]);
2843 nw64(TCAM_KEY_3, key[3]);
2844 nw64(TCAM_KEY_MASK_0, mask[0]);
2845 nw64(TCAM_KEY_MASK_1, mask[1]);
2846 nw64(TCAM_KEY_MASK_2, mask[2]);
2847 nw64(TCAM_KEY_MASK_3, mask[3]);
2848 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2849
2850 return tcam_wait_bit(np, TCAM_CTL_STAT);
2851 }
2852
2853 #if 0
2854 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2855 {
2856 int err;
2857
2858 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2859 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2860 if (!err)
2861 *data = nr64(TCAM_KEY_1);
2862
2863 return err;
2864 }
2865 #endif
2866
2867 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2868 {
2869 nw64(TCAM_KEY_1, assoc_data);
2870 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2871
2872 return tcam_wait_bit(np, TCAM_CTL_STAT);
2873 }
2874
2875 static void tcam_enable(struct niu *np, int on)
2876 {
2877 u64 val = nr64(FFLP_CFG_1);
2878
2879 if (on)
2880 val &= ~FFLP_CFG_1_TCAM_DIS;
2881 else
2882 val |= FFLP_CFG_1_TCAM_DIS;
2883 nw64(FFLP_CFG_1, val);
2884 }
2885
2886 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2887 {
2888 u64 val = nr64(FFLP_CFG_1);
2889
2890 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2891 FFLP_CFG_1_CAMLAT |
2892 FFLP_CFG_1_CAMRATIO);
2893 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2894 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2895 nw64(FFLP_CFG_1, val);
2896
2897 val = nr64(FFLP_CFG_1);
2898 val |= FFLP_CFG_1_FFLPINITDONE;
2899 nw64(FFLP_CFG_1, val);
2900 }
2901
2902 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2903 int on)
2904 {
2905 unsigned long reg;
2906 u64 val;
2907
2908 if (class < CLASS_CODE_ETHERTYPE1 ||
2909 class > CLASS_CODE_ETHERTYPE2)
2910 return -EINVAL;
2911
2912 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2913 val = nr64(reg);
2914 if (on)
2915 val |= L2_CLS_VLD;
2916 else
2917 val &= ~L2_CLS_VLD;
2918 nw64(reg, val);
2919
2920 return 0;
2921 }
2922
2923 #if 0
2924 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2925 u64 ether_type)
2926 {
2927 unsigned long reg;
2928 u64 val;
2929
2930 if (class < CLASS_CODE_ETHERTYPE1 ||
2931 class > CLASS_CODE_ETHERTYPE2 ||
2932 (ether_type & ~(u64)0xffff) != 0)
2933 return -EINVAL;
2934
2935 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2936 val = nr64(reg);
2937 val &= ~L2_CLS_ETYPE;
2938 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2939 nw64(reg, val);
2940
2941 return 0;
2942 }
2943 #endif
2944
2945 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2946 int on)
2947 {
2948 unsigned long reg;
2949 u64 val;
2950
2951 if (class < CLASS_CODE_USER_PROG1 ||
2952 class > CLASS_CODE_USER_PROG4)
2953 return -EINVAL;
2954
2955 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2956 val = nr64(reg);
2957 if (on)
2958 val |= L3_CLS_VALID;
2959 else
2960 val &= ~L3_CLS_VALID;
2961 nw64(reg, val);
2962
2963 return 0;
2964 }
2965
2966 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2967 int ipv6, u64 protocol_id,
2968 u64 tos_mask, u64 tos_val)
2969 {
2970 unsigned long reg;
2971 u64 val;
2972
2973 if (class < CLASS_CODE_USER_PROG1 ||
2974 class > CLASS_CODE_USER_PROG4 ||
2975 (protocol_id & ~(u64)0xff) != 0 ||
2976 (tos_mask & ~(u64)0xff) != 0 ||
2977 (tos_val & ~(u64)0xff) != 0)
2978 return -EINVAL;
2979
2980 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2981 val = nr64(reg);
2982 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2983 L3_CLS_TOSMASK | L3_CLS_TOS);
2984 if (ipv6)
2985 val |= L3_CLS_IPVER;
2986 val |= (protocol_id << L3_CLS_PID_SHIFT);
2987 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
2988 val |= (tos_val << L3_CLS_TOS_SHIFT);
2989 nw64(reg, val);
2990
2991 return 0;
2992 }
2993
2994 static int tcam_early_init(struct niu *np)
2995 {
2996 unsigned long i;
2997 int err;
2998
2999 tcam_enable(np, 0);
3000 tcam_set_lat_and_ratio(np,
3001 DEFAULT_TCAM_LATENCY,
3002 DEFAULT_TCAM_ACCESS_RATIO);
3003 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3004 err = tcam_user_eth_class_enable(np, i, 0);
3005 if (err)
3006 return err;
3007 }
3008 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3009 err = tcam_user_ip_class_enable(np, i, 0);
3010 if (err)
3011 return err;
3012 }
3013
3014 return 0;
3015 }
3016
3017 static int tcam_flush_all(struct niu *np)
3018 {
3019 unsigned long i;
3020
3021 for (i = 0; i < np->parent->tcam_num_entries; i++) {
3022 int err = tcam_flush(np, i);
3023 if (err)
3024 return err;
3025 }
3026 return 0;
3027 }
3028
3029 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3030 {
3031 return (u64)index | (num_entries == 1 ? HASH_TBL_ADDR_AUTOINC : 0);
3032 }
3033
3034 #if 0
3035 static int hash_read(struct niu *np, unsigned long partition,
3036 unsigned long index, unsigned long num_entries,
3037 u64 *data)
3038 {
3039 u64 val = hash_addr_regval(index, num_entries);
3040 unsigned long i;
3041
3042 if (partition >= FCRAM_NUM_PARTITIONS ||
3043 index + num_entries > FCRAM_SIZE)
3044 return -EINVAL;
3045
3046 nw64(HASH_TBL_ADDR(partition), val);
3047 for (i = 0; i < num_entries; i++)
3048 data[i] = nr64(HASH_TBL_DATA(partition));
3049
3050 return 0;
3051 }
3052 #endif
3053
3054 static int hash_write(struct niu *np, unsigned long partition,
3055 unsigned long index, unsigned long num_entries,
3056 u64 *data)
3057 {
3058 u64 val = hash_addr_regval(index, num_entries);
3059 unsigned long i;
3060
3061 if (partition >= FCRAM_NUM_PARTITIONS ||
3062 index + (num_entries * 8) > FCRAM_SIZE)
3063 return -EINVAL;
3064
3065 nw64(HASH_TBL_ADDR(partition), val);
3066 for (i = 0; i < num_entries; i++)
3067 nw64(HASH_TBL_DATA(partition), data[i]);
3068
3069 return 0;
3070 }
3071
3072 static void fflp_reset(struct niu *np)
3073 {
3074 u64 val;
3075
3076 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3077 udelay(10);
3078 nw64(FFLP_CFG_1, 0);
3079
3080 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3081 nw64(FFLP_CFG_1, val);
3082 }
3083
3084 static void fflp_set_timings(struct niu *np)
3085 {
3086 u64 val = nr64(FFLP_CFG_1);
3087
3088 val &= ~FFLP_CFG_1_FFLPINITDONE;
3089 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3090 nw64(FFLP_CFG_1, val);
3091
3092 val = nr64(FFLP_CFG_1);
3093 val |= FFLP_CFG_1_FFLPINITDONE;
3094 nw64(FFLP_CFG_1, val);
3095
3096 val = nr64(FCRAM_REF_TMR);
3097 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3098 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3099 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3100 nw64(FCRAM_REF_TMR, val);
3101 }
3102
3103 static int fflp_set_partition(struct niu *np, u64 partition,
3104 u64 mask, u64 base, int enable)
3105 {
3106 unsigned long reg;
3107 u64 val;
3108
3109 if (partition >= FCRAM_NUM_PARTITIONS ||
3110 (mask & ~(u64)0x1f) != 0 ||
3111 (base & ~(u64)0x1f) != 0)
3112 return -EINVAL;
3113
3114 reg = FLW_PRT_SEL(partition);
3115
3116 val = nr64(reg);
3117 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3118 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3119 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3120 if (enable)
3121 val |= FLW_PRT_SEL_EXT;
3122 nw64(reg, val);
3123
3124 return 0;
3125 }
3126
3127 static int fflp_disable_all_partitions(struct niu *np)
3128 {
3129 unsigned long i;
3130
3131 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3132 int err = fflp_set_partition(np, 0, 0, 0, 0);
3133 if (err)
3134 return err;
3135 }
3136 return 0;
3137 }
3138
3139 static void fflp_llcsnap_enable(struct niu *np, int on)
3140 {
3141 u64 val = nr64(FFLP_CFG_1);
3142
3143 if (on)
3144 val |= FFLP_CFG_1_LLCSNAP;
3145 else
3146 val &= ~FFLP_CFG_1_LLCSNAP;
3147 nw64(FFLP_CFG_1, val);
3148 }
3149
3150 static void fflp_errors_enable(struct niu *np, int on)
3151 {
3152 u64 val = nr64(FFLP_CFG_1);
3153
3154 if (on)
3155 val &= ~FFLP_CFG_1_ERRORDIS;
3156 else
3157 val |= FFLP_CFG_1_ERRORDIS;
3158 nw64(FFLP_CFG_1, val);
3159 }
3160
3161 static int fflp_hash_clear(struct niu *np)
3162 {
3163 struct fcram_hash_ipv4 ent;
3164 unsigned long i;
3165
3166 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3167 memset(&ent, 0, sizeof(ent));
3168 ent.header = HASH_HEADER_EXT;
3169
3170 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3171 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3172 if (err)
3173 return err;
3174 }
3175 return 0;
3176 }
3177
3178 static int fflp_early_init(struct niu *np)
3179 {
3180 struct niu_parent *parent;
3181 unsigned long flags;
3182 int err;
3183
3184 niu_lock_parent(np, flags);
3185
3186 parent = np->parent;
3187 err = 0;
3188 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3189 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3190 fflp_reset(np);
3191 fflp_set_timings(np);
3192 err = fflp_disable_all_partitions(np);
3193 if (err) {
3194 netif_printk(np, probe, KERN_DEBUG, np->dev,
3195 "fflp_disable_all_partitions failed, err=%d\n",
3196 err);
3197 goto out;
3198 }
3199 }
3200
3201 err = tcam_early_init(np);
3202 if (err) {
3203 netif_printk(np, probe, KERN_DEBUG, np->dev,
3204 "tcam_early_init failed, err=%d\n", err);
3205 goto out;
3206 }
3207 fflp_llcsnap_enable(np, 1);
3208 fflp_errors_enable(np, 0);
3209 nw64(H1POLY, 0);
3210 nw64(H2POLY, 0);
3211
3212 err = tcam_flush_all(np);
3213 if (err) {
3214 netif_printk(np, probe, KERN_DEBUG, np->dev,
3215 "tcam_flush_all failed, err=%d\n", err);
3216 goto out;
3217 }
3218 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3219 err = fflp_hash_clear(np);
3220 if (err) {
3221 netif_printk(np, probe, KERN_DEBUG, np->dev,
3222 "fflp_hash_clear failed, err=%d\n",
3223 err);
3224 goto out;
3225 }
3226 }
3227
3228 vlan_tbl_clear(np);
3229
3230 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3231 }
3232 out:
3233 niu_unlock_parent(np, flags);
3234 return err;
3235 }
3236
3237 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3238 {
3239 if (class_code < CLASS_CODE_USER_PROG1 ||
3240 class_code > CLASS_CODE_SCTP_IPV6)
3241 return -EINVAL;
3242
3243 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3244 return 0;
3245 }
3246
3247 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3248 {
3249 if (class_code < CLASS_CODE_USER_PROG1 ||
3250 class_code > CLASS_CODE_SCTP_IPV6)
3251 return -EINVAL;
3252
3253 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3254 return 0;
3255 }
3256
3257 /* Entries for the ports are interleaved in the TCAM */
3258 static u16 tcam_get_index(struct niu *np, u16 idx)
3259 {
3260 /* One entry reserved for IP fragment rule */
3261 if (idx >= (np->clas.tcam_sz - 1))
3262 idx = 0;
3263 return np->clas.tcam_top + ((idx+1) * np->parent->num_ports);
3264 }
3265
3266 static u16 tcam_get_size(struct niu *np)
3267 {
3268 /* One entry reserved for IP fragment rule */
3269 return np->clas.tcam_sz - 1;
3270 }
3271
3272 static u16 tcam_get_valid_entry_cnt(struct niu *np)
3273 {
3274 /* One entry reserved for IP fragment rule */
3275 return np->clas.tcam_valid_entries - 1;
3276 }
3277
3278 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3279 u32 offset, u32 size, u32 truesize)
3280 {
3281 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, offset, size);
3282
3283 skb->len += size;
3284 skb->data_len += size;
3285 skb->truesize += truesize;
3286 }
3287
3288 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3289 {
3290 a >>= PAGE_SHIFT;
3291 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3292
3293 return a & (MAX_RBR_RING_SIZE - 1);
3294 }
3295
3296 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3297 struct page ***link)
3298 {
3299 unsigned int h = niu_hash_rxaddr(rp, addr);
3300 struct page *p, **pp;
3301
3302 addr &= PAGE_MASK;
3303 pp = &rp->rxhash[h];
3304 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3305 if (p->index == addr) {
3306 *link = pp;
3307 goto found;
3308 }
3309 }
3310 BUG();
3311
3312 found:
3313 return p;
3314 }
3315
3316 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3317 {
3318 unsigned int h = niu_hash_rxaddr(rp, base);
3319
3320 page->index = base;
3321 page->mapping = (struct address_space *) rp->rxhash[h];
3322 rp->rxhash[h] = page;
3323 }
3324
3325 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3326 gfp_t mask, int start_index)
3327 {
3328 struct page *page;
3329 u64 addr;
3330 int i;
3331
3332 page = alloc_page(mask);
3333 if (!page)
3334 return -ENOMEM;
3335
3336 addr = np->ops->map_page(np->device, page, 0,
3337 PAGE_SIZE, DMA_FROM_DEVICE);
3338 if (!addr) {
3339 __free_page(page);
3340 return -ENOMEM;
3341 }
3342
3343 niu_hash_page(rp, page, addr);
3344 if (rp->rbr_blocks_per_page > 1)
3345 page_ref_add(page, rp->rbr_blocks_per_page - 1);
3346
3347 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3348 __le32 *rbr = &rp->rbr[start_index + i];
3349
3350 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3351 addr += rp->rbr_block_size;
3352 }
3353
3354 return 0;
3355 }
3356
3357 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3358 {
3359 int index = rp->rbr_index;
3360
3361 rp->rbr_pending++;
3362 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3363 int err = niu_rbr_add_page(np, rp, mask, index);
3364
3365 if (unlikely(err)) {
3366 rp->rbr_pending--;
3367 return;
3368 }
3369
3370 rp->rbr_index += rp->rbr_blocks_per_page;
3371 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3372 if (rp->rbr_index == rp->rbr_table_size)
3373 rp->rbr_index = 0;
3374
3375 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3376 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3377 rp->rbr_pending = 0;
3378 }
3379 }
3380 }
3381
3382 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3383 {
3384 unsigned int index = rp->rcr_index;
3385 int num_rcr = 0;
3386
3387 rp->rx_dropped++;
3388 while (1) {
3389 struct page *page, **link;
3390 u64 addr, val;
3391 u32 rcr_size;
3392
3393 num_rcr++;
3394
3395 val = le64_to_cpup(&rp->rcr[index]);
3396 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3397 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3398 page = niu_find_rxpage(rp, addr, &link);
3399
3400 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3401 RCR_ENTRY_PKTBUFSZ_SHIFT];
3402 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3403 *link = (struct page *) page->mapping;
3404 np->ops->unmap_page(np->device, page->index,
3405 PAGE_SIZE, DMA_FROM_DEVICE);
3406 page->index = 0;
3407 page->mapping = NULL;
3408 __free_page(page);
3409 rp->rbr_refill_pending++;
3410 }
3411
3412 index = NEXT_RCR(rp, index);
3413 if (!(val & RCR_ENTRY_MULTI))
3414 break;
3415
3416 }
3417 rp->rcr_index = index;
3418
3419 return num_rcr;
3420 }
3421
3422 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3423 struct rx_ring_info *rp)
3424 {
3425 unsigned int index = rp->rcr_index;
3426 struct rx_pkt_hdr1 *rh;
3427 struct sk_buff *skb;
3428 int len, num_rcr;
3429
3430 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3431 if (unlikely(!skb))
3432 return niu_rx_pkt_ignore(np, rp);
3433
3434 num_rcr = 0;
3435 while (1) {
3436 struct page *page, **link;
3437 u32 rcr_size, append_size;
3438 u64 addr, val, off;
3439
3440 num_rcr++;
3441
3442 val = le64_to_cpup(&rp->rcr[index]);
3443
3444 len = (val & RCR_ENTRY_L2_LEN) >>
3445 RCR_ENTRY_L2_LEN_SHIFT;
3446 len -= ETH_FCS_LEN;
3447
3448 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3449 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3450 page = niu_find_rxpage(rp, addr, &link);
3451
3452 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3453 RCR_ENTRY_PKTBUFSZ_SHIFT];
3454
3455 off = addr & ~PAGE_MASK;
3456 append_size = rcr_size;
3457 if (num_rcr == 1) {
3458 int ptype;
3459
3460 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3461 if ((ptype == RCR_PKT_TYPE_TCP ||
3462 ptype == RCR_PKT_TYPE_UDP) &&
3463 !(val & (RCR_ENTRY_NOPORT |
3464 RCR_ENTRY_ERROR)))
3465 skb->ip_summed = CHECKSUM_UNNECESSARY;
3466 else
3467 skb_checksum_none_assert(skb);
3468 } else if (!(val & RCR_ENTRY_MULTI))
3469 append_size = len - skb->len;
3470
3471 niu_rx_skb_append(skb, page, off, append_size, rcr_size);
3472 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3473 *link = (struct page *) page->mapping;
3474 np->ops->unmap_page(np->device, page->index,
3475 PAGE_SIZE, DMA_FROM_DEVICE);
3476 page->index = 0;
3477 page->mapping = NULL;
3478 rp->rbr_refill_pending++;
3479 } else
3480 get_page(page);
3481
3482 index = NEXT_RCR(rp, index);
3483 if (!(val & RCR_ENTRY_MULTI))
3484 break;
3485
3486 }
3487 rp->rcr_index = index;
3488
3489 len += sizeof(*rh);
3490 len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN);
3491 __pskb_pull_tail(skb, len);
3492
3493 rh = (struct rx_pkt_hdr1 *) skb->data;
3494 if (np->dev->features & NETIF_F_RXHASH)
3495 skb_set_hash(skb,
3496 ((u32)rh->hashval2_0 << 24 |
3497 (u32)rh->hashval2_1 << 16 |
3498 (u32)rh->hashval1_1 << 8 |
3499 (u32)rh->hashval1_2 << 0),
3500 PKT_HASH_TYPE_L3);
3501 skb_pull(skb, sizeof(*rh));
3502
3503 rp->rx_packets++;
3504 rp->rx_bytes += skb->len;
3505
3506 skb->protocol = eth_type_trans(skb, np->dev);
3507 skb_record_rx_queue(skb, rp->rx_channel);
3508 napi_gro_receive(napi, skb);
3509
3510 return num_rcr;
3511 }
3512
3513 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3514 {
3515 int blocks_per_page = rp->rbr_blocks_per_page;
3516 int err, index = rp->rbr_index;
3517
3518 err = 0;
3519 while (index < (rp->rbr_table_size - blocks_per_page)) {
3520 err = niu_rbr_add_page(np, rp, mask, index);
3521 if (unlikely(err))
3522 break;
3523
3524 index += blocks_per_page;
3525 }
3526
3527 rp->rbr_index = index;
3528 return err;
3529 }
3530
3531 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3532 {
3533 int i;
3534
3535 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3536 struct page *page;
3537
3538 page = rp->rxhash[i];
3539 while (page) {
3540 struct page *next = (struct page *) page->mapping;
3541 u64 base = page->index;
3542
3543 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3544 DMA_FROM_DEVICE);
3545 page->index = 0;
3546 page->mapping = NULL;
3547
3548 __free_page(page);
3549
3550 page = next;
3551 }
3552 }
3553
3554 for (i = 0; i < rp->rbr_table_size; i++)
3555 rp->rbr[i] = cpu_to_le32(0);
3556 rp->rbr_index = 0;
3557 }
3558
3559 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3560 {
3561 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3562 struct sk_buff *skb = tb->skb;
3563 struct tx_pkt_hdr *tp;
3564 u64 tx_flags;
3565 int i, len;
3566
3567 tp = (struct tx_pkt_hdr *) skb->data;
3568 tx_flags = le64_to_cpup(&tp->flags);
3569
3570 rp->tx_packets++;
3571 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3572 ((tx_flags & TXHDR_PAD) / 2));
3573
3574 len = skb_headlen(skb);
3575 np->ops->unmap_single(np->device, tb->mapping,
3576 len, DMA_TO_DEVICE);
3577
3578 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3579 rp->mark_pending--;
3580
3581 tb->skb = NULL;
3582 do {
3583 idx = NEXT_TX(rp, idx);
3584 len -= MAX_TX_DESC_LEN;
3585 } while (len > 0);
3586
3587 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3588 tb = &rp->tx_buffs[idx];
3589 BUG_ON(tb->skb != NULL);
3590 np->ops->unmap_page(np->device, tb->mapping,
3591 skb_frag_size(&skb_shinfo(skb)->frags[i]),
3592 DMA_TO_DEVICE);
3593 idx = NEXT_TX(rp, idx);
3594 }
3595
3596 dev_kfree_skb(skb);
3597
3598 return idx;
3599 }
3600
3601 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3602
3603 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3604 {
3605 struct netdev_queue *txq;
3606 u16 pkt_cnt, tmp;
3607 int cons, index;
3608 u64 cs;
3609
3610 index = (rp - np->tx_rings);
3611 txq = netdev_get_tx_queue(np->dev, index);
3612
3613 cs = rp->tx_cs;
3614 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3615 goto out;
3616
3617 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3618 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3619 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3620
3621 rp->last_pkt_cnt = tmp;
3622
3623 cons = rp->cons;
3624
3625 netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3626 "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
3627
3628 while (pkt_cnt--)
3629 cons = release_tx_packet(np, rp, cons);
3630
3631 rp->cons = cons;
3632 smp_mb();
3633
3634 out:
3635 if (unlikely(netif_tx_queue_stopped(txq) &&
3636 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3637 __netif_tx_lock(txq, smp_processor_id());
3638 if (netif_tx_queue_stopped(txq) &&
3639 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3640 netif_tx_wake_queue(txq);
3641 __netif_tx_unlock(txq);
3642 }
3643 }
3644
3645 static inline void niu_sync_rx_discard_stats(struct niu *np,
3646 struct rx_ring_info *rp,
3647 const int limit)
3648 {
3649 /* This elaborate scheme is needed for reading the RX discard
3650 * counters, as they are only 16-bit and can overflow quickly,
3651 * and because the overflow indication bit is not usable as
3652 * the counter value does not wrap, but remains at max value
3653 * 0xFFFF.
3654 *
3655 * In theory and in practice counters can be lost in between
3656 * reading nr64() and clearing the counter nw64(). For this
3657 * reason, the number of counter clearings nw64() is
3658 * limited/reduced though the limit parameter.
3659 */
3660 int rx_channel = rp->rx_channel;
3661 u32 misc, wred;
3662
3663 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3664 * following discard events: IPP (Input Port Process),
3665 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3666 * Block Ring) prefetch buffer is empty.
3667 */
3668 misc = nr64(RXMISC(rx_channel));
3669 if (unlikely((misc & RXMISC_COUNT) > limit)) {
3670 nw64(RXMISC(rx_channel), 0);
3671 rp->rx_errors += misc & RXMISC_COUNT;
3672
3673 if (unlikely(misc & RXMISC_OFLOW))
3674 dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3675 rx_channel);
3676
3677 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3678 "rx-%d: MISC drop=%u over=%u\n",
3679 rx_channel, misc, misc-limit);
3680 }
3681
3682 /* WRED (Weighted Random Early Discard) by hardware */
3683 wred = nr64(RED_DIS_CNT(rx_channel));
3684 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3685 nw64(RED_DIS_CNT(rx_channel), 0);
3686 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3687
3688 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3689 dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
3690
3691 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3692 "rx-%d: WRED drop=%u over=%u\n",
3693 rx_channel, wred, wred-limit);
3694 }
3695 }
3696
3697 static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3698 struct rx_ring_info *rp, int budget)
3699 {
3700 int qlen, rcr_done = 0, work_done = 0;
3701 struct rxdma_mailbox *mbox = rp->mbox;
3702 u64 stat;
3703
3704 #if 1
3705 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3706 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3707 #else
3708 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3709 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3710 #endif
3711 mbox->rx_dma_ctl_stat = 0;
3712 mbox->rcrstat_a = 0;
3713
3714 netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3715 "%s(chan[%d]), stat[%llx] qlen=%d\n",
3716 __func__, rp->rx_channel, (unsigned long long)stat, qlen);
3717
3718 rcr_done = work_done = 0;
3719 qlen = min(qlen, budget);
3720 while (work_done < qlen) {
3721 rcr_done += niu_process_rx_pkt(napi, np, rp);
3722 work_done++;
3723 }
3724
3725 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3726 unsigned int i;
3727
3728 for (i = 0; i < rp->rbr_refill_pending; i++)
3729 niu_rbr_refill(np, rp, GFP_ATOMIC);
3730 rp->rbr_refill_pending = 0;
3731 }
3732
3733 stat = (RX_DMA_CTL_STAT_MEX |
3734 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3735 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3736
3737 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3738
3739 /* Only sync discards stats when qlen indicate potential for drops */
3740 if (qlen > 10)
3741 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3742
3743 return work_done;
3744 }
3745
3746 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3747 {
3748 u64 v0 = lp->v0;
3749 u32 tx_vec = (v0 >> 32);
3750 u32 rx_vec = (v0 & 0xffffffff);
3751 int i, work_done = 0;
3752
3753 netif_printk(np, intr, KERN_DEBUG, np->dev,
3754 "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
3755
3756 for (i = 0; i < np->num_tx_rings; i++) {
3757 struct tx_ring_info *rp = &np->tx_rings[i];
3758 if (tx_vec & (1 << rp->tx_channel))
3759 niu_tx_work(np, rp);
3760 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3761 }
3762
3763 for (i = 0; i < np->num_rx_rings; i++) {
3764 struct rx_ring_info *rp = &np->rx_rings[i];
3765
3766 if (rx_vec & (1 << rp->rx_channel)) {
3767 int this_work_done;
3768
3769 this_work_done = niu_rx_work(&lp->napi, np, rp,
3770 budget);
3771
3772 budget -= this_work_done;
3773 work_done += this_work_done;
3774 }
3775 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3776 }
3777
3778 return work_done;
3779 }
3780
3781 static int niu_poll(struct napi_struct *napi, int budget)
3782 {
3783 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3784 struct niu *np = lp->np;
3785 int work_done;
3786
3787 work_done = niu_poll_core(np, lp, budget);
3788
3789 if (work_done < budget) {
3790 napi_complete_done(napi, work_done);
3791 niu_ldg_rearm(np, lp, 1);
3792 }
3793 return work_done;
3794 }
3795
3796 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3797 u64 stat)
3798 {
3799 netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
3800
3801 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3802 pr_cont("RBR_TMOUT ");
3803 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3804 pr_cont("RSP_CNT ");
3805 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3806 pr_cont("BYTE_EN_BUS ");
3807 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3808 pr_cont("RSP_DAT ");
3809 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3810 pr_cont("RCR_ACK ");
3811 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3812 pr_cont("RCR_SHA_PAR ");
3813 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3814 pr_cont("RBR_PRE_PAR ");
3815 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3816 pr_cont("CONFIG ");
3817 if (stat & RX_DMA_CTL_STAT_RCRINCON)
3818 pr_cont("RCRINCON ");
3819 if (stat & RX_DMA_CTL_STAT_RCRFULL)
3820 pr_cont("RCRFULL ");
3821 if (stat & RX_DMA_CTL_STAT_RBRFULL)
3822 pr_cont("RBRFULL ");
3823 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3824 pr_cont("RBRLOGPAGE ");
3825 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3826 pr_cont("CFIGLOGPAGE ");
3827 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3828 pr_cont("DC_FIDO ");
3829
3830 pr_cont(")\n");
3831 }
3832
3833 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3834 {
3835 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3836 int err = 0;
3837
3838
3839 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3840 RX_DMA_CTL_STAT_PORT_FATAL))
3841 err = -EINVAL;
3842
3843 if (err) {
3844 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3845 rp->rx_channel,
3846 (unsigned long long) stat);
3847
3848 niu_log_rxchan_errors(np, rp, stat);
3849 }
3850
3851 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3852 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3853
3854 return err;
3855 }
3856
3857 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3858 u64 cs)
3859 {
3860 netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
3861
3862 if (cs & TX_CS_MBOX_ERR)
3863 pr_cont("MBOX ");
3864 if (cs & TX_CS_PKT_SIZE_ERR)
3865 pr_cont("PKT_SIZE ");
3866 if (cs & TX_CS_TX_RING_OFLOW)
3867 pr_cont("TX_RING_OFLOW ");
3868 if (cs & TX_CS_PREF_BUF_PAR_ERR)
3869 pr_cont("PREF_BUF_PAR ");
3870 if (cs & TX_CS_NACK_PREF)
3871 pr_cont("NACK_PREF ");
3872 if (cs & TX_CS_NACK_PKT_RD)
3873 pr_cont("NACK_PKT_RD ");
3874 if (cs & TX_CS_CONF_PART_ERR)
3875 pr_cont("CONF_PART ");
3876 if (cs & TX_CS_PKT_PRT_ERR)
3877 pr_cont("PKT_PTR ");
3878
3879 pr_cont(")\n");
3880 }
3881
3882 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3883 {
3884 u64 cs, logh, logl;
3885
3886 cs = nr64(TX_CS(rp->tx_channel));
3887 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3888 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3889
3890 netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3891 rp->tx_channel,
3892 (unsigned long long)cs,
3893 (unsigned long long)logh,
3894 (unsigned long long)logl);
3895
3896 niu_log_txchan_errors(np, rp, cs);
3897
3898 return -ENODEV;
3899 }
3900
3901 static int niu_mif_interrupt(struct niu *np)
3902 {
3903 u64 mif_status = nr64(MIF_STATUS);
3904 int phy_mdint = 0;
3905
3906 if (np->flags & NIU_FLAGS_XMAC) {
3907 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3908
3909 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3910 phy_mdint = 1;
3911 }
3912
3913 netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3914 (unsigned long long)mif_status, phy_mdint);
3915
3916 return -ENODEV;
3917 }
3918
3919 static void niu_xmac_interrupt(struct niu *np)
3920 {
3921 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3922 u64 val;
3923
3924 val = nr64_mac(XTXMAC_STATUS);
3925 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3926 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3927 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3928 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3929 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3930 mp->tx_fifo_errors++;
3931 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3932 mp->tx_overflow_errors++;
3933 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3934 mp->tx_max_pkt_size_errors++;
3935 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3936 mp->tx_underflow_errors++;
3937
3938 val = nr64_mac(XRXMAC_STATUS);
3939 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3940 mp->rx_local_faults++;
3941 if (val & XRXMAC_STATUS_RFLT_DET)
3942 mp->rx_remote_faults++;
3943 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3944 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3945 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3946 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3947 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3948 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3949 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3950 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3951 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3952 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3953 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3954 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3955 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3956 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3957 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3958 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3959 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3960 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3961 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3962 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3963 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3964 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3965 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3966 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3967 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3968 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3969 if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
3970 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3971 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3972 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3973 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3974 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3975 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3976 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3977 if (val & XRXMAC_STATUS_RXUFLOW)
3978 mp->rx_underflows++;
3979 if (val & XRXMAC_STATUS_RXOFLOW)
3980 mp->rx_overflows++;
3981
3982 val = nr64_mac(XMAC_FC_STAT);
3983 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3984 mp->pause_off_state++;
3985 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3986 mp->pause_on_state++;
3987 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
3988 mp->pause_received++;
3989 }
3990
3991 static void niu_bmac_interrupt(struct niu *np)
3992 {
3993 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
3994 u64 val;
3995
3996 val = nr64_mac(BTXMAC_STATUS);
3997 if (val & BTXMAC_STATUS_UNDERRUN)
3998 mp->tx_underflow_errors++;
3999 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4000 mp->tx_max_pkt_size_errors++;
4001 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4002 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4003 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4004 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4005
4006 val = nr64_mac(BRXMAC_STATUS);
4007 if (val & BRXMAC_STATUS_OVERFLOW)
4008 mp->rx_overflows++;
4009 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4010 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4011 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4012 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4013 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4014 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4015 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4016 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4017
4018 val = nr64_mac(BMAC_CTRL_STATUS);
4019 if (val & BMAC_CTRL_STATUS_NOPAUSE)
4020 mp->pause_off_state++;
4021 if (val & BMAC_CTRL_STATUS_PAUSE)
4022 mp->pause_on_state++;
4023 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4024 mp->pause_received++;
4025 }
4026
4027 static int niu_mac_interrupt(struct niu *np)
4028 {
4029 if (np->flags & NIU_FLAGS_XMAC)
4030 niu_xmac_interrupt(np);
4031 else
4032 niu_bmac_interrupt(np);
4033
4034 return 0;
4035 }
4036
4037 static void niu_log_device_error(struct niu *np, u64 stat)
4038 {
4039 netdev_err(np->dev, "Core device errors ( ");
4040
4041 if (stat & SYS_ERR_MASK_META2)
4042 pr_cont("META2 ");
4043 if (stat & SYS_ERR_MASK_META1)
4044 pr_cont("META1 ");
4045 if (stat & SYS_ERR_MASK_PEU)
4046 pr_cont("PEU ");
4047 if (stat & SYS_ERR_MASK_TXC)
4048 pr_cont("TXC ");
4049 if (stat & SYS_ERR_MASK_RDMC)
4050 pr_cont("RDMC ");
4051 if (stat & SYS_ERR_MASK_TDMC)
4052 pr_cont("TDMC ");
4053 if (stat & SYS_ERR_MASK_ZCP)
4054 pr_cont("ZCP ");
4055 if (stat & SYS_ERR_MASK_FFLP)
4056 pr_cont("FFLP ");
4057 if (stat & SYS_ERR_MASK_IPP)
4058 pr_cont("IPP ");
4059 if (stat & SYS_ERR_MASK_MAC)
4060 pr_cont("MAC ");
4061 if (stat & SYS_ERR_MASK_SMX)
4062 pr_cont("SMX ");
4063
4064 pr_cont(")\n");
4065 }
4066
4067 static int niu_device_error(struct niu *np)
4068 {
4069 u64 stat = nr64(SYS_ERR_STAT);
4070
4071 netdev_err(np->dev, "Core device error, stat[%llx]\n",
4072 (unsigned long long)stat);
4073
4074 niu_log_device_error(np, stat);
4075
4076 return -ENODEV;
4077 }
4078
4079 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4080 u64 v0, u64 v1, u64 v2)
4081 {
4082
4083 int i, err = 0;
4084
4085 lp->v0 = v0;
4086 lp->v1 = v1;
4087 lp->v2 = v2;
4088
4089 if (v1 & 0x00000000ffffffffULL) {
4090 u32 rx_vec = (v1 & 0xffffffff);
4091
4092 for (i = 0; i < np->num_rx_rings; i++) {
4093 struct rx_ring_info *rp = &np->rx_rings[i];
4094
4095 if (rx_vec & (1 << rp->rx_channel)) {
4096 int r = niu_rx_error(np, rp);
4097 if (r) {
4098 err = r;
4099 } else {
4100 if (!v0)
4101 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4102 RX_DMA_CTL_STAT_MEX);
4103 }
4104 }
4105 }
4106 }
4107 if (v1 & 0x7fffffff00000000ULL) {
4108 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4109
4110 for (i = 0; i < np->num_tx_rings; i++) {
4111 struct tx_ring_info *rp = &np->tx_rings[i];
4112
4113 if (tx_vec & (1 << rp->tx_channel)) {
4114 int r = niu_tx_error(np, rp);
4115 if (r)
4116 err = r;
4117 }
4118 }
4119 }
4120 if ((v0 | v1) & 0x8000000000000000ULL) {
4121 int r = niu_mif_interrupt(np);
4122 if (r)
4123 err = r;
4124 }
4125 if (v2) {
4126 if (v2 & 0x01ef) {
4127 int r = niu_mac_interrupt(np);
4128 if (r)
4129 err = r;
4130 }
4131 if (v2 & 0x0210) {
4132 int r = niu_device_error(np);
4133 if (r)
4134 err = r;
4135 }
4136 }
4137
4138 if (err)
4139 niu_enable_interrupts(np, 0);
4140
4141 return err;
4142 }
4143
4144 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4145 int ldn)
4146 {
4147 struct rxdma_mailbox *mbox = rp->mbox;
4148 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4149
4150 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4151 RX_DMA_CTL_STAT_RCRTO);
4152 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4153
4154 netif_printk(np, intr, KERN_DEBUG, np->dev,
4155 "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
4156 }
4157
4158 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4159 int ldn)
4160 {
4161 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4162
4163 netif_printk(np, intr, KERN_DEBUG, np->dev,
4164 "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
4165 }
4166
4167 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4168 {
4169 struct niu_parent *parent = np->parent;
4170 u32 rx_vec, tx_vec;
4171 int i;
4172
4173 tx_vec = (v0 >> 32);
4174 rx_vec = (v0 & 0xffffffff);
4175
4176 for (i = 0; i < np->num_rx_rings; i++) {
4177 struct rx_ring_info *rp = &np->rx_rings[i];
4178 int ldn = LDN_RXDMA(rp->rx_channel);
4179
4180 if (parent->ldg_map[ldn] != ldg)
4181 continue;
4182
4183 nw64(LD_IM0(ldn), LD_IM0_MASK);
4184 if (rx_vec & (1 << rp->rx_channel))
4185 niu_rxchan_intr(np, rp, ldn);
4186 }
4187
4188 for (i = 0; i < np->num_tx_rings; i++) {
4189 struct tx_ring_info *rp = &np->tx_rings[i];
4190 int ldn = LDN_TXDMA(rp->tx_channel);
4191
4192 if (parent->ldg_map[ldn] != ldg)
4193 continue;
4194
4195 nw64(LD_IM0(ldn), LD_IM0_MASK);
4196 if (tx_vec & (1 << rp->tx_channel))
4197 niu_txchan_intr(np, rp, ldn);
4198 }
4199 }
4200
4201 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4202 u64 v0, u64 v1, u64 v2)
4203 {
4204 if (likely(napi_schedule_prep(&lp->napi))) {
4205 lp->v0 = v0;
4206 lp->v1 = v1;
4207 lp->v2 = v2;
4208 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4209 __napi_schedule(&lp->napi);
4210 }
4211 }
4212
4213 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4214 {
4215 struct niu_ldg *lp = dev_id;
4216 struct niu *np = lp->np;
4217 int ldg = lp->ldg_num;
4218 unsigned long flags;
4219 u64 v0, v1, v2;
4220
4221 if (netif_msg_intr(np))
4222 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4223 __func__, lp, ldg);
4224
4225 spin_lock_irqsave(&np->lock, flags);
4226
4227 v0 = nr64(LDSV0(ldg));
4228 v1 = nr64(LDSV1(ldg));
4229 v2 = nr64(LDSV2(ldg));
4230
4231 if (netif_msg_intr(np))
4232 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
4233 (unsigned long long) v0,
4234 (unsigned long long) v1,
4235 (unsigned long long) v2);
4236
4237 if (unlikely(!v0 && !v1 && !v2)) {
4238 spin_unlock_irqrestore(&np->lock, flags);
4239 return IRQ_NONE;
4240 }
4241
4242 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4243 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4244 if (err)
4245 goto out;
4246 }
4247 if (likely(v0 & ~((u64)1 << LDN_MIF)))
4248 niu_schedule_napi(np, lp, v0, v1, v2);
4249 else
4250 niu_ldg_rearm(np, lp, 1);
4251 out:
4252 spin_unlock_irqrestore(&np->lock, flags);
4253
4254 return IRQ_HANDLED;
4255 }
4256
4257 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4258 {
4259 if (rp->mbox) {
4260 np->ops->free_coherent(np->device,
4261 sizeof(struct rxdma_mailbox),
4262 rp->mbox, rp->mbox_dma);
4263 rp->mbox = NULL;
4264 }
4265 if (rp->rcr) {
4266 np->ops->free_coherent(np->device,
4267 MAX_RCR_RING_SIZE * sizeof(__le64),
4268 rp->rcr, rp->rcr_dma);
4269 rp->rcr = NULL;
4270 rp->rcr_table_size = 0;
4271 rp->rcr_index = 0;
4272 }
4273 if (rp->rbr) {
4274 niu_rbr_free(np, rp);
4275
4276 np->ops->free_coherent(np->device,
4277 MAX_RBR_RING_SIZE * sizeof(__le32),
4278 rp->rbr, rp->rbr_dma);
4279 rp->rbr = NULL;
4280 rp->rbr_table_size = 0;
4281 rp->rbr_index = 0;
4282 }
4283 kfree(rp->rxhash);
4284 rp->rxhash = NULL;
4285 }
4286
4287 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4288 {
4289 if (rp->mbox) {
4290 np->ops->free_coherent(np->device,
4291 sizeof(struct txdma_mailbox),
4292 rp->mbox, rp->mbox_dma);
4293 rp->mbox = NULL;
4294 }
4295 if (rp->descr) {
4296 int i;
4297
4298 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4299 if (rp->tx_buffs[i].skb)
4300 (void) release_tx_packet(np, rp, i);
4301 }
4302
4303 np->ops->free_coherent(np->device,
4304 MAX_TX_RING_SIZE * sizeof(__le64),
4305 rp->descr, rp->descr_dma);
4306 rp->descr = NULL;
4307 rp->pending = 0;
4308 rp->prod = 0;
4309 rp->cons = 0;
4310 rp->wrap_bit = 0;
4311 }
4312 }
4313
4314 static void niu_free_channels(struct niu *np)
4315 {
4316 int i;
4317
4318 if (np->rx_rings) {
4319 for (i = 0; i < np->num_rx_rings; i++) {
4320 struct rx_ring_info *rp = &np->rx_rings[i];
4321
4322 niu_free_rx_ring_info(np, rp);
4323 }
4324 kfree(np->rx_rings);
4325 np->rx_rings = NULL;
4326 np->num_rx_rings = 0;
4327 }
4328
4329 if (np->tx_rings) {
4330 for (i = 0; i < np->num_tx_rings; i++) {
4331 struct tx_ring_info *rp = &np->tx_rings[i];
4332
4333 niu_free_tx_ring_info(np, rp);
4334 }
4335 kfree(np->tx_rings);
4336 np->tx_rings = NULL;
4337 np->num_tx_rings = 0;
4338 }
4339 }
4340
4341 static int niu_alloc_rx_ring_info(struct niu *np,
4342 struct rx_ring_info *rp)
4343 {
4344 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4345
4346 rp->rxhash = kcalloc(MAX_RBR_RING_SIZE, sizeof(struct page *),
4347 GFP_KERNEL);
4348 if (!rp->rxhash)
4349 return -ENOMEM;
4350
4351 rp->mbox = np->ops->alloc_coherent(np->device,
4352 sizeof(struct rxdma_mailbox),
4353 &rp->mbox_dma, GFP_KERNEL);
4354 if (!rp->mbox)
4355 return -ENOMEM;
4356 if ((unsigned long)rp->mbox & (64UL - 1)) {
4357 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4358 rp->mbox);
4359 return -EINVAL;
4360 }
4361
4362 rp->rcr = np->ops->alloc_coherent(np->device,
4363 MAX_RCR_RING_SIZE * sizeof(__le64),
4364 &rp->rcr_dma, GFP_KERNEL);
4365 if (!rp->rcr)
4366 return -ENOMEM;
4367 if ((unsigned long)rp->rcr & (64UL - 1)) {
4368 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4369 rp->rcr);
4370 return -EINVAL;
4371 }
4372 rp->rcr_table_size = MAX_RCR_RING_SIZE;
4373 rp->rcr_index = 0;
4374
4375 rp->rbr = np->ops->alloc_coherent(np->device,
4376 MAX_RBR_RING_SIZE * sizeof(__le32),
4377 &rp->rbr_dma, GFP_KERNEL);
4378 if (!rp->rbr)
4379 return -ENOMEM;
4380 if ((unsigned long)rp->rbr & (64UL - 1)) {
4381 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4382 rp->rbr);
4383 return -EINVAL;
4384 }
4385 rp->rbr_table_size = MAX_RBR_RING_SIZE;
4386 rp->rbr_index = 0;
4387 rp->rbr_pending = 0;
4388
4389 return 0;
4390 }
4391
4392 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4393 {
4394 int mtu = np->dev->mtu;
4395
4396 /* These values are recommended by the HW designers for fair
4397 * utilization of DRR amongst the rings.
4398 */
4399 rp->max_burst = mtu + 32;
4400 if (rp->max_burst > 4096)
4401 rp->max_burst = 4096;
4402 }
4403
4404 static int niu_alloc_tx_ring_info(struct niu *np,
4405 struct tx_ring_info *rp)
4406 {
4407 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4408
4409 rp->mbox = np->ops->alloc_coherent(np->device,
4410 sizeof(struct txdma_mailbox),
4411 &rp->mbox_dma, GFP_KERNEL);
4412 if (!rp->mbox)
4413 return -ENOMEM;
4414 if ((unsigned long)rp->mbox & (64UL - 1)) {
4415 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4416 rp->mbox);
4417 return -EINVAL;
4418 }
4419
4420 rp->descr = np->ops->alloc_coherent(np->device,
4421 MAX_TX_RING_SIZE * sizeof(__le64),
4422 &rp->descr_dma, GFP_KERNEL);
4423 if (!rp->descr)
4424 return -ENOMEM;
4425 if ((unsigned long)rp->descr & (64UL - 1)) {
4426 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4427 rp->descr);
4428 return -EINVAL;
4429 }
4430
4431 rp->pending = MAX_TX_RING_SIZE;
4432 rp->prod = 0;
4433 rp->cons = 0;
4434 rp->wrap_bit = 0;
4435
4436 /* XXX make these configurable... XXX */
4437 rp->mark_freq = rp->pending / 4;
4438
4439 niu_set_max_burst(np, rp);
4440
4441 return 0;
4442 }
4443
4444 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4445 {
4446 u16 bss;
4447
4448 bss = min(PAGE_SHIFT, 15);
4449
4450 rp->rbr_block_size = 1 << bss;
4451 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4452
4453 rp->rbr_sizes[0] = 256;
4454 rp->rbr_sizes[1] = 1024;
4455 if (np->dev->mtu > ETH_DATA_LEN) {
4456 switch (PAGE_SIZE) {
4457 case 4 * 1024:
4458 rp->rbr_sizes[2] = 4096;
4459 break;
4460
4461 default:
4462 rp->rbr_sizes[2] = 8192;
4463 break;
4464 }
4465 } else {
4466 rp->rbr_sizes[2] = 2048;
4467 }
4468 rp->rbr_sizes[3] = rp->rbr_block_size;
4469 }
4470
4471 static int niu_alloc_channels(struct niu *np)
4472 {
4473 struct niu_parent *parent = np->parent;
4474 int first_rx_channel, first_tx_channel;
4475 int num_rx_rings, num_tx_rings;
4476 struct rx_ring_info *rx_rings;
4477 struct tx_ring_info *tx_rings;
4478 int i, port, err;
4479
4480 port = np->port;
4481 first_rx_channel = first_tx_channel = 0;
4482 for (i = 0; i < port; i++) {
4483 first_rx_channel += parent->rxchan_per_port[i];
4484 first_tx_channel += parent->txchan_per_port[i];
4485 }
4486
4487 num_rx_rings = parent->rxchan_per_port[port];
4488 num_tx_rings = parent->txchan_per_port[port];
4489
4490 rx_rings = kcalloc(num_rx_rings, sizeof(struct rx_ring_info),
4491 GFP_KERNEL);
4492 err = -ENOMEM;
4493 if (!rx_rings)
4494 goto out_err;
4495
4496 np->num_rx_rings = num_rx_rings;
4497 smp_wmb();
4498 np->rx_rings = rx_rings;
4499
4500 netif_set_real_num_rx_queues(np->dev, num_rx_rings);
4501
4502 for (i = 0; i < np->num_rx_rings; i++) {
4503 struct rx_ring_info *rp = &np->rx_rings[i];
4504
4505 rp->np = np;
4506 rp->rx_channel = first_rx_channel + i;
4507
4508 err = niu_alloc_rx_ring_info(np, rp);
4509 if (err)
4510 goto out_err;
4511
4512 niu_size_rbr(np, rp);
4513
4514 /* XXX better defaults, configurable, etc... XXX */
4515 rp->nonsyn_window = 64;
4516 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4517 rp->syn_window = 64;
4518 rp->syn_threshold = rp->rcr_table_size - 64;
4519 rp->rcr_pkt_threshold = 16;
4520 rp->rcr_timeout = 8;
4521 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4522 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4523 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4524
4525 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4526 if (err)
4527 return err;
4528 }
4529
4530 tx_rings = kcalloc(num_tx_rings, sizeof(struct tx_ring_info),
4531 GFP_KERNEL);
4532 err = -ENOMEM;
4533 if (!tx_rings)
4534 goto out_err;
4535
4536 np->num_tx_rings = num_tx_rings;
4537 smp_wmb();
4538 np->tx_rings = tx_rings;
4539
4540 netif_set_real_num_tx_queues(np->dev, num_tx_rings);
4541
4542 for (i = 0; i < np->num_tx_rings; i++) {
4543 struct tx_ring_info *rp = &np->tx_rings[i];
4544
4545 rp->np = np;
4546 rp->tx_channel = first_tx_channel + i;
4547
4548 err = niu_alloc_tx_ring_info(np, rp);
4549 if (err)
4550 goto out_err;
4551 }
4552
4553 return 0;
4554
4555 out_err:
4556 niu_free_channels(np);
4557 return err;
4558 }
4559
4560 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4561 {
4562 int limit = 1000;
4563
4564 while (--limit > 0) {
4565 u64 val = nr64(TX_CS(channel));
4566 if (val & TX_CS_SNG_STATE)
4567 return 0;
4568 }
4569 return -ENODEV;
4570 }
4571
4572 static int niu_tx_channel_stop(struct niu *np, int channel)
4573 {
4574 u64 val = nr64(TX_CS(channel));
4575
4576 val |= TX_CS_STOP_N_GO;
4577 nw64(TX_CS(channel), val);
4578
4579 return niu_tx_cs_sng_poll(np, channel);
4580 }
4581
4582 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4583 {
4584 int limit = 1000;
4585
4586 while (--limit > 0) {
4587 u64 val = nr64(TX_CS(channel));
4588 if (!(val & TX_CS_RST))
4589 return 0;
4590 }
4591 return -ENODEV;
4592 }
4593
4594 static int niu_tx_channel_reset(struct niu *np, int channel)
4595 {
4596 u64 val = nr64(TX_CS(channel));
4597 int err;
4598
4599 val |= TX_CS_RST;
4600 nw64(TX_CS(channel), val);
4601
4602 err = niu_tx_cs_reset_poll(np, channel);
4603 if (!err)
4604 nw64(TX_RING_KICK(channel), 0);
4605
4606 return err;
4607 }
4608
4609 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4610 {
4611 u64 val;
4612
4613 nw64(TX_LOG_MASK1(channel), 0);
4614 nw64(TX_LOG_VAL1(channel), 0);
4615 nw64(TX_LOG_MASK2(channel), 0);
4616 nw64(TX_LOG_VAL2(channel), 0);
4617 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4618 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4619 nw64(TX_LOG_PAGE_HDL(channel), 0);
4620
4621 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4622 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4623 nw64(TX_LOG_PAGE_VLD(channel), val);
4624
4625 /* XXX TXDMA 32bit mode? XXX */
4626
4627 return 0;
4628 }
4629
4630 static void niu_txc_enable_port(struct niu *np, int on)
4631 {
4632 unsigned long flags;
4633 u64 val, mask;
4634
4635 niu_lock_parent(np, flags);
4636 val = nr64(TXC_CONTROL);
4637 mask = (u64)1 << np->port;
4638 if (on) {
4639 val |= TXC_CONTROL_ENABLE | mask;
4640 } else {
4641 val &= ~mask;
4642 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4643 val &= ~TXC_CONTROL_ENABLE;
4644 }
4645 nw64(TXC_CONTROL, val);
4646 niu_unlock_parent(np, flags);
4647 }
4648
4649 static void niu_txc_set_imask(struct niu *np, u64 imask)
4650 {
4651 unsigned long flags;
4652 u64 val;
4653
4654 niu_lock_parent(np, flags);
4655 val = nr64(TXC_INT_MASK);
4656 val &= ~TXC_INT_MASK_VAL(np->port);
4657 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4658 niu_unlock_parent(np, flags);
4659 }
4660
4661 static void niu_txc_port_dma_enable(struct niu *np, int on)
4662 {
4663 u64 val = 0;
4664
4665 if (on) {
4666 int i;
4667
4668 for (i = 0; i < np->num_tx_rings; i++)
4669 val |= (1 << np->tx_rings[i].tx_channel);
4670 }
4671 nw64(TXC_PORT_DMA(np->port), val);
4672 }
4673
4674 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4675 {
4676 int err, channel = rp->tx_channel;
4677 u64 val, ring_len;
4678
4679 err = niu_tx_channel_stop(np, channel);
4680 if (err)
4681 return err;
4682
4683 err = niu_tx_channel_reset(np, channel);
4684 if (err)
4685 return err;
4686
4687 err = niu_tx_channel_lpage_init(np, channel);
4688 if (err)
4689 return err;
4690
4691 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4692 nw64(TX_ENT_MSK(channel), 0);
4693
4694 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4695 TX_RNG_CFIG_STADDR)) {
4696 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4697 channel, (unsigned long long)rp->descr_dma);
4698 return -EINVAL;
4699 }
4700
4701 /* The length field in TX_RNG_CFIG is measured in 64-byte
4702 * blocks. rp->pending is the number of TX descriptors in
4703 * our ring, 8 bytes each, thus we divide by 8 bytes more
4704 * to get the proper value the chip wants.
4705 */
4706 ring_len = (rp->pending / 8);
4707
4708 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4709 rp->descr_dma);
4710 nw64(TX_RNG_CFIG(channel), val);
4711
4712 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4713 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4714 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4715 channel, (unsigned long long)rp->mbox_dma);
4716 return -EINVAL;
4717 }
4718 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4719 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4720
4721 nw64(TX_CS(channel), 0);
4722
4723 rp->last_pkt_cnt = 0;
4724
4725 return 0;
4726 }
4727
4728 static void niu_init_rdc_groups(struct niu *np)
4729 {
4730 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4731 int i, first_table_num = tp->first_table_num;
4732
4733 for (i = 0; i < tp->num_tables; i++) {
4734 struct rdc_table *tbl = &tp->tables[i];
4735 int this_table = first_table_num + i;
4736 int slot;
4737
4738 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4739 nw64(RDC_TBL(this_table, slot),
4740 tbl->rxdma_channel[slot]);
4741 }
4742
4743 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4744 }
4745
4746 static void niu_init_drr_weight(struct niu *np)
4747 {
4748 int type = phy_decode(np->parent->port_phy, np->port);
4749 u64 val;
4750
4751 switch (type) {
4752 case PORT_TYPE_10G:
4753 val = PT_DRR_WEIGHT_DEFAULT_10G;
4754 break;
4755
4756 case PORT_TYPE_1G:
4757 default:
4758 val = PT_DRR_WEIGHT_DEFAULT_1G;
4759 break;
4760 }
4761 nw64(PT_DRR_WT(np->port), val);
4762 }
4763
4764 static int niu_init_hostinfo(struct niu *np)
4765 {
4766 struct niu_parent *parent = np->parent;
4767 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4768 int i, err, num_alt = niu_num_alt_addr(np);
4769 int first_rdc_table = tp->first_table_num;
4770
4771 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4772 if (err)
4773 return err;
4774
4775 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4776 if (err)
4777 return err;
4778
4779 for (i = 0; i < num_alt; i++) {
4780 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4781 if (err)
4782 return err;
4783 }
4784
4785 return 0;
4786 }
4787
4788 static int niu_rx_channel_reset(struct niu *np, int channel)
4789 {
4790 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4791 RXDMA_CFIG1_RST, 1000, 10,
4792 "RXDMA_CFIG1");
4793 }
4794
4795 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4796 {
4797 u64 val;
4798
4799 nw64(RX_LOG_MASK1(channel), 0);
4800 nw64(RX_LOG_VAL1(channel), 0);
4801 nw64(RX_LOG_MASK2(channel), 0);
4802 nw64(RX_LOG_VAL2(channel), 0);
4803 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4804 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4805 nw64(RX_LOG_PAGE_HDL(channel), 0);
4806
4807 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4808 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4809 nw64(RX_LOG_PAGE_VLD(channel), val);
4810
4811 return 0;
4812 }
4813
4814 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4815 {
4816 u64 val;
4817
4818 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4819 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4820 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4821 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4822 nw64(RDC_RED_PARA(rp->rx_channel), val);
4823 }
4824
4825 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4826 {
4827 u64 val = 0;
4828
4829 *ret = 0;
4830 switch (rp->rbr_block_size) {
4831 case 4 * 1024:
4832 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4833 break;
4834 case 8 * 1024:
4835 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4836 break;
4837 case 16 * 1024:
4838 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4839 break;
4840 case 32 * 1024:
4841 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4842 break;
4843 default:
4844 return -EINVAL;
4845 }
4846 val |= RBR_CFIG_B_VLD2;
4847 switch (rp->rbr_sizes[2]) {
4848 case 2 * 1024:
4849 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4850 break;
4851 case 4 * 1024:
4852 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4853 break;
4854 case 8 * 1024:
4855 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4856 break;
4857 case 16 * 1024:
4858 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4859 break;
4860
4861 default:
4862 return -EINVAL;
4863 }
4864 val |= RBR_CFIG_B_VLD1;
4865 switch (rp->rbr_sizes[1]) {
4866 case 1 * 1024:
4867 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4868 break;
4869 case 2 * 1024:
4870 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4871 break;
4872 case 4 * 1024:
4873 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4874 break;
4875 case 8 * 1024:
4876 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4877 break;
4878
4879 default:
4880 return -EINVAL;
4881 }
4882 val |= RBR_CFIG_B_VLD0;
4883 switch (rp->rbr_sizes[0]) {
4884 case 256:
4885 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4886 break;
4887 case 512:
4888 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4889 break;
4890 case 1 * 1024:
4891 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4892 break;
4893 case 2 * 1024:
4894 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4895 break;
4896
4897 default:
4898 return -EINVAL;
4899 }
4900
4901 *ret = val;
4902 return 0;
4903 }
4904
4905 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4906 {
4907 u64 val = nr64(RXDMA_CFIG1(channel));
4908 int limit;
4909
4910 if (on)
4911 val |= RXDMA_CFIG1_EN;
4912 else
4913 val &= ~RXDMA_CFIG1_EN;
4914 nw64(RXDMA_CFIG1(channel), val);
4915
4916 limit = 1000;
4917 while (--limit > 0) {
4918 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4919 break;
4920 udelay(10);
4921 }
4922 if (limit <= 0)
4923 return -ENODEV;
4924 return 0;
4925 }
4926
4927 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4928 {
4929 int err, channel = rp->rx_channel;
4930 u64 val;
4931
4932 err = niu_rx_channel_reset(np, channel);
4933 if (err)
4934 return err;
4935
4936 err = niu_rx_channel_lpage_init(np, channel);
4937 if (err)
4938 return err;
4939
4940 niu_rx_channel_wred_init(np, rp);
4941
4942 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4943 nw64(RX_DMA_CTL_STAT(channel),
4944 (RX_DMA_CTL_STAT_MEX |
4945 RX_DMA_CTL_STAT_RCRTHRES |
4946 RX_DMA_CTL_STAT_RCRTO |
4947 RX_DMA_CTL_STAT_RBR_EMPTY));
4948 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4949 nw64(RXDMA_CFIG2(channel),
4950 ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) |
4951 RXDMA_CFIG2_FULL_HDR));
4952 nw64(RBR_CFIG_A(channel),
4953 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4954 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4955 err = niu_compute_rbr_cfig_b(rp, &val);
4956 if (err)
4957 return err;
4958 nw64(RBR_CFIG_B(channel), val);
4959 nw64(RCRCFIG_A(channel),
4960 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4961 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4962 nw64(RCRCFIG_B(channel),
4963 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4964 RCRCFIG_B_ENTOUT |
4965 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4966
4967 err = niu_enable_rx_channel(np, channel, 1);
4968 if (err)
4969 return err;
4970
4971 nw64(RBR_KICK(channel), rp->rbr_index);
4972
4973 val = nr64(RX_DMA_CTL_STAT(channel));
4974 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4975 nw64(RX_DMA_CTL_STAT(channel), val);
4976
4977 return 0;
4978 }
4979
4980 static int niu_init_rx_channels(struct niu *np)
4981 {
4982 unsigned long flags;
4983 u64 seed = jiffies_64;
4984 int err, i;
4985
4986 niu_lock_parent(np, flags);
4987 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4988 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4989 niu_unlock_parent(np, flags);
4990
4991 /* XXX RXDMA 32bit mode? XXX */
4992
4993 niu_init_rdc_groups(np);
4994 niu_init_drr_weight(np);
4995
4996 err = niu_init_hostinfo(np);
4997 if (err)
4998 return err;
4999
5000 for (i = 0; i < np->num_rx_rings; i++) {
5001 struct rx_ring_info *rp = &np->rx_rings[i];
5002
5003 err = niu_init_one_rx_channel(np, rp);
5004 if (err)
5005 return err;
5006 }
5007
5008 return 0;
5009 }
5010
5011 static int niu_set_ip_frag_rule(struct niu *np)
5012 {
5013 struct niu_parent *parent = np->parent;
5014 struct niu_classifier *cp = &np->clas;
5015 struct niu_tcam_entry *tp;
5016 int index, err;
5017
5018 index = cp->tcam_top;
5019 tp = &parent->tcam[index];
5020
5021 /* Note that the noport bit is the same in both ipv4 and
5022 * ipv6 format TCAM entries.
5023 */
5024 memset(tp, 0, sizeof(*tp));
5025 tp->key[1] = TCAM_V4KEY1_NOPORT;
5026 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5027 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5028 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5029 err = tcam_write(np, index, tp->key, tp->key_mask);
5030 if (err)
5031 return err;
5032 err = tcam_assoc_write(np, index, tp->assoc_data);
5033 if (err)
5034 return err;
5035 tp->valid = 1;
5036 cp->tcam_valid_entries++;
5037
5038 return 0;
5039 }
5040
5041 static int niu_init_classifier_hw(struct niu *np)
5042 {
5043 struct niu_parent *parent = np->parent;
5044 struct niu_classifier *cp = &np->clas;
5045 int i, err;
5046
5047 nw64(H1POLY, cp->h1_init);
5048 nw64(H2POLY, cp->h2_init);
5049
5050 err = niu_init_hostinfo(np);
5051 if (err)
5052 return err;
5053
5054 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5055 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5056
5057 vlan_tbl_write(np, i, np->port,
5058 vp->vlan_pref, vp->rdc_num);
5059 }
5060
5061 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5062 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5063
5064 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5065 ap->rdc_num, ap->mac_pref);
5066 if (err)
5067 return err;
5068 }
5069
5070 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5071 int index = i - CLASS_CODE_USER_PROG1;
5072
5073 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5074 if (err)
5075 return err;
5076 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5077 if (err)
5078 return err;
5079 }
5080
5081 err = niu_set_ip_frag_rule(np);
5082 if (err)
5083 return err;
5084
5085 tcam_enable(np, 1);
5086
5087 return 0;
5088 }
5089
5090 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5091 {
5092 nw64(ZCP_RAM_DATA0, data[0]);
5093 nw64(ZCP_RAM_DATA1, data[1]);
5094 nw64(ZCP_RAM_DATA2, data[2]);
5095 nw64(ZCP_RAM_DATA3, data[3]);
5096 nw64(ZCP_RAM_DATA4, data[4]);
5097 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5098 nw64(ZCP_RAM_ACC,
5099 (ZCP_RAM_ACC_WRITE |
5100 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5101 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5102
5103 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5104 1000, 100);
5105 }
5106
5107 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5108 {
5109 int err;
5110
5111 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5112 1000, 100);
5113 if (err) {
5114 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5115 (unsigned long long)nr64(ZCP_RAM_ACC));
5116 return err;
5117 }
5118
5119 nw64(ZCP_RAM_ACC,
5120 (ZCP_RAM_ACC_READ |
5121 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5122 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5123
5124 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5125 1000, 100);
5126 if (err) {
5127 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5128 (unsigned long long)nr64(ZCP_RAM_ACC));
5129 return err;
5130 }
5131
5132 data[0] = nr64(ZCP_RAM_DATA0);
5133 data[1] = nr64(ZCP_RAM_DATA1);
5134 data[2] = nr64(ZCP_RAM_DATA2);
5135 data[3] = nr64(ZCP_RAM_DATA3);
5136 data[4] = nr64(ZCP_RAM_DATA4);
5137
5138 return 0;
5139 }
5140
5141 static void niu_zcp_cfifo_reset(struct niu *np)
5142 {
5143 u64 val = nr64(RESET_CFIFO);
5144
5145 val |= RESET_CFIFO_RST(np->port);
5146 nw64(RESET_CFIFO, val);
5147 udelay(10);
5148
5149 val &= ~RESET_CFIFO_RST(np->port);
5150 nw64(RESET_CFIFO, val);
5151 }
5152
5153 static int niu_init_zcp(struct niu *np)
5154 {
5155 u64 data[5], rbuf[5];
5156 int i, max, err;
5157
5158 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5159 if (np->port == 0 || np->port == 1)
5160 max = ATLAS_P0_P1_CFIFO_ENTRIES;
5161 else
5162 max = ATLAS_P2_P3_CFIFO_ENTRIES;
5163 } else
5164 max = NIU_CFIFO_ENTRIES;
5165
5166 data[0] = 0;
5167 data[1] = 0;
5168 data[2] = 0;
5169 data[3] = 0;
5170 data[4] = 0;
5171
5172 for (i = 0; i < max; i++) {
5173 err = niu_zcp_write(np, i, data);
5174 if (err)
5175 return err;
5176 err = niu_zcp_read(np, i, rbuf);
5177 if (err)
5178 return err;
5179 }
5180
5181 niu_zcp_cfifo_reset(np);
5182 nw64(CFIFO_ECC(np->port), 0);
5183 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5184 (void) nr64(ZCP_INT_STAT);
5185 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5186
5187 return 0;
5188 }
5189
5190 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5191 {
5192 u64 val = nr64_ipp(IPP_CFIG);
5193
5194 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5195 nw64_ipp(IPP_DFIFO_WR_PTR, index);
5196 nw64_ipp(IPP_DFIFO_WR0, data[0]);
5197 nw64_ipp(IPP_DFIFO_WR1, data[1]);
5198 nw64_ipp(IPP_DFIFO_WR2, data[2]);
5199 nw64_ipp(IPP_DFIFO_WR3, data[3]);
5200 nw64_ipp(IPP_DFIFO_WR4, data[4]);
5201 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5202 }
5203
5204 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5205 {
5206 nw64_ipp(IPP_DFIFO_RD_PTR, index);
5207 data[0] = nr64_ipp(IPP_DFIFO_RD0);
5208 data[1] = nr64_ipp(IPP_DFIFO_RD1);
5209 data[2] = nr64_ipp(IPP_DFIFO_RD2);
5210 data[3] = nr64_ipp(IPP_DFIFO_RD3);
5211 data[4] = nr64_ipp(IPP_DFIFO_RD4);
5212 }
5213
5214 static int niu_ipp_reset(struct niu *np)
5215 {
5216 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5217 1000, 100, "IPP_CFIG");
5218 }
5219
5220 static int niu_init_ipp(struct niu *np)
5221 {
5222 u64 data[5], rbuf[5], val;
5223 int i, max, err;
5224
5225 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5226 if (np->port == 0 || np->port == 1)
5227 max = ATLAS_P0_P1_DFIFO_ENTRIES;
5228 else
5229 max = ATLAS_P2_P3_DFIFO_ENTRIES;
5230 } else
5231 max = NIU_DFIFO_ENTRIES;
5232
5233 data[0] = 0;
5234 data[1] = 0;
5235 data[2] = 0;
5236 data[3] = 0;
5237 data[4] = 0;
5238
5239 for (i = 0; i < max; i++) {
5240 niu_ipp_write(np, i, data);
5241 niu_ipp_read(np, i, rbuf);
5242 }
5243
5244 (void) nr64_ipp(IPP_INT_STAT);
5245 (void) nr64_ipp(IPP_INT_STAT);
5246
5247 err = niu_ipp_reset(np);
5248 if (err)
5249 return err;
5250
5251 (void) nr64_ipp(IPP_PKT_DIS);
5252 (void) nr64_ipp(IPP_BAD_CS_CNT);
5253 (void) nr64_ipp(IPP_ECC);
5254
5255 (void) nr64_ipp(IPP_INT_STAT);
5256
5257 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5258
5259 val = nr64_ipp(IPP_CFIG);
5260 val &= ~IPP_CFIG_IP_MAX_PKT;
5261 val |= (IPP_CFIG_IPP_ENABLE |
5262 IPP_CFIG_DFIFO_ECC_EN |
5263 IPP_CFIG_DROP_BAD_CRC |
5264 IPP_CFIG_CKSUM_EN |
5265 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5266 nw64_ipp(IPP_CFIG, val);
5267
5268 return 0;
5269 }
5270
5271 static void niu_handle_led(struct niu *np, int status)
5272 {
5273 u64 val;
5274 val = nr64_mac(XMAC_CONFIG);
5275
5276 if ((np->flags & NIU_FLAGS_10G) != 0 &&
5277 (np->flags & NIU_FLAGS_FIBER) != 0) {
5278 if (status) {
5279 val |= XMAC_CONFIG_LED_POLARITY;
5280 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5281 } else {
5282 val |= XMAC_CONFIG_FORCE_LED_ON;
5283 val &= ~XMAC_CONFIG_LED_POLARITY;
5284 }
5285 }
5286
5287 nw64_mac(XMAC_CONFIG, val);
5288 }
5289
5290 static void niu_init_xif_xmac(struct niu *np)
5291 {
5292 struct niu_link_config *lp = &np->link_config;
5293 u64 val;
5294
5295 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5296 val = nr64(MIF_CONFIG);
5297 val |= MIF_CONFIG_ATCA_GE;
5298 nw64(MIF_CONFIG, val);
5299 }
5300
5301 val = nr64_mac(XMAC_CONFIG);
5302 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5303
5304 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5305
5306 if (lp->loopback_mode == LOOPBACK_MAC) {
5307 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5308 val |= XMAC_CONFIG_LOOPBACK;
5309 } else {
5310 val &= ~XMAC_CONFIG_LOOPBACK;
5311 }
5312
5313 if (np->flags & NIU_FLAGS_10G) {
5314 val &= ~XMAC_CONFIG_LFS_DISABLE;
5315 } else {
5316 val |= XMAC_CONFIG_LFS_DISABLE;
5317 if (!(np->flags & NIU_FLAGS_FIBER) &&
5318 !(np->flags & NIU_FLAGS_XCVR_SERDES))
5319 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5320 else
5321 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5322 }
5323
5324 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5325
5326 if (lp->active_speed == SPEED_100)
5327 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5328 else
5329 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5330
5331 nw64_mac(XMAC_CONFIG, val);
5332
5333 val = nr64_mac(XMAC_CONFIG);
5334 val &= ~XMAC_CONFIG_MODE_MASK;
5335 if (np->flags & NIU_FLAGS_10G) {
5336 val |= XMAC_CONFIG_MODE_XGMII;
5337 } else {
5338 if (lp->active_speed == SPEED_1000)
5339 val |= XMAC_CONFIG_MODE_GMII;
5340 else
5341 val |= XMAC_CONFIG_MODE_MII;
5342 }
5343
5344 nw64_mac(XMAC_CONFIG, val);
5345 }
5346
5347 static void niu_init_xif_bmac(struct niu *np)
5348 {
5349 struct niu_link_config *lp = &np->link_config;
5350 u64 val;
5351
5352 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5353
5354 if (lp->loopback_mode == LOOPBACK_MAC)
5355 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5356 else
5357 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5358
5359 if (lp->active_speed == SPEED_1000)
5360 val |= BMAC_XIF_CONFIG_GMII_MODE;
5361 else
5362 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5363
5364 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5365 BMAC_XIF_CONFIG_LED_POLARITY);
5366
5367 if (!(np->flags & NIU_FLAGS_10G) &&
5368 !(np->flags & NIU_FLAGS_FIBER) &&
5369 lp->active_speed == SPEED_100)
5370 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5371 else
5372 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5373
5374 nw64_mac(BMAC_XIF_CONFIG, val);
5375 }
5376
5377 static void niu_init_xif(struct niu *np)
5378 {
5379 if (np->flags & NIU_FLAGS_XMAC)
5380 niu_init_xif_xmac(np);
5381 else
5382 niu_init_xif_bmac(np);
5383 }
5384
5385 static void niu_pcs_mii_reset(struct niu *np)
5386 {
5387 int limit = 1000;
5388 u64 val = nr64_pcs(PCS_MII_CTL);
5389 val |= PCS_MII_CTL_RST;
5390 nw64_pcs(PCS_MII_CTL, val);
5391 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5392 udelay(100);
5393 val = nr64_pcs(PCS_MII_CTL);
5394 }
5395 }
5396
5397 static void niu_xpcs_reset(struct niu *np)
5398 {
5399 int limit = 1000;
5400 u64 val = nr64_xpcs(XPCS_CONTROL1);
5401 val |= XPCS_CONTROL1_RESET;
5402 nw64_xpcs(XPCS_CONTROL1, val);
5403 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5404 udelay(100);
5405 val = nr64_xpcs(XPCS_CONTROL1);
5406 }
5407 }
5408
5409 static int niu_init_pcs(struct niu *np)
5410 {
5411 struct niu_link_config *lp = &np->link_config;
5412 u64 val;
5413
5414 switch (np->flags & (NIU_FLAGS_10G |
5415 NIU_FLAGS_FIBER |
5416 NIU_FLAGS_XCVR_SERDES)) {
5417 case NIU_FLAGS_FIBER:
5418 /* 1G fiber */
5419 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5420 nw64_pcs(PCS_DPATH_MODE, 0);
5421 niu_pcs_mii_reset(np);
5422 break;
5423
5424 case NIU_FLAGS_10G:
5425 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5426 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5427 /* 10G SERDES */
5428 if (!(np->flags & NIU_FLAGS_XMAC))
5429 return -EINVAL;
5430
5431 /* 10G copper or fiber */
5432 val = nr64_mac(XMAC_CONFIG);
5433 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5434 nw64_mac(XMAC_CONFIG, val);
5435
5436 niu_xpcs_reset(np);
5437
5438 val = nr64_xpcs(XPCS_CONTROL1);
5439 if (lp->loopback_mode == LOOPBACK_PHY)
5440 val |= XPCS_CONTROL1_LOOPBACK;
5441 else
5442 val &= ~XPCS_CONTROL1_LOOPBACK;
5443 nw64_xpcs(XPCS_CONTROL1, val);
5444
5445 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5446 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5447 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5448 break;
5449
5450
5451 case NIU_FLAGS_XCVR_SERDES:
5452 /* 1G SERDES */
5453 niu_pcs_mii_reset(np);
5454 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5455 nw64_pcs(PCS_DPATH_MODE, 0);
5456 break;
5457
5458 case 0:
5459 /* 1G copper */
5460 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5461 /* 1G RGMII FIBER */
5462 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5463 niu_pcs_mii_reset(np);
5464 break;
5465
5466 default:
5467 return -EINVAL;
5468 }
5469
5470 return 0;
5471 }
5472
5473 static int niu_reset_tx_xmac(struct niu *np)
5474 {
5475 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5476 (XTXMAC_SW_RST_REG_RS |
5477 XTXMAC_SW_RST_SOFT_RST),
5478 1000, 100, "XTXMAC_SW_RST");
5479 }
5480
5481 static int niu_reset_tx_bmac(struct niu *np)
5482 {
5483 int limit;
5484
5485 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5486 limit = 1000;
5487 while (--limit >= 0) {
5488 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5489 break;
5490 udelay(100);
5491 }
5492 if (limit < 0) {
5493 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
5494 np->port,
5495 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5496 return -ENODEV;
5497 }
5498
5499 return 0;
5500 }
5501
5502 static int niu_reset_tx_mac(struct niu *np)
5503 {
5504 if (np->flags & NIU_FLAGS_XMAC)
5505 return niu_reset_tx_xmac(np);
5506 else
5507 return niu_reset_tx_bmac(np);
5508 }
5509
5510 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5511 {
5512 u64 val;
5513
5514 val = nr64_mac(XMAC_MIN);
5515 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5516 XMAC_MIN_RX_MIN_PKT_SIZE);
5517 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5518 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5519 nw64_mac(XMAC_MIN, val);
5520
5521 nw64_mac(XMAC_MAX, max);
5522
5523 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5524
5525 val = nr64_mac(XMAC_IPG);
5526 if (np->flags & NIU_FLAGS_10G) {
5527 val &= ~XMAC_IPG_IPG_XGMII;
5528 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5529 } else {
5530 val &= ~XMAC_IPG_IPG_MII_GMII;
5531 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5532 }
5533 nw64_mac(XMAC_IPG, val);
5534
5535 val = nr64_mac(XMAC_CONFIG);
5536 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5537 XMAC_CONFIG_STRETCH_MODE |
5538 XMAC_CONFIG_VAR_MIN_IPG_EN |
5539 XMAC_CONFIG_TX_ENABLE);
5540 nw64_mac(XMAC_CONFIG, val);
5541
5542 nw64_mac(TXMAC_FRM_CNT, 0);
5543 nw64_mac(TXMAC_BYTE_CNT, 0);
5544 }
5545
5546 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5547 {
5548 u64 val;
5549
5550 nw64_mac(BMAC_MIN_FRAME, min);
5551 nw64_mac(BMAC_MAX_FRAME, max);
5552
5553 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5554 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5555 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5556
5557 val = nr64_mac(BTXMAC_CONFIG);
5558 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5559 BTXMAC_CONFIG_ENABLE);
5560 nw64_mac(BTXMAC_CONFIG, val);
5561 }
5562
5563 static void niu_init_tx_mac(struct niu *np)
5564 {
5565 u64 min, max;
5566
5567 min = 64;
5568 if (np->dev->mtu > ETH_DATA_LEN)
5569 max = 9216;
5570 else
5571 max = 1522;
5572
5573 /* The XMAC_MIN register only accepts values for TX min which
5574 * have the low 3 bits cleared.
5575 */
5576 BUG_ON(min & 0x7);
5577
5578 if (np->flags & NIU_FLAGS_XMAC)
5579 niu_init_tx_xmac(np, min, max);
5580 else
5581 niu_init_tx_bmac(np, min, max);
5582 }
5583
5584 static int niu_reset_rx_xmac(struct niu *np)
5585 {
5586 int limit;
5587
5588 nw64_mac(XRXMAC_SW_RST,
5589 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5590 limit = 1000;
5591 while (--limit >= 0) {
5592 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5593 XRXMAC_SW_RST_SOFT_RST)))
5594 break;
5595 udelay(100);
5596 }
5597 if (limit < 0) {
5598 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
5599 np->port,
5600 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5601 return -ENODEV;
5602 }
5603
5604 return 0;
5605 }
5606
5607 static int niu_reset_rx_bmac(struct niu *np)
5608 {
5609 int limit;
5610
5611 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5612 limit = 1000;
5613 while (--limit >= 0) {
5614 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5615 break;
5616 udelay(100);
5617 }
5618 if (limit < 0) {
5619 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
5620 np->port,
5621 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5622 return -ENODEV;
5623 }
5624
5625 return 0;
5626 }
5627
5628 static int niu_reset_rx_mac(struct niu *np)
5629 {
5630 if (np->flags & NIU_FLAGS_XMAC)
5631 return niu_reset_rx_xmac(np);
5632 else
5633 return niu_reset_rx_bmac(np);
5634 }
5635
5636 static void niu_init_rx_xmac(struct niu *np)
5637 {
5638 struct niu_parent *parent = np->parent;
5639 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5640 int first_rdc_table = tp->first_table_num;
5641 unsigned long i;
5642 u64 val;
5643
5644 nw64_mac(XMAC_ADD_FILT0, 0);
5645 nw64_mac(XMAC_ADD_FILT1, 0);
5646 nw64_mac(XMAC_ADD_FILT2, 0);
5647 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5648 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5649 for (i = 0; i < MAC_NUM_HASH; i++)
5650 nw64_mac(XMAC_HASH_TBL(i), 0);
5651 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5652 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5653 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5654
5655 val = nr64_mac(XMAC_CONFIG);
5656 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5657 XMAC_CONFIG_PROMISCUOUS |
5658 XMAC_CONFIG_PROMISC_GROUP |
5659 XMAC_CONFIG_ERR_CHK_DIS |
5660 XMAC_CONFIG_RX_CRC_CHK_DIS |
5661 XMAC_CONFIG_RESERVED_MULTICAST |
5662 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5663 XMAC_CONFIG_ADDR_FILTER_EN |
5664 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5665 XMAC_CONFIG_STRIP_CRC |
5666 XMAC_CONFIG_PASS_FLOW_CTRL |
5667 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5668 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5669 nw64_mac(XMAC_CONFIG, val);
5670
5671 nw64_mac(RXMAC_BT_CNT, 0);
5672 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5673 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5674 nw64_mac(RXMAC_FRAG_CNT, 0);
5675 nw64_mac(RXMAC_HIST_CNT1, 0);
5676 nw64_mac(RXMAC_HIST_CNT2, 0);
5677 nw64_mac(RXMAC_HIST_CNT3, 0);
5678 nw64_mac(RXMAC_HIST_CNT4, 0);
5679 nw64_mac(RXMAC_HIST_CNT5, 0);
5680 nw64_mac(RXMAC_HIST_CNT6, 0);
5681 nw64_mac(RXMAC_HIST_CNT7, 0);
5682 nw64_mac(RXMAC_MPSZER_CNT, 0);
5683 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5684 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5685 nw64_mac(LINK_FAULT_CNT, 0);
5686 }
5687
5688 static void niu_init_rx_bmac(struct niu *np)
5689 {
5690 struct niu_parent *parent = np->parent;
5691 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5692 int first_rdc_table = tp->first_table_num;
5693 unsigned long i;
5694 u64 val;
5695
5696 nw64_mac(BMAC_ADD_FILT0, 0);
5697 nw64_mac(BMAC_ADD_FILT1, 0);
5698 nw64_mac(BMAC_ADD_FILT2, 0);
5699 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5700 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5701 for (i = 0; i < MAC_NUM_HASH; i++)
5702 nw64_mac(BMAC_HASH_TBL(i), 0);
5703 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5704 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5705 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5706
5707 val = nr64_mac(BRXMAC_CONFIG);
5708 val &= ~(BRXMAC_CONFIG_ENABLE |
5709 BRXMAC_CONFIG_STRIP_PAD |
5710 BRXMAC_CONFIG_STRIP_FCS |
5711 BRXMAC_CONFIG_PROMISC |
5712 BRXMAC_CONFIG_PROMISC_GRP |
5713 BRXMAC_CONFIG_ADDR_FILT_EN |
5714 BRXMAC_CONFIG_DISCARD_DIS);
5715 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5716 nw64_mac(BRXMAC_CONFIG, val);
5717
5718 val = nr64_mac(BMAC_ADDR_CMPEN);
5719 val |= BMAC_ADDR_CMPEN_EN0;
5720 nw64_mac(BMAC_ADDR_CMPEN, val);
5721 }
5722
5723 static void niu_init_rx_mac(struct niu *np)
5724 {
5725 niu_set_primary_mac(np, np->dev->dev_addr);
5726
5727 if (np->flags & NIU_FLAGS_XMAC)
5728 niu_init_rx_xmac(np);
5729 else
5730 niu_init_rx_bmac(np);
5731 }
5732
5733 static void niu_enable_tx_xmac(struct niu *np, int on)
5734 {
5735 u64 val = nr64_mac(XMAC_CONFIG);
5736
5737 if (on)
5738 val |= XMAC_CONFIG_TX_ENABLE;
5739 else
5740 val &= ~XMAC_CONFIG_TX_ENABLE;
5741 nw64_mac(XMAC_CONFIG, val);
5742 }
5743
5744 static void niu_enable_tx_bmac(struct niu *np, int on)
5745 {
5746 u64 val = nr64_mac(BTXMAC_CONFIG);
5747
5748 if (on)
5749 val |= BTXMAC_CONFIG_ENABLE;
5750 else
5751 val &= ~BTXMAC_CONFIG_ENABLE;
5752 nw64_mac(BTXMAC_CONFIG, val);
5753 }
5754
5755 static void niu_enable_tx_mac(struct niu *np, int on)
5756 {
5757 if (np->flags & NIU_FLAGS_XMAC)
5758 niu_enable_tx_xmac(np, on);
5759 else
5760 niu_enable_tx_bmac(np, on);
5761 }
5762
5763 static void niu_enable_rx_xmac(struct niu *np, int on)
5764 {
5765 u64 val = nr64_mac(XMAC_CONFIG);
5766
5767 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5768 XMAC_CONFIG_PROMISCUOUS);
5769
5770 if (np->flags & NIU_FLAGS_MCAST)
5771 val |= XMAC_CONFIG_HASH_FILTER_EN;
5772 if (np->flags & NIU_FLAGS_PROMISC)
5773 val |= XMAC_CONFIG_PROMISCUOUS;
5774
5775 if (on)
5776 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5777 else
5778 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5779 nw64_mac(XMAC_CONFIG, val);
5780 }
5781
5782 static void niu_enable_rx_bmac(struct niu *np, int on)
5783 {
5784 u64 val = nr64_mac(BRXMAC_CONFIG);
5785
5786 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5787 BRXMAC_CONFIG_PROMISC);
5788
5789 if (np->flags & NIU_FLAGS_MCAST)
5790 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5791 if (np->flags & NIU_FLAGS_PROMISC)
5792 val |= BRXMAC_CONFIG_PROMISC;
5793
5794 if (on)
5795 val |= BRXMAC_CONFIG_ENABLE;
5796 else
5797 val &= ~BRXMAC_CONFIG_ENABLE;
5798 nw64_mac(BRXMAC_CONFIG, val);
5799 }
5800
5801 static void niu_enable_rx_mac(struct niu *np, int on)
5802 {
5803 if (np->flags & NIU_FLAGS_XMAC)
5804 niu_enable_rx_xmac(np, on);
5805 else
5806 niu_enable_rx_bmac(np, on);
5807 }
5808
5809 static int niu_init_mac(struct niu *np)
5810 {
5811 int err;
5812
5813 niu_init_xif(np);
5814 err = niu_init_pcs(np);
5815 if (err)
5816 return err;
5817
5818 err = niu_reset_tx_mac(np);
5819 if (err)
5820 return err;
5821 niu_init_tx_mac(np);
5822 err = niu_reset_rx_mac(np);
5823 if (err)
5824 return err;
5825 niu_init_rx_mac(np);
5826
5827 /* This looks hookey but the RX MAC reset we just did will
5828 * undo some of the state we setup in niu_init_tx_mac() so we
5829 * have to call it again. In particular, the RX MAC reset will
5830 * set the XMAC_MAX register back to it's default value.
5831 */
5832 niu_init_tx_mac(np);
5833 niu_enable_tx_mac(np, 1);
5834
5835 niu_enable_rx_mac(np, 1);
5836
5837 return 0;
5838 }
5839
5840 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5841 {
5842 (void) niu_tx_channel_stop(np, rp->tx_channel);
5843 }
5844
5845 static void niu_stop_tx_channels(struct niu *np)
5846 {
5847 int i;
5848
5849 for (i = 0; i < np->num_tx_rings; i++) {
5850 struct tx_ring_info *rp = &np->tx_rings[i];
5851
5852 niu_stop_one_tx_channel(np, rp);
5853 }
5854 }
5855
5856 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5857 {
5858 (void) niu_tx_channel_reset(np, rp->tx_channel);
5859 }
5860
5861 static void niu_reset_tx_channels(struct niu *np)
5862 {
5863 int i;
5864
5865 for (i = 0; i < np->num_tx_rings; i++) {
5866 struct tx_ring_info *rp = &np->tx_rings[i];
5867
5868 niu_reset_one_tx_channel(np, rp);
5869 }
5870 }
5871
5872 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5873 {
5874 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5875 }
5876
5877 static void niu_stop_rx_channels(struct niu *np)
5878 {
5879 int i;
5880
5881 for (i = 0; i < np->num_rx_rings; i++) {
5882 struct rx_ring_info *rp = &np->rx_rings[i];
5883
5884 niu_stop_one_rx_channel(np, rp);
5885 }
5886 }
5887
5888 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5889 {
5890 int channel = rp->rx_channel;
5891
5892 (void) niu_rx_channel_reset(np, channel);
5893 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5894 nw64(RX_DMA_CTL_STAT(channel), 0);
5895 (void) niu_enable_rx_channel(np, channel, 0);
5896 }
5897
5898 static void niu_reset_rx_channels(struct niu *np)
5899 {
5900 int i;
5901
5902 for (i = 0; i < np->num_rx_rings; i++) {
5903 struct rx_ring_info *rp = &np->rx_rings[i];
5904
5905 niu_reset_one_rx_channel(np, rp);
5906 }
5907 }
5908
5909 static void niu_disable_ipp(struct niu *np)
5910 {
5911 u64 rd, wr, val;
5912 int limit;
5913
5914 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5915 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5916 limit = 100;
5917 while (--limit >= 0 && (rd != wr)) {
5918 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5919 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5920 }
5921 if (limit < 0 &&
5922 (rd != 0 && wr != 1)) {
5923 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5924 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5925 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
5926 }
5927
5928 val = nr64_ipp(IPP_CFIG);
5929 val &= ~(IPP_CFIG_IPP_ENABLE |
5930 IPP_CFIG_DFIFO_ECC_EN |
5931 IPP_CFIG_DROP_BAD_CRC |
5932 IPP_CFIG_CKSUM_EN);
5933 nw64_ipp(IPP_CFIG, val);
5934
5935 (void) niu_ipp_reset(np);
5936 }
5937
5938 static int niu_init_hw(struct niu *np)
5939 {
5940 int i, err;
5941
5942 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
5943 niu_txc_enable_port(np, 1);
5944 niu_txc_port_dma_enable(np, 1);
5945 niu_txc_set_imask(np, 0);
5946
5947 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
5948 for (i = 0; i < np->num_tx_rings; i++) {
5949 struct tx_ring_info *rp = &np->tx_rings[i];
5950
5951 err = niu_init_one_tx_channel(np, rp);
5952 if (err)
5953 return err;
5954 }
5955
5956 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
5957 err = niu_init_rx_channels(np);
5958 if (err)
5959 goto out_uninit_tx_channels;
5960
5961 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
5962 err = niu_init_classifier_hw(np);
5963 if (err)
5964 goto out_uninit_rx_channels;
5965
5966 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
5967 err = niu_init_zcp(np);
5968 if (err)
5969 goto out_uninit_rx_channels;
5970
5971 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
5972 err = niu_init_ipp(np);
5973 if (err)
5974 goto out_uninit_rx_channels;
5975
5976 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
5977 err = niu_init_mac(np);
5978 if (err)
5979 goto out_uninit_ipp;
5980
5981 return 0;
5982
5983 out_uninit_ipp:
5984 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
5985 niu_disable_ipp(np);
5986
5987 out_uninit_rx_channels:
5988 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
5989 niu_stop_rx_channels(np);
5990 niu_reset_rx_channels(np);
5991
5992 out_uninit_tx_channels:
5993 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
5994 niu_stop_tx_channels(np);
5995 niu_reset_tx_channels(np);
5996
5997 return err;
5998 }
5999
6000 static void niu_stop_hw(struct niu *np)
6001 {
6002 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
6003 niu_enable_interrupts(np, 0);
6004
6005 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
6006 niu_enable_rx_mac(np, 0);
6007
6008 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
6009 niu_disable_ipp(np);
6010
6011 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
6012 niu_stop_tx_channels(np);
6013
6014 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
6015 niu_stop_rx_channels(np);
6016
6017 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
6018 niu_reset_tx_channels(np);
6019
6020 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
6021 niu_reset_rx_channels(np);
6022 }
6023
6024 static void niu_set_irq_name(struct niu *np)
6025 {
6026 int port = np->port;
6027 int i, j = 1;
6028
6029 sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6030
6031 if (port == 0) {
6032 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6033 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6034 j = 3;
6035 }
6036
6037 for (i = 0; i < np->num_ldg - j; i++) {
6038 if (i < np->num_rx_rings)
6039 sprintf(np->irq_name[i+j], "%s-rx-%d",
6040 np->dev->name, i);
6041 else if (i < np->num_tx_rings + np->num_rx_rings)
6042 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6043 i - np->num_rx_rings);
6044 }
6045 }
6046
6047 static int niu_request_irq(struct niu *np)
6048 {
6049 int i, j, err;
6050
6051 niu_set_irq_name(np);
6052
6053 err = 0;
6054 for (i = 0; i < np->num_ldg; i++) {
6055 struct niu_ldg *lp = &np->ldg[i];
6056
6057 err = request_irq(lp->irq, niu_interrupt, IRQF_SHARED,
6058 np->irq_name[i], lp);
6059 if (err)
6060 goto out_free_irqs;
6061
6062 }
6063
6064 return 0;
6065
6066 out_free_irqs:
6067 for (j = 0; j < i; j++) {
6068 struct niu_ldg *lp = &np->ldg[j];
6069
6070 free_irq(lp->irq, lp);
6071 }
6072 return err;
6073 }
6074
6075 static void niu_free_irq(struct niu *np)
6076 {
6077 int i;
6078
6079 for (i = 0; i < np->num_ldg; i++) {
6080 struct niu_ldg *lp = &np->ldg[i];
6081
6082 free_irq(lp->irq, lp);
6083 }
6084 }
6085
6086 static void niu_enable_napi(struct niu *np)
6087 {
6088 int i;
6089
6090 for (i = 0; i < np->num_ldg; i++)
6091 napi_enable(&np->ldg[i].napi);
6092 }
6093
6094 static void niu_disable_napi(struct niu *np)
6095 {
6096 int i;
6097
6098 for (i = 0; i < np->num_ldg; i++)
6099 napi_disable(&np->ldg[i].napi);
6100 }
6101
6102 static int niu_open(struct net_device *dev)
6103 {
6104 struct niu *np = netdev_priv(dev);
6105 int err;
6106
6107 netif_carrier_off(dev);
6108
6109 err = niu_alloc_channels(np);
6110 if (err)
6111 goto out_err;
6112
6113 err = niu_enable_interrupts(np, 0);
6114 if (err)
6115 goto out_free_channels;
6116
6117 err = niu_request_irq(np);
6118 if (err)
6119 goto out_free_channels;
6120
6121 niu_enable_napi(np);
6122
6123 spin_lock_irq(&np->lock);
6124
6125 err = niu_init_hw(np);
6126 if (!err) {
6127 timer_setup(&np->timer, niu_timer, 0);
6128 np->timer.expires = jiffies + HZ;
6129
6130 err = niu_enable_interrupts(np, 1);
6131 if (err)
6132 niu_stop_hw(np);
6133 }
6134
6135 spin_unlock_irq(&np->lock);
6136
6137 if (err) {
6138 niu_disable_napi(np);
6139 goto out_free_irq;
6140 }
6141
6142 netif_tx_start_all_queues(dev);
6143
6144 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6145 netif_carrier_on(dev);
6146
6147 add_timer(&np->timer);
6148
6149 return 0;
6150
6151 out_free_irq:
6152 niu_free_irq(np);
6153
6154 out_free_channels:
6155 niu_free_channels(np);
6156
6157 out_err:
6158 return err;
6159 }
6160
6161 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6162 {
6163 cancel_work_sync(&np->reset_task);
6164
6165 niu_disable_napi(np);
6166 netif_tx_stop_all_queues(dev);
6167
6168 del_timer_sync(&np->timer);
6169
6170 spin_lock_irq(&np->lock);
6171
6172 niu_stop_hw(np);
6173
6174 spin_unlock_irq(&np->lock);
6175 }
6176
6177 static int niu_close(struct net_device *dev)
6178 {
6179 struct niu *np = netdev_priv(dev);
6180
6181 niu_full_shutdown(np, dev);
6182
6183 niu_free_irq(np);
6184
6185 niu_free_channels(np);
6186
6187 niu_handle_led(np, 0);
6188
6189 return 0;
6190 }
6191
6192 static void niu_sync_xmac_stats(struct niu *np)
6193 {
6194 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6195
6196 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6197 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6198
6199 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6200 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6201 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6202 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6203 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6204 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6205 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6206 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6207 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6208 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6209 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6210 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6211 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6212 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6213 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6214 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6215 }
6216
6217 static void niu_sync_bmac_stats(struct niu *np)
6218 {
6219 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6220
6221 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6222 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6223
6224 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6225 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6226 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6227 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6228 }
6229
6230 static void niu_sync_mac_stats(struct niu *np)
6231 {
6232 if (np->flags & NIU_FLAGS_XMAC)
6233 niu_sync_xmac_stats(np);
6234 else
6235 niu_sync_bmac_stats(np);
6236 }
6237
6238 static void niu_get_rx_stats(struct niu *np,
6239 struct rtnl_link_stats64 *stats)
6240 {
6241 u64 pkts, dropped, errors, bytes;
6242 struct rx_ring_info *rx_rings;
6243 int i;
6244
6245 pkts = dropped = errors = bytes = 0;
6246
6247 rx_rings = READ_ONCE(np->rx_rings);
6248 if (!rx_rings)
6249 goto no_rings;
6250
6251 for (i = 0; i < np->num_rx_rings; i++) {
6252 struct rx_ring_info *rp = &rx_rings[i];
6253
6254 niu_sync_rx_discard_stats(np, rp, 0);
6255
6256 pkts += rp->rx_packets;
6257 bytes += rp->rx_bytes;
6258 dropped += rp->rx_dropped;
6259 errors += rp->rx_errors;
6260 }
6261
6262 no_rings:
6263 stats->rx_packets = pkts;
6264 stats->rx_bytes = bytes;
6265 stats->rx_dropped = dropped;
6266 stats->rx_errors = errors;
6267 }
6268
6269 static void niu_get_tx_stats(struct niu *np,
6270 struct rtnl_link_stats64 *stats)
6271 {
6272 u64 pkts, errors, bytes;
6273 struct tx_ring_info *tx_rings;
6274 int i;
6275
6276 pkts = errors = bytes = 0;
6277
6278 tx_rings = READ_ONCE(np->tx_rings);
6279 if (!tx_rings)
6280 goto no_rings;
6281
6282 for (i = 0; i < np->num_tx_rings; i++) {
6283 struct tx_ring_info *rp = &tx_rings[i];
6284
6285 pkts += rp->tx_packets;
6286 bytes += rp->tx_bytes;
6287 errors += rp->tx_errors;
6288 }
6289
6290 no_rings:
6291 stats->tx_packets = pkts;
6292 stats->tx_bytes = bytes;
6293 stats->tx_errors = errors;
6294 }
6295
6296 static void niu_get_stats(struct net_device *dev,
6297 struct rtnl_link_stats64 *stats)
6298 {
6299 struct niu *np = netdev_priv(dev);
6300
6301 if (netif_running(dev)) {
6302 niu_get_rx_stats(np, stats);
6303 niu_get_tx_stats(np, stats);
6304 }
6305 }
6306
6307 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6308 {
6309 int i;
6310
6311 for (i = 0; i < 16; i++)
6312 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6313 }
6314
6315 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6316 {
6317 int i;
6318
6319 for (i = 0; i < 16; i++)
6320 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6321 }
6322
6323 static void niu_load_hash(struct niu *np, u16 *hash)
6324 {
6325 if (np->flags & NIU_FLAGS_XMAC)
6326 niu_load_hash_xmac(np, hash);
6327 else
6328 niu_load_hash_bmac(np, hash);
6329 }
6330
6331 static void niu_set_rx_mode(struct net_device *dev)
6332 {
6333 struct niu *np = netdev_priv(dev);
6334 int i, alt_cnt, err;
6335 struct netdev_hw_addr *ha;
6336 unsigned long flags;
6337 u16 hash[16] = { 0, };
6338
6339 spin_lock_irqsave(&np->lock, flags);
6340 niu_enable_rx_mac(np, 0);
6341
6342 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6343 if (dev->flags & IFF_PROMISC)
6344 np->flags |= NIU_FLAGS_PROMISC;
6345 if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
6346 np->flags |= NIU_FLAGS_MCAST;
6347
6348 alt_cnt = netdev_uc_count(dev);
6349 if (alt_cnt > niu_num_alt_addr(np)) {
6350 alt_cnt = 0;
6351 np->flags |= NIU_FLAGS_PROMISC;
6352 }
6353
6354 if (alt_cnt) {
6355 int index = 0;
6356
6357 netdev_for_each_uc_addr(ha, dev) {
6358 err = niu_set_alt_mac(np, index, ha->addr);
6359 if (err)
6360 netdev_warn(dev, "Error %d adding alt mac %d\n",
6361 err, index);
6362 err = niu_enable_alt_mac(np, index, 1);
6363 if (err)
6364 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6365 err, index);
6366
6367 index++;
6368 }
6369 } else {
6370 int alt_start;
6371 if (np->flags & NIU_FLAGS_XMAC)
6372 alt_start = 0;
6373 else
6374 alt_start = 1;
6375 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6376 err = niu_enable_alt_mac(np, i, 0);
6377 if (err)
6378 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6379 err, i);
6380 }
6381 }
6382 if (dev->flags & IFF_ALLMULTI) {
6383 for (i = 0; i < 16; i++)
6384 hash[i] = 0xffff;
6385 } else if (!netdev_mc_empty(dev)) {
6386 netdev_for_each_mc_addr(ha, dev) {
6387 u32 crc = ether_crc_le(ETH_ALEN, ha->addr);
6388
6389 crc >>= 24;
6390 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6391 }
6392 }
6393
6394 if (np->flags & NIU_FLAGS_MCAST)
6395 niu_load_hash(np, hash);
6396
6397 niu_enable_rx_mac(np, 1);
6398 spin_unlock_irqrestore(&np->lock, flags);
6399 }
6400
6401 static int niu_set_mac_addr(struct net_device *dev, void *p)
6402 {
6403 struct niu *np = netdev_priv(dev);
6404 struct sockaddr *addr = p;
6405 unsigned long flags;
6406
6407 if (!is_valid_ether_addr(addr->sa_data))
6408 return -EADDRNOTAVAIL;
6409
6410 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6411
6412 if (!netif_running(dev))
6413 return 0;
6414
6415 spin_lock_irqsave(&np->lock, flags);
6416 niu_enable_rx_mac(np, 0);
6417 niu_set_primary_mac(np, dev->dev_addr);
6418 niu_enable_rx_mac(np, 1);
6419 spin_unlock_irqrestore(&np->lock, flags);
6420
6421 return 0;
6422 }
6423
6424 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6425 {
6426 return -EOPNOTSUPP;
6427 }
6428
6429 static void niu_netif_stop(struct niu *np)
6430 {
6431 netif_trans_update(np->dev); /* prevent tx timeout */
6432
6433 niu_disable_napi(np);
6434
6435 netif_tx_disable(np->dev);
6436 }
6437
6438 static void niu_netif_start(struct niu *np)
6439 {
6440 /* NOTE: unconditional netif_wake_queue is only appropriate
6441 * so long as all callers are assured to have free tx slots
6442 * (such as after niu_init_hw).
6443 */
6444 netif_tx_wake_all_queues(np->dev);
6445
6446 niu_enable_napi(np);
6447
6448 niu_enable_interrupts(np, 1);
6449 }
6450
6451 static void niu_reset_buffers(struct niu *np)
6452 {
6453 int i, j, k, err;
6454
6455 if (np->rx_rings) {
6456 for (i = 0; i < np->num_rx_rings; i++) {
6457 struct rx_ring_info *rp = &np->rx_rings[i];
6458
6459 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6460 struct page *page;
6461
6462 page = rp->rxhash[j];
6463 while (page) {
6464 struct page *next =
6465 (struct page *) page->mapping;
6466 u64 base = page->index;
6467 base = base >> RBR_DESCR_ADDR_SHIFT;
6468 rp->rbr[k++] = cpu_to_le32(base);
6469 page = next;
6470 }
6471 }
6472 for (; k < MAX_RBR_RING_SIZE; k++) {
6473 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6474 if (unlikely(err))
6475 break;
6476 }
6477
6478 rp->rbr_index = rp->rbr_table_size - 1;
6479 rp->rcr_index = 0;
6480 rp->rbr_pending = 0;
6481 rp->rbr_refill_pending = 0;
6482 }
6483 }
6484 if (np->tx_rings) {
6485 for (i = 0; i < np->num_tx_rings; i++) {
6486 struct tx_ring_info *rp = &np->tx_rings[i];
6487
6488 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6489 if (rp->tx_buffs[j].skb)
6490 (void) release_tx_packet(np, rp, j);
6491 }
6492
6493 rp->pending = MAX_TX_RING_SIZE;
6494 rp->prod = 0;
6495 rp->cons = 0;
6496 rp->wrap_bit = 0;
6497 }
6498 }
6499 }
6500
6501 static void niu_reset_task(struct work_struct *work)
6502 {
6503 struct niu *np = container_of(work, struct niu, reset_task);
6504 unsigned long flags;
6505 int err;
6506
6507 spin_lock_irqsave(&np->lock, flags);
6508 if (!netif_running(np->dev)) {
6509 spin_unlock_irqrestore(&np->lock, flags);
6510 return;
6511 }
6512
6513 spin_unlock_irqrestore(&np->lock, flags);
6514
6515 del_timer_sync(&np->timer);
6516
6517 niu_netif_stop(np);
6518
6519 spin_lock_irqsave(&np->lock, flags);
6520
6521 niu_stop_hw(np);
6522
6523 spin_unlock_irqrestore(&np->lock, flags);
6524
6525 niu_reset_buffers(np);
6526
6527 spin_lock_irqsave(&np->lock, flags);
6528
6529 err = niu_init_hw(np);
6530 if (!err) {
6531 np->timer.expires = jiffies + HZ;
6532 add_timer(&np->timer);
6533 niu_netif_start(np);
6534 }
6535
6536 spin_unlock_irqrestore(&np->lock, flags);
6537 }
6538
6539 static void niu_tx_timeout(struct net_device *dev)
6540 {
6541 struct niu *np = netdev_priv(dev);
6542
6543 dev_err(np->device, "%s: Transmit timed out, resetting\n",
6544 dev->name);
6545
6546 schedule_work(&np->reset_task);
6547 }
6548
6549 static void niu_set_txd(struct tx_ring_info *rp, int index,
6550 u64 mapping, u64 len, u64 mark,
6551 u64 n_frags)
6552 {
6553 __le64 *desc = &rp->descr[index];
6554
6555 *desc = cpu_to_le64(mark |
6556 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6557 (len << TX_DESC_TR_LEN_SHIFT) |
6558 (mapping & TX_DESC_SAD));
6559 }
6560
6561 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6562 u64 pad_bytes, u64 len)
6563 {
6564 u16 eth_proto, eth_proto_inner;
6565 u64 csum_bits, l3off, ihl, ret;
6566 u8 ip_proto;
6567 int ipv6;
6568
6569 eth_proto = be16_to_cpu(ehdr->h_proto);
6570 eth_proto_inner = eth_proto;
6571 if (eth_proto == ETH_P_8021Q) {
6572 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6573 __be16 val = vp->h_vlan_encapsulated_proto;
6574
6575 eth_proto_inner = be16_to_cpu(val);
6576 }
6577
6578 ipv6 = ihl = 0;
6579 switch (skb->protocol) {
6580 case cpu_to_be16(ETH_P_IP):
6581 ip_proto = ip_hdr(skb)->protocol;
6582 ihl = ip_hdr(skb)->ihl;
6583 break;
6584 case cpu_to_be16(ETH_P_IPV6):
6585 ip_proto = ipv6_hdr(skb)->nexthdr;
6586 ihl = (40 >> 2);
6587 ipv6 = 1;
6588 break;
6589 default:
6590 ip_proto = ihl = 0;
6591 break;
6592 }
6593
6594 csum_bits = TXHDR_CSUM_NONE;
6595 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6596 u64 start, stuff;
6597
6598 csum_bits = (ip_proto == IPPROTO_TCP ?
6599 TXHDR_CSUM_TCP :
6600 (ip_proto == IPPROTO_UDP ?
6601 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6602
6603 start = skb_checksum_start_offset(skb) -
6604 (pad_bytes + sizeof(struct tx_pkt_hdr));
6605 stuff = start + skb->csum_offset;
6606
6607 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6608 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6609 }
6610
6611 l3off = skb_network_offset(skb) -
6612 (pad_bytes + sizeof(struct tx_pkt_hdr));
6613
6614 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6615 (len << TXHDR_LEN_SHIFT) |
6616 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6617 (ihl << TXHDR_IHL_SHIFT) |
6618 ((eth_proto_inner < ETH_P_802_3_MIN) ? TXHDR_LLC : 0) |
6619 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6620 (ipv6 ? TXHDR_IP_VER : 0) |
6621 csum_bits);
6622
6623 return ret;
6624 }
6625
6626 static netdev_tx_t niu_start_xmit(struct sk_buff *skb,
6627 struct net_device *dev)
6628 {
6629 struct niu *np = netdev_priv(dev);
6630 unsigned long align, headroom;
6631 struct netdev_queue *txq;
6632 struct tx_ring_info *rp;
6633 struct tx_pkt_hdr *tp;
6634 unsigned int len, nfg;
6635 struct ethhdr *ehdr;
6636 int prod, i, tlen;
6637 u64 mapping, mrk;
6638
6639 i = skb_get_queue_mapping(skb);
6640 rp = &np->tx_rings[i];
6641 txq = netdev_get_tx_queue(dev, i);
6642
6643 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6644 netif_tx_stop_queue(txq);
6645 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name);
6646 rp->tx_errors++;
6647 return NETDEV_TX_BUSY;
6648 }
6649
6650 if (eth_skb_pad(skb))
6651 goto out;
6652
6653 len = sizeof(struct tx_pkt_hdr) + 15;
6654 if (skb_headroom(skb) < len) {
6655 struct sk_buff *skb_new;
6656
6657 skb_new = skb_realloc_headroom(skb, len);
6658 if (!skb_new)
6659 goto out_drop;
6660 kfree_skb(skb);
6661 skb = skb_new;
6662 } else
6663 skb_orphan(skb);
6664
6665 align = ((unsigned long) skb->data & (16 - 1));
6666 headroom = align + sizeof(struct tx_pkt_hdr);
6667
6668 ehdr = (struct ethhdr *) skb->data;
6669 tp = skb_push(skb, headroom);
6670
6671 len = skb->len - sizeof(struct tx_pkt_hdr);
6672 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6673 tp->resv = 0;
6674
6675 len = skb_headlen(skb);
6676 mapping = np->ops->map_single(np->device, skb->data,
6677 len, DMA_TO_DEVICE);
6678
6679 prod = rp->prod;
6680
6681 rp->tx_buffs[prod].skb = skb;
6682 rp->tx_buffs[prod].mapping = mapping;
6683
6684 mrk = TX_DESC_SOP;
6685 if (++rp->mark_counter == rp->mark_freq) {
6686 rp->mark_counter = 0;
6687 mrk |= TX_DESC_MARK;
6688 rp->mark_pending++;
6689 }
6690
6691 tlen = len;
6692 nfg = skb_shinfo(skb)->nr_frags;
6693 while (tlen > 0) {
6694 tlen -= MAX_TX_DESC_LEN;
6695 nfg++;
6696 }
6697
6698 while (len > 0) {
6699 unsigned int this_len = len;
6700
6701 if (this_len > MAX_TX_DESC_LEN)
6702 this_len = MAX_TX_DESC_LEN;
6703
6704 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6705 mrk = nfg = 0;
6706
6707 prod = NEXT_TX(rp, prod);
6708 mapping += this_len;
6709 len -= this_len;
6710 }
6711
6712 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6713 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6714
6715 len = skb_frag_size(frag);
6716 mapping = np->ops->map_page(np->device, skb_frag_page(frag),
6717 frag->page_offset, len,
6718 DMA_TO_DEVICE);
6719
6720 rp->tx_buffs[prod].skb = NULL;
6721 rp->tx_buffs[prod].mapping = mapping;
6722
6723 niu_set_txd(rp, prod, mapping, len, 0, 0);
6724
6725 prod = NEXT_TX(rp, prod);
6726 }
6727
6728 if (prod < rp->prod)
6729 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6730 rp->prod = prod;
6731
6732 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6733
6734 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6735 netif_tx_stop_queue(txq);
6736 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6737 netif_tx_wake_queue(txq);
6738 }
6739
6740 out:
6741 return NETDEV_TX_OK;
6742
6743 out_drop:
6744 rp->tx_errors++;
6745 kfree_skb(skb);
6746 goto out;
6747 }
6748
6749 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6750 {
6751 struct niu *np = netdev_priv(dev);
6752 int err, orig_jumbo, new_jumbo;
6753
6754 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6755 new_jumbo = (new_mtu > ETH_DATA_LEN);
6756
6757 dev->mtu = new_mtu;
6758
6759 if (!netif_running(dev) ||
6760 (orig_jumbo == new_jumbo))
6761 return 0;
6762
6763 niu_full_shutdown(np, dev);
6764
6765 niu_free_channels(np);
6766
6767 niu_enable_napi(np);
6768
6769 err = niu_alloc_channels(np);
6770 if (err)
6771 return err;
6772
6773 spin_lock_irq(&np->lock);
6774
6775 err = niu_init_hw(np);
6776 if (!err) {
6777 timer_setup(&np->timer, niu_timer, 0);
6778 np->timer.expires = jiffies + HZ;
6779
6780 err = niu_enable_interrupts(np, 1);
6781 if (err)
6782 niu_stop_hw(np);
6783 }
6784
6785 spin_unlock_irq(&np->lock);
6786
6787 if (!err) {
6788 netif_tx_start_all_queues(dev);
6789 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6790 netif_carrier_on(dev);
6791
6792 add_timer(&np->timer);
6793 }
6794
6795 return err;
6796 }
6797
6798 static void niu_get_drvinfo(struct net_device *dev,
6799 struct ethtool_drvinfo *info)
6800 {
6801 struct niu *np = netdev_priv(dev);
6802 struct niu_vpd *vpd = &np->vpd;
6803
6804 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
6805 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
6806 snprintf(info->fw_version, sizeof(info->fw_version), "%d.%d",
6807 vpd->fcode_major, vpd->fcode_minor);
6808 if (np->parent->plat_type != PLAT_TYPE_NIU)
6809 strlcpy(info->bus_info, pci_name(np->pdev),
6810 sizeof(info->bus_info));
6811 }
6812
6813 static int niu_get_link_ksettings(struct net_device *dev,
6814 struct ethtool_link_ksettings *cmd)
6815 {
6816 struct niu *np = netdev_priv(dev);
6817 struct niu_link_config *lp;
6818
6819 lp = &np->link_config;
6820
6821 memset(cmd, 0, sizeof(*cmd));
6822 cmd->base.phy_address = np->phy_addr;
6823 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
6824 lp->supported);
6825 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
6826 lp->active_advertising);
6827 cmd->base.autoneg = lp->active_autoneg;
6828 cmd->base.speed = lp->active_speed;
6829 cmd->base.duplex = lp->active_duplex;
6830 cmd->base.port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6831
6832 return 0;
6833 }
6834
6835 static int niu_set_link_ksettings(struct net_device *dev,
6836 const struct ethtool_link_ksettings *cmd)
6837 {
6838 struct niu *np = netdev_priv(dev);
6839 struct niu_link_config *lp = &np->link_config;
6840
6841 ethtool_convert_link_mode_to_legacy_u32(&lp->advertising,
6842 cmd->link_modes.advertising);
6843 lp->speed = cmd->base.speed;
6844 lp->duplex = cmd->base.duplex;
6845 lp->autoneg = cmd->base.autoneg;
6846 return niu_init_link(np);
6847 }
6848
6849 static u32 niu_get_msglevel(struct net_device *dev)
6850 {
6851 struct niu *np = netdev_priv(dev);
6852 return np->msg_enable;
6853 }
6854
6855 static void niu_set_msglevel(struct net_device *dev, u32 value)
6856 {
6857 struct niu *np = netdev_priv(dev);
6858 np->msg_enable = value;
6859 }
6860
6861 static int niu_nway_reset(struct net_device *dev)
6862 {
6863 struct niu *np = netdev_priv(dev);
6864
6865 if (np->link_config.autoneg)
6866 return niu_init_link(np);
6867
6868 return 0;
6869 }
6870
6871 static int niu_get_eeprom_len(struct net_device *dev)
6872 {
6873 struct niu *np = netdev_priv(dev);
6874
6875 return np->eeprom_len;
6876 }
6877
6878 static int niu_get_eeprom(struct net_device *dev,
6879 struct ethtool_eeprom *eeprom, u8 *data)
6880 {
6881 struct niu *np = netdev_priv(dev);
6882 u32 offset, len, val;
6883
6884 offset = eeprom->offset;
6885 len = eeprom->len;
6886
6887 if (offset + len < offset)
6888 return -EINVAL;
6889 if (offset >= np->eeprom_len)
6890 return -EINVAL;
6891 if (offset + len > np->eeprom_len)
6892 len = eeprom->len = np->eeprom_len - offset;
6893
6894 if (offset & 3) {
6895 u32 b_offset, b_count;
6896
6897 b_offset = offset & 3;
6898 b_count = 4 - b_offset;
6899 if (b_count > len)
6900 b_count = len;
6901
6902 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6903 memcpy(data, ((char *)&val) + b_offset, b_count);
6904 data += b_count;
6905 len -= b_count;
6906 offset += b_count;
6907 }
6908 while (len >= 4) {
6909 val = nr64(ESPC_NCR(offset / 4));
6910 memcpy(data, &val, 4);
6911 data += 4;
6912 len -= 4;
6913 offset += 4;
6914 }
6915 if (len) {
6916 val = nr64(ESPC_NCR(offset / 4));
6917 memcpy(data, &val, len);
6918 }
6919 return 0;
6920 }
6921
6922 static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6923 {
6924 switch (flow_type) {
6925 case TCP_V4_FLOW:
6926 case TCP_V6_FLOW:
6927 *pid = IPPROTO_TCP;
6928 break;
6929 case UDP_V4_FLOW:
6930 case UDP_V6_FLOW:
6931 *pid = IPPROTO_UDP;
6932 break;
6933 case SCTP_V4_FLOW:
6934 case SCTP_V6_FLOW:
6935 *pid = IPPROTO_SCTP;
6936 break;
6937 case AH_V4_FLOW:
6938 case AH_V6_FLOW:
6939 *pid = IPPROTO_AH;
6940 break;
6941 case ESP_V4_FLOW:
6942 case ESP_V6_FLOW:
6943 *pid = IPPROTO_ESP;
6944 break;
6945 default:
6946 *pid = 0;
6947 break;
6948 }
6949 }
6950
6951 static int niu_class_to_ethflow(u64 class, int *flow_type)
6952 {
6953 switch (class) {
6954 case CLASS_CODE_TCP_IPV4:
6955 *flow_type = TCP_V4_FLOW;
6956 break;
6957 case CLASS_CODE_UDP_IPV4:
6958 *flow_type = UDP_V4_FLOW;
6959 break;
6960 case CLASS_CODE_AH_ESP_IPV4:
6961 *flow_type = AH_V4_FLOW;
6962 break;
6963 case CLASS_CODE_SCTP_IPV4:
6964 *flow_type = SCTP_V4_FLOW;
6965 break;
6966 case CLASS_CODE_TCP_IPV6:
6967 *flow_type = TCP_V6_FLOW;
6968 break;
6969 case CLASS_CODE_UDP_IPV6:
6970 *flow_type = UDP_V6_FLOW;
6971 break;
6972 case CLASS_CODE_AH_ESP_IPV6:
6973 *flow_type = AH_V6_FLOW;
6974 break;
6975 case CLASS_CODE_SCTP_IPV6:
6976 *flow_type = SCTP_V6_FLOW;
6977 break;
6978 case CLASS_CODE_USER_PROG1:
6979 case CLASS_CODE_USER_PROG2:
6980 case CLASS_CODE_USER_PROG3:
6981 case CLASS_CODE_USER_PROG4:
6982 *flow_type = IP_USER_FLOW;
6983 break;
6984 default:
6985 return -EINVAL;
6986 }
6987
6988 return 0;
6989 }
6990
6991 static int niu_ethflow_to_class(int flow_type, u64 *class)
6992 {
6993 switch (flow_type) {
6994 case TCP_V4_FLOW:
6995 *class = CLASS_CODE_TCP_IPV4;
6996 break;
6997 case UDP_V4_FLOW:
6998 *class = CLASS_CODE_UDP_IPV4;
6999 break;
7000 case AH_ESP_V4_FLOW:
7001 case AH_V4_FLOW:
7002 case ESP_V4_FLOW:
7003 *class = CLASS_CODE_AH_ESP_IPV4;
7004 break;
7005 case SCTP_V4_FLOW:
7006 *class = CLASS_CODE_SCTP_IPV4;
7007 break;
7008 case TCP_V6_FLOW:
7009 *class = CLASS_CODE_TCP_IPV6;
7010 break;
7011 case UDP_V6_FLOW:
7012 *class = CLASS_CODE_UDP_IPV6;
7013 break;
7014 case AH_ESP_V6_FLOW:
7015 case AH_V6_FLOW:
7016 case ESP_V6_FLOW:
7017 *class = CLASS_CODE_AH_ESP_IPV6;
7018 break;
7019 case SCTP_V6_FLOW:
7020 *class = CLASS_CODE_SCTP_IPV6;
7021 break;
7022 default:
7023 return 0;
7024 }
7025
7026 return 1;
7027 }
7028
7029 static u64 niu_flowkey_to_ethflow(u64 flow_key)
7030 {
7031 u64 ethflow = 0;
7032
7033 if (flow_key & FLOW_KEY_L2DA)
7034 ethflow |= RXH_L2DA;
7035 if (flow_key & FLOW_KEY_VLAN)
7036 ethflow |= RXH_VLAN;
7037 if (flow_key & FLOW_KEY_IPSA)
7038 ethflow |= RXH_IP_SRC;
7039 if (flow_key & FLOW_KEY_IPDA)
7040 ethflow |= RXH_IP_DST;
7041 if (flow_key & FLOW_KEY_PROTO)
7042 ethflow |= RXH_L3_PROTO;
7043 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7044 ethflow |= RXH_L4_B_0_1;
7045 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7046 ethflow |= RXH_L4_B_2_3;
7047
7048 return ethflow;
7049
7050 }
7051
7052 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7053 {
7054 u64 key = 0;
7055
7056 if (ethflow & RXH_L2DA)
7057 key |= FLOW_KEY_L2DA;
7058 if (ethflow & RXH_VLAN)
7059 key |= FLOW_KEY_VLAN;
7060 if (ethflow & RXH_IP_SRC)
7061 key |= FLOW_KEY_IPSA;
7062 if (ethflow & RXH_IP_DST)
7063 key |= FLOW_KEY_IPDA;
7064 if (ethflow & RXH_L3_PROTO)
7065 key |= FLOW_KEY_PROTO;
7066 if (ethflow & RXH_L4_B_0_1)
7067 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7068 if (ethflow & RXH_L4_B_2_3)
7069 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7070
7071 *flow_key = key;
7072
7073 return 1;
7074
7075 }
7076
7077 static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7078 {
7079 u64 class;
7080
7081 nfc->data = 0;
7082
7083 if (!niu_ethflow_to_class(nfc->flow_type, &class))
7084 return -EINVAL;
7085
7086 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7087 TCAM_KEY_DISC)
7088 nfc->data = RXH_DISCARD;
7089 else
7090 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
7091 CLASS_CODE_USER_PROG1]);
7092 return 0;
7093 }
7094
7095 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7096 struct ethtool_rx_flow_spec *fsp)
7097 {
7098 u32 tmp;
7099 u16 prt;
7100
7101 tmp = (tp->key[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7102 fsp->h_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7103
7104 tmp = (tp->key[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7105 fsp->h_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
7106
7107 tmp = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7108 fsp->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7109
7110 tmp = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7111 fsp->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
7112
7113 fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7114 TCAM_V4KEY2_TOS_SHIFT;
7115 fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7116 TCAM_V4KEY2_TOS_SHIFT;
7117
7118 switch (fsp->flow_type) {
7119 case TCP_V4_FLOW:
7120 case UDP_V4_FLOW:
7121 case SCTP_V4_FLOW:
7122 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7123 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7124 fsp->h_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7125
7126 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7127 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7128 fsp->h_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
7129
7130 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7131 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7132 fsp->m_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7133
7134 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7135 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7136 fsp->m_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
7137 break;
7138 case AH_V4_FLOW:
7139 case ESP_V4_FLOW:
7140 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7141 TCAM_V4KEY2_PORT_SPI_SHIFT;
7142 fsp->h_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
7143
7144 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7145 TCAM_V4KEY2_PORT_SPI_SHIFT;
7146 fsp->m_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
7147 break;
7148 case IP_USER_FLOW:
7149 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7150 TCAM_V4KEY2_PORT_SPI_SHIFT;
7151 fsp->h_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
7152
7153 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7154 TCAM_V4KEY2_PORT_SPI_SHIFT;
7155 fsp->m_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
7156
7157 fsp->h_u.usr_ip4_spec.proto =
7158 (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7159 TCAM_V4KEY2_PROTO_SHIFT;
7160 fsp->m_u.usr_ip4_spec.proto =
7161 (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7162 TCAM_V4KEY2_PROTO_SHIFT;
7163
7164 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7165 break;
7166 default:
7167 break;
7168 }
7169 }
7170
7171 static int niu_get_ethtool_tcam_entry(struct niu *np,
7172 struct ethtool_rxnfc *nfc)
7173 {
7174 struct niu_parent *parent = np->parent;
7175 struct niu_tcam_entry *tp;
7176 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7177 u16 idx;
7178 u64 class;
7179 int ret = 0;
7180
7181 idx = tcam_get_index(np, (u16)nfc->fs.location);
7182
7183 tp = &parent->tcam[idx];
7184 if (!tp->valid) {
7185 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n",
7186 parent->index, (u16)nfc->fs.location, idx);
7187 return -EINVAL;
7188 }
7189
7190 /* fill the flow spec entry */
7191 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7192 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7193 ret = niu_class_to_ethflow(class, &fsp->flow_type);
7194 if (ret < 0) {
7195 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n",
7196 parent->index);
7197 goto out;
7198 }
7199
7200 if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7201 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7202 TCAM_V4KEY2_PROTO_SHIFT;
7203 if (proto == IPPROTO_ESP) {
7204 if (fsp->flow_type == AH_V4_FLOW)
7205 fsp->flow_type = ESP_V4_FLOW;
7206 else
7207 fsp->flow_type = ESP_V6_FLOW;
7208 }
7209 }
7210
7211 switch (fsp->flow_type) {
7212 case TCP_V4_FLOW:
7213 case UDP_V4_FLOW:
7214 case SCTP_V4_FLOW:
7215 case AH_V4_FLOW:
7216 case ESP_V4_FLOW:
7217 niu_get_ip4fs_from_tcam_key(tp, fsp);
7218 break;
7219 case TCP_V6_FLOW:
7220 case UDP_V6_FLOW:
7221 case SCTP_V6_FLOW:
7222 case AH_V6_FLOW:
7223 case ESP_V6_FLOW:
7224 /* Not yet implemented */
7225 ret = -EINVAL;
7226 break;
7227 case IP_USER_FLOW:
7228 niu_get_ip4fs_from_tcam_key(tp, fsp);
7229 break;
7230 default:
7231 ret = -EINVAL;
7232 break;
7233 }
7234
7235 if (ret < 0)
7236 goto out;
7237
7238 if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7239 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7240 else
7241 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7242 TCAM_ASSOCDATA_OFFSET_SHIFT;
7243
7244 /* put the tcam size here */
7245 nfc->data = tcam_get_size(np);
7246 out:
7247 return ret;
7248 }
7249
7250 static int niu_get_ethtool_tcam_all(struct niu *np,
7251 struct ethtool_rxnfc *nfc,
7252 u32 *rule_locs)
7253 {
7254 struct niu_parent *parent = np->parent;
7255 struct niu_tcam_entry *tp;
7256 int i, idx, cnt;
7257 unsigned long flags;
7258 int ret = 0;
7259
7260 /* put the tcam size here */
7261 nfc->data = tcam_get_size(np);
7262
7263 niu_lock_parent(np, flags);
7264 for (cnt = 0, i = 0; i < nfc->data; i++) {
7265 idx = tcam_get_index(np, i);
7266 tp = &parent->tcam[idx];
7267 if (!tp->valid)
7268 continue;
7269 if (cnt == nfc->rule_cnt) {
7270 ret = -EMSGSIZE;
7271 break;
7272 }
7273 rule_locs[cnt] = i;
7274 cnt++;
7275 }
7276 niu_unlock_parent(np, flags);
7277
7278 nfc->rule_cnt = cnt;
7279
7280 return ret;
7281 }
7282
7283 static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7284 u32 *rule_locs)
7285 {
7286 struct niu *np = netdev_priv(dev);
7287 int ret = 0;
7288
7289 switch (cmd->cmd) {
7290 case ETHTOOL_GRXFH:
7291 ret = niu_get_hash_opts(np, cmd);
7292 break;
7293 case ETHTOOL_GRXRINGS:
7294 cmd->data = np->num_rx_rings;
7295 break;
7296 case ETHTOOL_GRXCLSRLCNT:
7297 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7298 break;
7299 case ETHTOOL_GRXCLSRULE:
7300 ret = niu_get_ethtool_tcam_entry(np, cmd);
7301 break;
7302 case ETHTOOL_GRXCLSRLALL:
7303 ret = niu_get_ethtool_tcam_all(np, cmd, rule_locs);
7304 break;
7305 default:
7306 ret = -EINVAL;
7307 break;
7308 }
7309
7310 return ret;
7311 }
7312
7313 static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7314 {
7315 u64 class;
7316 u64 flow_key = 0;
7317 unsigned long flags;
7318
7319 if (!niu_ethflow_to_class(nfc->flow_type, &class))
7320 return -EINVAL;
7321
7322 if (class < CLASS_CODE_USER_PROG1 ||
7323 class > CLASS_CODE_SCTP_IPV6)
7324 return -EINVAL;
7325
7326 if (nfc->data & RXH_DISCARD) {
7327 niu_lock_parent(np, flags);
7328 flow_key = np->parent->tcam_key[class -
7329 CLASS_CODE_USER_PROG1];
7330 flow_key |= TCAM_KEY_DISC;
7331 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7332 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7333 niu_unlock_parent(np, flags);
7334 return 0;
7335 } else {
7336 /* Discard was set before, but is not set now */
7337 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7338 TCAM_KEY_DISC) {
7339 niu_lock_parent(np, flags);
7340 flow_key = np->parent->tcam_key[class -
7341 CLASS_CODE_USER_PROG1];
7342 flow_key &= ~TCAM_KEY_DISC;
7343 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7344 flow_key);
7345 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7346 flow_key;
7347 niu_unlock_parent(np, flags);
7348 }
7349 }
7350
7351 if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
7352 return -EINVAL;
7353
7354 niu_lock_parent(np, flags);
7355 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7356 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7357 niu_unlock_parent(np, flags);
7358
7359 return 0;
7360 }
7361
7362 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7363 struct niu_tcam_entry *tp,
7364 int l2_rdc_tab, u64 class)
7365 {
7366 u8 pid = 0;
7367 u32 sip, dip, sipm, dipm, spi, spim;
7368 u16 sport, dport, spm, dpm;
7369
7370 sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7371 sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7372 dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7373 dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7374
7375 tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7376 tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7377 tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7378 tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7379
7380 tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7381 tp->key[3] |= dip;
7382
7383 tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7384 tp->key_mask[3] |= dipm;
7385
7386 tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7387 TCAM_V4KEY2_TOS_SHIFT);
7388 tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7389 TCAM_V4KEY2_TOS_SHIFT);
7390 switch (fsp->flow_type) {
7391 case TCP_V4_FLOW:
7392 case UDP_V4_FLOW:
7393 case SCTP_V4_FLOW:
7394 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7395 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7396 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7397 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7398
7399 tp->key[2] |= (((u64)sport << 16) | dport);
7400 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7401 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7402 break;
7403 case AH_V4_FLOW:
7404 case ESP_V4_FLOW:
7405 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7406 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7407
7408 tp->key[2] |= spi;
7409 tp->key_mask[2] |= spim;
7410 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7411 break;
7412 case IP_USER_FLOW:
7413 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7414 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7415
7416 tp->key[2] |= spi;
7417 tp->key_mask[2] |= spim;
7418 pid = fsp->h_u.usr_ip4_spec.proto;
7419 break;
7420 default:
7421 break;
7422 }
7423
7424 tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7425 if (pid) {
7426 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7427 }
7428 }
7429
7430 static int niu_add_ethtool_tcam_entry(struct niu *np,
7431 struct ethtool_rxnfc *nfc)
7432 {
7433 struct niu_parent *parent = np->parent;
7434 struct niu_tcam_entry *tp;
7435 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7436 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7437 int l2_rdc_table = rdc_table->first_table_num;
7438 u16 idx;
7439 u64 class;
7440 unsigned long flags;
7441 int err, ret;
7442
7443 ret = 0;
7444
7445 idx = nfc->fs.location;
7446 if (idx >= tcam_get_size(np))
7447 return -EINVAL;
7448
7449 if (fsp->flow_type == IP_USER_FLOW) {
7450 int i;
7451 int add_usr_cls = 0;
7452 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7453 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7454
7455 if (uspec->ip_ver != ETH_RX_NFC_IP4)
7456 return -EINVAL;
7457
7458 niu_lock_parent(np, flags);
7459
7460 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7461 if (parent->l3_cls[i]) {
7462 if (uspec->proto == parent->l3_cls_pid[i]) {
7463 class = parent->l3_cls[i];
7464 parent->l3_cls_refcnt[i]++;
7465 add_usr_cls = 1;
7466 break;
7467 }
7468 } else {
7469 /* Program new user IP class */
7470 switch (i) {
7471 case 0:
7472 class = CLASS_CODE_USER_PROG1;
7473 break;
7474 case 1:
7475 class = CLASS_CODE_USER_PROG2;
7476 break;
7477 case 2:
7478 class = CLASS_CODE_USER_PROG3;
7479 break;
7480 case 3:
7481 class = CLASS_CODE_USER_PROG4;
7482 break;
7483 default:
7484 break;
7485 }
7486 ret = tcam_user_ip_class_set(np, class, 0,
7487 uspec->proto,
7488 uspec->tos,
7489 umask->tos);
7490 if (ret)
7491 goto out;
7492
7493 ret = tcam_user_ip_class_enable(np, class, 1);
7494 if (ret)
7495 goto out;
7496 parent->l3_cls[i] = class;
7497 parent->l3_cls_pid[i] = uspec->proto;
7498 parent->l3_cls_refcnt[i]++;
7499 add_usr_cls = 1;
7500 break;
7501 }
7502 }
7503 if (!add_usr_cls) {
7504 netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n",
7505 parent->index, __func__, uspec->proto);
7506 ret = -EINVAL;
7507 goto out;
7508 }
7509 niu_unlock_parent(np, flags);
7510 } else {
7511 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7512 return -EINVAL;
7513 }
7514 }
7515
7516 niu_lock_parent(np, flags);
7517
7518 idx = tcam_get_index(np, idx);
7519 tp = &parent->tcam[idx];
7520
7521 memset(tp, 0, sizeof(*tp));
7522
7523 /* fill in the tcam key and mask */
7524 switch (fsp->flow_type) {
7525 case TCP_V4_FLOW:
7526 case UDP_V4_FLOW:
7527 case SCTP_V4_FLOW:
7528 case AH_V4_FLOW:
7529 case ESP_V4_FLOW:
7530 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7531 break;
7532 case TCP_V6_FLOW:
7533 case UDP_V6_FLOW:
7534 case SCTP_V6_FLOW:
7535 case AH_V6_FLOW:
7536 case ESP_V6_FLOW:
7537 /* Not yet implemented */
7538 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7539 parent->index, __func__, fsp->flow_type);
7540 ret = -EINVAL;
7541 goto out;
7542 case IP_USER_FLOW:
7543 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7544 break;
7545 default:
7546 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n",
7547 parent->index, __func__, fsp->flow_type);
7548 ret = -EINVAL;
7549 goto out;
7550 }
7551
7552 /* fill in the assoc data */
7553 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7554 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7555 } else {
7556 if (fsp->ring_cookie >= np->num_rx_rings) {
7557 netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n",
7558 parent->index, __func__,
7559 (long long)fsp->ring_cookie);
7560 ret = -EINVAL;
7561 goto out;
7562 }
7563 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7564 (fsp->ring_cookie <<
7565 TCAM_ASSOCDATA_OFFSET_SHIFT));
7566 }
7567
7568 err = tcam_write(np, idx, tp->key, tp->key_mask);
7569 if (err) {
7570 ret = -EINVAL;
7571 goto out;
7572 }
7573 err = tcam_assoc_write(np, idx, tp->assoc_data);
7574 if (err) {
7575 ret = -EINVAL;
7576 goto out;
7577 }
7578
7579 /* validate the entry */
7580 tp->valid = 1;
7581 np->clas.tcam_valid_entries++;
7582 out:
7583 niu_unlock_parent(np, flags);
7584
7585 return ret;
7586 }
7587
7588 static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7589 {
7590 struct niu_parent *parent = np->parent;
7591 struct niu_tcam_entry *tp;
7592 u16 idx;
7593 unsigned long flags;
7594 u64 class;
7595 int ret = 0;
7596
7597 if (loc >= tcam_get_size(np))
7598 return -EINVAL;
7599
7600 niu_lock_parent(np, flags);
7601
7602 idx = tcam_get_index(np, loc);
7603 tp = &parent->tcam[idx];
7604
7605 /* if the entry is of a user defined class, then update*/
7606 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7607 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7608
7609 if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7610 int i;
7611 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7612 if (parent->l3_cls[i] == class) {
7613 parent->l3_cls_refcnt[i]--;
7614 if (!parent->l3_cls_refcnt[i]) {
7615 /* disable class */
7616 ret = tcam_user_ip_class_enable(np,
7617 class,
7618 0);
7619 if (ret)
7620 goto out;
7621 parent->l3_cls[i] = 0;
7622 parent->l3_cls_pid[i] = 0;
7623 }
7624 break;
7625 }
7626 }
7627 if (i == NIU_L3_PROG_CLS) {
7628 netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n",
7629 parent->index, __func__,
7630 (unsigned long long)class);
7631 ret = -EINVAL;
7632 goto out;
7633 }
7634 }
7635
7636 ret = tcam_flush(np, idx);
7637 if (ret)
7638 goto out;
7639
7640 /* invalidate the entry */
7641 tp->valid = 0;
7642 np->clas.tcam_valid_entries--;
7643 out:
7644 niu_unlock_parent(np, flags);
7645
7646 return ret;
7647 }
7648
7649 static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7650 {
7651 struct niu *np = netdev_priv(dev);
7652 int ret = 0;
7653
7654 switch (cmd->cmd) {
7655 case ETHTOOL_SRXFH:
7656 ret = niu_set_hash_opts(np, cmd);
7657 break;
7658 case ETHTOOL_SRXCLSRLINS:
7659 ret = niu_add_ethtool_tcam_entry(np, cmd);
7660 break;
7661 case ETHTOOL_SRXCLSRLDEL:
7662 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7663 break;
7664 default:
7665 ret = -EINVAL;
7666 break;
7667 }
7668
7669 return ret;
7670 }
7671
7672 static const struct {
7673 const char string[ETH_GSTRING_LEN];
7674 } niu_xmac_stat_keys[] = {
7675 { "tx_frames" },
7676 { "tx_bytes" },
7677 { "tx_fifo_errors" },
7678 { "tx_overflow_errors" },
7679 { "tx_max_pkt_size_errors" },
7680 { "tx_underflow_errors" },
7681 { "rx_local_faults" },
7682 { "rx_remote_faults" },
7683 { "rx_link_faults" },
7684 { "rx_align_errors" },
7685 { "rx_frags" },
7686 { "rx_mcasts" },
7687 { "rx_bcasts" },
7688 { "rx_hist_cnt1" },
7689 { "rx_hist_cnt2" },
7690 { "rx_hist_cnt3" },
7691 { "rx_hist_cnt4" },
7692 { "rx_hist_cnt5" },
7693 { "rx_hist_cnt6" },
7694 { "rx_hist_cnt7" },
7695 { "rx_octets" },
7696 { "rx_code_violations" },
7697 { "rx_len_errors" },
7698 { "rx_crc_errors" },
7699 { "rx_underflows" },
7700 { "rx_overflows" },
7701 { "pause_off_state" },
7702 { "pause_on_state" },
7703 { "pause_received" },
7704 };
7705
7706 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7707
7708 static const struct {
7709 const char string[ETH_GSTRING_LEN];
7710 } niu_bmac_stat_keys[] = {
7711 { "tx_underflow_errors" },
7712 { "tx_max_pkt_size_errors" },
7713 { "tx_bytes" },
7714 { "tx_frames" },
7715 { "rx_overflows" },
7716 { "rx_frames" },
7717 { "rx_align_errors" },
7718 { "rx_crc_errors" },
7719 { "rx_len_errors" },
7720 { "pause_off_state" },
7721 { "pause_on_state" },
7722 { "pause_received" },
7723 };
7724
7725 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7726
7727 static const struct {
7728 const char string[ETH_GSTRING_LEN];
7729 } niu_rxchan_stat_keys[] = {
7730 { "rx_channel" },
7731 { "rx_packets" },
7732 { "rx_bytes" },
7733 { "rx_dropped" },
7734 { "rx_errors" },
7735 };
7736
7737 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7738
7739 static const struct {
7740 const char string[ETH_GSTRING_LEN];
7741 } niu_txchan_stat_keys[] = {
7742 { "tx_channel" },
7743 { "tx_packets" },
7744 { "tx_bytes" },
7745 { "tx_errors" },
7746 };
7747
7748 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7749
7750 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7751 {
7752 struct niu *np = netdev_priv(dev);
7753 int i;
7754
7755 if (stringset != ETH_SS_STATS)
7756 return;
7757
7758 if (np->flags & NIU_FLAGS_XMAC) {
7759 memcpy(data, niu_xmac_stat_keys,
7760 sizeof(niu_xmac_stat_keys));
7761 data += sizeof(niu_xmac_stat_keys);
7762 } else {
7763 memcpy(data, niu_bmac_stat_keys,
7764 sizeof(niu_bmac_stat_keys));
7765 data += sizeof(niu_bmac_stat_keys);
7766 }
7767 for (i = 0; i < np->num_rx_rings; i++) {
7768 memcpy(data, niu_rxchan_stat_keys,
7769 sizeof(niu_rxchan_stat_keys));
7770 data += sizeof(niu_rxchan_stat_keys);
7771 }
7772 for (i = 0; i < np->num_tx_rings; i++) {
7773 memcpy(data, niu_txchan_stat_keys,
7774 sizeof(niu_txchan_stat_keys));
7775 data += sizeof(niu_txchan_stat_keys);
7776 }
7777 }
7778
7779 static int niu_get_sset_count(struct net_device *dev, int stringset)
7780 {
7781 struct niu *np = netdev_priv(dev);
7782
7783 if (stringset != ETH_SS_STATS)
7784 return -EINVAL;
7785
7786 return (np->flags & NIU_FLAGS_XMAC ?
7787 NUM_XMAC_STAT_KEYS :
7788 NUM_BMAC_STAT_KEYS) +
7789 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7790 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS);
7791 }
7792
7793 static void niu_get_ethtool_stats(struct net_device *dev,
7794 struct ethtool_stats *stats, u64 *data)
7795 {
7796 struct niu *np = netdev_priv(dev);
7797 int i;
7798
7799 niu_sync_mac_stats(np);
7800 if (np->flags & NIU_FLAGS_XMAC) {
7801 memcpy(data, &np->mac_stats.xmac,
7802 sizeof(struct niu_xmac_stats));
7803 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7804 } else {
7805 memcpy(data, &np->mac_stats.bmac,
7806 sizeof(struct niu_bmac_stats));
7807 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7808 }
7809 for (i = 0; i < np->num_rx_rings; i++) {
7810 struct rx_ring_info *rp = &np->rx_rings[i];
7811
7812 niu_sync_rx_discard_stats(np, rp, 0);
7813
7814 data[0] = rp->rx_channel;
7815 data[1] = rp->rx_packets;
7816 data[2] = rp->rx_bytes;
7817 data[3] = rp->rx_dropped;
7818 data[4] = rp->rx_errors;
7819 data += 5;
7820 }
7821 for (i = 0; i < np->num_tx_rings; i++) {
7822 struct tx_ring_info *rp = &np->tx_rings[i];
7823
7824 data[0] = rp->tx_channel;
7825 data[1] = rp->tx_packets;
7826 data[2] = rp->tx_bytes;
7827 data[3] = rp->tx_errors;
7828 data += 4;
7829 }
7830 }
7831
7832 static u64 niu_led_state_save(struct niu *np)
7833 {
7834 if (np->flags & NIU_FLAGS_XMAC)
7835 return nr64_mac(XMAC_CONFIG);
7836 else
7837 return nr64_mac(BMAC_XIF_CONFIG);
7838 }
7839
7840 static void niu_led_state_restore(struct niu *np, u64 val)
7841 {
7842 if (np->flags & NIU_FLAGS_XMAC)
7843 nw64_mac(XMAC_CONFIG, val);
7844 else
7845 nw64_mac(BMAC_XIF_CONFIG, val);
7846 }
7847
7848 static void niu_force_led(struct niu *np, int on)
7849 {
7850 u64 val, reg, bit;
7851
7852 if (np->flags & NIU_FLAGS_XMAC) {
7853 reg = XMAC_CONFIG;
7854 bit = XMAC_CONFIG_FORCE_LED_ON;
7855 } else {
7856 reg = BMAC_XIF_CONFIG;
7857 bit = BMAC_XIF_CONFIG_LINK_LED;
7858 }
7859
7860 val = nr64_mac(reg);
7861 if (on)
7862 val |= bit;
7863 else
7864 val &= ~bit;
7865 nw64_mac(reg, val);
7866 }
7867
7868 static int niu_set_phys_id(struct net_device *dev,
7869 enum ethtool_phys_id_state state)
7870
7871 {
7872 struct niu *np = netdev_priv(dev);
7873
7874 if (!netif_running(dev))
7875 return -EAGAIN;
7876
7877 switch (state) {
7878 case ETHTOOL_ID_ACTIVE:
7879 np->orig_led_state = niu_led_state_save(np);
7880 return 1; /* cycle on/off once per second */
7881
7882 case ETHTOOL_ID_ON:
7883 niu_force_led(np, 1);
7884 break;
7885
7886 case ETHTOOL_ID_OFF:
7887 niu_force_led(np, 0);
7888 break;
7889
7890 case ETHTOOL_ID_INACTIVE:
7891 niu_led_state_restore(np, np->orig_led_state);
7892 }
7893
7894 return 0;
7895 }
7896
7897 static const struct ethtool_ops niu_ethtool_ops = {
7898 .get_drvinfo = niu_get_drvinfo,
7899 .get_link = ethtool_op_get_link,
7900 .get_msglevel = niu_get_msglevel,
7901 .set_msglevel = niu_set_msglevel,
7902 .nway_reset = niu_nway_reset,
7903 .get_eeprom_len = niu_get_eeprom_len,
7904 .get_eeprom = niu_get_eeprom,
7905 .get_strings = niu_get_strings,
7906 .get_sset_count = niu_get_sset_count,
7907 .get_ethtool_stats = niu_get_ethtool_stats,
7908 .set_phys_id = niu_set_phys_id,
7909 .get_rxnfc = niu_get_nfc,
7910 .set_rxnfc = niu_set_nfc,
7911 .get_link_ksettings = niu_get_link_ksettings,
7912 .set_link_ksettings = niu_set_link_ksettings,
7913 };
7914
7915 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7916 int ldg, int ldn)
7917 {
7918 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7919 return -EINVAL;
7920 if (ldn < 0 || ldn > LDN_MAX)
7921 return -EINVAL;
7922
7923 parent->ldg_map[ldn] = ldg;
7924
7925 if (np->parent->plat_type == PLAT_TYPE_NIU) {
7926 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7927 * the firmware, and we're not supposed to change them.
7928 * Validate the mapping, because if it's wrong we probably
7929 * won't get any interrupts and that's painful to debug.
7930 */
7931 if (nr64(LDG_NUM(ldn)) != ldg) {
7932 dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
7933 np->port, ldn, ldg,
7934 (unsigned long long) nr64(LDG_NUM(ldn)));
7935 return -EINVAL;
7936 }
7937 } else
7938 nw64(LDG_NUM(ldn), ldg);
7939
7940 return 0;
7941 }
7942
7943 static int niu_set_ldg_timer_res(struct niu *np, int res)
7944 {
7945 if (res < 0 || res > LDG_TIMER_RES_VAL)
7946 return -EINVAL;
7947
7948
7949 nw64(LDG_TIMER_RES, res);
7950
7951 return 0;
7952 }
7953
7954 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7955 {
7956 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7957 (func < 0 || func > 3) ||
7958 (vector < 0 || vector > 0x1f))
7959 return -EINVAL;
7960
7961 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7962
7963 return 0;
7964 }
7965
7966 static int niu_pci_eeprom_read(struct niu *np, u32 addr)
7967 {
7968 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7969 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7970 int limit;
7971
7972 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7973 return -EINVAL;
7974
7975 frame = frame_base;
7976 nw64(ESPC_PIO_STAT, frame);
7977 limit = 64;
7978 do {
7979 udelay(5);
7980 frame = nr64(ESPC_PIO_STAT);
7981 if (frame & ESPC_PIO_STAT_READ_END)
7982 break;
7983 } while (limit--);
7984 if (!(frame & ESPC_PIO_STAT_READ_END)) {
7985 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
7986 (unsigned long long) frame);
7987 return -ENODEV;
7988 }
7989
7990 frame = frame_base;
7991 nw64(ESPC_PIO_STAT, frame);
7992 limit = 64;
7993 do {
7994 udelay(5);
7995 frame = nr64(ESPC_PIO_STAT);
7996 if (frame & ESPC_PIO_STAT_READ_END)
7997 break;
7998 } while (limit--);
7999 if (!(frame & ESPC_PIO_STAT_READ_END)) {
8000 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
8001 (unsigned long long) frame);
8002 return -ENODEV;
8003 }
8004
8005 frame = nr64(ESPC_PIO_STAT);
8006 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
8007 }
8008
8009 static int niu_pci_eeprom_read16(struct niu *np, u32 off)
8010 {
8011 int err = niu_pci_eeprom_read(np, off);
8012 u16 val;
8013
8014 if (err < 0)
8015 return err;
8016 val = (err << 8);
8017 err = niu_pci_eeprom_read(np, off + 1);
8018 if (err < 0)
8019 return err;
8020 val |= (err & 0xff);
8021
8022 return val;
8023 }
8024
8025 static int niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8026 {
8027 int err = niu_pci_eeprom_read(np, off);
8028 u16 val;
8029
8030 if (err < 0)
8031 return err;
8032
8033 val = (err & 0xff);
8034 err = niu_pci_eeprom_read(np, off + 1);
8035 if (err < 0)
8036 return err;
8037
8038 val |= (err & 0xff) << 8;
8039
8040 return val;
8041 }
8042
8043 static int niu_pci_vpd_get_propname(struct niu *np, u32 off, char *namebuf,
8044 int namebuf_len)
8045 {
8046 int i;
8047
8048 for (i = 0; i < namebuf_len; i++) {
8049 int err = niu_pci_eeprom_read(np, off + i);
8050 if (err < 0)
8051 return err;
8052 *namebuf++ = err;
8053 if (!err)
8054 break;
8055 }
8056 if (i >= namebuf_len)
8057 return -EINVAL;
8058
8059 return i + 1;
8060 }
8061
8062 static void niu_vpd_parse_version(struct niu *np)
8063 {
8064 struct niu_vpd *vpd = &np->vpd;
8065 int len = strlen(vpd->version) + 1;
8066 const char *s = vpd->version;
8067 int i;
8068
8069 for (i = 0; i < len - 5; i++) {
8070 if (!strncmp(s + i, "FCode ", 6))
8071 break;
8072 }
8073 if (i >= len - 5)
8074 return;
8075
8076 s += i + 5;
8077 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8078
8079 netif_printk(np, probe, KERN_DEBUG, np->dev,
8080 "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8081 vpd->fcode_major, vpd->fcode_minor);
8082 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8083 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8084 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8085 np->flags |= NIU_FLAGS_VPD_VALID;
8086 }
8087
8088 /* ESPC_PIO_EN_ENABLE must be set */
8089 static int niu_pci_vpd_scan_props(struct niu *np, u32 start, u32 end)
8090 {
8091 unsigned int found_mask = 0;
8092 #define FOUND_MASK_MODEL 0x00000001
8093 #define FOUND_MASK_BMODEL 0x00000002
8094 #define FOUND_MASK_VERS 0x00000004
8095 #define FOUND_MASK_MAC 0x00000008
8096 #define FOUND_MASK_NMAC 0x00000010
8097 #define FOUND_MASK_PHY 0x00000020
8098 #define FOUND_MASK_ALL 0x0000003f
8099
8100 netif_printk(np, probe, KERN_DEBUG, np->dev,
8101 "VPD_SCAN: start[%x] end[%x]\n", start, end);
8102 while (start < end) {
8103 int len, err, prop_len;
8104 char namebuf[64];
8105 u8 *prop_buf;
8106 int max_len;
8107
8108 if (found_mask == FOUND_MASK_ALL) {
8109 niu_vpd_parse_version(np);
8110 return 1;
8111 }
8112
8113 err = niu_pci_eeprom_read(np, start + 2);
8114 if (err < 0)
8115 return err;
8116 len = err;
8117 start += 3;
8118
8119 prop_len = niu_pci_eeprom_read(np, start + 4);
8120 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8121 if (err < 0)
8122 return err;
8123
8124 prop_buf = NULL;
8125 max_len = 0;
8126 if (!strcmp(namebuf, "model")) {
8127 prop_buf = np->vpd.model;
8128 max_len = NIU_VPD_MODEL_MAX;
8129 found_mask |= FOUND_MASK_MODEL;
8130 } else if (!strcmp(namebuf, "board-model")) {
8131 prop_buf = np->vpd.board_model;
8132 max_len = NIU_VPD_BD_MODEL_MAX;
8133 found_mask |= FOUND_MASK_BMODEL;
8134 } else if (!strcmp(namebuf, "version")) {
8135 prop_buf = np->vpd.version;
8136 max_len = NIU_VPD_VERSION_MAX;
8137 found_mask |= FOUND_MASK_VERS;
8138 } else if (!strcmp(namebuf, "local-mac-address")) {
8139 prop_buf = np->vpd.local_mac;
8140 max_len = ETH_ALEN;
8141 found_mask |= FOUND_MASK_MAC;
8142 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8143 prop_buf = &np->vpd.mac_num;
8144 max_len = 1;
8145 found_mask |= FOUND_MASK_NMAC;
8146 } else if (!strcmp(namebuf, "phy-type")) {
8147 prop_buf = np->vpd.phy_type;
8148 max_len = NIU_VPD_PHY_TYPE_MAX;
8149 found_mask |= FOUND_MASK_PHY;
8150 }
8151
8152 if (max_len && prop_len > max_len) {
8153 dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len);
8154 return -EINVAL;
8155 }
8156
8157 if (prop_buf) {
8158 u32 off = start + 5 + err;
8159 int i;
8160
8161 netif_printk(np, probe, KERN_DEBUG, np->dev,
8162 "VPD_SCAN: Reading in property [%s] len[%d]\n",
8163 namebuf, prop_len);
8164 for (i = 0; i < prop_len; i++)
8165 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
8166 }
8167
8168 start += len;
8169 }
8170
8171 return 0;
8172 }
8173
8174 /* ESPC_PIO_EN_ENABLE must be set */
8175 static void niu_pci_vpd_fetch(struct niu *np, u32 start)
8176 {
8177 u32 offset;
8178 int err;
8179
8180 err = niu_pci_eeprom_read16_swp(np, start + 1);
8181 if (err < 0)
8182 return;
8183
8184 offset = err + 3;
8185
8186 while (start + offset < ESPC_EEPROM_SIZE) {
8187 u32 here = start + offset;
8188 u32 end;
8189
8190 err = niu_pci_eeprom_read(np, here);
8191 if (err != 0x90)
8192 return;
8193
8194 err = niu_pci_eeprom_read16_swp(np, here + 1);
8195 if (err < 0)
8196 return;
8197
8198 here = start + offset + 3;
8199 end = start + offset + err;
8200
8201 offset += err;
8202
8203 err = niu_pci_vpd_scan_props(np, here, end);
8204 if (err < 0 || err == 1)
8205 return;
8206 }
8207 }
8208
8209 /* ESPC_PIO_EN_ENABLE must be set */
8210 static u32 niu_pci_vpd_offset(struct niu *np)
8211 {
8212 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8213 int err;
8214
8215 while (start < end) {
8216 ret = start;
8217
8218 /* ROM header signature? */
8219 err = niu_pci_eeprom_read16(np, start + 0);
8220 if (err != 0x55aa)
8221 return 0;
8222
8223 /* Apply offset to PCI data structure. */
8224 err = niu_pci_eeprom_read16(np, start + 23);
8225 if (err < 0)
8226 return 0;
8227 start += err;
8228
8229 /* Check for "PCIR" signature. */
8230 err = niu_pci_eeprom_read16(np, start + 0);
8231 if (err != 0x5043)
8232 return 0;
8233 err = niu_pci_eeprom_read16(np, start + 2);
8234 if (err != 0x4952)
8235 return 0;
8236
8237 /* Check for OBP image type. */
8238 err = niu_pci_eeprom_read(np, start + 20);
8239 if (err < 0)
8240 return 0;
8241 if (err != 0x01) {
8242 err = niu_pci_eeprom_read(np, ret + 2);
8243 if (err < 0)
8244 return 0;
8245
8246 start = ret + (err * 512);
8247 continue;
8248 }
8249
8250 err = niu_pci_eeprom_read16_swp(np, start + 8);
8251 if (err < 0)
8252 return err;
8253 ret += err;
8254
8255 err = niu_pci_eeprom_read(np, ret + 0);
8256 if (err != 0x82)
8257 return 0;
8258
8259 return ret;
8260 }
8261
8262 return 0;
8263 }
8264
8265 static int niu_phy_type_prop_decode(struct niu *np, const char *phy_prop)
8266 {
8267 if (!strcmp(phy_prop, "mif")) {
8268 /* 1G copper, MII */
8269 np->flags &= ~(NIU_FLAGS_FIBER |
8270 NIU_FLAGS_10G);
8271 np->mac_xcvr = MAC_XCVR_MII;
8272 } else if (!strcmp(phy_prop, "xgf")) {
8273 /* 10G fiber, XPCS */
8274 np->flags |= (NIU_FLAGS_10G |
8275 NIU_FLAGS_FIBER);
8276 np->mac_xcvr = MAC_XCVR_XPCS;
8277 } else if (!strcmp(phy_prop, "pcs")) {
8278 /* 1G fiber, PCS */
8279 np->flags &= ~NIU_FLAGS_10G;
8280 np->flags |= NIU_FLAGS_FIBER;
8281 np->mac_xcvr = MAC_XCVR_PCS;
8282 } else if (!strcmp(phy_prop, "xgc")) {
8283 /* 10G copper, XPCS */
8284 np->flags |= NIU_FLAGS_10G;
8285 np->flags &= ~NIU_FLAGS_FIBER;
8286 np->mac_xcvr = MAC_XCVR_XPCS;
8287 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8288 /* 10G Serdes or 1G Serdes, default to 10G */
8289 np->flags |= NIU_FLAGS_10G;
8290 np->flags &= ~NIU_FLAGS_FIBER;
8291 np->flags |= NIU_FLAGS_XCVR_SERDES;
8292 np->mac_xcvr = MAC_XCVR_XPCS;
8293 } else {
8294 return -EINVAL;
8295 }
8296 return 0;
8297 }
8298
8299 static int niu_pci_vpd_get_nports(struct niu *np)
8300 {
8301 int ports = 0;
8302
8303 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8304 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8305 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8306 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8307 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
8308 ports = 4;
8309 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8310 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8311 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8312 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
8313 ports = 2;
8314 }
8315
8316 return ports;
8317 }
8318
8319 static void niu_pci_vpd_validate(struct niu *np)
8320 {
8321 struct net_device *dev = np->dev;
8322 struct niu_vpd *vpd = &np->vpd;
8323 u8 val8;
8324
8325 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
8326 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n");
8327
8328 np->flags &= ~NIU_FLAGS_VPD_VALID;
8329 return;
8330 }
8331
8332 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8333 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8334 np->flags |= NIU_FLAGS_10G;
8335 np->flags &= ~NIU_FLAGS_FIBER;
8336 np->flags |= NIU_FLAGS_XCVR_SERDES;
8337 np->mac_xcvr = MAC_XCVR_PCS;
8338 if (np->port > 1) {
8339 np->flags |= NIU_FLAGS_FIBER;
8340 np->flags &= ~NIU_FLAGS_10G;
8341 }
8342 if (np->flags & NIU_FLAGS_10G)
8343 np->mac_xcvr = MAC_XCVR_XPCS;
8344 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8345 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8346 NIU_FLAGS_HOTPLUG_PHY);
8347 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8348 dev_err(np->device, "Illegal phy string [%s]\n",
8349 np->vpd.phy_type);
8350 dev_err(np->device, "Falling back to SPROM\n");
8351 np->flags &= ~NIU_FLAGS_VPD_VALID;
8352 return;
8353 }
8354
8355 memcpy(dev->dev_addr, vpd->local_mac, ETH_ALEN);
8356
8357 val8 = dev->dev_addr[5];
8358 dev->dev_addr[5] += np->port;
8359 if (dev->dev_addr[5] < val8)
8360 dev->dev_addr[4]++;
8361 }
8362
8363 static int niu_pci_probe_sprom(struct niu *np)
8364 {
8365 struct net_device *dev = np->dev;
8366 int len, i;
8367 u64 val, sum;
8368 u8 val8;
8369
8370 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8371 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8372 len = val / 4;
8373
8374 np->eeprom_len = len;
8375
8376 netif_printk(np, probe, KERN_DEBUG, np->dev,
8377 "SPROM: Image size %llu\n", (unsigned long long)val);
8378
8379 sum = 0;
8380 for (i = 0; i < len; i++) {
8381 val = nr64(ESPC_NCR(i));
8382 sum += (val >> 0) & 0xff;
8383 sum += (val >> 8) & 0xff;
8384 sum += (val >> 16) & 0xff;
8385 sum += (val >> 24) & 0xff;
8386 }
8387 netif_printk(np, probe, KERN_DEBUG, np->dev,
8388 "SPROM: Checksum %x\n", (int)(sum & 0xff));
8389 if ((sum & 0xff) != 0xab) {
8390 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff));
8391 return -EINVAL;
8392 }
8393
8394 val = nr64(ESPC_PHY_TYPE);
8395 switch (np->port) {
8396 case 0:
8397 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
8398 ESPC_PHY_TYPE_PORT0_SHIFT;
8399 break;
8400 case 1:
8401 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
8402 ESPC_PHY_TYPE_PORT1_SHIFT;
8403 break;
8404 case 2:
8405 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
8406 ESPC_PHY_TYPE_PORT2_SHIFT;
8407 break;
8408 case 3:
8409 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
8410 ESPC_PHY_TYPE_PORT3_SHIFT;
8411 break;
8412 default:
8413 dev_err(np->device, "Bogus port number %u\n",
8414 np->port);
8415 return -EINVAL;
8416 }
8417 netif_printk(np, probe, KERN_DEBUG, np->dev,
8418 "SPROM: PHY type %x\n", val8);
8419
8420 switch (val8) {
8421 case ESPC_PHY_TYPE_1G_COPPER:
8422 /* 1G copper, MII */
8423 np->flags &= ~(NIU_FLAGS_FIBER |
8424 NIU_FLAGS_10G);
8425 np->mac_xcvr = MAC_XCVR_MII;
8426 break;
8427
8428 case ESPC_PHY_TYPE_1G_FIBER:
8429 /* 1G fiber, PCS */
8430 np->flags &= ~NIU_FLAGS_10G;
8431 np->flags |= NIU_FLAGS_FIBER;
8432 np->mac_xcvr = MAC_XCVR_PCS;
8433 break;
8434
8435 case ESPC_PHY_TYPE_10G_COPPER:
8436 /* 10G copper, XPCS */
8437 np->flags |= NIU_FLAGS_10G;
8438 np->flags &= ~NIU_FLAGS_FIBER;
8439 np->mac_xcvr = MAC_XCVR_XPCS;
8440 break;
8441
8442 case ESPC_PHY_TYPE_10G_FIBER:
8443 /* 10G fiber, XPCS */
8444 np->flags |= (NIU_FLAGS_10G |
8445 NIU_FLAGS_FIBER);
8446 np->mac_xcvr = MAC_XCVR_XPCS;
8447 break;
8448
8449 default:
8450 dev_err(np->device, "Bogus SPROM phy type %u\n", val8);
8451 return -EINVAL;
8452 }
8453
8454 val = nr64(ESPC_MAC_ADDR0);
8455 netif_printk(np, probe, KERN_DEBUG, np->dev,
8456 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
8457 dev->dev_addr[0] = (val >> 0) & 0xff;
8458 dev->dev_addr[1] = (val >> 8) & 0xff;
8459 dev->dev_addr[2] = (val >> 16) & 0xff;
8460 dev->dev_addr[3] = (val >> 24) & 0xff;
8461
8462 val = nr64(ESPC_MAC_ADDR1);
8463 netif_printk(np, probe, KERN_DEBUG, np->dev,
8464 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
8465 dev->dev_addr[4] = (val >> 0) & 0xff;
8466 dev->dev_addr[5] = (val >> 8) & 0xff;
8467
8468 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
8469 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n",
8470 dev->dev_addr);
8471 return -EINVAL;
8472 }
8473
8474 val8 = dev->dev_addr[5];
8475 dev->dev_addr[5] += np->port;
8476 if (dev->dev_addr[5] < val8)
8477 dev->dev_addr[4]++;
8478
8479 val = nr64(ESPC_MOD_STR_LEN);
8480 netif_printk(np, probe, KERN_DEBUG, np->dev,
8481 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8482 if (val >= 8 * 4)
8483 return -EINVAL;
8484
8485 for (i = 0; i < val; i += 4) {
8486 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8487
8488 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
8489 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
8490 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8491 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8492 }
8493 np->vpd.model[val] = '\0';
8494
8495 val = nr64(ESPC_BD_MOD_STR_LEN);
8496 netif_printk(np, probe, KERN_DEBUG, np->dev,
8497 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8498 if (val >= 4 * 4)
8499 return -EINVAL;
8500
8501 for (i = 0; i < val; i += 4) {
8502 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8503
8504 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
8505 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
8506 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8507 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8508 }
8509 np->vpd.board_model[val] = '\0';
8510
8511 np->vpd.mac_num =
8512 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
8513 netif_printk(np, probe, KERN_DEBUG, np->dev,
8514 "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num);
8515
8516 return 0;
8517 }
8518
8519 static int niu_get_and_validate_port(struct niu *np)
8520 {
8521 struct niu_parent *parent = np->parent;
8522
8523 if (np->port <= 1)
8524 np->flags |= NIU_FLAGS_XMAC;
8525
8526 if (!parent->num_ports) {
8527 if (parent->plat_type == PLAT_TYPE_NIU) {
8528 parent->num_ports = 2;
8529 } else {
8530 parent->num_ports = niu_pci_vpd_get_nports(np);
8531 if (!parent->num_ports) {
8532 /* Fall back to SPROM as last resort.
8533 * This will fail on most cards.
8534 */
8535 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8536 ESPC_NUM_PORTS_MACS_VAL;
8537
8538 /* All of the current probing methods fail on
8539 * Maramba on-board parts.
8540 */
8541 if (!parent->num_ports)
8542 parent->num_ports = 4;
8543 }
8544 }
8545 }
8546
8547 if (np->port >= parent->num_ports)
8548 return -ENODEV;
8549
8550 return 0;
8551 }
8552
8553 static int phy_record(struct niu_parent *parent, struct phy_probe_info *p,
8554 int dev_id_1, int dev_id_2, u8 phy_port, int type)
8555 {
8556 u32 id = (dev_id_1 << 16) | dev_id_2;
8557 u8 idx;
8558
8559 if (dev_id_1 < 0 || dev_id_2 < 0)
8560 return 0;
8561 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
8562 /* Because of the NIU_PHY_ID_MASK being applied, the 8704
8563 * test covers the 8706 as well.
8564 */
8565 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
8566 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011))
8567 return 0;
8568 } else {
8569 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8570 return 0;
8571 }
8572
8573 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8574 parent->index, id,
8575 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" :
8576 type == PHY_TYPE_PCS ? "PCS" : "MII",
8577 phy_port);
8578
8579 if (p->cur[type] >= NIU_MAX_PORTS) {
8580 pr_err("Too many PHY ports\n");
8581 return -EINVAL;
8582 }
8583 idx = p->cur[type];
8584 p->phy_id[type][idx] = id;
8585 p->phy_port[type][idx] = phy_port;
8586 p->cur[type] = idx + 1;
8587 return 0;
8588 }
8589
8590 static int port_has_10g(struct phy_probe_info *p, int port)
8591 {
8592 int i;
8593
8594 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8595 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8596 return 1;
8597 }
8598 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8599 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8600 return 1;
8601 }
8602
8603 return 0;
8604 }
8605
8606 static int count_10g_ports(struct phy_probe_info *p, int *lowest)
8607 {
8608 int port, cnt;
8609
8610 cnt = 0;
8611 *lowest = 32;
8612 for (port = 8; port < 32; port++) {
8613 if (port_has_10g(p, port)) {
8614 if (!cnt)
8615 *lowest = port;
8616 cnt++;
8617 }
8618 }
8619
8620 return cnt;
8621 }
8622
8623 static int count_1g_ports(struct phy_probe_info *p, int *lowest)
8624 {
8625 *lowest = 32;
8626 if (p->cur[PHY_TYPE_MII])
8627 *lowest = p->phy_port[PHY_TYPE_MII][0];
8628
8629 return p->cur[PHY_TYPE_MII];
8630 }
8631
8632 static void niu_n2_divide_channels(struct niu_parent *parent)
8633 {
8634 int num_ports = parent->num_ports;
8635 int i;
8636
8637 for (i = 0; i < num_ports; i++) {
8638 parent->rxchan_per_port[i] = (16 / num_ports);
8639 parent->txchan_per_port[i] = (16 / num_ports);
8640
8641 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8642 parent->index, i,
8643 parent->rxchan_per_port[i],
8644 parent->txchan_per_port[i]);
8645 }
8646 }
8647
8648 static void niu_divide_channels(struct niu_parent *parent,
8649 int num_10g, int num_1g)
8650 {
8651 int num_ports = parent->num_ports;
8652 int rx_chans_per_10g, rx_chans_per_1g;
8653 int tx_chans_per_10g, tx_chans_per_1g;
8654 int i, tot_rx, tot_tx;
8655
8656 if (!num_10g || !num_1g) {
8657 rx_chans_per_10g = rx_chans_per_1g =
8658 (NIU_NUM_RXCHAN / num_ports);
8659 tx_chans_per_10g = tx_chans_per_1g =
8660 (NIU_NUM_TXCHAN / num_ports);
8661 } else {
8662 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8663 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8664 (rx_chans_per_1g * num_1g)) /
8665 num_10g;
8666
8667 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8668 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8669 (tx_chans_per_1g * num_1g)) /
8670 num_10g;
8671 }
8672
8673 tot_rx = tot_tx = 0;
8674 for (i = 0; i < num_ports; i++) {
8675 int type = phy_decode(parent->port_phy, i);
8676
8677 if (type == PORT_TYPE_10G) {
8678 parent->rxchan_per_port[i] = rx_chans_per_10g;
8679 parent->txchan_per_port[i] = tx_chans_per_10g;
8680 } else {
8681 parent->rxchan_per_port[i] = rx_chans_per_1g;
8682 parent->txchan_per_port[i] = tx_chans_per_1g;
8683 }
8684 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8685 parent->index, i,
8686 parent->rxchan_per_port[i],
8687 parent->txchan_per_port[i]);
8688 tot_rx += parent->rxchan_per_port[i];
8689 tot_tx += parent->txchan_per_port[i];
8690 }
8691
8692 if (tot_rx > NIU_NUM_RXCHAN) {
8693 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
8694 parent->index, tot_rx);
8695 for (i = 0; i < num_ports; i++)
8696 parent->rxchan_per_port[i] = 1;
8697 }
8698 if (tot_tx > NIU_NUM_TXCHAN) {
8699 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
8700 parent->index, tot_tx);
8701 for (i = 0; i < num_ports; i++)
8702 parent->txchan_per_port[i] = 1;
8703 }
8704 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
8705 pr_warn("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8706 parent->index, tot_rx, tot_tx);
8707 }
8708 }
8709
8710 static void niu_divide_rdc_groups(struct niu_parent *parent,
8711 int num_10g, int num_1g)
8712 {
8713 int i, num_ports = parent->num_ports;
8714 int rdc_group, rdc_groups_per_port;
8715 int rdc_channel_base;
8716
8717 rdc_group = 0;
8718 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8719
8720 rdc_channel_base = 0;
8721
8722 for (i = 0; i < num_ports; i++) {
8723 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8724 int grp, num_channels = parent->rxchan_per_port[i];
8725 int this_channel_offset;
8726
8727 tp->first_table_num = rdc_group;
8728 tp->num_tables = rdc_groups_per_port;
8729 this_channel_offset = 0;
8730 for (grp = 0; grp < tp->num_tables; grp++) {
8731 struct rdc_table *rt = &tp->tables[grp];
8732 int slot;
8733
8734 pr_info("niu%d: Port %d RDC tbl(%d) [ ",
8735 parent->index, i, tp->first_table_num + grp);
8736 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8737 rt->rxdma_channel[slot] =
8738 rdc_channel_base + this_channel_offset;
8739
8740 pr_cont("%d ", rt->rxdma_channel[slot]);
8741
8742 if (++this_channel_offset == num_channels)
8743 this_channel_offset = 0;
8744 }
8745 pr_cont("]\n");
8746 }
8747
8748 parent->rdc_default[i] = rdc_channel_base;
8749
8750 rdc_channel_base += num_channels;
8751 rdc_group += rdc_groups_per_port;
8752 }
8753 }
8754
8755 static int fill_phy_probe_info(struct niu *np, struct niu_parent *parent,
8756 struct phy_probe_info *info)
8757 {
8758 unsigned long flags;
8759 int port, err;
8760
8761 memset(info, 0, sizeof(*info));
8762
8763 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8764 niu_lock_parent(np, flags);
8765 err = 0;
8766 for (port = 8; port < 32; port++) {
8767 int dev_id_1, dev_id_2;
8768
8769 dev_id_1 = mdio_read(np, port,
8770 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8771 dev_id_2 = mdio_read(np, port,
8772 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8773 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8774 PHY_TYPE_PMA_PMD);
8775 if (err)
8776 break;
8777 dev_id_1 = mdio_read(np, port,
8778 NIU_PCS_DEV_ADDR, MII_PHYSID1);
8779 dev_id_2 = mdio_read(np, port,
8780 NIU_PCS_DEV_ADDR, MII_PHYSID2);
8781 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8782 PHY_TYPE_PCS);
8783 if (err)
8784 break;
8785 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8786 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8787 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8788 PHY_TYPE_MII);
8789 if (err)
8790 break;
8791 }
8792 niu_unlock_parent(np, flags);
8793
8794 return err;
8795 }
8796
8797 static int walk_phys(struct niu *np, struct niu_parent *parent)
8798 {
8799 struct phy_probe_info *info = &parent->phy_probe_info;
8800 int lowest_10g, lowest_1g;
8801 int num_10g, num_1g;
8802 u32 val;
8803 int err;
8804
8805 num_10g = num_1g = 0;
8806
8807 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8808 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8809 num_10g = 0;
8810 num_1g = 2;
8811 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8812 parent->num_ports = 4;
8813 val = (phy_encode(PORT_TYPE_1G, 0) |
8814 phy_encode(PORT_TYPE_1G, 1) |
8815 phy_encode(PORT_TYPE_1G, 2) |
8816 phy_encode(PORT_TYPE_1G, 3));
8817 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8818 num_10g = 2;
8819 num_1g = 0;
8820 parent->num_ports = 2;
8821 val = (phy_encode(PORT_TYPE_10G, 0) |
8822 phy_encode(PORT_TYPE_10G, 1));
8823 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8824 (parent->plat_type == PLAT_TYPE_NIU)) {
8825 /* this is the Monza case */
8826 if (np->flags & NIU_FLAGS_10G) {
8827 val = (phy_encode(PORT_TYPE_10G, 0) |
8828 phy_encode(PORT_TYPE_10G, 1));
8829 } else {
8830 val = (phy_encode(PORT_TYPE_1G, 0) |
8831 phy_encode(PORT_TYPE_1G, 1));
8832 }
8833 } else {
8834 err = fill_phy_probe_info(np, parent, info);
8835 if (err)
8836 return err;
8837
8838 num_10g = count_10g_ports(info, &lowest_10g);
8839 num_1g = count_1g_ports(info, &lowest_1g);
8840
8841 switch ((num_10g << 4) | num_1g) {
8842 case 0x24:
8843 if (lowest_1g == 10)
8844 parent->plat_type = PLAT_TYPE_VF_P0;
8845 else if (lowest_1g == 26)
8846 parent->plat_type = PLAT_TYPE_VF_P1;
8847 else
8848 goto unknown_vg_1g_port;
8849
8850 /* fallthru */
8851 case 0x22:
8852 val = (phy_encode(PORT_TYPE_10G, 0) |
8853 phy_encode(PORT_TYPE_10G, 1) |
8854 phy_encode(PORT_TYPE_1G, 2) |
8855 phy_encode(PORT_TYPE_1G, 3));
8856 break;
8857
8858 case 0x20:
8859 val = (phy_encode(PORT_TYPE_10G, 0) |
8860 phy_encode(PORT_TYPE_10G, 1));
8861 break;
8862
8863 case 0x10:
8864 val = phy_encode(PORT_TYPE_10G, np->port);
8865 break;
8866
8867 case 0x14:
8868 if (lowest_1g == 10)
8869 parent->plat_type = PLAT_TYPE_VF_P0;
8870 else if (lowest_1g == 26)
8871 parent->plat_type = PLAT_TYPE_VF_P1;
8872 else
8873 goto unknown_vg_1g_port;
8874
8875 /* fallthru */
8876 case 0x13:
8877 if ((lowest_10g & 0x7) == 0)
8878 val = (phy_encode(PORT_TYPE_10G, 0) |
8879 phy_encode(PORT_TYPE_1G, 1) |
8880 phy_encode(PORT_TYPE_1G, 2) |
8881 phy_encode(PORT_TYPE_1G, 3));
8882 else
8883 val = (phy_encode(PORT_TYPE_1G, 0) |
8884 phy_encode(PORT_TYPE_10G, 1) |
8885 phy_encode(PORT_TYPE_1G, 2) |
8886 phy_encode(PORT_TYPE_1G, 3));
8887 break;
8888
8889 case 0x04:
8890 if (lowest_1g == 10)
8891 parent->plat_type = PLAT_TYPE_VF_P0;
8892 else if (lowest_1g == 26)
8893 parent->plat_type = PLAT_TYPE_VF_P1;
8894 else
8895 goto unknown_vg_1g_port;
8896
8897 val = (phy_encode(PORT_TYPE_1G, 0) |
8898 phy_encode(PORT_TYPE_1G, 1) |
8899 phy_encode(PORT_TYPE_1G, 2) |
8900 phy_encode(PORT_TYPE_1G, 3));
8901 break;
8902
8903 default:
8904 pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
8905 num_10g, num_1g);
8906 return -EINVAL;
8907 }
8908 }
8909
8910 parent->port_phy = val;
8911
8912 if (parent->plat_type == PLAT_TYPE_NIU)
8913 niu_n2_divide_channels(parent);
8914 else
8915 niu_divide_channels(parent, num_10g, num_1g);
8916
8917 niu_divide_rdc_groups(parent, num_10g, num_1g);
8918
8919 return 0;
8920
8921 unknown_vg_1g_port:
8922 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g);
8923 return -EINVAL;
8924 }
8925
8926 static int niu_probe_ports(struct niu *np)
8927 {
8928 struct niu_parent *parent = np->parent;
8929 int err, i;
8930
8931 if (parent->port_phy == PORT_PHY_UNKNOWN) {
8932 err = walk_phys(np, parent);
8933 if (err)
8934 return err;
8935
8936 niu_set_ldg_timer_res(np, 2);
8937 for (i = 0; i <= LDN_MAX; i++)
8938 niu_ldn_irq_enable(np, i, 0);
8939 }
8940
8941 if (parent->port_phy == PORT_PHY_INVALID)
8942 return -EINVAL;
8943
8944 return 0;
8945 }
8946
8947 static int niu_classifier_swstate_init(struct niu *np)
8948 {
8949 struct niu_classifier *cp = &np->clas;
8950
8951 cp->tcam_top = (u16) np->port;
8952 cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
8953 cp->h1_init = 0xffffffff;
8954 cp->h2_init = 0xffff;
8955
8956 return fflp_early_init(np);
8957 }
8958
8959 static void niu_link_config_init(struct niu *np)
8960 {
8961 struct niu_link_config *lp = &np->link_config;
8962
8963 lp->advertising = (ADVERTISED_10baseT_Half |
8964 ADVERTISED_10baseT_Full |
8965 ADVERTISED_100baseT_Half |
8966 ADVERTISED_100baseT_Full |
8967 ADVERTISED_1000baseT_Half |
8968 ADVERTISED_1000baseT_Full |
8969 ADVERTISED_10000baseT_Full |
8970 ADVERTISED_Autoneg);
8971 lp->speed = lp->active_speed = SPEED_INVALID;
8972 lp->duplex = DUPLEX_FULL;
8973 lp->active_duplex = DUPLEX_INVALID;
8974 lp->autoneg = 1;
8975 #if 0
8976 lp->loopback_mode = LOOPBACK_MAC;
8977 lp->active_speed = SPEED_10000;
8978 lp->active_duplex = DUPLEX_FULL;
8979 #else
8980 lp->loopback_mode = LOOPBACK_DISABLED;
8981 #endif
8982 }
8983
8984 static int niu_init_mac_ipp_pcs_base(struct niu *np)
8985 {
8986 switch (np->port) {
8987 case 0:
8988 np->mac_regs = np->regs + XMAC_PORT0_OFF;
8989 np->ipp_off = 0x00000;
8990 np->pcs_off = 0x04000;
8991 np->xpcs_off = 0x02000;
8992 break;
8993
8994 case 1:
8995 np->mac_regs = np->regs + XMAC_PORT1_OFF;
8996 np->ipp_off = 0x08000;
8997 np->pcs_off = 0x0a000;
8998 np->xpcs_off = 0x08000;
8999 break;
9000
9001 case 2:
9002 np->mac_regs = np->regs + BMAC_PORT2_OFF;
9003 np->ipp_off = 0x04000;
9004 np->pcs_off = 0x0e000;
9005 np->xpcs_off = ~0UL;
9006 break;
9007
9008 case 3:
9009 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9010 np->ipp_off = 0x0c000;
9011 np->pcs_off = 0x12000;
9012 np->xpcs_off = ~0UL;
9013 break;
9014
9015 default:
9016 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
9017 return -EINVAL;
9018 }
9019
9020 return 0;
9021 }
9022
9023 static void niu_try_msix(struct niu *np, u8 *ldg_num_map)
9024 {
9025 struct msix_entry msi_vec[NIU_NUM_LDG];
9026 struct niu_parent *parent = np->parent;
9027 struct pci_dev *pdev = np->pdev;
9028 int i, num_irqs;
9029 u8 first_ldg;
9030
9031 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9032 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9033 ldg_num_map[i] = first_ldg + i;
9034
9035 num_irqs = (parent->rxchan_per_port[np->port] +
9036 parent->txchan_per_port[np->port] +
9037 (np->port == 0 ? 3 : 1));
9038 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9039
9040 for (i = 0; i < num_irqs; i++) {
9041 msi_vec[i].vector = 0;
9042 msi_vec[i].entry = i;
9043 }
9044
9045 num_irqs = pci_enable_msix_range(pdev, msi_vec, 1, num_irqs);
9046 if (num_irqs < 0) {
9047 np->flags &= ~NIU_FLAGS_MSIX;
9048 return;
9049 }
9050
9051 np->flags |= NIU_FLAGS_MSIX;
9052 for (i = 0; i < num_irqs; i++)
9053 np->ldg[i].irq = msi_vec[i].vector;
9054 np->num_ldg = num_irqs;
9055 }
9056
9057 static int niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9058 {
9059 #ifdef CONFIG_SPARC64
9060 struct platform_device *op = np->op;
9061 const u32 *int_prop;
9062 int i;
9063
9064 int_prop = of_get_property(op->dev.of_node, "interrupts", NULL);
9065 if (!int_prop)
9066 return -ENODEV;
9067
9068 for (i = 0; i < op->archdata.num_irqs; i++) {
9069 ldg_num_map[i] = int_prop[i];
9070 np->ldg[i].irq = op->archdata.irqs[i];
9071 }
9072
9073 np->num_ldg = op->archdata.num_irqs;
9074
9075 return 0;
9076 #else
9077 return -EINVAL;
9078 #endif
9079 }
9080
9081 static int niu_ldg_init(struct niu *np)
9082 {
9083 struct niu_parent *parent = np->parent;
9084 u8 ldg_num_map[NIU_NUM_LDG];
9085 int first_chan, num_chan;
9086 int i, err, ldg_rotor;
9087 u8 port;
9088
9089 np->num_ldg = 1;
9090 np->ldg[0].irq = np->dev->irq;
9091 if (parent->plat_type == PLAT_TYPE_NIU) {
9092 err = niu_n2_irq_init(np, ldg_num_map);
9093 if (err)
9094 return err;
9095 } else
9096 niu_try_msix(np, ldg_num_map);
9097
9098 port = np->port;
9099 for (i = 0; i < np->num_ldg; i++) {
9100 struct niu_ldg *lp = &np->ldg[i];
9101
9102 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9103
9104 lp->np = np;
9105 lp->ldg_num = ldg_num_map[i];
9106 lp->timer = 2; /* XXX */
9107
9108 /* On N2 NIU the firmware has setup the SID mappings so they go
9109 * to the correct values that will route the LDG to the proper
9110 * interrupt in the NCU interrupt table.
9111 */
9112 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9113 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9114 if (err)
9115 return err;
9116 }
9117 }
9118
9119 /* We adopt the LDG assignment ordering used by the N2 NIU
9120 * 'interrupt' properties because that simplifies a lot of
9121 * things. This ordering is:
9122 *
9123 * MAC
9124 * MIF (if port zero)
9125 * SYSERR (if port zero)
9126 * RX channels
9127 * TX channels
9128 */
9129
9130 ldg_rotor = 0;
9131
9132 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9133 LDN_MAC(port));
9134 if (err)
9135 return err;
9136
9137 ldg_rotor++;
9138 if (ldg_rotor == np->num_ldg)
9139 ldg_rotor = 0;
9140
9141 if (port == 0) {
9142 err = niu_ldg_assign_ldn(np, parent,
9143 ldg_num_map[ldg_rotor],
9144 LDN_MIF);
9145 if (err)
9146 return err;
9147
9148 ldg_rotor++;
9149 if (ldg_rotor == np->num_ldg)
9150 ldg_rotor = 0;
9151
9152 err = niu_ldg_assign_ldn(np, parent,
9153 ldg_num_map[ldg_rotor],
9154 LDN_DEVICE_ERROR);
9155 if (err)
9156 return err;
9157
9158 ldg_rotor++;
9159 if (ldg_rotor == np->num_ldg)
9160 ldg_rotor = 0;
9161
9162 }
9163
9164 first_chan = 0;
9165 for (i = 0; i < port; i++)
9166 first_chan += parent->rxchan_per_port[i];
9167 num_chan = parent->rxchan_per_port[port];
9168
9169 for (i = first_chan; i < (first_chan + num_chan); i++) {
9170 err = niu_ldg_assign_ldn(np, parent,
9171 ldg_num_map[ldg_rotor],
9172 LDN_RXDMA(i));
9173 if (err)
9174 return err;
9175 ldg_rotor++;
9176 if (ldg_rotor == np->num_ldg)
9177 ldg_rotor = 0;
9178 }
9179
9180 first_chan = 0;
9181 for (i = 0; i < port; i++)
9182 first_chan += parent->txchan_per_port[i];
9183 num_chan = parent->txchan_per_port[port];
9184 for (i = first_chan; i < (first_chan + num_chan); i++) {
9185 err = niu_ldg_assign_ldn(np, parent,
9186 ldg_num_map[ldg_rotor],
9187 LDN_TXDMA(i));
9188 if (err)
9189 return err;
9190 ldg_rotor++;
9191 if (ldg_rotor == np->num_ldg)
9192 ldg_rotor = 0;
9193 }
9194
9195 return 0;
9196 }
9197
9198 static void niu_ldg_free(struct niu *np)
9199 {
9200 if (np->flags & NIU_FLAGS_MSIX)
9201 pci_disable_msix(np->pdev);
9202 }
9203
9204 static int niu_get_of_props(struct niu *np)
9205 {
9206 #ifdef CONFIG_SPARC64
9207 struct net_device *dev = np->dev;
9208 struct device_node *dp;
9209 const char *phy_type;
9210 const u8 *mac_addr;
9211 const char *model;
9212 int prop_len;
9213
9214 if (np->parent->plat_type == PLAT_TYPE_NIU)
9215 dp = np->op->dev.of_node;
9216 else
9217 dp = pci_device_to_OF_node(np->pdev);
9218
9219 phy_type = of_get_property(dp, "phy-type", &prop_len);
9220 if (!phy_type) {
9221 netdev_err(dev, "%pOF: OF node lacks phy-type property\n", dp);
9222 return -EINVAL;
9223 }
9224
9225 if (!strcmp(phy_type, "none"))
9226 return -ENODEV;
9227
9228 strcpy(np->vpd.phy_type, phy_type);
9229
9230 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
9231 netdev_err(dev, "%pOF: Illegal phy string [%s]\n",
9232 dp, np->vpd.phy_type);
9233 return -EINVAL;
9234 }
9235
9236 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9237 if (!mac_addr) {
9238 netdev_err(dev, "%pOF: OF node lacks local-mac-address property\n",
9239 dp);
9240 return -EINVAL;
9241 }
9242 if (prop_len != dev->addr_len) {
9243 netdev_err(dev, "%pOF: OF MAC address prop len (%d) is wrong\n",
9244 dp, prop_len);
9245 }
9246 memcpy(dev->dev_addr, mac_addr, dev->addr_len);
9247 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
9248 netdev_err(dev, "%pOF: OF MAC address is invalid\n", dp);
9249 netdev_err(dev, "%pOF: [ %pM ]\n", dp, dev->dev_addr);
9250 return -EINVAL;
9251 }
9252
9253 model = of_get_property(dp, "model", &prop_len);
9254
9255 if (model)
9256 strcpy(np->vpd.model, model);
9257
9258 if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
9259 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
9260 NIU_FLAGS_HOTPLUG_PHY);
9261 }
9262
9263 return 0;
9264 #else
9265 return -EINVAL;
9266 #endif
9267 }
9268
9269 static int niu_get_invariants(struct niu *np)
9270 {
9271 int err, have_props;
9272 u32 offset;
9273
9274 err = niu_get_of_props(np);
9275 if (err == -ENODEV)
9276 return err;
9277
9278 have_props = !err;
9279
9280 err = niu_init_mac_ipp_pcs_base(np);
9281 if (err)
9282 return err;
9283
9284 if (have_props) {
9285 err = niu_get_and_validate_port(np);
9286 if (err)
9287 return err;
9288
9289 } else {
9290 if (np->parent->plat_type == PLAT_TYPE_NIU)
9291 return -EINVAL;
9292
9293 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9294 offset = niu_pci_vpd_offset(np);
9295 netif_printk(np, probe, KERN_DEBUG, np->dev,
9296 "%s() VPD offset [%08x]\n", __func__, offset);
9297 if (offset)
9298 niu_pci_vpd_fetch(np, offset);
9299 nw64(ESPC_PIO_EN, 0);
9300
9301 if (np->flags & NIU_FLAGS_VPD_VALID) {
9302 niu_pci_vpd_validate(np);
9303 err = niu_get_and_validate_port(np);
9304 if (err)
9305 return err;
9306 }
9307
9308 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
9309 err = niu_get_and_validate_port(np);
9310 if (err)
9311 return err;
9312 err = niu_pci_probe_sprom(np);
9313 if (err)
9314 return err;
9315 }
9316 }
9317
9318 err = niu_probe_ports(np);
9319 if (err)
9320 return err;
9321
9322 niu_ldg_init(np);
9323
9324 niu_classifier_swstate_init(np);
9325 niu_link_config_init(np);
9326
9327 err = niu_determine_phy_disposition(np);
9328 if (!err)
9329 err = niu_init_link(np);
9330
9331 return err;
9332 }
9333
9334 static LIST_HEAD(niu_parent_list);
9335 static DEFINE_MUTEX(niu_parent_lock);
9336 static int niu_parent_index;
9337
9338 static ssize_t show_port_phy(struct device *dev,
9339 struct device_attribute *attr, char *buf)
9340 {
9341 struct platform_device *plat_dev = to_platform_device(dev);
9342 struct niu_parent *p = dev_get_platdata(&plat_dev->dev);
9343 u32 port_phy = p->port_phy;
9344 char *orig_buf = buf;
9345 int i;
9346
9347 if (port_phy == PORT_PHY_UNKNOWN ||
9348 port_phy == PORT_PHY_INVALID)
9349 return 0;
9350
9351 for (i = 0; i < p->num_ports; i++) {
9352 const char *type_str;
9353 int type;
9354
9355 type = phy_decode(port_phy, i);
9356 if (type == PORT_TYPE_10G)
9357 type_str = "10G";
9358 else
9359 type_str = "1G";
9360 buf += sprintf(buf,
9361 (i == 0) ? "%s" : " %s",
9362 type_str);
9363 }
9364 buf += sprintf(buf, "\n");
9365 return buf - orig_buf;
9366 }
9367
9368 static ssize_t show_plat_type(struct device *dev,
9369 struct device_attribute *attr, char *buf)
9370 {
9371 struct platform_device *plat_dev = to_platform_device(dev);
9372 struct niu_parent *p = dev_get_platdata(&plat_dev->dev);
9373 const char *type_str;
9374
9375 switch (p->plat_type) {
9376 case PLAT_TYPE_ATLAS:
9377 type_str = "atlas";
9378 break;
9379 case PLAT_TYPE_NIU:
9380 type_str = "niu";
9381 break;
9382 case PLAT_TYPE_VF_P0:
9383 type_str = "vf_p0";
9384 break;
9385 case PLAT_TYPE_VF_P1:
9386 type_str = "vf_p1";
9387 break;
9388 default:
9389 type_str = "unknown";
9390 break;
9391 }
9392
9393 return sprintf(buf, "%s\n", type_str);
9394 }
9395
9396 static ssize_t __show_chan_per_port(struct device *dev,
9397 struct device_attribute *attr, char *buf,
9398 int rx)
9399 {
9400 struct platform_device *plat_dev = to_platform_device(dev);
9401 struct niu_parent *p = dev_get_platdata(&plat_dev->dev);
9402 char *orig_buf = buf;
9403 u8 *arr;
9404 int i;
9405
9406 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9407
9408 for (i = 0; i < p->num_ports; i++) {
9409 buf += sprintf(buf,
9410 (i == 0) ? "%d" : " %d",
9411 arr[i]);
9412 }
9413 buf += sprintf(buf, "\n");
9414
9415 return buf - orig_buf;
9416 }
9417
9418 static ssize_t show_rxchan_per_port(struct device *dev,
9419 struct device_attribute *attr, char *buf)
9420 {
9421 return __show_chan_per_port(dev, attr, buf, 1);
9422 }
9423
9424 static ssize_t show_txchan_per_port(struct device *dev,
9425 struct device_attribute *attr, char *buf)
9426 {
9427 return __show_chan_per_port(dev, attr, buf, 1);
9428 }
9429
9430 static ssize_t show_num_ports(struct device *dev,
9431 struct device_attribute *attr, char *buf)
9432 {
9433 struct platform_device *plat_dev = to_platform_device(dev);
9434 struct niu_parent *p = dev_get_platdata(&plat_dev->dev);
9435
9436 return sprintf(buf, "%d\n", p->num_ports);
9437 }
9438
9439 static struct device_attribute niu_parent_attributes[] = {
9440 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
9441 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
9442 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
9443 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
9444 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
9445 {}
9446 };
9447
9448 static struct niu_parent *niu_new_parent(struct niu *np,
9449 union niu_parent_id *id, u8 ptype)
9450 {
9451 struct platform_device *plat_dev;
9452 struct niu_parent *p;
9453 int i;
9454
9455 plat_dev = platform_device_register_simple("niu-board", niu_parent_index,
9456 NULL, 0);
9457 if (IS_ERR(plat_dev))
9458 return NULL;
9459
9460 for (i = 0; niu_parent_attributes[i].attr.name; i++) {
9461 int err = device_create_file(&plat_dev->dev,
9462 &niu_parent_attributes[i]);
9463 if (err)
9464 goto fail_unregister;
9465 }
9466
9467 p = kzalloc(sizeof(*p), GFP_KERNEL);
9468 if (!p)
9469 goto fail_unregister;
9470
9471 p->index = niu_parent_index++;
9472
9473 plat_dev->dev.platform_data = p;
9474 p->plat_dev = plat_dev;
9475
9476 memcpy(&p->id, id, sizeof(*id));
9477 p->plat_type = ptype;
9478 INIT_LIST_HEAD(&p->list);
9479 atomic_set(&p->refcnt, 0);
9480 list_add(&p->list, &niu_parent_list);
9481 spin_lock_init(&p->lock);
9482
9483 p->rxdma_clock_divider = 7500;
9484
9485 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9486 if (p->plat_type == PLAT_TYPE_NIU)
9487 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9488
9489 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9490 int index = i - CLASS_CODE_USER_PROG1;
9491
9492 p->tcam_key[index] = TCAM_KEY_TSEL;
9493 p->flow_key[index] = (FLOW_KEY_IPSA |
9494 FLOW_KEY_IPDA |
9495 FLOW_KEY_PROTO |
9496 (FLOW_KEY_L4_BYTE12 <<
9497 FLOW_KEY_L4_0_SHIFT) |
9498 (FLOW_KEY_L4_BYTE12 <<
9499 FLOW_KEY_L4_1_SHIFT));
9500 }
9501
9502 for (i = 0; i < LDN_MAX + 1; i++)
9503 p->ldg_map[i] = LDG_INVALID;
9504
9505 return p;
9506
9507 fail_unregister:
9508 platform_device_unregister(plat_dev);
9509 return NULL;
9510 }
9511
9512 static struct niu_parent *niu_get_parent(struct niu *np,
9513 union niu_parent_id *id, u8 ptype)
9514 {
9515 struct niu_parent *p, *tmp;
9516 int port = np->port;
9517
9518 mutex_lock(&niu_parent_lock);
9519 p = NULL;
9520 list_for_each_entry(tmp, &niu_parent_list, list) {
9521 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9522 p = tmp;
9523 break;
9524 }
9525 }
9526 if (!p)
9527 p = niu_new_parent(np, id, ptype);
9528
9529 if (p) {
9530 char port_name[8];
9531 int err;
9532
9533 sprintf(port_name, "port%d", port);
9534 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9535 &np->device->kobj,
9536 port_name);
9537 if (!err) {
9538 p->ports[port] = np;
9539 atomic_inc(&p->refcnt);
9540 }
9541 }
9542 mutex_unlock(&niu_parent_lock);
9543
9544 return p;
9545 }
9546
9547 static void niu_put_parent(struct niu *np)
9548 {
9549 struct niu_parent *p = np->parent;
9550 u8 port = np->port;
9551 char port_name[8];
9552
9553 BUG_ON(!p || p->ports[port] != np);
9554
9555 netif_printk(np, probe, KERN_DEBUG, np->dev,
9556 "%s() port[%u]\n", __func__, port);
9557
9558 sprintf(port_name, "port%d", port);
9559
9560 mutex_lock(&niu_parent_lock);
9561
9562 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9563
9564 p->ports[port] = NULL;
9565 np->parent = NULL;
9566
9567 if (atomic_dec_and_test(&p->refcnt)) {
9568 list_del(&p->list);
9569 platform_device_unregister(p->plat_dev);
9570 }
9571
9572 mutex_unlock(&niu_parent_lock);
9573 }
9574
9575 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9576 u64 *handle, gfp_t flag)
9577 {
9578 dma_addr_t dh;
9579 void *ret;
9580
9581 ret = dma_alloc_coherent(dev, size, &dh, flag);
9582 if (ret)
9583 *handle = dh;
9584 return ret;
9585 }
9586
9587 static void niu_pci_free_coherent(struct device *dev, size_t size,
9588 void *cpu_addr, u64 handle)
9589 {
9590 dma_free_coherent(dev, size, cpu_addr, handle);
9591 }
9592
9593 static u64 niu_pci_map_page(struct device *dev, struct page *page,
9594 unsigned long offset, size_t size,
9595 enum dma_data_direction direction)
9596 {
9597 return dma_map_page(dev, page, offset, size, direction);
9598 }
9599
9600 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9601 size_t size, enum dma_data_direction direction)
9602 {
9603 dma_unmap_page(dev, dma_address, size, direction);
9604 }
9605
9606 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9607 size_t size,
9608 enum dma_data_direction direction)
9609 {
9610 return dma_map_single(dev, cpu_addr, size, direction);
9611 }
9612
9613 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9614 size_t size,
9615 enum dma_data_direction direction)
9616 {
9617 dma_unmap_single(dev, dma_address, size, direction);
9618 }
9619
9620 static const struct niu_ops niu_pci_ops = {
9621 .alloc_coherent = niu_pci_alloc_coherent,
9622 .free_coherent = niu_pci_free_coherent,
9623 .map_page = niu_pci_map_page,
9624 .unmap_page = niu_pci_unmap_page,
9625 .map_single = niu_pci_map_single,
9626 .unmap_single = niu_pci_unmap_single,
9627 };
9628
9629 static void niu_driver_version(void)
9630 {
9631 static int niu_version_printed;
9632
9633 if (niu_version_printed++ == 0)
9634 pr_info("%s", version);
9635 }
9636
9637 static struct net_device *niu_alloc_and_init(struct device *gen_dev,
9638 struct pci_dev *pdev,
9639 struct platform_device *op,
9640 const struct niu_ops *ops, u8 port)
9641 {
9642 struct net_device *dev;
9643 struct niu *np;
9644
9645 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
9646 if (!dev)
9647 return NULL;
9648
9649 SET_NETDEV_DEV(dev, gen_dev);
9650
9651 np = netdev_priv(dev);
9652 np->dev = dev;
9653 np->pdev = pdev;
9654 np->op = op;
9655 np->device = gen_dev;
9656 np->ops = ops;
9657
9658 np->msg_enable = niu_debug;
9659
9660 spin_lock_init(&np->lock);
9661 INIT_WORK(&np->reset_task, niu_reset_task);
9662
9663 np->port = port;
9664
9665 return dev;
9666 }
9667
9668 static const struct net_device_ops niu_netdev_ops = {
9669 .ndo_open = niu_open,
9670 .ndo_stop = niu_close,
9671 .ndo_start_xmit = niu_start_xmit,
9672 .ndo_get_stats64 = niu_get_stats,
9673 .ndo_set_rx_mode = niu_set_rx_mode,
9674 .ndo_validate_addr = eth_validate_addr,
9675 .ndo_set_mac_address = niu_set_mac_addr,
9676 .ndo_do_ioctl = niu_ioctl,
9677 .ndo_tx_timeout = niu_tx_timeout,
9678 .ndo_change_mtu = niu_change_mtu,
9679 };
9680
9681 static void niu_assign_netdev_ops(struct net_device *dev)
9682 {
9683 dev->netdev_ops = &niu_netdev_ops;
9684 dev->ethtool_ops = &niu_ethtool_ops;
9685 dev->watchdog_timeo = NIU_TX_TIMEOUT;
9686 }
9687
9688 static void niu_device_announce(struct niu *np)
9689 {
9690 struct net_device *dev = np->dev;
9691
9692 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
9693
9694 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9695 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9696 dev->name,
9697 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9698 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9699 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9700 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9701 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9702 np->vpd.phy_type);
9703 } else {
9704 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9705 dev->name,
9706 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9707 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9708 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9709 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9710 "COPPER")),
9711 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9712 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9713 np->vpd.phy_type);
9714 }
9715 }
9716
9717 static void niu_set_basic_features(struct net_device *dev)
9718 {
9719 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXHASH;
9720 dev->features |= dev->hw_features | NETIF_F_RXCSUM;
9721 }
9722
9723 static int niu_pci_init_one(struct pci_dev *pdev,
9724 const struct pci_device_id *ent)
9725 {
9726 union niu_parent_id parent_id;
9727 struct net_device *dev;
9728 struct niu *np;
9729 int err;
9730 u64 dma_mask;
9731
9732 niu_driver_version();
9733
9734 err = pci_enable_device(pdev);
9735 if (err) {
9736 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9737 return err;
9738 }
9739
9740 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9741 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9742 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
9743 err = -ENODEV;
9744 goto err_out_disable_pdev;
9745 }
9746
9747 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9748 if (err) {
9749 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9750 goto err_out_disable_pdev;
9751 }
9752
9753 if (!pci_is_pcie(pdev)) {
9754 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
9755 err = -ENODEV;
9756 goto err_out_free_res;
9757 }
9758
9759 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9760 &niu_pci_ops, PCI_FUNC(pdev->devfn));
9761 if (!dev) {
9762 err = -ENOMEM;
9763 goto err_out_free_res;
9764 }
9765 np = netdev_priv(dev);
9766
9767 memset(&parent_id, 0, sizeof(parent_id));
9768 parent_id.pci.domain = pci_domain_nr(pdev->bus);
9769 parent_id.pci.bus = pdev->bus->number;
9770 parent_id.pci.device = PCI_SLOT(pdev->devfn);
9771
9772 np->parent = niu_get_parent(np, &parent_id,
9773 PLAT_TYPE_ATLAS);
9774 if (!np->parent) {
9775 err = -ENOMEM;
9776 goto err_out_free_dev;
9777 }
9778
9779 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
9780 PCI_EXP_DEVCTL_NOSNOOP_EN,
9781 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
9782 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE |
9783 PCI_EXP_DEVCTL_RELAX_EN);
9784
9785 dma_mask = DMA_BIT_MASK(44);
9786 err = pci_set_dma_mask(pdev, dma_mask);
9787 if (!err) {
9788 dev->features |= NETIF_F_HIGHDMA;
9789 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9790 if (err) {
9791 dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
9792 goto err_out_release_parent;
9793 }
9794 }
9795 if (err) {
9796 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9797 if (err) {
9798 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
9799 goto err_out_release_parent;
9800 }
9801 }
9802
9803 niu_set_basic_features(dev);
9804
9805 dev->priv_flags |= IFF_UNICAST_FLT;
9806
9807 np->regs = pci_ioremap_bar(pdev, 0);
9808 if (!np->regs) {
9809 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9810 err = -ENOMEM;
9811 goto err_out_release_parent;
9812 }
9813
9814 pci_set_master(pdev);
9815 pci_save_state(pdev);
9816
9817 dev->irq = pdev->irq;
9818
9819 /* MTU range: 68 - 9216 */
9820 dev->min_mtu = ETH_MIN_MTU;
9821 dev->max_mtu = NIU_MAX_MTU;
9822
9823 niu_assign_netdev_ops(dev);
9824
9825 err = niu_get_invariants(np);
9826 if (err) {
9827 if (err != -ENODEV)
9828 dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
9829 goto err_out_iounmap;
9830 }
9831
9832 err = register_netdev(dev);
9833 if (err) {
9834 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
9835 goto err_out_iounmap;
9836 }
9837
9838 pci_set_drvdata(pdev, dev);
9839
9840 niu_device_announce(np);
9841
9842 return 0;
9843
9844 err_out_iounmap:
9845 if (np->regs) {
9846 iounmap(np->regs);
9847 np->regs = NULL;
9848 }
9849
9850 err_out_release_parent:
9851 niu_put_parent(np);
9852
9853 err_out_free_dev:
9854 free_netdev(dev);
9855
9856 err_out_free_res:
9857 pci_release_regions(pdev);
9858
9859 err_out_disable_pdev:
9860 pci_disable_device(pdev);
9861
9862 return err;
9863 }
9864
9865 static void niu_pci_remove_one(struct pci_dev *pdev)
9866 {
9867 struct net_device *dev = pci_get_drvdata(pdev);
9868
9869 if (dev) {
9870 struct niu *np = netdev_priv(dev);
9871
9872 unregister_netdev(dev);
9873 if (np->regs) {
9874 iounmap(np->regs);
9875 np->regs = NULL;
9876 }
9877
9878 niu_ldg_free(np);
9879
9880 niu_put_parent(np);
9881
9882 free_netdev(dev);
9883 pci_release_regions(pdev);
9884 pci_disable_device(pdev);
9885 }
9886 }
9887
9888 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9889 {
9890 struct net_device *dev = pci_get_drvdata(pdev);
9891 struct niu *np = netdev_priv(dev);
9892 unsigned long flags;
9893
9894 if (!netif_running(dev))
9895 return 0;
9896
9897 flush_work(&np->reset_task);
9898 niu_netif_stop(np);
9899
9900 del_timer_sync(&np->timer);
9901
9902 spin_lock_irqsave(&np->lock, flags);
9903 niu_enable_interrupts(np, 0);
9904 spin_unlock_irqrestore(&np->lock, flags);
9905
9906 netif_device_detach(dev);
9907
9908 spin_lock_irqsave(&np->lock, flags);
9909 niu_stop_hw(np);
9910 spin_unlock_irqrestore(&np->lock, flags);
9911
9912 pci_save_state(pdev);
9913
9914 return 0;
9915 }
9916
9917 static int niu_resume(struct pci_dev *pdev)
9918 {
9919 struct net_device *dev = pci_get_drvdata(pdev);
9920 struct niu *np = netdev_priv(dev);
9921 unsigned long flags;
9922 int err;
9923
9924 if (!netif_running(dev))
9925 return 0;
9926
9927 pci_restore_state(pdev);
9928
9929 netif_device_attach(dev);
9930
9931 spin_lock_irqsave(&np->lock, flags);
9932
9933 err = niu_init_hw(np);
9934 if (!err) {
9935 np->timer.expires = jiffies + HZ;
9936 add_timer(&np->timer);
9937 niu_netif_start(np);
9938 }
9939
9940 spin_unlock_irqrestore(&np->lock, flags);
9941
9942 return err;
9943 }
9944
9945 static struct pci_driver niu_pci_driver = {
9946 .name = DRV_MODULE_NAME,
9947 .id_table = niu_pci_tbl,
9948 .probe = niu_pci_init_one,
9949 .remove = niu_pci_remove_one,
9950 .suspend = niu_suspend,
9951 .resume = niu_resume,
9952 };
9953
9954 #ifdef CONFIG_SPARC64
9955 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
9956 u64 *dma_addr, gfp_t flag)
9957 {
9958 unsigned long order = get_order(size);
9959 unsigned long page = __get_free_pages(flag, order);
9960
9961 if (page == 0UL)
9962 return NULL;
9963 memset((char *)page, 0, PAGE_SIZE << order);
9964 *dma_addr = __pa(page);
9965
9966 return (void *) page;
9967 }
9968
9969 static void niu_phys_free_coherent(struct device *dev, size_t size,
9970 void *cpu_addr, u64 handle)
9971 {
9972 unsigned long order = get_order(size);
9973
9974 free_pages((unsigned long) cpu_addr, order);
9975 }
9976
9977 static u64 niu_phys_map_page(struct device *dev, struct page *page,
9978 unsigned long offset, size_t size,
9979 enum dma_data_direction direction)
9980 {
9981 return page_to_phys(page) + offset;
9982 }
9983
9984 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
9985 size_t size, enum dma_data_direction direction)
9986 {
9987 /* Nothing to do. */
9988 }
9989
9990 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
9991 size_t size,
9992 enum dma_data_direction direction)
9993 {
9994 return __pa(cpu_addr);
9995 }
9996
9997 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
9998 size_t size,
9999 enum dma_data_direction direction)
10000 {
10001 /* Nothing to do. */
10002 }
10003
10004 static const struct niu_ops niu_phys_ops = {
10005 .alloc_coherent = niu_phys_alloc_coherent,
10006 .free_coherent = niu_phys_free_coherent,
10007 .map_page = niu_phys_map_page,
10008 .unmap_page = niu_phys_unmap_page,
10009 .map_single = niu_phys_map_single,
10010 .unmap_single = niu_phys_unmap_single,
10011 };
10012
10013 static int niu_of_probe(struct platform_device *op)
10014 {
10015 union niu_parent_id parent_id;
10016 struct net_device *dev;
10017 struct niu *np;
10018 const u32 *reg;
10019 int err;
10020
10021 niu_driver_version();
10022
10023 reg = of_get_property(op->dev.of_node, "reg", NULL);
10024 if (!reg) {
10025 dev_err(&op->dev, "%pOF: No 'reg' property, aborting\n",
10026 op->dev.of_node);
10027 return -ENODEV;
10028 }
10029
10030 dev = niu_alloc_and_init(&op->dev, NULL, op,
10031 &niu_phys_ops, reg[0] & 0x1);
10032 if (!dev) {
10033 err = -ENOMEM;
10034 goto err_out;
10035 }
10036 np = netdev_priv(dev);
10037
10038 memset(&parent_id, 0, sizeof(parent_id));
10039 parent_id.of = of_get_parent(op->dev.of_node);
10040
10041 np->parent = niu_get_parent(np, &parent_id,
10042 PLAT_TYPE_NIU);
10043 if (!np->parent) {
10044 err = -ENOMEM;
10045 goto err_out_free_dev;
10046 }
10047
10048 niu_set_basic_features(dev);
10049
10050 np->regs = of_ioremap(&op->resource[1], 0,
10051 resource_size(&op->resource[1]),
10052 "niu regs");
10053 if (!np->regs) {
10054 dev_err(&op->dev, "Cannot map device registers, aborting\n");
10055 err = -ENOMEM;
10056 goto err_out_release_parent;
10057 }
10058
10059 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
10060 resource_size(&op->resource[2]),
10061 "niu vregs-1");
10062 if (!np->vir_regs_1) {
10063 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n");
10064 err = -ENOMEM;
10065 goto err_out_iounmap;
10066 }
10067
10068 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
10069 resource_size(&op->resource[3]),
10070 "niu vregs-2");
10071 if (!np->vir_regs_2) {
10072 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n");
10073 err = -ENOMEM;
10074 goto err_out_iounmap;
10075 }
10076
10077 niu_assign_netdev_ops(dev);
10078
10079 err = niu_get_invariants(np);
10080 if (err) {
10081 if (err != -ENODEV)
10082 dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n");
10083 goto err_out_iounmap;
10084 }
10085
10086 err = register_netdev(dev);
10087 if (err) {
10088 dev_err(&op->dev, "Cannot register net device, aborting\n");
10089 goto err_out_iounmap;
10090 }
10091
10092 platform_set_drvdata(op, dev);
10093
10094 niu_device_announce(np);
10095
10096 return 0;
10097
10098 err_out_iounmap:
10099 if (np->vir_regs_1) {
10100 of_iounmap(&op->resource[2], np->vir_regs_1,
10101 resource_size(&op->resource[2]));
10102 np->vir_regs_1 = NULL;
10103 }
10104
10105 if (np->vir_regs_2) {
10106 of_iounmap(&op->resource[3], np->vir_regs_2,
10107 resource_size(&op->resource[3]));
10108 np->vir_regs_2 = NULL;
10109 }
10110
10111 if (np->regs) {
10112 of_iounmap(&op->resource[1], np->regs,
10113 resource_size(&op->resource[1]));
10114 np->regs = NULL;
10115 }
10116
10117 err_out_release_parent:
10118 niu_put_parent(np);
10119
10120 err_out_free_dev:
10121 free_netdev(dev);
10122
10123 err_out:
10124 return err;
10125 }
10126
10127 static int niu_of_remove(struct platform_device *op)
10128 {
10129 struct net_device *dev = platform_get_drvdata(op);
10130
10131 if (dev) {
10132 struct niu *np = netdev_priv(dev);
10133
10134 unregister_netdev(dev);
10135
10136 if (np->vir_regs_1) {
10137 of_iounmap(&op->resource[2], np->vir_regs_1,
10138 resource_size(&op->resource[2]));
10139 np->vir_regs_1 = NULL;
10140 }
10141
10142 if (np->vir_regs_2) {
10143 of_iounmap(&op->resource[3], np->vir_regs_2,
10144 resource_size(&op->resource[3]));
10145 np->vir_regs_2 = NULL;
10146 }
10147
10148 if (np->regs) {
10149 of_iounmap(&op->resource[1], np->regs,
10150 resource_size(&op->resource[1]));
10151 np->regs = NULL;
10152 }
10153
10154 niu_ldg_free(np);
10155
10156 niu_put_parent(np);
10157
10158 free_netdev(dev);
10159 }
10160 return 0;
10161 }
10162
10163 static const struct of_device_id niu_match[] = {
10164 {
10165 .name = "network",
10166 .compatible = "SUNW,niusl",
10167 },
10168 {},
10169 };
10170 MODULE_DEVICE_TABLE(of, niu_match);
10171
10172 static struct platform_driver niu_of_driver = {
10173 .driver = {
10174 .name = "niu",
10175 .of_match_table = niu_match,
10176 },
10177 .probe = niu_of_probe,
10178 .remove = niu_of_remove,
10179 };
10180
10181 #endif /* CONFIG_SPARC64 */
10182
10183 static int __init niu_init(void)
10184 {
10185 int err = 0;
10186
10187 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
10188
10189 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10190
10191 #ifdef CONFIG_SPARC64
10192 err = platform_driver_register(&niu_of_driver);
10193 #endif
10194
10195 if (!err) {
10196 err = pci_register_driver(&niu_pci_driver);
10197 #ifdef CONFIG_SPARC64
10198 if (err)
10199 platform_driver_unregister(&niu_of_driver);
10200 #endif
10201 }
10202
10203 return err;
10204 }
10205
10206 static void __exit niu_exit(void)
10207 {
10208 pci_unregister_driver(&niu_pci_driver);
10209 #ifdef CONFIG_SPARC64
10210 platform_driver_unregister(&niu_of_driver);
10211 #endif
10212 }
10213
10214 module_init(niu_init);
10215 module_exit(niu_exit);
CRIS linux kernel tree