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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[cris-mirror.git] / drivers / usb / host / ehci-fsl.c
blobc5094cb88cd5d61a1c00544a16c343aa304d02d1
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2005-2009 MontaVista Software, Inc.
4 * Copyright 2008,2012,2015 Freescale Semiconductor, Inc.
5 *
6 * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided
7 * by Hunter Wu.
8 * Power Management support by Dave Liu <daveliu@freescale.com>,
9 * Jerry Huang <Chang-Ming.Huang@freescale.com> and
10 * Anton Vorontsov <avorontsov@ru.mvista.com>.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/types.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/err.h>
19 #include <linux/usb.h>
20 #include <linux/usb/ehci_def.h>
21 #include <linux/usb/hcd.h>
22 #include <linux/usb/otg.h>
23 #include <linux/platform_device.h>
24 #include <linux/fsl_devices.h>
25 #include <linux/of_platform.h>
26
27 #include "ehci.h"
28 #include "ehci-fsl.h"
29
30 #define DRIVER_DESC "Freescale EHCI Host controller driver"
31 #define DRV_NAME "ehci-fsl"
32
33 static struct hc_driver __read_mostly fsl_ehci_hc_driver;
34
35 /* configure so an HC device and id are always provided */
36 /* always called with process context; sleeping is OK */
37
38 /*
39 * fsl_ehci_drv_probe - initialize FSL-based HCDs
40 * @pdev: USB Host Controller being probed
41 * Context: !in_interrupt()
42 *
43 * Allocates basic resources for this USB host controller.
44 *
45 */
46 static int fsl_ehci_drv_probe(struct platform_device *pdev)
47 {
48 struct fsl_usb2_platform_data *pdata;
49 struct usb_hcd *hcd;
50 struct resource *res;
51 int irq;
52 int retval;
53
54 pr_debug("initializing FSL-SOC USB Controller\n");
55
56 /* Need platform data for setup */
57 pdata = dev_get_platdata(&pdev->dev);
58 if (!pdata) {
59 dev_err(&pdev->dev,
60 "No platform data for %s.\n", dev_name(&pdev->dev));
61 return -ENODEV;
62 }
63
64 /*
65 * This is a host mode driver, verify that we're supposed to be
66 * in host mode.
67 */
68 if (!((pdata->operating_mode == FSL_USB2_DR_HOST) ||
69 (pdata->operating_mode == FSL_USB2_MPH_HOST) ||
70 (pdata->operating_mode == FSL_USB2_DR_OTG))) {
71 dev_err(&pdev->dev,
72 "Non Host Mode configured for %s. Wrong driver linked.\n",
73 dev_name(&pdev->dev));
74 return -ENODEV;
75 }
76
77 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
78 if (!res) {
79 dev_err(&pdev->dev,
80 "Found HC with no IRQ. Check %s setup!\n",
81 dev_name(&pdev->dev));
82 return -ENODEV;
83 }
84 irq = res->start;
85
86 hcd = __usb_create_hcd(&fsl_ehci_hc_driver, pdev->dev.parent,
87 &pdev->dev, dev_name(&pdev->dev), NULL);
88 if (!hcd) {
89 retval = -ENOMEM;
90 goto err1;
91 }
92
93 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
94 hcd->regs = devm_ioremap_resource(&pdev->dev, res);
95 if (IS_ERR(hcd->regs)) {
96 retval = PTR_ERR(hcd->regs);
97 goto err2;
98 }
99
100 hcd->rsrc_start = res->start;
101 hcd->rsrc_len = resource_size(res);
102
103 pdata->regs = hcd->regs;
104
105 if (pdata->power_budget)
106 hcd->power_budget = pdata->power_budget;
107
108 /*
109 * do platform specific init: check the clock, grab/config pins, etc.
110 */
111 if (pdata->init && pdata->init(pdev)) {
112 retval = -ENODEV;
113 goto err2;
114 }
115
116 /* Enable USB controller, 83xx or 8536 */
117 if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6)
118 clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
119 CONTROL_REGISTER_W1C_MASK, 0x4);
120
121 /*
122 * Enable UTMI phy and program PTS field in UTMI mode before asserting
123 * controller reset for USB Controller version 2.5
124 */
125 if (pdata->has_fsl_erratum_a007792) {
126 clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
127 CONTROL_REGISTER_W1C_MASK, CTRL_UTMI_PHY_EN);
128 writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1);
129 }
130
131 /* Don't need to set host mode here. It will be done by tdi_reset() */
132
133 retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
134 if (retval != 0)
135 goto err2;
136 device_wakeup_enable(hcd->self.controller);
137
138 #ifdef CONFIG_USB_OTG
139 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
140 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
141
142 hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
143 dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n",
144 hcd, ehci, hcd->usb_phy);
145
146 if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
147 retval = otg_set_host(hcd->usb_phy->otg,
148 &ehci_to_hcd(ehci)->self);
149 if (retval) {
150 usb_put_phy(hcd->usb_phy);
151 goto err2;
152 }
153 } else {
154 dev_err(&pdev->dev, "can't find phy\n");
155 retval = -ENODEV;
156 goto err2;
157 }
158 }
159 #endif
160 return retval;
161
162 err2:
163 usb_put_hcd(hcd);
164 err1:
165 dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
166 if (pdata->exit)
167 pdata->exit(pdev);
168 return retval;
169 }
170
171 static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
172 enum fsl_usb2_phy_modes phy_mode,
173 unsigned int port_offset)
174 {
175 u32 portsc;
176 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
177 void __iomem *non_ehci = hcd->regs;
178 struct device *dev = hcd->self.controller;
179 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
180
181 if (pdata->controller_ver < 0) {
182 dev_warn(hcd->self.controller, "Could not get controller version\n");
183 return -ENODEV;
184 }
185
186 portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
187 portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
188
189 switch (phy_mode) {
190 case FSL_USB2_PHY_ULPI:
191 if (pdata->have_sysif_regs && pdata->controller_ver) {
192 /* controller version 1.6 or above */
193 clrbits32(non_ehci + FSL_SOC_USB_CTRL,
194 CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN);
195 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
196 CONTROL_REGISTER_W1C_MASK,
197 ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN);
198 }
199 portsc |= PORT_PTS_ULPI;
200 break;
201 case FSL_USB2_PHY_SERIAL:
202 portsc |= PORT_PTS_SERIAL;
203 break;
204 case FSL_USB2_PHY_UTMI_WIDE:
205 portsc |= PORT_PTS_PTW;
206 /* fall through */
207 case FSL_USB2_PHY_UTMI:
208 case FSL_USB2_PHY_UTMI_DUAL:
209 if (pdata->have_sysif_regs && pdata->controller_ver) {
210 /* controller version 1.6 or above */
211 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
212 CONTROL_REGISTER_W1C_MASK, UTMI_PHY_EN);
213 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to
214 become stable - 10ms*/
215 }
216 /* enable UTMI PHY */
217 if (pdata->have_sysif_regs)
218 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
219 CONTROL_REGISTER_W1C_MASK,
220 CTRL_UTMI_PHY_EN);
221 portsc |= PORT_PTS_UTMI;
222 break;
223 case FSL_USB2_PHY_NONE:
224 break;
225 }
226
227 /*
228 * check PHY_CLK_VALID to determine phy clock presence before writing
229 * to portsc
230 */
231 if (pdata->check_phy_clk_valid) {
232 if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) &
233 PHY_CLK_VALID)) {
234 dev_warn(hcd->self.controller,
235 "USB PHY clock invalid\n");
236 return -EINVAL;
237 }
238 }
239
240 ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
241
242 if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs)
243 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
244 CONTROL_REGISTER_W1C_MASK, USB_CTRL_USB_EN);
245
246 return 0;
247 }
248
249 static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
250 {
251 struct usb_hcd *hcd = ehci_to_hcd(ehci);
252 struct fsl_usb2_platform_data *pdata;
253 void __iomem *non_ehci = hcd->regs;
254
255 pdata = dev_get_platdata(hcd->self.controller);
256
257 if (pdata->have_sysif_regs) {
258 /*
259 * Turn on cache snooping hardware, since some PowerPC platforms
260 * wholly rely on hardware to deal with cache coherent
261 */
262
263 /* Setup Snooping for all the 4GB space */
264 /* SNOOP1 starts from 0x0, size 2G */
265 iowrite32be(0x0 | SNOOP_SIZE_2GB,
266 non_ehci + FSL_SOC_USB_SNOOP1);
267 /* SNOOP2 starts from 0x80000000, size 2G */
268 iowrite32be(0x80000000 | SNOOP_SIZE_2GB,
269 non_ehci + FSL_SOC_USB_SNOOP2);
270 }
271
272 /* Deal with USB erratum A-005275 */
273 if (pdata->has_fsl_erratum_a005275 == 1)
274 ehci->has_fsl_hs_errata = 1;
275
276 if (pdata->has_fsl_erratum_a005697 == 1)
277 ehci->has_fsl_susp_errata = 1;
278
279 if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
280 (pdata->operating_mode == FSL_USB2_DR_OTG))
281 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
282 return -EINVAL;
283
284 if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
285 unsigned int chip, rev, svr;
286
287 svr = mfspr(SPRN_SVR);
288 chip = svr >> 16;
289 rev = (svr >> 4) & 0xf;
290
291 /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
292 if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
293 ehci->has_fsl_port_bug = 1;
294
295 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
296 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
297 return -EINVAL;
298
299 if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
300 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1))
301 return -EINVAL;
302 }
303
304 if (pdata->have_sysif_regs) {
305 #ifdef CONFIG_FSL_SOC_BOOKE
306 iowrite32be(0x00000008, non_ehci + FSL_SOC_USB_PRICTRL);
307 iowrite32be(0x00000080, non_ehci + FSL_SOC_USB_AGECNTTHRSH);
308 #else
309 iowrite32be(0x0000000c, non_ehci + FSL_SOC_USB_PRICTRL);
310 iowrite32be(0x00000040, non_ehci + FSL_SOC_USB_AGECNTTHRSH);
311 #endif
312 iowrite32be(0x00000001, non_ehci + FSL_SOC_USB_SICTRL);
313 }
314
315 return 0;
316 }
317
318 /* called after powerup, by probe or system-pm "wakeup" */
319 static int ehci_fsl_reinit(struct ehci_hcd *ehci)
320 {
321 if (ehci_fsl_usb_setup(ehci))
322 return -EINVAL;
323
324 return 0;
325 }
326
327 /* called during probe() after chip reset completes */
328 static int ehci_fsl_setup(struct usb_hcd *hcd)
329 {
330 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
331 int retval;
332 struct fsl_usb2_platform_data *pdata;
333 struct device *dev;
334
335 dev = hcd->self.controller;
336 pdata = dev_get_platdata(hcd->self.controller);
337 ehci->big_endian_desc = pdata->big_endian_desc;
338 ehci->big_endian_mmio = pdata->big_endian_mmio;
339
340 /* EHCI registers start at offset 0x100 */
341 ehci->caps = hcd->regs + 0x100;
342
343 #ifdef CONFIG_PPC_83xx
344 /*
345 * Deal with MPC834X that need port power to be cycled after the power
346 * fault condition is removed. Otherwise the state machine does not
347 * reflect PORTSC[CSC] correctly.
348 */
349 ehci->need_oc_pp_cycle = 1;
350 #endif
351
352 hcd->has_tt = 1;
353
354 retval = ehci_setup(hcd);
355 if (retval)
356 return retval;
357
358 if (of_device_is_compatible(dev->parent->of_node,
359 "fsl,mpc5121-usb2-dr")) {
360 /*
361 * set SBUSCFG:AHBBRST so that control msgs don't
362 * fail when doing heavy PATA writes.
363 */
364 ehci_writel(ehci, SBUSCFG_INCR8,
365 hcd->regs + FSL_SOC_USB_SBUSCFG);
366 }
367
368 retval = ehci_fsl_reinit(ehci);
369 return retval;
370 }
371
372 struct ehci_fsl {
373 struct ehci_hcd ehci;
374
375 #ifdef CONFIG_PM
376 /* Saved USB PHY settings, need to restore after deep sleep. */
377 u32 usb_ctrl;
378 #endif
379 };
380
381 #ifdef CONFIG_PM
382
383 #ifdef CONFIG_PPC_MPC512x
384 static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
385 {
386 struct usb_hcd *hcd = dev_get_drvdata(dev);
387 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
388 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
389 u32 tmp;
390
391 #ifdef CONFIG_DYNAMIC_DEBUG
392 u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
393 mode &= USBMODE_CM_MASK;
394 tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */
395
396 dev_dbg(dev, "suspend=%d already_suspended=%d "
397 "mode=%d usbcmd %08x\n", pdata->suspended,
398 pdata->already_suspended, mode, tmp);
399 #endif
400
401 /*
402 * If the controller is already suspended, then this must be a
403 * PM suspend. Remember this fact, so that we will leave the
404 * controller suspended at PM resume time.
405 */
406 if (pdata->suspended) {
407 dev_dbg(dev, "already suspended, leaving early\n");
408 pdata->already_suspended = 1;
409 return 0;
410 }
411
412 dev_dbg(dev, "suspending...\n");
413
414 ehci->rh_state = EHCI_RH_SUSPENDED;
415 dev->power.power_state = PMSG_SUSPEND;
416
417 /* ignore non-host interrupts */
418 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
419
420 /* stop the controller */
421 tmp = ehci_readl(ehci, &ehci->regs->command);
422 tmp &= ~CMD_RUN;
423 ehci_writel(ehci, tmp, &ehci->regs->command);
424
425 /* save EHCI registers */
426 pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
427 pdata->pm_command &= ~CMD_RUN;
428 pdata->pm_status = ehci_readl(ehci, &ehci->regs->status);
429 pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable);
430 pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index);
431 pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment);
432 pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list);
433 pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next);
434 pdata->pm_configured_flag =
435 ehci_readl(ehci, &ehci->regs->configured_flag);
436 pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
437 pdata->pm_usbgenctrl = ehci_readl(ehci,
438 hcd->regs + FSL_SOC_USB_USBGENCTRL);
439
440 /* clear the W1C bits */
441 pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
442
443 pdata->suspended = 1;
444
445 /* clear PP to cut power to the port */
446 tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
447 tmp &= ~PORT_POWER;
448 ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
449
450 return 0;
451 }
452
453 static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
454 {
455 struct usb_hcd *hcd = dev_get_drvdata(dev);
456 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
457 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
458 u32 tmp;
459
460 dev_dbg(dev, "suspend=%d already_suspended=%d\n",
461 pdata->suspended, pdata->already_suspended);
462
463 /*
464 * If the controller was already suspended at suspend time,
465 * then don't resume it now.
466 */
467 if (pdata->already_suspended) {
468 dev_dbg(dev, "already suspended, leaving early\n");
469 pdata->already_suspended = 0;
470 return 0;
471 }
472
473 if (!pdata->suspended) {
474 dev_dbg(dev, "not suspended, leaving early\n");
475 return 0;
476 }
477
478 pdata->suspended = 0;
479
480 dev_dbg(dev, "resuming...\n");
481
482 /* set host mode */
483 tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
484 ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
485
486 ehci_writel(ehci, pdata->pm_usbgenctrl,
487 hcd->regs + FSL_SOC_USB_USBGENCTRL);
488 ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
489 hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
490
491 ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG);
492
493 /* restore EHCI registers */
494 ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
495 ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
496 ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
497 ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
498 ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
499 ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
500 ehci_writel(ehci, pdata->pm_configured_flag,
501 &ehci->regs->configured_flag);
502 ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
503
504 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
505 ehci->rh_state = EHCI_RH_RUNNING;
506 dev->power.power_state = PMSG_ON;
507
508 tmp = ehci_readl(ehci, &ehci->regs->command);
509 tmp |= CMD_RUN;
510 ehci_writel(ehci, tmp, &ehci->regs->command);
511
512 usb_hcd_resume_root_hub(hcd);
513
514 return 0;
515 }
516 #else
517 static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
518 {
519 return 0;
520 }
521
522 static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
523 {
524 return 0;
525 }
526 #endif /* CONFIG_PPC_MPC512x */
527
528 static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
529 {
530 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
531
532 return container_of(ehci, struct ehci_fsl, ehci);
533 }
534
535 static int ehci_fsl_drv_suspend(struct device *dev)
536 {
537 struct usb_hcd *hcd = dev_get_drvdata(dev);
538 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
539 void __iomem *non_ehci = hcd->regs;
540
541 if (of_device_is_compatible(dev->parent->of_node,
542 "fsl,mpc5121-usb2-dr")) {
543 return ehci_fsl_mpc512x_drv_suspend(dev);
544 }
545
546 ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
547 device_may_wakeup(dev));
548 if (!fsl_deep_sleep())
549 return 0;
550
551 ehci_fsl->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
552 return 0;
553 }
554
555 static int ehci_fsl_drv_resume(struct device *dev)
556 {
557 struct usb_hcd *hcd = dev_get_drvdata(dev);
558 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
559 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
560 void __iomem *non_ehci = hcd->regs;
561
562 if (of_device_is_compatible(dev->parent->of_node,
563 "fsl,mpc5121-usb2-dr")) {
564 return ehci_fsl_mpc512x_drv_resume(dev);
565 }
566
567 ehci_prepare_ports_for_controller_resume(ehci);
568 if (!fsl_deep_sleep())
569 return 0;
570
571 usb_root_hub_lost_power(hcd->self.root_hub);
572
573 /* Restore USB PHY settings and enable the controller. */
574 iowrite32be(ehci_fsl->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL);
575
576 ehci_reset(ehci);
577 ehci_fsl_reinit(ehci);
578
579 return 0;
580 }
581
582 static int ehci_fsl_drv_restore(struct device *dev)
583 {
584 struct usb_hcd *hcd = dev_get_drvdata(dev);
585
586 usb_root_hub_lost_power(hcd->self.root_hub);
587 return 0;
588 }
589
590 static const struct dev_pm_ops ehci_fsl_pm_ops = {
591 .suspend = ehci_fsl_drv_suspend,
592 .resume = ehci_fsl_drv_resume,
593 .restore = ehci_fsl_drv_restore,
594 };
595
596 #define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops)
597 #else
598 #define EHCI_FSL_PM_OPS NULL
599 #endif /* CONFIG_PM */
600
601 #ifdef CONFIG_USB_OTG
602 static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
603 {
604 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
605 u32 status;
606
607 if (!port)
608 return -EINVAL;
609
610 port--;
611
612 /* start port reset before HNP protocol time out */
613 status = readl(&ehci->regs->port_status[port]);
614 if (!(status & PORT_CONNECT))
615 return -ENODEV;
616
617 /* hub_wq will finish the reset later */
618 if (ehci_is_TDI(ehci)) {
619 writel(PORT_RESET |
620 (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)),
621 &ehci->regs->port_status[port]);
622 } else {
623 writel(PORT_RESET, &ehci->regs->port_status[port]);
624 }
625
626 return 0;
627 }
628 #else
629 #define ehci_start_port_reset NULL
630 #endif /* CONFIG_USB_OTG */
631
632 static const struct ehci_driver_overrides ehci_fsl_overrides __initconst = {
633 .extra_priv_size = sizeof(struct ehci_fsl),
634 .reset = ehci_fsl_setup,
635 };
636
637 /**
638 * fsl_ehci_drv_remove - shutdown processing for FSL-based HCDs
639 * @dev: USB Host Controller being removed
640 * Context: !in_interrupt()
641 *
642 * Reverses the effect of usb_hcd_fsl_probe().
643 *
644 */
645
646 static int fsl_ehci_drv_remove(struct platform_device *pdev)
647 {
648 struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
649 struct usb_hcd *hcd = platform_get_drvdata(pdev);
650
651 if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
652 otg_set_host(hcd->usb_phy->otg, NULL);
653 usb_put_phy(hcd->usb_phy);
654 }
655
656 usb_remove_hcd(hcd);
657
658 /*
659 * do platform specific un-initialization:
660 * release iomux pins, disable clock, etc.
661 */
662 if (pdata->exit)
663 pdata->exit(pdev);
664 usb_put_hcd(hcd);
665
666 return 0;
667 }
668
669 static struct platform_driver ehci_fsl_driver = {
670 .probe = fsl_ehci_drv_probe,
671 .remove = fsl_ehci_drv_remove,
672 .shutdown = usb_hcd_platform_shutdown,
673 .driver = {
674 .name = "fsl-ehci",
675 .pm = EHCI_FSL_PM_OPS,
676 },
677 };
678
679 static int __init ehci_fsl_init(void)
680 {
681 if (usb_disabled())
682 return -ENODEV;
683
684 pr_info(DRV_NAME ": " DRIVER_DESC "\n");
685
686 ehci_init_driver(&fsl_ehci_hc_driver, &ehci_fsl_overrides);
687
688 fsl_ehci_hc_driver.product_desc =
689 "Freescale On-Chip EHCI Host Controller";
690 fsl_ehci_hc_driver.start_port_reset = ehci_start_port_reset;
691
692
693 return platform_driver_register(&ehci_fsl_driver);
694 }
695 module_init(ehci_fsl_init);
696
697 static void __exit ehci_fsl_cleanup(void)
698 {
699 platform_driver_unregister(&ehci_fsl_driver);
700 }
701 module_exit(ehci_fsl_cleanup);
702
703 MODULE_DESCRIPTION(DRIVER_DESC);
704 MODULE_LICENSE("GPL");
705 MODULE_ALIAS("platform:" DRV_NAME);
CRIS linux kernel tree