drivers/usb/host/xhci-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver PCI Bus Glue.
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/acpi.h>
  15
  16 #include "xhci.h"
  17 #include "xhci-trace.h"
  18
  19 #define SSIC_PORT_NUM           2
  20 #define SSIC_PORT_CFG2          0x880c
  21 #define SSIC_PORT_CFG2_OFFSET   0x30
  22 #define PROG_DONE               (1 << 30)
  23 #define SSIC_PORT_UNUSED        (1 << 31)
  24
  25 /* Device for a quirk */
  26 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  27 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  28 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  29 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  30
  31 #define PCI_VENDOR_ID_ETRON             0x1b6f
  32 #define PCI_DEVICE_ID_EJ168             0x7023
  33
  34 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  35 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  36 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  37 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  38 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  39 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  40 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  41 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  42 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  43 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  44
  45 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  46 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  47 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  48 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  49 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  50
  51 static const char hcd_name[] = "xhci_hcd";
  52
  53 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  54
  55 static int xhci_pci_setup(struct usb_hcd *hcd);
  56
  57 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  58         .reset = xhci_pci_setup,
  59 };
  60
  61 /* called after powerup, by probe or system-pm "wakeup" */
  62 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  63 {
  64         /*
  65          * TODO: Implement finding debug ports later.
  66          * TODO: see if there are any quirks that need to be added to handle
  67          * new extended capabilities.
  68          */
  69
  70         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  71         if (!pci_set_mwi(pdev))
  72                 xhci_dbg(xhci, "MWI active\n");
  73
  74         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  75         return 0;
  76 }
  77
  78 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  79 {
  80         struct pci_dev          *pdev = to_pci_dev(dev);
  81
  82         /* Look for vendor-specific quirks */
  83         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  84                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
  85                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
  86                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  87                                 pdev->revision == 0x0) {
  88                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
  89                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  90                                 "QUIRK: Fresco Logic xHC needs configure"
  91                                 " endpoint cmd after reset endpoint");
  92                 }
  93                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  94                                 pdev->revision == 0x4) {
  95                         xhci->quirks |= XHCI_SLOW_SUSPEND;
  96                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  97                                 "QUIRK: Fresco Logic xHC revision %u"
  98                                 "must be suspended extra slowly",
  99                                 pdev->revision);
 100                 }
 101                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 102                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 103                 /* Fresco Logic confirms: all revisions of this chip do not
 104                  * support MSI, even though some of them claim to in their PCI
 105                  * capabilities.
 106                  */
 107                 xhci->quirks |= XHCI_BROKEN_MSI;
 108                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 109                                 "QUIRK: Fresco Logic revision %u "
 110                                 "has broken MSI implementation",
 111                                 pdev->revision);
 112                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 113         }
 114
 115         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 116                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 117                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 118
 119         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 120                 xhci->quirks |= XHCI_NEC_HOST;
 121
 122         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 123                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 124
 125         /* AMD PLL quirk */
 126         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
 127                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 128
 129         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 130                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 131
 132         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 133                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 134                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 135                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 136                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 137                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 138
 139         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 140                 xhci->quirks |= XHCI_LPM_SUPPORT;
 141                 xhci->quirks |= XHCI_INTEL_HOST;
 142                 xhci->quirks |= XHCI_AVOID_BEI;
 143         }
 144         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 145                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 146                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 147                 xhci->limit_active_eps = 64;
 148                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 149                 /*
 150                  * PPT desktop boards DH77EB and DH77DF will power back on after
 151                  * a few seconds of being shutdown.  The fix for this is to
 152                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 153                  * DMI information to find those particular boards (since each
 154                  * vendor will change the board name), so we have to key off all
 155                  * PPT chipsets.
 156                  */
 157                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 158         }
 159         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 160                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 161                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 162                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 163                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 164         }
 165         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 166                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 167                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 168                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 169                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 170                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 171                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 172                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
 173                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 174         }
 175         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 176                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
 177                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 178         }
 179         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 180             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 181              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 182              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 183                 xhci->quirks |= XHCI_MISSING_CAS;
 184
 185         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 186                         pdev->device == PCI_DEVICE_ID_EJ168) {
 187                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 188                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 189                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 190         }
 191         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 192                         pdev->device == 0x0014)
 193                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 194         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 195                         pdev->device == 0x0015)
 196                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 197         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 198                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 199
 200         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 201         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 202                         pdev->device == 0x3432)
 203                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 204
 205         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 206                         pdev->device == 0x1042)
 207                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 208         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 209                         pdev->device == 0x1142)
 210                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 211
 212         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 213                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 214                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 215
 216         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 217                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 218
 219         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 220                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 221                                 "QUIRK: Resetting on resume");
 222 }
 223
 224 #ifdef CONFIG_ACPI
 225 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 226 {
 227         static const guid_t intel_dsm_guid =
 228                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 229                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 230         union acpi_object *obj;
 231
 232         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 233                                 NULL);
 234         ACPI_FREE(obj);
 235 }
 236 #else
 237 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 238 #endif /* CONFIG_ACPI */
 239
 240 /* called during probe() after chip reset completes */
 241 static int xhci_pci_setup(struct usb_hcd *hcd)
 242 {
 243         struct xhci_hcd         *xhci;
 244         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 245         int                     retval;
 246
 247         xhci = hcd_to_xhci(hcd);
 248         if (!xhci->sbrn)
 249                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 250
 251         /* imod_interval is the interrupt moderation value in nanoseconds. */
 252         xhci->imod_interval = 40000;
 253
 254         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 255         if (retval)
 256                 return retval;
 257
 258         if (!usb_hcd_is_primary_hcd(hcd))
 259                 return 0;
 260
 261         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 262
 263         /* Find any debug ports */
 264         return xhci_pci_reinit(xhci, pdev);
 265 }
 266
 267 /*
 268  * We need to register our own PCI probe function (instead of the USB core's
 269  * function) in order to create a second roothub under xHCI.
 270  */
 271 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 272 {
 273         int retval;
 274         struct xhci_hcd *xhci;
 275         struct hc_driver *driver;
 276         struct usb_hcd *hcd;
 277
 278         driver = (struct hc_driver *)id->driver_data;
 279
 280         /* For some HW implementation, a XHCI reset is just not enough... */
 281         if (usb_xhci_needs_pci_reset(dev)) {
 282                 dev_info(&dev->dev, "Resetting\n");
 283                 if (pci_reset_function_locked(dev))
 284                         dev_warn(&dev->dev, "Reset failed");
 285         }
 286
 287         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 288         pm_runtime_get_noresume(&dev->dev);
 289
 290         /* Register the USB 2.0 roothub.
 291          * FIXME: USB core must know to register the USB 2.0 roothub first.
 292          * This is sort of silly, because we could just set the HCD driver flags
 293          * to say USB 2.0, but I'm not sure what the implications would be in
 294          * the other parts of the HCD code.
 295          */
 296         retval = usb_hcd_pci_probe(dev, id);
 297
 298         if (retval)
 299                 goto put_runtime_pm;
 300
 301         /* USB 2.0 roothub is stored in the PCI device now. */
 302         hcd = dev_get_drvdata(&dev->dev);
 303         xhci = hcd_to_xhci(hcd);
 304         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 305                                 pci_name(dev), hcd);
 306         if (!xhci->shared_hcd) {
 307                 retval = -ENOMEM;
 308                 goto dealloc_usb2_hcd;
 309         }
 310
 311         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 312                         IRQF_SHARED);
 313         if (retval)
 314                 goto put_usb3_hcd;
 315         /* Roothub already marked as USB 3.0 speed */
 316
 317         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 318                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 319                 xhci->shared_hcd->can_do_streams = 1;
 320
 321         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 322                 xhci_pme_acpi_rtd3_enable(dev);
 323
 324         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 325         pm_runtime_put_noidle(&dev->dev);
 326
 327         return 0;
 328
 329 put_usb3_hcd:
 330         usb_put_hcd(xhci->shared_hcd);
 331 dealloc_usb2_hcd:
 332         usb_hcd_pci_remove(dev);
 333 put_runtime_pm:
 334         pm_runtime_put_noidle(&dev->dev);
 335         return retval;
 336 }
 337
 338 static void xhci_pci_remove(struct pci_dev *dev)
 339 {
 340         struct xhci_hcd *xhci;
 341
 342         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 343         xhci->xhc_state |= XHCI_STATE_REMOVING;
 344         if (xhci->shared_hcd) {
 345                 usb_remove_hcd(xhci->shared_hcd);
 346                 usb_put_hcd(xhci->shared_hcd);
 347         }
 348
 349         /* Workaround for spurious wakeups at shutdown with HSW */
 350         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 351                 pci_set_power_state(dev, PCI_D3hot);
 352
 353         usb_hcd_pci_remove(dev);
 354 }
 355
 356 #ifdef CONFIG_PM
 357 /*
 358  * In some Intel xHCI controllers, in order to get D3 working,
 359  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 360  * SSIC PORT need to be marked as "unused" before putting xHCI
 361  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 362  * Without this change, xHCI might not enter D3 state.
 363  */
 364 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 365 {
 366         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 367         u32 val;
 368         void __iomem *reg;
 369         int i;
 370
 371         for (i = 0; i < SSIC_PORT_NUM; i++) {
 372                 reg = (void __iomem *) xhci->cap_regs +
 373                                 SSIC_PORT_CFG2 +
 374                                 i * SSIC_PORT_CFG2_OFFSET;
 375
 376                 /* Notify SSIC that SSIC profile programming is not done. */
 377                 val = readl(reg) & ~PROG_DONE;
 378                 writel(val, reg);
 379
 380                 /* Mark SSIC port as unused(suspend) or used(resume) */
 381                 val = readl(reg);
 382                 if (suspend)
 383                         val |= SSIC_PORT_UNUSED;
 384                 else
 385                         val &= ~SSIC_PORT_UNUSED;
 386                 writel(val, reg);
 387
 388                 /* Notify SSIC that SSIC profile programming is done */
 389                 val = readl(reg) | PROG_DONE;
 390                 writel(val, reg);
 391                 readl(reg);
 392         }
 393 }
 394
 395 /*
 396  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 397  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 398  */
 399 static void xhci_pme_quirk(struct usb_hcd *hcd)
 400 {
 401         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 402         void __iomem *reg;
 403         u32 val;
 404
 405         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 406         val = readl(reg);
 407         writel(val | BIT(28), reg);
 408         readl(reg);
 409 }
 410
 411 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 412 {
 413         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 414         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 415         int                     ret;
 416
 417         /*
 418          * Systems with the TI redriver that loses port status change events
 419          * need to have the registers polled during D3, so avoid D3cold.
 420          */
 421         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 422                 pci_d3cold_disable(pdev);
 423
 424         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 425                 xhci_pme_quirk(hcd);
 426
 427         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 428                 xhci_ssic_port_unused_quirk(hcd, true);
 429
 430         ret = xhci_suspend(xhci, do_wakeup);
 431         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 432                 xhci_ssic_port_unused_quirk(hcd, false);
 433
 434         return ret;
 435 }
 436
 437 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 438 {
 439         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 440         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 441         int                     retval = 0;
 442
 443         /* The BIOS on systems with the Intel Panther Point chipset may or may
 444          * not support xHCI natively.  That means that during system resume, it
 445          * may switch the ports back to EHCI so that users can use their
 446          * keyboard to select a kernel from GRUB after resume from hibernate.
 447          *
 448          * The BIOS is supposed to remember whether the OS had xHCI ports
 449          * enabled before resume, and switch the ports back to xHCI when the
 450          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 451          * writers.
 452          *
 453          * Unconditionally switch the ports back to xHCI after a system resume.
 454          * It should not matter whether the EHCI or xHCI controller is
 455          * resumed first. It's enough to do the switchover in xHCI because
 456          * USB core won't notice anything as the hub driver doesn't start
 457          * running again until after all the devices (including both EHCI and
 458          * xHCI host controllers) have been resumed.
 459          */
 460
 461         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 462                 usb_enable_intel_xhci_ports(pdev);
 463
 464         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 465                 xhci_ssic_port_unused_quirk(hcd, false);
 466
 467         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 468                 xhci_pme_quirk(hcd);
 469
 470         retval = xhci_resume(xhci, hibernated);
 471         return retval;
 472 }
 473 #endif /* CONFIG_PM */
 474
 475 /*-------------------------------------------------------------------------*/
 476
 477 /* PCI driver selection metadata; PCI hotplugging uses this */
 478 static const struct pci_device_id pci_ids[] = { {
 479         /* handle any USB 3.0 xHCI controller */
 480         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 481         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
 482         },
 483         { /* end: all zeroes */ }
 484 };
 485 MODULE_DEVICE_TABLE(pci, pci_ids);
 486
 487 /* pci driver glue; this is a "new style" PCI driver module */
 488 static struct pci_driver xhci_pci_driver = {
 489         .name =         (char *) hcd_name,
 490         .id_table =     pci_ids,
 491
 492         .probe =        xhci_pci_probe,
 493         .remove =       xhci_pci_remove,
 494         /* suspend and resume implemented later */
 495
 496         .shutdown =     usb_hcd_pci_shutdown,
 497 #ifdef CONFIG_PM
 498         .driver = {
 499                 .pm = &usb_hcd_pci_pm_ops
 500         },
 501 #endif
 502 };
 503
 504 static int __init xhci_pci_init(void)
 505 {
 506         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 507 #ifdef CONFIG_PM
 508         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 509         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 510 #endif
 511         return pci_register_driver(&xhci_pci_driver);
 512 }
 513 module_init(xhci_pci_init);
 514
 515 static void __exit xhci_pci_exit(void)
 516 {
 517         pci_unregister_driver(&xhci_pci_driver);
 518 }
 519 module_exit(xhci_pci_exit);
 520
 521 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 522 MODULE_LICENSE("GPL");