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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[cris-mirror.git] / drivers / usb / musb / musb_gadget.c
blob293e5b8da5651a7f7168cc69eb9ff0eadf7dd961
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MUSB OTG driver peripheral support
4 *
5 * Copyright 2005 Mentor Graphics Corporation
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
8 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/list.h>
13 #include <linux/timer.h>
14 #include <linux/module.h>
15 #include <linux/smp.h>
16 #include <linux/spinlock.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/slab.h>
20
21 #include "musb_core.h"
22 #include "musb_trace.h"
23
24
25 /* ----------------------------------------------------------------------- */
26
27 #define is_buffer_mapped(req) (is_dma_capable() && \
28 (req->map_state != UN_MAPPED))
29
30 /* Maps the buffer to dma */
31
32 static inline void map_dma_buffer(struct musb_request *request,
33 struct musb *musb, struct musb_ep *musb_ep)
34 {
35 int compatible = true;
36 struct dma_controller *dma = musb->dma_controller;
37
38 request->map_state = UN_MAPPED;
39
40 if (!is_dma_capable() || !musb_ep->dma)
41 return;
42
43 /* Check if DMA engine can handle this request.
44 * DMA code must reject the USB request explicitly.
45 * Default behaviour is to map the request.
46 */
47 if (dma->is_compatible)
48 compatible = dma->is_compatible(musb_ep->dma,
49 musb_ep->packet_sz, request->request.buf,
50 request->request.length);
51 if (!compatible)
52 return;
53
54 if (request->request.dma == DMA_ADDR_INVALID) {
55 dma_addr_t dma_addr;
56 int ret;
57
58 dma_addr = dma_map_single(
59 musb->controller,
60 request->request.buf,
61 request->request.length,
62 request->tx
63 ? DMA_TO_DEVICE
64 : DMA_FROM_DEVICE);
65 ret = dma_mapping_error(musb->controller, dma_addr);
66 if (ret)
67 return;
68
69 request->request.dma = dma_addr;
70 request->map_state = MUSB_MAPPED;
71 } else {
72 dma_sync_single_for_device(musb->controller,
73 request->request.dma,
74 request->request.length,
75 request->tx
76 ? DMA_TO_DEVICE
77 : DMA_FROM_DEVICE);
78 request->map_state = PRE_MAPPED;
79 }
80 }
81
82 /* Unmap the buffer from dma and maps it back to cpu */
83 static inline void unmap_dma_buffer(struct musb_request *request,
84 struct musb *musb)
85 {
86 struct musb_ep *musb_ep = request->ep;
87
88 if (!is_buffer_mapped(request) || !musb_ep->dma)
89 return;
90
91 if (request->request.dma == DMA_ADDR_INVALID) {
92 dev_vdbg(musb->controller,
93 "not unmapping a never mapped buffer\n");
94 return;
95 }
96 if (request->map_state == MUSB_MAPPED) {
97 dma_unmap_single(musb->controller,
98 request->request.dma,
99 request->request.length,
100 request->tx
101 ? DMA_TO_DEVICE
102 : DMA_FROM_DEVICE);
103 request->request.dma = DMA_ADDR_INVALID;
104 } else { /* PRE_MAPPED */
105 dma_sync_single_for_cpu(musb->controller,
106 request->request.dma,
107 request->request.length,
108 request->tx
109 ? DMA_TO_DEVICE
110 : DMA_FROM_DEVICE);
111 }
112 request->map_state = UN_MAPPED;
113 }
114
115 /*
116 * Immediately complete a request.
117 *
118 * @param request the request to complete
119 * @param status the status to complete the request with
120 * Context: controller locked, IRQs blocked.
121 */
122 void musb_g_giveback(
123 struct musb_ep *ep,
124 struct usb_request *request,
125 int status)
126 __releases(ep->musb->lock)
127 __acquires(ep->musb->lock)
128 {
129 struct musb_request *req;
130 struct musb *musb;
131 int busy = ep->busy;
132
133 req = to_musb_request(request);
134
135 list_del(&req->list);
136 if (req->request.status == -EINPROGRESS)
137 req->request.status = status;
138 musb = req->musb;
139
140 ep->busy = 1;
141 spin_unlock(&musb->lock);
142
143 if (!dma_mapping_error(&musb->g.dev, request->dma))
144 unmap_dma_buffer(req, musb);
145
146 trace_musb_req_gb(req);
147 usb_gadget_giveback_request(&req->ep->end_point, &req->request);
148 spin_lock(&musb->lock);
149 ep->busy = busy;
150 }
151
152 /* ----------------------------------------------------------------------- */
153
154 /*
155 * Abort requests queued to an endpoint using the status. Synchronous.
156 * caller locked controller and blocked irqs, and selected this ep.
157 */
158 static void nuke(struct musb_ep *ep, const int status)
159 {
160 struct musb *musb = ep->musb;
161 struct musb_request *req = NULL;
162 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
163
164 ep->busy = 1;
165
166 if (is_dma_capable() && ep->dma) {
167 struct dma_controller *c = ep->musb->dma_controller;
168 int value;
169
170 if (ep->is_in) {
171 /*
172 * The programming guide says that we must not clear
173 * the DMAMODE bit before DMAENAB, so we only
174 * clear it in the second write...
175 */
176 musb_writew(epio, MUSB_TXCSR,
177 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
178 musb_writew(epio, MUSB_TXCSR,
179 0 | MUSB_TXCSR_FLUSHFIFO);
180 } else {
181 musb_writew(epio, MUSB_RXCSR,
182 0 | MUSB_RXCSR_FLUSHFIFO);
183 musb_writew(epio, MUSB_RXCSR,
184 0 | MUSB_RXCSR_FLUSHFIFO);
185 }
186
187 value = c->channel_abort(ep->dma);
188 musb_dbg(musb, "%s: abort DMA --> %d", ep->name, value);
189 c->channel_release(ep->dma);
190 ep->dma = NULL;
191 }
192
193 while (!list_empty(&ep->req_list)) {
194 req = list_first_entry(&ep->req_list, struct musb_request, list);
195 musb_g_giveback(ep, &req->request, status);
196 }
197 }
198
199 /* ----------------------------------------------------------------------- */
200
201 /* Data transfers - pure PIO, pure DMA, or mixed mode */
202
203 /*
204 * This assumes the separate CPPI engine is responding to DMA requests
205 * from the usb core ... sequenced a bit differently from mentor dma.
206 */
207
208 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
209 {
210 if (can_bulk_split(musb, ep->type))
211 return ep->hw_ep->max_packet_sz_tx;
212 else
213 return ep->packet_sz;
214 }
215
216 /*
217 * An endpoint is transmitting data. This can be called either from
218 * the IRQ routine or from ep.queue() to kickstart a request on an
219 * endpoint.
220 *
221 * Context: controller locked, IRQs blocked, endpoint selected
222 */
223 static void txstate(struct musb *musb, struct musb_request *req)
224 {
225 u8 epnum = req->epnum;
226 struct musb_ep *musb_ep;
227 void __iomem *epio = musb->endpoints[epnum].regs;
228 struct usb_request *request;
229 u16 fifo_count = 0, csr;
230 int use_dma = 0;
231
232 musb_ep = req->ep;
233
234 /* Check if EP is disabled */
235 if (!musb_ep->desc) {
236 musb_dbg(musb, "ep:%s disabled - ignore request",
237 musb_ep->end_point.name);
238 return;
239 }
240
241 /* we shouldn't get here while DMA is active ... but we do ... */
242 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
243 musb_dbg(musb, "dma pending...");
244 return;
245 }
246
247 /* read TXCSR before */
248 csr = musb_readw(epio, MUSB_TXCSR);
249
250 request = &req->request;
251 fifo_count = min(max_ep_writesize(musb, musb_ep),
252 (int)(request->length - request->actual));
253
254 if (csr & MUSB_TXCSR_TXPKTRDY) {
255 musb_dbg(musb, "%s old packet still ready , txcsr %03x",
256 musb_ep->end_point.name, csr);
257 return;
258 }
259
260 if (csr & MUSB_TXCSR_P_SENDSTALL) {
261 musb_dbg(musb, "%s stalling, txcsr %03x",
262 musb_ep->end_point.name, csr);
263 return;
264 }
265
266 musb_dbg(musb, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x",
267 epnum, musb_ep->packet_sz, fifo_count,
268 csr);
269
270 #ifndef CONFIG_MUSB_PIO_ONLY
271 if (is_buffer_mapped(req)) {
272 struct dma_controller *c = musb->dma_controller;
273 size_t request_size;
274
275 /* setup DMA, then program endpoint CSR */
276 request_size = min_t(size_t, request->length - request->actual,
277 musb_ep->dma->max_len);
278
279 use_dma = (request->dma != DMA_ADDR_INVALID && request_size);
280
281 /* MUSB_TXCSR_P_ISO is still set correctly */
282
283 if (musb_dma_inventra(musb) || musb_dma_ux500(musb)) {
284 if (request_size < musb_ep->packet_sz)
285 musb_ep->dma->desired_mode = 0;
286 else
287 musb_ep->dma->desired_mode = 1;
288
289 use_dma = use_dma && c->channel_program(
290 musb_ep->dma, musb_ep->packet_sz,
291 musb_ep->dma->desired_mode,
292 request->dma + request->actual, request_size);
293 if (use_dma) {
294 if (musb_ep->dma->desired_mode == 0) {
295 /*
296 * We must not clear the DMAMODE bit
297 * before the DMAENAB bit -- and the
298 * latter doesn't always get cleared
299 * before we get here...
300 */
301 csr &= ~(MUSB_TXCSR_AUTOSET
302 | MUSB_TXCSR_DMAENAB);
303 musb_writew(epio, MUSB_TXCSR, csr
304 | MUSB_TXCSR_P_WZC_BITS);
305 csr &= ~MUSB_TXCSR_DMAMODE;
306 csr |= (MUSB_TXCSR_DMAENAB |
307 MUSB_TXCSR_MODE);
308 /* against programming guide */
309 } else {
310 csr |= (MUSB_TXCSR_DMAENAB
311 | MUSB_TXCSR_DMAMODE
312 | MUSB_TXCSR_MODE);
313 /*
314 * Enable Autoset according to table
315 * below
316 * bulk_split hb_mult Autoset_Enable
317 * 0 0 Yes(Normal)
318 * 0 >0 No(High BW ISO)
319 * 1 0 Yes(HS bulk)
320 * 1 >0 Yes(FS bulk)
321 */
322 if (!musb_ep->hb_mult ||
323 can_bulk_split(musb,
324 musb_ep->type))
325 csr |= MUSB_TXCSR_AUTOSET;
326 }
327 csr &= ~MUSB_TXCSR_P_UNDERRUN;
328
329 musb_writew(epio, MUSB_TXCSR, csr);
330 }
331 }
332
333 if (is_cppi_enabled(musb)) {
334 /* program endpoint CSR first, then setup DMA */
335 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
336 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
337 MUSB_TXCSR_MODE;
338 musb_writew(epio, MUSB_TXCSR, (MUSB_TXCSR_P_WZC_BITS &
339 ~MUSB_TXCSR_P_UNDERRUN) | csr);
340
341 /* ensure writebuffer is empty */
342 csr = musb_readw(epio, MUSB_TXCSR);
343
344 /*
345 * NOTE host side sets DMAENAB later than this; both are
346 * OK since the transfer dma glue (between CPPI and
347 * Mentor fifos) just tells CPPI it could start. Data
348 * only moves to the USB TX fifo when both fifos are
349 * ready.
350 */
351 /*
352 * "mode" is irrelevant here; handle terminating ZLPs
353 * like PIO does, since the hardware RNDIS mode seems
354 * unreliable except for the
355 * last-packet-is-already-short case.
356 */
357 use_dma = use_dma && c->channel_program(
358 musb_ep->dma, musb_ep->packet_sz,
359 0,
360 request->dma + request->actual,
361 request_size);
362 if (!use_dma) {
363 c->channel_release(musb_ep->dma);
364 musb_ep->dma = NULL;
365 csr &= ~MUSB_TXCSR_DMAENAB;
366 musb_writew(epio, MUSB_TXCSR, csr);
367 /* invariant: prequest->buf is non-null */
368 }
369 } else if (tusb_dma_omap(musb))
370 use_dma = use_dma && c->channel_program(
371 musb_ep->dma, musb_ep->packet_sz,
372 request->zero,
373 request->dma + request->actual,
374 request_size);
375 }
376 #endif
377
378 if (!use_dma) {
379 /*
380 * Unmap the dma buffer back to cpu if dma channel
381 * programming fails
382 */
383 unmap_dma_buffer(req, musb);
384
385 musb_write_fifo(musb_ep->hw_ep, fifo_count,
386 (u8 *) (request->buf + request->actual));
387 request->actual += fifo_count;
388 csr |= MUSB_TXCSR_TXPKTRDY;
389 csr &= ~MUSB_TXCSR_P_UNDERRUN;
390 musb_writew(epio, MUSB_TXCSR, csr);
391 }
392
393 /* host may already have the data when this message shows... */
394 musb_dbg(musb, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d",
395 musb_ep->end_point.name, use_dma ? "dma" : "pio",
396 request->actual, request->length,
397 musb_readw(epio, MUSB_TXCSR),
398 fifo_count,
399 musb_readw(epio, MUSB_TXMAXP));
400 }
401
402 /*
403 * FIFO state update (e.g. data ready).
404 * Called from IRQ, with controller locked.
405 */
406 void musb_g_tx(struct musb *musb, u8 epnum)
407 {
408 u16 csr;
409 struct musb_request *req;
410 struct usb_request *request;
411 u8 __iomem *mbase = musb->mregs;
412 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
413 void __iomem *epio = musb->endpoints[epnum].regs;
414 struct dma_channel *dma;
415
416 musb_ep_select(mbase, epnum);
417 req = next_request(musb_ep);
418 request = &req->request;
419
420 trace_musb_req_tx(req);
421 csr = musb_readw(epio, MUSB_TXCSR);
422 musb_dbg(musb, "<== %s, txcsr %04x", musb_ep->end_point.name, csr);
423
424 dma = is_dma_capable() ? musb_ep->dma : NULL;
425
426 /*
427 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
428 * probably rates reporting as a host error.
429 */
430 if (csr & MUSB_TXCSR_P_SENTSTALL) {
431 csr |= MUSB_TXCSR_P_WZC_BITS;
432 csr &= ~MUSB_TXCSR_P_SENTSTALL;
433 musb_writew(epio, MUSB_TXCSR, csr);
434 return;
435 }
436
437 if (csr & MUSB_TXCSR_P_UNDERRUN) {
438 /* We NAKed, no big deal... little reason to care. */
439 csr |= MUSB_TXCSR_P_WZC_BITS;
440 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
441 musb_writew(epio, MUSB_TXCSR, csr);
442 dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
443 epnum, request);
444 }
445
446 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
447 /*
448 * SHOULD NOT HAPPEN... has with CPPI though, after
449 * changing SENDSTALL (and other cases); harmless?
450 */
451 musb_dbg(musb, "%s dma still busy?", musb_ep->end_point.name);
452 return;
453 }
454
455 if (request) {
456 u8 is_dma = 0;
457 bool short_packet = false;
458
459 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
460 is_dma = 1;
461 csr |= MUSB_TXCSR_P_WZC_BITS;
462 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
463 MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET);
464 musb_writew(epio, MUSB_TXCSR, csr);
465 /* Ensure writebuffer is empty. */
466 csr = musb_readw(epio, MUSB_TXCSR);
467 request->actual += musb_ep->dma->actual_len;
468 musb_dbg(musb, "TXCSR%d %04x, DMA off, len %zu, req %p",
469 epnum, csr, musb_ep->dma->actual_len, request);
470 }
471
472 /*
473 * First, maybe a terminating short packet. Some DMA
474 * engines might handle this by themselves.
475 */
476 if ((request->zero && request->length)
477 && (request->length % musb_ep->packet_sz == 0)
478 && (request->actual == request->length))
479 short_packet = true;
480
481 if ((musb_dma_inventra(musb) || musb_dma_ux500(musb)) &&
482 (is_dma && (!dma->desired_mode ||
483 (request->actual &
484 (musb_ep->packet_sz - 1)))))
485 short_packet = true;
486
487 if (short_packet) {
488 /*
489 * On DMA completion, FIFO may not be
490 * available yet...
491 */
492 if (csr & MUSB_TXCSR_TXPKTRDY)
493 return;
494
495 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
496 | MUSB_TXCSR_TXPKTRDY);
497 request->zero = 0;
498 }
499
500 if (request->actual == request->length) {
501 musb_g_giveback(musb_ep, request, 0);
502 /*
503 * In the giveback function the MUSB lock is
504 * released and acquired after sometime. During
505 * this time period the INDEX register could get
506 * changed by the gadget_queue function especially
507 * on SMP systems. Reselect the INDEX to be sure
508 * we are reading/modifying the right registers
509 */
510 musb_ep_select(mbase, epnum);
511 req = musb_ep->desc ? next_request(musb_ep) : NULL;
512 if (!req) {
513 musb_dbg(musb, "%s idle now",
514 musb_ep->end_point.name);
515 return;
516 }
517 }
518
519 txstate(musb, req);
520 }
521 }
522
523 /* ------------------------------------------------------------ */
524
525 /*
526 * Context: controller locked, IRQs blocked, endpoint selected
527 */
528 static void rxstate(struct musb *musb, struct musb_request *req)
529 {
530 const u8 epnum = req->epnum;
531 struct usb_request *request = &req->request;
532 struct musb_ep *musb_ep;
533 void __iomem *epio = musb->endpoints[epnum].regs;
534 unsigned len = 0;
535 u16 fifo_count;
536 u16 csr = musb_readw(epio, MUSB_RXCSR);
537 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
538 u8 use_mode_1;
539
540 if (hw_ep->is_shared_fifo)
541 musb_ep = &hw_ep->ep_in;
542 else
543 musb_ep = &hw_ep->ep_out;
544
545 fifo_count = musb_ep->packet_sz;
546
547 /* Check if EP is disabled */
548 if (!musb_ep->desc) {
549 musb_dbg(musb, "ep:%s disabled - ignore request",
550 musb_ep->end_point.name);
551 return;
552 }
553
554 /* We shouldn't get here while DMA is active, but we do... */
555 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
556 musb_dbg(musb, "DMA pending...");
557 return;
558 }
559
560 if (csr & MUSB_RXCSR_P_SENDSTALL) {
561 musb_dbg(musb, "%s stalling, RXCSR %04x",
562 musb_ep->end_point.name, csr);
563 return;
564 }
565
566 if (is_cppi_enabled(musb) && is_buffer_mapped(req)) {
567 struct dma_controller *c = musb->dma_controller;
568 struct dma_channel *channel = musb_ep->dma;
569
570 /* NOTE: CPPI won't actually stop advancing the DMA
571 * queue after short packet transfers, so this is almost
572 * always going to run as IRQ-per-packet DMA so that
573 * faults will be handled correctly.
574 */
575 if (c->channel_program(channel,
576 musb_ep->packet_sz,
577 !request->short_not_ok,
578 request->dma + request->actual,
579 request->length - request->actual)) {
580
581 /* make sure that if an rxpkt arrived after the irq,
582 * the cppi engine will be ready to take it as soon
583 * as DMA is enabled
584 */
585 csr &= ~(MUSB_RXCSR_AUTOCLEAR
586 | MUSB_RXCSR_DMAMODE);
587 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
588 musb_writew(epio, MUSB_RXCSR, csr);
589 return;
590 }
591 }
592
593 if (csr & MUSB_RXCSR_RXPKTRDY) {
594 fifo_count = musb_readw(epio, MUSB_RXCOUNT);
595
596 /*
597 * Enable Mode 1 on RX transfers only when short_not_ok flag
598 * is set. Currently short_not_ok flag is set only from
599 * file_storage and f_mass_storage drivers
600 */
601
602 if (request->short_not_ok && fifo_count == musb_ep->packet_sz)
603 use_mode_1 = 1;
604 else
605 use_mode_1 = 0;
606
607 if (request->actual < request->length) {
608 if (!is_buffer_mapped(req))
609 goto buffer_aint_mapped;
610
611 if (musb_dma_inventra(musb)) {
612 struct dma_controller *c;
613 struct dma_channel *channel;
614 int use_dma = 0;
615 unsigned int transfer_size;
616
617 c = musb->dma_controller;
618 channel = musb_ep->dma;
619
620 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
621 * mode 0 only. So we do not get endpoint interrupts due to DMA
622 * completion. We only get interrupts from DMA controller.
623 *
624 * We could operate in DMA mode 1 if we knew the size of the tranfer
625 * in advance. For mass storage class, request->length = what the host
626 * sends, so that'd work. But for pretty much everything else,
627 * request->length is routinely more than what the host sends. For
628 * most these gadgets, end of is signified either by a short packet,
629 * or filling the last byte of the buffer. (Sending extra data in
630 * that last pckate should trigger an overflow fault.) But in mode 1,
631 * we don't get DMA completion interrupt for short packets.
632 *
633 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
634 * to get endpoint interrupt on every DMA req, but that didn't seem
635 * to work reliably.
636 *
637 * REVISIT an updated g_file_storage can set req->short_not_ok, which
638 * then becomes usable as a runtime "use mode 1" hint...
639 */
640
641 /* Experimental: Mode1 works with mass storage use cases */
642 if (use_mode_1) {
643 csr |= MUSB_RXCSR_AUTOCLEAR;
644 musb_writew(epio, MUSB_RXCSR, csr);
645 csr |= MUSB_RXCSR_DMAENAB;
646 musb_writew(epio, MUSB_RXCSR, csr);
647
648 /*
649 * this special sequence (enabling and then
650 * disabling MUSB_RXCSR_DMAMODE) is required
651 * to get DMAReq to activate
652 */
653 musb_writew(epio, MUSB_RXCSR,
654 csr | MUSB_RXCSR_DMAMODE);
655 musb_writew(epio, MUSB_RXCSR, csr);
656
657 transfer_size = min_t(unsigned int,
658 request->length -
659 request->actual,
660 channel->max_len);
661 musb_ep->dma->desired_mode = 1;
662 } else {
663 if (!musb_ep->hb_mult &&
664 musb_ep->hw_ep->rx_double_buffered)
665 csr |= MUSB_RXCSR_AUTOCLEAR;
666 csr |= MUSB_RXCSR_DMAENAB;
667 musb_writew(epio, MUSB_RXCSR, csr);
668
669 transfer_size = min(request->length - request->actual,
670 (unsigned)fifo_count);
671 musb_ep->dma->desired_mode = 0;
672 }
673
674 use_dma = c->channel_program(
675 channel,
676 musb_ep->packet_sz,
677 channel->desired_mode,
678 request->dma
679 + request->actual,
680 transfer_size);
681
682 if (use_dma)
683 return;
684 }
685
686 if ((musb_dma_ux500(musb)) &&
687 (request->actual < request->length)) {
688
689 struct dma_controller *c;
690 struct dma_channel *channel;
691 unsigned int transfer_size = 0;
692
693 c = musb->dma_controller;
694 channel = musb_ep->dma;
695
696 /* In case first packet is short */
697 if (fifo_count < musb_ep->packet_sz)
698 transfer_size = fifo_count;
699 else if (request->short_not_ok)
700 transfer_size = min_t(unsigned int,
701 request->length -
702 request->actual,
703 channel->max_len);
704 else
705 transfer_size = min_t(unsigned int,
706 request->length -
707 request->actual,
708 (unsigned)fifo_count);
709
710 csr &= ~MUSB_RXCSR_DMAMODE;
711 csr |= (MUSB_RXCSR_DMAENAB |
712 MUSB_RXCSR_AUTOCLEAR);
713
714 musb_writew(epio, MUSB_RXCSR, csr);
715
716 if (transfer_size <= musb_ep->packet_sz) {
717 musb_ep->dma->desired_mode = 0;
718 } else {
719 musb_ep->dma->desired_mode = 1;
720 /* Mode must be set after DMAENAB */
721 csr |= MUSB_RXCSR_DMAMODE;
722 musb_writew(epio, MUSB_RXCSR, csr);
723 }
724
725 if (c->channel_program(channel,
726 musb_ep->packet_sz,
727 channel->desired_mode,
728 request->dma
729 + request->actual,
730 transfer_size))
731
732 return;
733 }
734
735 len = request->length - request->actual;
736 musb_dbg(musb, "%s OUT/RX pio fifo %d/%d, maxpacket %d",
737 musb_ep->end_point.name,
738 fifo_count, len,
739 musb_ep->packet_sz);
740
741 fifo_count = min_t(unsigned, len, fifo_count);
742
743 if (tusb_dma_omap(musb)) {
744 struct dma_controller *c = musb->dma_controller;
745 struct dma_channel *channel = musb_ep->dma;
746 u32 dma_addr = request->dma + request->actual;
747 int ret;
748
749 ret = c->channel_program(channel,
750 musb_ep->packet_sz,
751 channel->desired_mode,
752 dma_addr,
753 fifo_count);
754 if (ret)
755 return;
756 }
757
758 /*
759 * Unmap the dma buffer back to cpu if dma channel
760 * programming fails. This buffer is mapped if the
761 * channel allocation is successful
762 */
763 unmap_dma_buffer(req, musb);
764
765 /*
766 * Clear DMAENAB and AUTOCLEAR for the
767 * PIO mode transfer
768 */
769 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
770 musb_writew(epio, MUSB_RXCSR, csr);
771
772 buffer_aint_mapped:
773 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
774 (request->buf + request->actual));
775 request->actual += fifo_count;
776
777 /* REVISIT if we left anything in the fifo, flush
778 * it and report -EOVERFLOW
779 */
780
781 /* ack the read! */
782 csr |= MUSB_RXCSR_P_WZC_BITS;
783 csr &= ~MUSB_RXCSR_RXPKTRDY;
784 musb_writew(epio, MUSB_RXCSR, csr);
785 }
786 }
787
788 /* reach the end or short packet detected */
789 if (request->actual == request->length ||
790 fifo_count < musb_ep->packet_sz)
791 musb_g_giveback(musb_ep, request, 0);
792 }
793
794 /*
795 * Data ready for a request; called from IRQ
796 */
797 void musb_g_rx(struct musb *musb, u8 epnum)
798 {
799 u16 csr;
800 struct musb_request *req;
801 struct usb_request *request;
802 void __iomem *mbase = musb->mregs;
803 struct musb_ep *musb_ep;
804 void __iomem *epio = musb->endpoints[epnum].regs;
805 struct dma_channel *dma;
806 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
807
808 if (hw_ep->is_shared_fifo)
809 musb_ep = &hw_ep->ep_in;
810 else
811 musb_ep = &hw_ep->ep_out;
812
813 musb_ep_select(mbase, epnum);
814
815 req = next_request(musb_ep);
816 if (!req)
817 return;
818
819 trace_musb_req_rx(req);
820 request = &req->request;
821
822 csr = musb_readw(epio, MUSB_RXCSR);
823 dma = is_dma_capable() ? musb_ep->dma : NULL;
824
825 musb_dbg(musb, "<== %s, rxcsr %04x%s %p", musb_ep->end_point.name,
826 csr, dma ? " (dma)" : "", request);
827
828 if (csr & MUSB_RXCSR_P_SENTSTALL) {
829 csr |= MUSB_RXCSR_P_WZC_BITS;
830 csr &= ~MUSB_RXCSR_P_SENTSTALL;
831 musb_writew(epio, MUSB_RXCSR, csr);
832 return;
833 }
834
835 if (csr & MUSB_RXCSR_P_OVERRUN) {
836 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
837 csr &= ~MUSB_RXCSR_P_OVERRUN;
838 musb_writew(epio, MUSB_RXCSR, csr);
839
840 musb_dbg(musb, "%s iso overrun on %p", musb_ep->name, request);
841 if (request->status == -EINPROGRESS)
842 request->status = -EOVERFLOW;
843 }
844 if (csr & MUSB_RXCSR_INCOMPRX) {
845 /* REVISIT not necessarily an error */
846 musb_dbg(musb, "%s, incomprx", musb_ep->end_point.name);
847 }
848
849 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
850 /* "should not happen"; likely RXPKTRDY pending for DMA */
851 musb_dbg(musb, "%s busy, csr %04x",
852 musb_ep->end_point.name, csr);
853 return;
854 }
855
856 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
857 csr &= ~(MUSB_RXCSR_AUTOCLEAR
858 | MUSB_RXCSR_DMAENAB
859 | MUSB_RXCSR_DMAMODE);
860 musb_writew(epio, MUSB_RXCSR,
861 MUSB_RXCSR_P_WZC_BITS | csr);
862
863 request->actual += musb_ep->dma->actual_len;
864
865 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
866 defined(CONFIG_USB_UX500_DMA)
867 /* Autoclear doesn't clear RxPktRdy for short packets */
868 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
869 || (dma->actual_len
870 & (musb_ep->packet_sz - 1))) {
871 /* ack the read! */
872 csr &= ~MUSB_RXCSR_RXPKTRDY;
873 musb_writew(epio, MUSB_RXCSR, csr);
874 }
875
876 /* incomplete, and not short? wait for next IN packet */
877 if ((request->actual < request->length)
878 && (musb_ep->dma->actual_len
879 == musb_ep->packet_sz)) {
880 /* In double buffer case, continue to unload fifo if
881 * there is Rx packet in FIFO.
882 **/
883 csr = musb_readw(epio, MUSB_RXCSR);
884 if ((csr & MUSB_RXCSR_RXPKTRDY) &&
885 hw_ep->rx_double_buffered)
886 goto exit;
887 return;
888 }
889 #endif
890 musb_g_giveback(musb_ep, request, 0);
891 /*
892 * In the giveback function the MUSB lock is
893 * released and acquired after sometime. During
894 * this time period the INDEX register could get
895 * changed by the gadget_queue function especially
896 * on SMP systems. Reselect the INDEX to be sure
897 * we are reading/modifying the right registers
898 */
899 musb_ep_select(mbase, epnum);
900
901 req = next_request(musb_ep);
902 if (!req)
903 return;
904 }
905 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
906 defined(CONFIG_USB_UX500_DMA)
907 exit:
908 #endif
909 /* Analyze request */
910 rxstate(musb, req);
911 }
912
913 /* ------------------------------------------------------------ */
914
915 static int musb_gadget_enable(struct usb_ep *ep,
916 const struct usb_endpoint_descriptor *desc)
917 {
918 unsigned long flags;
919 struct musb_ep *musb_ep;
920 struct musb_hw_ep *hw_ep;
921 void __iomem *regs;
922 struct musb *musb;
923 void __iomem *mbase;
924 u8 epnum;
925 u16 csr;
926 unsigned tmp;
927 int status = -EINVAL;
928
929 if (!ep || !desc)
930 return -EINVAL;
931
932 musb_ep = to_musb_ep(ep);
933 hw_ep = musb_ep->hw_ep;
934 regs = hw_ep->regs;
935 musb = musb_ep->musb;
936 mbase = musb->mregs;
937 epnum = musb_ep->current_epnum;
938
939 spin_lock_irqsave(&musb->lock, flags);
940
941 if (musb_ep->desc) {
942 status = -EBUSY;
943 goto fail;
944 }
945 musb_ep->type = usb_endpoint_type(desc);
946
947 /* check direction and (later) maxpacket size against endpoint */
948 if (usb_endpoint_num(desc) != epnum)
949 goto fail;
950
951 /* REVISIT this rules out high bandwidth periodic transfers */
952 tmp = usb_endpoint_maxp_mult(desc) - 1;
953 if (tmp) {
954 int ok;
955
956 if (usb_endpoint_dir_in(desc))
957 ok = musb->hb_iso_tx;
958 else
959 ok = musb->hb_iso_rx;
960
961 if (!ok) {
962 musb_dbg(musb, "no support for high bandwidth ISO");
963 goto fail;
964 }
965 musb_ep->hb_mult = tmp;
966 } else {
967 musb_ep->hb_mult = 0;
968 }
969
970 musb_ep->packet_sz = usb_endpoint_maxp(desc);
971 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
972
973 /* enable the interrupts for the endpoint, set the endpoint
974 * packet size (or fail), set the mode, clear the fifo
975 */
976 musb_ep_select(mbase, epnum);
977 if (usb_endpoint_dir_in(desc)) {
978
979 if (hw_ep->is_shared_fifo)
980 musb_ep->is_in = 1;
981 if (!musb_ep->is_in)
982 goto fail;
983
984 if (tmp > hw_ep->max_packet_sz_tx) {
985 musb_dbg(musb, "packet size beyond hardware FIFO size");
986 goto fail;
987 }
988
989 musb->intrtxe |= (1 << epnum);
990 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
991
992 /* REVISIT if can_bulk_split(), use by updating "tmp";
993 * likewise high bandwidth periodic tx
994 */
995 /* Set TXMAXP with the FIFO size of the endpoint
996 * to disable double buffering mode.
997 */
998 if (musb->double_buffer_not_ok) {
999 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
1000 } else {
1001 if (can_bulk_split(musb, musb_ep->type))
1002 musb_ep->hb_mult = (hw_ep->max_packet_sz_tx /
1003 musb_ep->packet_sz) - 1;
1004 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
1005 | (musb_ep->hb_mult << 11));
1006 }
1007
1008 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
1009 if (musb_readw(regs, MUSB_TXCSR)
1010 & MUSB_TXCSR_FIFONOTEMPTY)
1011 csr |= MUSB_TXCSR_FLUSHFIFO;
1012 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1013 csr |= MUSB_TXCSR_P_ISO;
1014
1015 /* set twice in case of double buffering */
1016 musb_writew(regs, MUSB_TXCSR, csr);
1017 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1018 musb_writew(regs, MUSB_TXCSR, csr);
1019
1020 } else {
1021
1022 if (hw_ep->is_shared_fifo)
1023 musb_ep->is_in = 0;
1024 if (musb_ep->is_in)
1025 goto fail;
1026
1027 if (tmp > hw_ep->max_packet_sz_rx) {
1028 musb_dbg(musb, "packet size beyond hardware FIFO size");
1029 goto fail;
1030 }
1031
1032 musb->intrrxe |= (1 << epnum);
1033 musb_writew(mbase, MUSB_INTRRXE, musb->intrrxe);
1034
1035 /* REVISIT if can_bulk_combine() use by updating "tmp"
1036 * likewise high bandwidth periodic rx
1037 */
1038 /* Set RXMAXP with the FIFO size of the endpoint
1039 * to disable double buffering mode.
1040 */
1041 if (musb->double_buffer_not_ok)
1042 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx);
1043 else
1044 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
1045 | (musb_ep->hb_mult << 11));
1046
1047 /* force shared fifo to OUT-only mode */
1048 if (hw_ep->is_shared_fifo) {
1049 csr = musb_readw(regs, MUSB_TXCSR);
1050 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
1051 musb_writew(regs, MUSB_TXCSR, csr);
1052 }
1053
1054 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
1055 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1056 csr |= MUSB_RXCSR_P_ISO;
1057 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
1058 csr |= MUSB_RXCSR_DISNYET;
1059
1060 /* set twice in case of double buffering */
1061 musb_writew(regs, MUSB_RXCSR, csr);
1062 musb_writew(regs, MUSB_RXCSR, csr);
1063 }
1064
1065 /* NOTE: all the I/O code _should_ work fine without DMA, in case
1066 * for some reason you run out of channels here.
1067 */
1068 if (is_dma_capable() && musb->dma_controller) {
1069 struct dma_controller *c = musb->dma_controller;
1070
1071 musb_ep->dma = c->channel_alloc(c, hw_ep,
1072 (desc->bEndpointAddress & USB_DIR_IN));
1073 } else
1074 musb_ep->dma = NULL;
1075
1076 musb_ep->desc = desc;
1077 musb_ep->busy = 0;
1078 musb_ep->wedged = 0;
1079 status = 0;
1080
1081 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1082 musb_driver_name, musb_ep->end_point.name,
1083 musb_ep_xfertype_string(musb_ep->type),
1084 musb_ep->is_in ? "IN" : "OUT",
1085 musb_ep->dma ? "dma, " : "",
1086 musb_ep->packet_sz);
1087
1088 schedule_delayed_work(&musb->irq_work, 0);
1089
1090 fail:
1091 spin_unlock_irqrestore(&musb->lock, flags);
1092 return status;
1093 }
1094
1095 /*
1096 * Disable an endpoint flushing all requests queued.
1097 */
1098 static int musb_gadget_disable(struct usb_ep *ep)
1099 {
1100 unsigned long flags;
1101 struct musb *musb;
1102 u8 epnum;
1103 struct musb_ep *musb_ep;
1104 void __iomem *epio;
1105 int status = 0;
1106
1107 musb_ep = to_musb_ep(ep);
1108 musb = musb_ep->musb;
1109 epnum = musb_ep->current_epnum;
1110 epio = musb->endpoints[epnum].regs;
1111
1112 spin_lock_irqsave(&musb->lock, flags);
1113 musb_ep_select(musb->mregs, epnum);
1114
1115 /* zero the endpoint sizes */
1116 if (musb_ep->is_in) {
1117 musb->intrtxe &= ~(1 << epnum);
1118 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
1119 musb_writew(epio, MUSB_TXMAXP, 0);
1120 } else {
1121 musb->intrrxe &= ~(1 << epnum);
1122 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
1123 musb_writew(epio, MUSB_RXMAXP, 0);
1124 }
1125
1126 /* abort all pending DMA and requests */
1127 nuke(musb_ep, -ESHUTDOWN);
1128
1129 musb_ep->desc = NULL;
1130 musb_ep->end_point.desc = NULL;
1131
1132 schedule_delayed_work(&musb->irq_work, 0);
1133
1134 spin_unlock_irqrestore(&(musb->lock), flags);
1135
1136 musb_dbg(musb, "%s", musb_ep->end_point.name);
1137
1138 return status;
1139 }
1140
1141 /*
1142 * Allocate a request for an endpoint.
1143 * Reused by ep0 code.
1144 */
1145 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1146 {
1147 struct musb_ep *musb_ep = to_musb_ep(ep);
1148 struct musb_request *request = NULL;
1149
1150 request = kzalloc(sizeof *request, gfp_flags);
1151 if (!request)
1152 return NULL;
1153
1154 request->request.dma = DMA_ADDR_INVALID;
1155 request->epnum = musb_ep->current_epnum;
1156 request->ep = musb_ep;
1157
1158 trace_musb_req_alloc(request);
1159 return &request->request;
1160 }
1161
1162 /*
1163 * Free a request
1164 * Reused by ep0 code.
1165 */
1166 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1167 {
1168 struct musb_request *request = to_musb_request(req);
1169
1170 trace_musb_req_free(request);
1171 kfree(request);
1172 }
1173
1174 static LIST_HEAD(buffers);
1175
1176 struct free_record {
1177 struct list_head list;
1178 struct device *dev;
1179 unsigned bytes;
1180 dma_addr_t dma;
1181 };
1182
1183 /*
1184 * Context: controller locked, IRQs blocked.
1185 */
1186 void musb_ep_restart(struct musb *musb, struct musb_request *req)
1187 {
1188 trace_musb_req_start(req);
1189 musb_ep_select(musb->mregs, req->epnum);
1190 if (req->tx)
1191 txstate(musb, req);
1192 else
1193 rxstate(musb, req);
1194 }
1195
1196 static int musb_ep_restart_resume_work(struct musb *musb, void *data)
1197 {
1198 struct musb_request *req = data;
1199
1200 musb_ep_restart(musb, req);
1201
1202 return 0;
1203 }
1204
1205 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1206 gfp_t gfp_flags)
1207 {
1208 struct musb_ep *musb_ep;
1209 struct musb_request *request;
1210 struct musb *musb;
1211 int status;
1212 unsigned long lockflags;
1213
1214 if (!ep || !req)
1215 return -EINVAL;
1216 if (!req->buf)
1217 return -ENODATA;
1218
1219 musb_ep = to_musb_ep(ep);
1220 musb = musb_ep->musb;
1221
1222 request = to_musb_request(req);
1223 request->musb = musb;
1224
1225 if (request->ep != musb_ep)
1226 return -EINVAL;
1227
1228 status = pm_runtime_get(musb->controller);
1229 if ((status != -EINPROGRESS) && status < 0) {
1230 dev_err(musb->controller,
1231 "pm runtime get failed in %s\n",
1232 __func__);
1233 pm_runtime_put_noidle(musb->controller);
1234
1235 return status;
1236 }
1237 status = 0;
1238
1239 trace_musb_req_enq(request);
1240
1241 /* request is mine now... */
1242 request->request.actual = 0;
1243 request->request.status = -EINPROGRESS;
1244 request->epnum = musb_ep->current_epnum;
1245 request->tx = musb_ep->is_in;
1246
1247 map_dma_buffer(request, musb, musb_ep);
1248
1249 spin_lock_irqsave(&musb->lock, lockflags);
1250
1251 /* don't queue if the ep is down */
1252 if (!musb_ep->desc) {
1253 musb_dbg(musb, "req %p queued to %s while ep %s",
1254 req, ep->name, "disabled");
1255 status = -ESHUTDOWN;
1256 unmap_dma_buffer(request, musb);
1257 goto unlock;
1258 }
1259
1260 /* add request to the list */
1261 list_add_tail(&request->list, &musb_ep->req_list);
1262
1263 /* it this is the head of the queue, start i/o ... */
1264 if (!musb_ep->busy && &request->list == musb_ep->req_list.next) {
1265 status = musb_queue_resume_work(musb,
1266 musb_ep_restart_resume_work,
1267 request);
1268 if (status < 0)
1269 dev_err(musb->controller, "%s resume work: %i\n",
1270 __func__, status);
1271 }
1272
1273 unlock:
1274 spin_unlock_irqrestore(&musb->lock, lockflags);
1275 pm_runtime_mark_last_busy(musb->controller);
1276 pm_runtime_put_autosuspend(musb->controller);
1277
1278 return status;
1279 }
1280
1281 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1282 {
1283 struct musb_ep *musb_ep = to_musb_ep(ep);
1284 struct musb_request *req = to_musb_request(request);
1285 struct musb_request *r;
1286 unsigned long flags;
1287 int status = 0;
1288 struct musb *musb = musb_ep->musb;
1289
1290 if (!ep || !request || req->ep != musb_ep)
1291 return -EINVAL;
1292
1293 trace_musb_req_deq(req);
1294
1295 spin_lock_irqsave(&musb->lock, flags);
1296
1297 list_for_each_entry(r, &musb_ep->req_list, list) {
1298 if (r == req)
1299 break;
1300 }
1301 if (r != req) {
1302 dev_err(musb->controller, "request %p not queued to %s\n",
1303 request, ep->name);
1304 status = -EINVAL;
1305 goto done;
1306 }
1307
1308 /* if the hardware doesn't have the request, easy ... */
1309 if (musb_ep->req_list.next != &req->list || musb_ep->busy)
1310 musb_g_giveback(musb_ep, request, -ECONNRESET);
1311
1312 /* ... else abort the dma transfer ... */
1313 else if (is_dma_capable() && musb_ep->dma) {
1314 struct dma_controller *c = musb->dma_controller;
1315
1316 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1317 if (c->channel_abort)
1318 status = c->channel_abort(musb_ep->dma);
1319 else
1320 status = -EBUSY;
1321 if (status == 0)
1322 musb_g_giveback(musb_ep, request, -ECONNRESET);
1323 } else {
1324 /* NOTE: by sticking to easily tested hardware/driver states,
1325 * we leave counting of in-flight packets imprecise.
1326 */
1327 musb_g_giveback(musb_ep, request, -ECONNRESET);
1328 }
1329
1330 done:
1331 spin_unlock_irqrestore(&musb->lock, flags);
1332 return status;
1333 }
1334
1335 /*
1336 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1337 * data but will queue requests.
1338 *
1339 * exported to ep0 code
1340 */
1341 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1342 {
1343 struct musb_ep *musb_ep = to_musb_ep(ep);
1344 u8 epnum = musb_ep->current_epnum;
1345 struct musb *musb = musb_ep->musb;
1346 void __iomem *epio = musb->endpoints[epnum].regs;
1347 void __iomem *mbase;
1348 unsigned long flags;
1349 u16 csr;
1350 struct musb_request *request;
1351 int status = 0;
1352
1353 if (!ep)
1354 return -EINVAL;
1355 mbase = musb->mregs;
1356
1357 spin_lock_irqsave(&musb->lock, flags);
1358
1359 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1360 status = -EINVAL;
1361 goto done;
1362 }
1363
1364 musb_ep_select(mbase, epnum);
1365
1366 request = next_request(musb_ep);
1367 if (value) {
1368 if (request) {
1369 musb_dbg(musb, "request in progress, cannot halt %s",
1370 ep->name);
1371 status = -EAGAIN;
1372 goto done;
1373 }
1374 /* Cannot portably stall with non-empty FIFO */
1375 if (musb_ep->is_in) {
1376 csr = musb_readw(epio, MUSB_TXCSR);
1377 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1378 musb_dbg(musb, "FIFO busy, cannot halt %s",
1379 ep->name);
1380 status = -EAGAIN;
1381 goto done;
1382 }
1383 }
1384 } else
1385 musb_ep->wedged = 0;
1386
1387 /* set/clear the stall and toggle bits */
1388 musb_dbg(musb, "%s: %s stall", ep->name, value ? "set" : "clear");
1389 if (musb_ep->is_in) {
1390 csr = musb_readw(epio, MUSB_TXCSR);
1391 csr |= MUSB_TXCSR_P_WZC_BITS
1392 | MUSB_TXCSR_CLRDATATOG;
1393 if (value)
1394 csr |= MUSB_TXCSR_P_SENDSTALL;
1395 else
1396 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1397 | MUSB_TXCSR_P_SENTSTALL);
1398 csr &= ~MUSB_TXCSR_TXPKTRDY;
1399 musb_writew(epio, MUSB_TXCSR, csr);
1400 } else {
1401 csr = musb_readw(epio, MUSB_RXCSR);
1402 csr |= MUSB_RXCSR_P_WZC_BITS
1403 | MUSB_RXCSR_FLUSHFIFO
1404 | MUSB_RXCSR_CLRDATATOG;
1405 if (value)
1406 csr |= MUSB_RXCSR_P_SENDSTALL;
1407 else
1408 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1409 | MUSB_RXCSR_P_SENTSTALL);
1410 musb_writew(epio, MUSB_RXCSR, csr);
1411 }
1412
1413 /* maybe start the first request in the queue */
1414 if (!musb_ep->busy && !value && request) {
1415 musb_dbg(musb, "restarting the request");
1416 musb_ep_restart(musb, request);
1417 }
1418
1419 done:
1420 spin_unlock_irqrestore(&musb->lock, flags);
1421 return status;
1422 }
1423
1424 /*
1425 * Sets the halt feature with the clear requests ignored
1426 */
1427 static int musb_gadget_set_wedge(struct usb_ep *ep)
1428 {
1429 struct musb_ep *musb_ep = to_musb_ep(ep);
1430
1431 if (!ep)
1432 return -EINVAL;
1433
1434 musb_ep->wedged = 1;
1435
1436 return usb_ep_set_halt(ep);
1437 }
1438
1439 static int musb_gadget_fifo_status(struct usb_ep *ep)
1440 {
1441 struct musb_ep *musb_ep = to_musb_ep(ep);
1442 void __iomem *epio = musb_ep->hw_ep->regs;
1443 int retval = -EINVAL;
1444
1445 if (musb_ep->desc && !musb_ep->is_in) {
1446 struct musb *musb = musb_ep->musb;
1447 int epnum = musb_ep->current_epnum;
1448 void __iomem *mbase = musb->mregs;
1449 unsigned long flags;
1450
1451 spin_lock_irqsave(&musb->lock, flags);
1452
1453 musb_ep_select(mbase, epnum);
1454 /* FIXME return zero unless RXPKTRDY is set */
1455 retval = musb_readw(epio, MUSB_RXCOUNT);
1456
1457 spin_unlock_irqrestore(&musb->lock, flags);
1458 }
1459 return retval;
1460 }
1461
1462 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1463 {
1464 struct musb_ep *musb_ep = to_musb_ep(ep);
1465 struct musb *musb = musb_ep->musb;
1466 u8 epnum = musb_ep->current_epnum;
1467 void __iomem *epio = musb->endpoints[epnum].regs;
1468 void __iomem *mbase;
1469 unsigned long flags;
1470 u16 csr;
1471
1472 mbase = musb->mregs;
1473
1474 spin_lock_irqsave(&musb->lock, flags);
1475 musb_ep_select(mbase, (u8) epnum);
1476
1477 /* disable interrupts */
1478 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe & ~(1 << epnum));
1479
1480 if (musb_ep->is_in) {
1481 csr = musb_readw(epio, MUSB_TXCSR);
1482 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1483 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1484 /*
1485 * Setting both TXPKTRDY and FLUSHFIFO makes controller
1486 * to interrupt current FIFO loading, but not flushing
1487 * the already loaded ones.
1488 */
1489 csr &= ~MUSB_TXCSR_TXPKTRDY;
1490 musb_writew(epio, MUSB_TXCSR, csr);
1491 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1492 musb_writew(epio, MUSB_TXCSR, csr);
1493 }
1494 } else {
1495 csr = musb_readw(epio, MUSB_RXCSR);
1496 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1497 musb_writew(epio, MUSB_RXCSR, csr);
1498 musb_writew(epio, MUSB_RXCSR, csr);
1499 }
1500
1501 /* re-enable interrupt */
1502 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
1503 spin_unlock_irqrestore(&musb->lock, flags);
1504 }
1505
1506 static const struct usb_ep_ops musb_ep_ops = {
1507 .enable = musb_gadget_enable,
1508 .disable = musb_gadget_disable,
1509 .alloc_request = musb_alloc_request,
1510 .free_request = musb_free_request,
1511 .queue = musb_gadget_queue,
1512 .dequeue = musb_gadget_dequeue,
1513 .set_halt = musb_gadget_set_halt,
1514 .set_wedge = musb_gadget_set_wedge,
1515 .fifo_status = musb_gadget_fifo_status,
1516 .fifo_flush = musb_gadget_fifo_flush
1517 };
1518
1519 /* ----------------------------------------------------------------------- */
1520
1521 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1522 {
1523 struct musb *musb = gadget_to_musb(gadget);
1524
1525 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1526 }
1527
1528 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1529 {
1530 struct musb *musb = gadget_to_musb(gadget);
1531 void __iomem *mregs = musb->mregs;
1532 unsigned long flags;
1533 int status = -EINVAL;
1534 u8 power, devctl;
1535 int retries;
1536
1537 spin_lock_irqsave(&musb->lock, flags);
1538
1539 switch (musb->xceiv->otg->state) {
1540 case OTG_STATE_B_PERIPHERAL:
1541 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1542 * that's part of the standard usb 1.1 state machine, and
1543 * doesn't affect OTG transitions.
1544 */
1545 if (musb->may_wakeup && musb->is_suspended)
1546 break;
1547 goto done;
1548 case OTG_STATE_B_IDLE:
1549 /* Start SRP ... OTG not required. */
1550 devctl = musb_readb(mregs, MUSB_DEVCTL);
1551 musb_dbg(musb, "Sending SRP: devctl: %02x", devctl);
1552 devctl |= MUSB_DEVCTL_SESSION;
1553 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1554 devctl = musb_readb(mregs, MUSB_DEVCTL);
1555 retries = 100;
1556 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1557 devctl = musb_readb(mregs, MUSB_DEVCTL);
1558 if (retries-- < 1)
1559 break;
1560 }
1561 retries = 10000;
1562 while (devctl & MUSB_DEVCTL_SESSION) {
1563 devctl = musb_readb(mregs, MUSB_DEVCTL);
1564 if (retries-- < 1)
1565 break;
1566 }
1567
1568 spin_unlock_irqrestore(&musb->lock, flags);
1569 otg_start_srp(musb->xceiv->otg);
1570 spin_lock_irqsave(&musb->lock, flags);
1571
1572 /* Block idling for at least 1s */
1573 musb_platform_try_idle(musb,
1574 jiffies + msecs_to_jiffies(1 * HZ));
1575
1576 status = 0;
1577 goto done;
1578 default:
1579 musb_dbg(musb, "Unhandled wake: %s",
1580 usb_otg_state_string(musb->xceiv->otg->state));
1581 goto done;
1582 }
1583
1584 status = 0;
1585
1586 power = musb_readb(mregs, MUSB_POWER);
1587 power |= MUSB_POWER_RESUME;
1588 musb_writeb(mregs, MUSB_POWER, power);
1589 musb_dbg(musb, "issue wakeup");
1590
1591 /* FIXME do this next chunk in a timer callback, no udelay */
1592 mdelay(2);
1593
1594 power = musb_readb(mregs, MUSB_POWER);
1595 power &= ~MUSB_POWER_RESUME;
1596 musb_writeb(mregs, MUSB_POWER, power);
1597 done:
1598 spin_unlock_irqrestore(&musb->lock, flags);
1599 return status;
1600 }
1601
1602 static int
1603 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1604 {
1605 gadget->is_selfpowered = !!is_selfpowered;
1606 return 0;
1607 }
1608
1609 static void musb_pullup(struct musb *musb, int is_on)
1610 {
1611 u8 power;
1612
1613 power = musb_readb(musb->mregs, MUSB_POWER);
1614 if (is_on)
1615 power |= MUSB_POWER_SOFTCONN;
1616 else
1617 power &= ~MUSB_POWER_SOFTCONN;
1618
1619 /* FIXME if on, HdrcStart; if off, HdrcStop */
1620
1621 musb_dbg(musb, "gadget D+ pullup %s",
1622 is_on ? "on" : "off");
1623 musb_writeb(musb->mregs, MUSB_POWER, power);
1624 }
1625
1626 #if 0
1627 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1628 {
1629 musb_dbg(musb, "<= %s =>\n", __func__);
1630
1631 /*
1632 * FIXME iff driver's softconnect flag is set (as it is during probe,
1633 * though that can clear it), just musb_pullup().
1634 */
1635
1636 return -EINVAL;
1637 }
1638 #endif
1639
1640 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1641 {
1642 struct musb *musb = gadget_to_musb(gadget);
1643
1644 if (!musb->xceiv->set_power)
1645 return -EOPNOTSUPP;
1646 return usb_phy_set_power(musb->xceiv, mA);
1647 }
1648
1649 static void musb_gadget_work(struct work_struct *work)
1650 {
1651 struct musb *musb;
1652 unsigned long flags;
1653
1654 musb = container_of(work, struct musb, gadget_work.work);
1655 pm_runtime_get_sync(musb->controller);
1656 spin_lock_irqsave(&musb->lock, flags);
1657 musb_pullup(musb, musb->softconnect);
1658 spin_unlock_irqrestore(&musb->lock, flags);
1659 pm_runtime_mark_last_busy(musb->controller);
1660 pm_runtime_put_autosuspend(musb->controller);
1661 }
1662
1663 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1664 {
1665 struct musb *musb = gadget_to_musb(gadget);
1666 unsigned long flags;
1667
1668 is_on = !!is_on;
1669
1670 /* NOTE: this assumes we are sensing vbus; we'd rather
1671 * not pullup unless the B-session is active.
1672 */
1673 spin_lock_irqsave(&musb->lock, flags);
1674 if (is_on != musb->softconnect) {
1675 musb->softconnect = is_on;
1676 schedule_delayed_work(&musb->gadget_work, 0);
1677 }
1678 spin_unlock_irqrestore(&musb->lock, flags);
1679
1680 return 0;
1681 }
1682
1683 #ifdef CONFIG_BLACKFIN
1684 static struct usb_ep *musb_match_ep(struct usb_gadget *g,
1685 struct usb_endpoint_descriptor *desc,
1686 struct usb_ss_ep_comp_descriptor *ep_comp)
1687 {
1688 struct usb_ep *ep = NULL;
1689
1690 switch (usb_endpoint_type(desc)) {
1691 case USB_ENDPOINT_XFER_ISOC:
1692 case USB_ENDPOINT_XFER_BULK:
1693 if (usb_endpoint_dir_in(desc))
1694 ep = gadget_find_ep_by_name(g, "ep5in");
1695 else
1696 ep = gadget_find_ep_by_name(g, "ep6out");
1697 break;
1698 case USB_ENDPOINT_XFER_INT:
1699 if (usb_endpoint_dir_in(desc))
1700 ep = gadget_find_ep_by_name(g, "ep1in");
1701 else
1702 ep = gadget_find_ep_by_name(g, "ep2out");
1703 break;
1704 default:
1705 break;
1706 }
1707
1708 if (ep && usb_gadget_ep_match_desc(g, ep, desc, ep_comp))
1709 return ep;
1710
1711 return NULL;
1712 }
1713 #else
1714 #define musb_match_ep NULL
1715 #endif
1716
1717 static int musb_gadget_start(struct usb_gadget *g,
1718 struct usb_gadget_driver *driver);
1719 static int musb_gadget_stop(struct usb_gadget *g);
1720
1721 static const struct usb_gadget_ops musb_gadget_operations = {
1722 .get_frame = musb_gadget_get_frame,
1723 .wakeup = musb_gadget_wakeup,
1724 .set_selfpowered = musb_gadget_set_self_powered,
1725 /* .vbus_session = musb_gadget_vbus_session, */
1726 .vbus_draw = musb_gadget_vbus_draw,
1727 .pullup = musb_gadget_pullup,
1728 .udc_start = musb_gadget_start,
1729 .udc_stop = musb_gadget_stop,
1730 .match_ep = musb_match_ep,
1731 };
1732
1733 /* ----------------------------------------------------------------------- */
1734
1735 /* Registration */
1736
1737 /* Only this registration code "knows" the rule (from USB standards)
1738 * about there being only one external upstream port. It assumes
1739 * all peripheral ports are external...
1740 */
1741
1742 static void
1743 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1744 {
1745 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1746
1747 memset(ep, 0, sizeof *ep);
1748
1749 ep->current_epnum = epnum;
1750 ep->musb = musb;
1751 ep->hw_ep = hw_ep;
1752 ep->is_in = is_in;
1753
1754 INIT_LIST_HEAD(&ep->req_list);
1755
1756 sprintf(ep->name, "ep%d%s", epnum,
1757 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1758 is_in ? "in" : "out"));
1759 ep->end_point.name = ep->name;
1760 INIT_LIST_HEAD(&ep->end_point.ep_list);
1761 if (!epnum) {
1762 usb_ep_set_maxpacket_limit(&ep->end_point, 64);
1763 ep->end_point.caps.type_control = true;
1764 ep->end_point.ops = &musb_g_ep0_ops;
1765 musb->g.ep0 = &ep->end_point;
1766 } else {
1767 if (is_in)
1768 usb_ep_set_maxpacket_limit(&ep->end_point, hw_ep->max_packet_sz_tx);
1769 else
1770 usb_ep_set_maxpacket_limit(&ep->end_point, hw_ep->max_packet_sz_rx);
1771 ep->end_point.caps.type_iso = true;
1772 ep->end_point.caps.type_bulk = true;
1773 ep->end_point.caps.type_int = true;
1774 ep->end_point.ops = &musb_ep_ops;
1775 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1776 }
1777
1778 if (!epnum || hw_ep->is_shared_fifo) {
1779 ep->end_point.caps.dir_in = true;
1780 ep->end_point.caps.dir_out = true;
1781 } else if (is_in)
1782 ep->end_point.caps.dir_in = true;
1783 else
1784 ep->end_point.caps.dir_out = true;
1785 }
1786
1787 /*
1788 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1789 * to the rest of the driver state.
1790 */
1791 static inline void musb_g_init_endpoints(struct musb *musb)
1792 {
1793 u8 epnum;
1794 struct musb_hw_ep *hw_ep;
1795 unsigned count = 0;
1796
1797 /* initialize endpoint list just once */
1798 INIT_LIST_HEAD(&(musb->g.ep_list));
1799
1800 for (epnum = 0, hw_ep = musb->endpoints;
1801 epnum < musb->nr_endpoints;
1802 epnum++, hw_ep++) {
1803 if (hw_ep->is_shared_fifo /* || !epnum */) {
1804 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1805 count++;
1806 } else {
1807 if (hw_ep->max_packet_sz_tx) {
1808 init_peripheral_ep(musb, &hw_ep->ep_in,
1809 epnum, 1);
1810 count++;
1811 }
1812 if (hw_ep->max_packet_sz_rx) {
1813 init_peripheral_ep(musb, &hw_ep->ep_out,
1814 epnum, 0);
1815 count++;
1816 }
1817 }
1818 }
1819 }
1820
1821 /* called once during driver setup to initialize and link into
1822 * the driver model; memory is zeroed.
1823 */
1824 int musb_gadget_setup(struct musb *musb)
1825 {
1826 int status;
1827
1828 /* REVISIT minor race: if (erroneously) setting up two
1829 * musb peripherals at the same time, only the bus lock
1830 * is probably held.
1831 */
1832
1833 musb->g.ops = &musb_gadget_operations;
1834 musb->g.max_speed = USB_SPEED_HIGH;
1835 musb->g.speed = USB_SPEED_UNKNOWN;
1836
1837 MUSB_DEV_MODE(musb);
1838 musb->xceiv->otg->default_a = 0;
1839 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
1840
1841 /* this "gadget" abstracts/virtualizes the controller */
1842 musb->g.name = musb_driver_name;
1843 #if IS_ENABLED(CONFIG_USB_MUSB_DUAL_ROLE)
1844 musb->g.is_otg = 1;
1845 #elif IS_ENABLED(CONFIG_USB_MUSB_GADGET)
1846 musb->g.is_otg = 0;
1847 #endif
1848 INIT_DELAYED_WORK(&musb->gadget_work, musb_gadget_work);
1849 musb_g_init_endpoints(musb);
1850
1851 musb->is_active = 0;
1852 musb_platform_try_idle(musb, 0);
1853
1854 status = usb_add_gadget_udc(musb->controller, &musb->g);
1855 if (status)
1856 goto err;
1857
1858 return 0;
1859 err:
1860 musb->g.dev.parent = NULL;
1861 device_unregister(&musb->g.dev);
1862 return status;
1863 }
1864
1865 void musb_gadget_cleanup(struct musb *musb)
1866 {
1867 if (musb->port_mode == MUSB_PORT_MODE_HOST)
1868 return;
1869
1870 cancel_delayed_work_sync(&musb->gadget_work);
1871 usb_del_gadget_udc(&musb->g);
1872 }
1873
1874 /*
1875 * Register the gadget driver. Used by gadget drivers when
1876 * registering themselves with the controller.
1877 *
1878 * -EINVAL something went wrong (not driver)
1879 * -EBUSY another gadget is already using the controller
1880 * -ENOMEM no memory to perform the operation
1881 *
1882 * @param driver the gadget driver
1883 * @return <0 if error, 0 if everything is fine
1884 */
1885 static int musb_gadget_start(struct usb_gadget *g,
1886 struct usb_gadget_driver *driver)
1887 {
1888 struct musb *musb = gadget_to_musb(g);
1889 struct usb_otg *otg = musb->xceiv->otg;
1890 unsigned long flags;
1891 int retval = 0;
1892
1893 if (driver->max_speed < USB_SPEED_HIGH) {
1894 retval = -EINVAL;
1895 goto err;
1896 }
1897
1898 pm_runtime_get_sync(musb->controller);
1899
1900 musb->softconnect = 0;
1901 musb->gadget_driver = driver;
1902
1903 spin_lock_irqsave(&musb->lock, flags);
1904 musb->is_active = 1;
1905
1906 otg_set_peripheral(otg, &musb->g);
1907 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
1908 spin_unlock_irqrestore(&musb->lock, flags);
1909
1910 musb_start(musb);
1911
1912 /* REVISIT: funcall to other code, which also
1913 * handles power budgeting ... this way also
1914 * ensures HdrcStart is indirectly called.
1915 */
1916 if (musb->xceiv->last_event == USB_EVENT_ID)
1917 musb_platform_set_vbus(musb, 1);
1918
1919 pm_runtime_mark_last_busy(musb->controller);
1920 pm_runtime_put_autosuspend(musb->controller);
1921
1922 return 0;
1923
1924 err:
1925 return retval;
1926 }
1927
1928 /*
1929 * Unregister the gadget driver. Used by gadget drivers when
1930 * unregistering themselves from the controller.
1931 *
1932 * @param driver the gadget driver to unregister
1933 */
1934 static int musb_gadget_stop(struct usb_gadget *g)
1935 {
1936 struct musb *musb = gadget_to_musb(g);
1937 unsigned long flags;
1938
1939 pm_runtime_get_sync(musb->controller);
1940
1941 /*
1942 * REVISIT always use otg_set_peripheral() here too;
1943 * this needs to shut down the OTG engine.
1944 */
1945
1946 spin_lock_irqsave(&musb->lock, flags);
1947
1948 musb_hnp_stop(musb);
1949
1950 (void) musb_gadget_vbus_draw(&musb->g, 0);
1951
1952 musb->xceiv->otg->state = OTG_STATE_UNDEFINED;
1953 musb_stop(musb);
1954 otg_set_peripheral(musb->xceiv->otg, NULL);
1955
1956 musb->is_active = 0;
1957 musb->gadget_driver = NULL;
1958 musb_platform_try_idle(musb, 0);
1959 spin_unlock_irqrestore(&musb->lock, flags);
1960
1961 /*
1962 * FIXME we need to be able to register another
1963 * gadget driver here and have everything work;
1964 * that currently misbehaves.
1965 */
1966
1967 /* Force check of devctl register for PM runtime */
1968 schedule_delayed_work(&musb->irq_work, 0);
1969
1970 pm_runtime_mark_last_busy(musb->controller);
1971 pm_runtime_put_autosuspend(musb->controller);
1972
1973 return 0;
1974 }
1975
1976 /* ----------------------------------------------------------------------- */
1977
1978 /* lifecycle operations called through plat_uds.c */
1979
1980 void musb_g_resume(struct musb *musb)
1981 {
1982 musb->is_suspended = 0;
1983 switch (musb->xceiv->otg->state) {
1984 case OTG_STATE_B_IDLE:
1985 break;
1986 case OTG_STATE_B_WAIT_ACON:
1987 case OTG_STATE_B_PERIPHERAL:
1988 musb->is_active = 1;
1989 if (musb->gadget_driver && musb->gadget_driver->resume) {
1990 spin_unlock(&musb->lock);
1991 musb->gadget_driver->resume(&musb->g);
1992 spin_lock(&musb->lock);
1993 }
1994 break;
1995 default:
1996 WARNING("unhandled RESUME transition (%s)\n",
1997 usb_otg_state_string(musb->xceiv->otg->state));
1998 }
1999 }
2000
2001 /* called when SOF packets stop for 3+ msec */
2002 void musb_g_suspend(struct musb *musb)
2003 {
2004 u8 devctl;
2005
2006 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2007 musb_dbg(musb, "musb_g_suspend: devctl %02x", devctl);
2008
2009 switch (musb->xceiv->otg->state) {
2010 case OTG_STATE_B_IDLE:
2011 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2012 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
2013 break;
2014 case OTG_STATE_B_PERIPHERAL:
2015 musb->is_suspended = 1;
2016 if (musb->gadget_driver && musb->gadget_driver->suspend) {
2017 spin_unlock(&musb->lock);
2018 musb->gadget_driver->suspend(&musb->g);
2019 spin_lock(&musb->lock);
2020 }
2021 break;
2022 default:
2023 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
2024 * A_PERIPHERAL may need care too
2025 */
2026 WARNING("unhandled SUSPEND transition (%s)",
2027 usb_otg_state_string(musb->xceiv->otg->state));
2028 }
2029 }
2030
2031 /* Called during SRP */
2032 void musb_g_wakeup(struct musb *musb)
2033 {
2034 musb_gadget_wakeup(&musb->g);
2035 }
2036
2037 /* called when VBUS drops below session threshold, and in other cases */
2038 void musb_g_disconnect(struct musb *musb)
2039 {
2040 void __iomem *mregs = musb->mregs;
2041 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
2042
2043 musb_dbg(musb, "musb_g_disconnect: devctl %02x", devctl);
2044
2045 /* clear HR */
2046 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
2047
2048 /* don't draw vbus until new b-default session */
2049 (void) musb_gadget_vbus_draw(&musb->g, 0);
2050
2051 musb->g.speed = USB_SPEED_UNKNOWN;
2052 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
2053 spin_unlock(&musb->lock);
2054 musb->gadget_driver->disconnect(&musb->g);
2055 spin_lock(&musb->lock);
2056 }
2057
2058 switch (musb->xceiv->otg->state) {
2059 default:
2060 musb_dbg(musb, "Unhandled disconnect %s, setting a_idle",
2061 usb_otg_state_string(musb->xceiv->otg->state));
2062 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2063 MUSB_HST_MODE(musb);
2064 break;
2065 case OTG_STATE_A_PERIPHERAL:
2066 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
2067 MUSB_HST_MODE(musb);
2068 break;
2069 case OTG_STATE_B_WAIT_ACON:
2070 case OTG_STATE_B_HOST:
2071 case OTG_STATE_B_PERIPHERAL:
2072 case OTG_STATE_B_IDLE:
2073 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2074 break;
2075 case OTG_STATE_B_SRP_INIT:
2076 break;
2077 }
2078
2079 musb->is_active = 0;
2080 }
2081
2082 void musb_g_reset(struct musb *musb)
2083 __releases(musb->lock)
2084 __acquires(musb->lock)
2085 {
2086 void __iomem *mbase = musb->mregs;
2087 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2088 u8 power;
2089
2090 musb_dbg(musb, "<== %s driver '%s'",
2091 (devctl & MUSB_DEVCTL_BDEVICE)
2092 ? "B-Device" : "A-Device",
2093 musb->gadget_driver
2094 ? musb->gadget_driver->driver.name
2095 : NULL
2096 );
2097
2098 /* report reset, if we didn't already (flushing EP state) */
2099 if (musb->gadget_driver && musb->g.speed != USB_SPEED_UNKNOWN) {
2100 spin_unlock(&musb->lock);
2101 usb_gadget_udc_reset(&musb->g, musb->gadget_driver);
2102 spin_lock(&musb->lock);
2103 }
2104
2105 /* clear HR */
2106 else if (devctl & MUSB_DEVCTL_HR)
2107 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2108
2109
2110 /* what speed did we negotiate? */
2111 power = musb_readb(mbase, MUSB_POWER);
2112 musb->g.speed = (power & MUSB_POWER_HSMODE)
2113 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2114
2115 /* start in USB_STATE_DEFAULT */
2116 musb->is_active = 1;
2117 musb->is_suspended = 0;
2118 MUSB_DEV_MODE(musb);
2119 musb->address = 0;
2120 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2121
2122 musb->may_wakeup = 0;
2123 musb->g.b_hnp_enable = 0;
2124 musb->g.a_alt_hnp_support = 0;
2125 musb->g.a_hnp_support = 0;
2126 musb->g.quirk_zlp_not_supp = 1;
2127
2128 /* Normal reset, as B-Device;
2129 * or else after HNP, as A-Device
2130 */
2131 if (!musb->g.is_otg) {
2132 /* USB device controllers that are not OTG compatible
2133 * may not have DEVCTL register in silicon.
2134 * In that case, do not rely on devctl for setting
2135 * peripheral mode.
2136 */
2137 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
2138 musb->g.is_a_peripheral = 0;
2139 } else if (devctl & MUSB_DEVCTL_BDEVICE) {
2140 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
2141 musb->g.is_a_peripheral = 0;
2142 } else {
2143 musb->xceiv->otg->state = OTG_STATE_A_PERIPHERAL;
2144 musb->g.is_a_peripheral = 1;
2145 }
2146
2147 /* start with default limits on VBUS power draw */
2148 (void) musb_gadget_vbus_draw(&musb->g, 8);
2149 }
CRIS linux kernel tree