sound/pci/rme9652/hdsp.c

   1 /*
   2  *   ALSA driver for RME Hammerfall DSP audio interface(s)
   3  *
   4  *      Copyright (c) 2002  Paul Davis
   5  *                          Marcus Andersson
   6  *                          Thomas Charbonnel
   7  *
   8  *   This program is free software; you can redistribute it and/or modify
   9  *   it under the terms of the GNU General Public License as published by
  10  *   the Free Software Foundation; either version 2 of the License, or
  11  *   (at your option) any later version.
  12  *
  13  *   This program is distributed in the hope that it will be useful,
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *   GNU General Public License for more details.
  17  *
  18  *   You should have received a copy of the GNU General Public License
  19  *   along with this program; if not, write to the Free Software
  20  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  21  *
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/delay.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/pci.h>
  28 #include <linux/firmware.h>
  29 #include <linux/module.h>
  30 #include <linux/math64.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/io.h>
  33
  34 #include <sound/core.h>
  35 #include <sound/control.h>
  36 #include <sound/pcm.h>
  37 #include <sound/info.h>
  38 #include <sound/asoundef.h>
  39 #include <sound/rawmidi.h>
  40 #include <sound/hwdep.h>
  41 #include <sound/initval.h>
  42 #include <sound/hdsp.h>
  43
  44 #include <asm/byteorder.h>
  45 #include <asm/current.h>
  46
  47 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  48 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  49 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable this card */
  50
  51 module_param_array(index, int, NULL, 0444);
  52 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
  53 module_param_array(id, charp, NULL, 0444);
  54 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
  55 module_param_array(enable, bool, NULL, 0444);
  56 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
  57 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
  58 MODULE_DESCRIPTION("RME Hammerfall DSP");
  59 MODULE_LICENSE("GPL");
  60 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
  61                 "{RME HDSP-9652},"
  62                 "{RME HDSP-9632}}");
  63 MODULE_FIRMWARE("rpm_firmware.bin");
  64 MODULE_FIRMWARE("multiface_firmware.bin");
  65 MODULE_FIRMWARE("multiface_firmware_rev11.bin");
  66 MODULE_FIRMWARE("digiface_firmware.bin");
  67 MODULE_FIRMWARE("digiface_firmware_rev11.bin");
  68
  69 #define HDSP_MAX_CHANNELS        26
  70 #define HDSP_MAX_DS_CHANNELS     14
  71 #define HDSP_MAX_QS_CHANNELS     8
  72 #define DIGIFACE_SS_CHANNELS     26
  73 #define DIGIFACE_DS_CHANNELS     14
  74 #define MULTIFACE_SS_CHANNELS    18
  75 #define MULTIFACE_DS_CHANNELS    14
  76 #define H9652_SS_CHANNELS        26
  77 #define H9652_DS_CHANNELS        14
  78 /* This does not include possible Analog Extension Boards
  79    AEBs are detected at card initialization
  80 */
  81 #define H9632_SS_CHANNELS        12
  82 #define H9632_DS_CHANNELS        8
  83 #define H9632_QS_CHANNELS        4
  84 #define RPM_CHANNELS             6
  85
  86 /* Write registers. These are defined as byte-offsets from the iobase value.
  87  */
  88 #define HDSP_resetPointer               0
  89 #define HDSP_freqReg                    0
  90 #define HDSP_outputBufferAddress        32
  91 #define HDSP_inputBufferAddress         36
  92 #define HDSP_controlRegister            64
  93 #define HDSP_interruptConfirmation      96
  94 #define HDSP_outputEnable               128
  95 #define HDSP_control2Reg                256
  96 #define HDSP_midiDataOut0               352
  97 #define HDSP_midiDataOut1               356
  98 #define HDSP_fifoData                   368
  99 #define HDSP_inputEnable                384
 100
 101 /* Read registers. These are defined as byte-offsets from the iobase value
 102  */
 103
 104 #define HDSP_statusRegister    0
 105 #define HDSP_timecode        128
 106 #define HDSP_status2Register 192
 107 #define HDSP_midiDataIn0     360
 108 #define HDSP_midiDataIn1     364
 109 #define HDSP_midiStatusOut0  384
 110 #define HDSP_midiStatusOut1  388
 111 #define HDSP_midiStatusIn0   392
 112 #define HDSP_midiStatusIn1   396
 113 #define HDSP_fifoStatus      400
 114
 115 /* the meters are regular i/o-mapped registers, but offset
 116    considerably from the rest. the peak registers are reset
 117    when read; the least-significant 4 bits are full-scale counters;
 118    the actual peak value is in the most-significant 24 bits.
 119 */
 120
 121 #define HDSP_playbackPeakLevel  4096  /* 26 * 32 bit values */
 122 #define HDSP_inputPeakLevel     4224  /* 26 * 32 bit values */
 123 #define HDSP_outputPeakLevel    4352  /* (26+2) * 32 bit values */
 124 #define HDSP_playbackRmsLevel   4612  /* 26 * 64 bit values */
 125 #define HDSP_inputRmsLevel      4868  /* 26 * 64 bit values */
 126
 127
 128 /* This is for H9652 cards
 129    Peak values are read downward from the base
 130    Rms values are read upward
 131    There are rms values for the outputs too
 132    26*3 values are read in ss mode
 133    14*3 in ds mode, with no gap between values
 134 */
 135 #define HDSP_9652_peakBase      7164
 136 #define HDSP_9652_rmsBase       4096
 137
 138 /* c.f. the hdsp_9632_meters_t struct */
 139 #define HDSP_9632_metersBase    4096
 140
 141 #define HDSP_IO_EXTENT     7168
 142
 143 /* control2 register bits */
 144
 145 #define HDSP_TMS                0x01
 146 #define HDSP_TCK                0x02
 147 #define HDSP_TDI                0x04
 148 #define HDSP_JTAG               0x08
 149 #define HDSP_PWDN               0x10
 150 #define HDSP_PROGRAM            0x020
 151 #define HDSP_CONFIG_MODE_0      0x040
 152 #define HDSP_CONFIG_MODE_1      0x080
 153 #define HDSP_VERSION_BIT        (0x100 | HDSP_S_LOAD)
 154 #define HDSP_BIGENDIAN_MODE     0x200
 155 #define HDSP_RD_MULTIPLE        0x400
 156 #define HDSP_9652_ENABLE_MIXER  0x800
 157 #define HDSP_S200               0x800
 158 #define HDSP_S300               (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
 159 #define HDSP_CYCLIC_MODE        0x1000
 160 #define HDSP_TDO                0x10000000
 161
 162 #define HDSP_S_PROGRAM      (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
 163 #define HDSP_S_LOAD         (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
 164
 165 /* Control Register bits */
 166
 167 #define HDSP_Start                (1<<0)  /* start engine */
 168 #define HDSP_Latency0             (1<<1)  /* buffer size = 2^n where n is defined by Latency{2,1,0} */
 169 #define HDSP_Latency1             (1<<2)  /* [ see above ] */
 170 #define HDSP_Latency2             (1<<3)  /* [ see above ] */
 171 #define HDSP_ClockModeMaster      (1<<4)  /* 1=Master, 0=Slave/Autosync */
 172 #define HDSP_AudioInterruptEnable (1<<5)  /* what do you think ? */
 173 #define HDSP_Frequency0           (1<<6)  /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
 174 #define HDSP_Frequency1           (1<<7)  /* 0=32kHz/64kHz/128kHz */
 175 #define HDSP_DoubleSpeed          (1<<8)  /* 0=normal speed, 1=double speed */
 176 #define HDSP_SPDIFProfessional    (1<<9)  /* 0=consumer, 1=professional */
 177 #define HDSP_SPDIFEmphasis        (1<<10) /* 0=none, 1=on */
 178 #define HDSP_SPDIFNonAudio        (1<<11) /* 0=off, 1=on */
 179 #define HDSP_SPDIFOpticalOut      (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
 180 #define HDSP_SyncRef2             (1<<13)
 181 #define HDSP_SPDIFInputSelect0    (1<<14)
 182 #define HDSP_SPDIFInputSelect1    (1<<15)
 183 #define HDSP_SyncRef0             (1<<16)
 184 #define HDSP_SyncRef1             (1<<17)
 185 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
 186 #define HDSP_XLRBreakoutCable     (1<<20) /* For H9632 cards */
 187 #define HDSP_Midi0InterruptEnable (1<<22)
 188 #define HDSP_Midi1InterruptEnable (1<<23)
 189 #define HDSP_LineOut              (1<<24)
 190 #define HDSP_ADGain0              (1<<25) /* From here : H9632 specific */
 191 #define HDSP_ADGain1              (1<<26)
 192 #define HDSP_DAGain0              (1<<27)
 193 #define HDSP_DAGain1              (1<<28)
 194 #define HDSP_PhoneGain0           (1<<29)
 195 #define HDSP_PhoneGain1           (1<<30)
 196 #define HDSP_QuadSpeed            (1<<31)
 197
 198 /* RPM uses some of the registers for special purposes */
 199 #define HDSP_RPM_Inp12            0x04A00
 200 #define HDSP_RPM_Inp12_Phon_6dB   0x00800  /* Dolby */
 201 #define HDSP_RPM_Inp12_Phon_0dB   0x00000  /* .. */
 202 #define HDSP_RPM_Inp12_Phon_n6dB  0x04000  /* inp_0 */
 203 #define HDSP_RPM_Inp12_Line_0dB   0x04200  /* Dolby+PRO */
 204 #define HDSP_RPM_Inp12_Line_n6dB  0x00200  /* PRO */
 205
 206 #define HDSP_RPM_Inp34            0x32000
 207 #define HDSP_RPM_Inp34_Phon_6dB   0x20000  /* SyncRef1 */
 208 #define HDSP_RPM_Inp34_Phon_0dB   0x00000  /* .. */
 209 #define HDSP_RPM_Inp34_Phon_n6dB  0x02000  /* SyncRef2 */
 210 #define HDSP_RPM_Inp34_Line_0dB   0x30000  /* SyncRef1+SyncRef0 */
 211 #define HDSP_RPM_Inp34_Line_n6dB  0x10000  /* SyncRef0 */
 212
 213 #define HDSP_RPM_Bypass           0x01000
 214
 215 #define HDSP_RPM_Disconnect       0x00001
 216
 217 #define HDSP_ADGainMask       (HDSP_ADGain0|HDSP_ADGain1)
 218 #define HDSP_ADGainMinus10dBV  HDSP_ADGainMask
 219 #define HDSP_ADGainPlus4dBu   (HDSP_ADGain0)
 220 #define HDSP_ADGainLowGain     0
 221
 222 #define HDSP_DAGainMask         (HDSP_DAGain0|HDSP_DAGain1)
 223 #define HDSP_DAGainHighGain      HDSP_DAGainMask
 224 #define HDSP_DAGainPlus4dBu     (HDSP_DAGain0)
 225 #define HDSP_DAGainMinus10dBV    0
 226
 227 #define HDSP_PhoneGainMask      (HDSP_PhoneGain0|HDSP_PhoneGain1)
 228 #define HDSP_PhoneGain0dB        HDSP_PhoneGainMask
 229 #define HDSP_PhoneGainMinus6dB  (HDSP_PhoneGain0)
 230 #define HDSP_PhoneGainMinus12dB  0
 231
 232 #define HDSP_LatencyMask    (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
 233 #define HDSP_FrequencyMask  (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
 234
 235 #define HDSP_SPDIFInputMask    (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 236 #define HDSP_SPDIFInputADAT1    0
 237 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
 238 #define HDSP_SPDIFInputCdrom   (HDSP_SPDIFInputSelect1)
 239 #define HDSP_SPDIFInputAES     (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 240
 241 #define HDSP_SyncRefMask        (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
 242 #define HDSP_SyncRef_ADAT1       0
 243 #define HDSP_SyncRef_ADAT2      (HDSP_SyncRef0)
 244 #define HDSP_SyncRef_ADAT3      (HDSP_SyncRef1)
 245 #define HDSP_SyncRef_SPDIF      (HDSP_SyncRef0|HDSP_SyncRef1)
 246 #define HDSP_SyncRef_WORD       (HDSP_SyncRef2)
 247 #define HDSP_SyncRef_ADAT_SYNC  (HDSP_SyncRef0|HDSP_SyncRef2)
 248
 249 /* Sample Clock Sources */
 250
 251 #define HDSP_CLOCK_SOURCE_AUTOSYNC           0
 252 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ     1
 253 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ   2
 254 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ     3
 255 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ     4
 256 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ   5
 257 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ     6
 258 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ    7
 259 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ  8
 260 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ    9
 261
 262 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
 263
 264 #define HDSP_SYNC_FROM_WORD      0
 265 #define HDSP_SYNC_FROM_SPDIF     1
 266 #define HDSP_SYNC_FROM_ADAT1     2
 267 #define HDSP_SYNC_FROM_ADAT_SYNC 3
 268 #define HDSP_SYNC_FROM_ADAT2     4
 269 #define HDSP_SYNC_FROM_ADAT3     5
 270
 271 /* SyncCheck status */
 272
 273 #define HDSP_SYNC_CHECK_NO_LOCK 0
 274 #define HDSP_SYNC_CHECK_LOCK    1
 275 #define HDSP_SYNC_CHECK_SYNC    2
 276
 277 /* AutoSync references - used by "autosync_ref" control switch */
 278
 279 #define HDSP_AUTOSYNC_FROM_WORD      0
 280 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
 281 #define HDSP_AUTOSYNC_FROM_SPDIF     2
 282 #define HDSP_AUTOSYNC_FROM_NONE      3
 283 #define HDSP_AUTOSYNC_FROM_ADAT1     4
 284 #define HDSP_AUTOSYNC_FROM_ADAT2     5
 285 #define HDSP_AUTOSYNC_FROM_ADAT3     6
 286
 287 /* Possible sources of S/PDIF input */
 288
 289 #define HDSP_SPDIFIN_OPTICAL  0 /* optical  (ADAT1) */
 290 #define HDSP_SPDIFIN_COAXIAL  1 /* coaxial (RCA) */
 291 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
 292 #define HDSP_SPDIFIN_AES      3 /* xlr for H9632 (AES)*/
 293
 294 #define HDSP_Frequency32KHz    HDSP_Frequency0
 295 #define HDSP_Frequency44_1KHz  HDSP_Frequency1
 296 #define HDSP_Frequency48KHz    (HDSP_Frequency1|HDSP_Frequency0)
 297 #define HDSP_Frequency64KHz    (HDSP_DoubleSpeed|HDSP_Frequency0)
 298 #define HDSP_Frequency88_2KHz  (HDSP_DoubleSpeed|HDSP_Frequency1)
 299 #define HDSP_Frequency96KHz    (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 300 /* For H9632 cards */
 301 #define HDSP_Frequency128KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
 302 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
 303 #define HDSP_Frequency192KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 304 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
 305         return 104857600000000 / rate; // 100 MHz
 306         return 110100480000000 / rate; // 105 MHz
 307 */
 308 #define DDS_NUMERATOR 104857600000000ULL;  /*  =  2^20 * 10^8 */
 309
 310 #define hdsp_encode_latency(x)       (((x)<<1) & HDSP_LatencyMask)
 311 #define hdsp_decode_latency(x)       (((x) & HDSP_LatencyMask)>>1)
 312
 313 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
 314 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
 315
 316 /* Status Register bits */
 317
 318 #define HDSP_audioIRQPending    (1<<0)
 319 #define HDSP_Lock2              (1<<1)     /* this is for Digiface and H9652 */
 320 #define HDSP_spdifFrequency3    HDSP_Lock2 /* this is for H9632 only */
 321 #define HDSP_Lock1              (1<<2)
 322 #define HDSP_Lock0              (1<<3)
 323 #define HDSP_SPDIFSync          (1<<4)
 324 #define HDSP_TimecodeLock       (1<<5)
 325 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
 326 #define HDSP_Sync2              (1<<16)
 327 #define HDSP_Sync1              (1<<17)
 328 #define HDSP_Sync0              (1<<18)
 329 #define HDSP_DoubleSpeedStatus  (1<<19)
 330 #define HDSP_ConfigError        (1<<20)
 331 #define HDSP_DllError           (1<<21)
 332 #define HDSP_spdifFrequency0    (1<<22)
 333 #define HDSP_spdifFrequency1    (1<<23)
 334 #define HDSP_spdifFrequency2    (1<<24)
 335 #define HDSP_SPDIFErrorFlag     (1<<25)
 336 #define HDSP_BufferID           (1<<26)
 337 #define HDSP_TimecodeSync       (1<<27)
 338 #define HDSP_AEBO               (1<<28) /* H9632 specific Analog Extension Boards */
 339 #define HDSP_AEBI               (1<<29) /* 0 = present, 1 = absent */
 340 #define HDSP_midi0IRQPending    (1<<30)
 341 #define HDSP_midi1IRQPending    (1<<31)
 342
 343 #define HDSP_spdifFrequencyMask    (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
 344 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
 345                                       HDSP_spdifFrequency1|\
 346                                       HDSP_spdifFrequency2|\
 347                                       HDSP_spdifFrequency3)
 348
 349 #define HDSP_spdifFrequency32KHz   (HDSP_spdifFrequency0)
 350 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
 351 #define HDSP_spdifFrequency48KHz   (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
 352
 353 #define HDSP_spdifFrequency64KHz   (HDSP_spdifFrequency2)
 354 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
 355 #define HDSP_spdifFrequency96KHz   (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
 356
 357 /* This is for H9632 cards */
 358 #define HDSP_spdifFrequency128KHz   (HDSP_spdifFrequency0|\
 359                                      HDSP_spdifFrequency1|\
 360                                      HDSP_spdifFrequency2)
 361 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
 362 #define HDSP_spdifFrequency192KHz   (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
 363
 364 /* Status2 Register bits */
 365
 366 #define HDSP_version0     (1<<0)
 367 #define HDSP_version1     (1<<1)
 368 #define HDSP_version2     (1<<2)
 369 #define HDSP_wc_lock      (1<<3)
 370 #define HDSP_wc_sync      (1<<4)
 371 #define HDSP_inp_freq0    (1<<5)
 372 #define HDSP_inp_freq1    (1<<6)
 373 #define HDSP_inp_freq2    (1<<7)
 374 #define HDSP_SelSyncRef0  (1<<8)
 375 #define HDSP_SelSyncRef1  (1<<9)
 376 #define HDSP_SelSyncRef2  (1<<10)
 377
 378 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
 379
 380 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
 381 #define HDSP_systemFrequency32   (HDSP_inp_freq0)
 382 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
 383 #define HDSP_systemFrequency48   (HDSP_inp_freq0|HDSP_inp_freq1)
 384 #define HDSP_systemFrequency64   (HDSP_inp_freq2)
 385 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
 386 #define HDSP_systemFrequency96   (HDSP_inp_freq1|HDSP_inp_freq2)
 387 /* FIXME : more values for 9632 cards ? */
 388
 389 #define HDSP_SelSyncRefMask        (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
 390 #define HDSP_SelSyncRef_ADAT1      0
 391 #define HDSP_SelSyncRef_ADAT2      (HDSP_SelSyncRef0)
 392 #define HDSP_SelSyncRef_ADAT3      (HDSP_SelSyncRef1)
 393 #define HDSP_SelSyncRef_SPDIF      (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
 394 #define HDSP_SelSyncRef_WORD       (HDSP_SelSyncRef2)
 395 #define HDSP_SelSyncRef_ADAT_SYNC  (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
 396
 397 /* Card state flags */
 398
 399 #define HDSP_InitializationComplete  (1<<0)
 400 #define HDSP_FirmwareLoaded          (1<<1)
 401 #define HDSP_FirmwareCached          (1<<2)
 402
 403 /* FIFO wait times, defined in terms of 1/10ths of msecs */
 404
 405 #define HDSP_LONG_WAIT   5000
 406 #define HDSP_SHORT_WAIT  30
 407
 408 #define UNITY_GAIN                       32768
 409 #define MINUS_INFINITY_GAIN              0
 410
 411 /* the size of a substream (1 mono data stream) */
 412
 413 #define HDSP_CHANNEL_BUFFER_SAMPLES  (16*1024)
 414 #define HDSP_CHANNEL_BUFFER_BYTES    (4*HDSP_CHANNEL_BUFFER_SAMPLES)
 415
 416 /* the size of the area we need to allocate for DMA transfers. the
 417    size is the same regardless of the number of channels - the
 418    Multiface still uses the same memory area.
 419
 420    Note that we allocate 1 more channel than is apparently needed
 421    because the h/w seems to write 1 byte beyond the end of the last
 422    page. Sigh.
 423 */
 424
 425 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
 426 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
 427
 428 #define HDSP_FIRMWARE_SIZE      (24413 * 4)
 429
 430 struct hdsp_9632_meters {
 431     u32 input_peak[16];
 432     u32 playback_peak[16];
 433     u32 output_peak[16];
 434     u32 xxx_peak[16];
 435     u32 padding[64];
 436     u32 input_rms_low[16];
 437     u32 playback_rms_low[16];
 438     u32 output_rms_low[16];
 439     u32 xxx_rms_low[16];
 440     u32 input_rms_high[16];
 441     u32 playback_rms_high[16];
 442     u32 output_rms_high[16];
 443     u32 xxx_rms_high[16];
 444 };
 445
 446 struct hdsp_midi {
 447     struct hdsp             *hdsp;
 448     int                      id;
 449     struct snd_rawmidi           *rmidi;
 450     struct snd_rawmidi_substream *input;
 451     struct snd_rawmidi_substream *output;
 452     char                     istimer; /* timer in use */
 453     struct timer_list        timer;
 454     spinlock_t               lock;
 455     int                      pending;
 456 };
 457
 458 struct hdsp {
 459         spinlock_t            lock;
 460         struct snd_pcm_substream *capture_substream;
 461         struct snd_pcm_substream *playback_substream;
 462         struct hdsp_midi      midi[2];
 463         struct tasklet_struct midi_tasklet;
 464         int                   use_midi_tasklet;
 465         int                   precise_ptr;
 466         u32                   control_register;      /* cached value */
 467         u32                   control2_register;     /* cached value */
 468         u32                   creg_spdif;
 469         u32                   creg_spdif_stream;
 470         int                   clock_source_locked;
 471         char                 *card_name;         /* digiface/multiface/rpm */
 472         enum HDSP_IO_Type     io_type;               /* ditto, but for code use */
 473         unsigned short        firmware_rev;
 474         unsigned short        state;                 /* stores state bits */
 475         const struct firmware *firmware;
 476         u32                  *fw_uploaded;
 477         size_t                period_bytes;          /* guess what this is */
 478         unsigned char         max_channels;
 479         unsigned char         qs_in_channels;        /* quad speed mode for H9632 */
 480         unsigned char         ds_in_channels;
 481         unsigned char         ss_in_channels;       /* different for multiface/digiface */
 482         unsigned char         qs_out_channels;
 483         unsigned char         ds_out_channels;
 484         unsigned char         ss_out_channels;
 485
 486         struct snd_dma_buffer capture_dma_buf;
 487         struct snd_dma_buffer playback_dma_buf;
 488         unsigned char        *capture_buffer;       /* suitably aligned address */
 489         unsigned char        *playback_buffer;      /* suitably aligned address */
 490
 491         pid_t                 capture_pid;
 492         pid_t                 playback_pid;
 493         int                   running;
 494         int                   system_sample_rate;
 495         char                 *channel_map;
 496         int                   dev;
 497         int                   irq;
 498         unsigned long         port;
 499         void __iomem         *iobase;
 500         struct snd_card *card;
 501         struct snd_pcm *pcm;
 502         struct snd_hwdep          *hwdep;
 503         struct pci_dev       *pci;
 504         struct snd_kcontrol *spdif_ctl;
 505         unsigned short        mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
 506         unsigned int          dds_value; /* last value written to freq register */
 507 };
 508
 509 /* These tables map the ALSA channels 1..N to the channels that we
 510    need to use in order to find the relevant channel buffer. RME
 511    refer to this kind of mapping as between "the ADAT channel and
 512    the DMA channel." We index it using the logical audio channel,
 513    and the value is the DMA channel (i.e. channel buffer number)
 514    where the data for that channel can be read/written from/to.
 515 */
 516
 517 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
 518         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
 519         18, 19, 20, 21, 22, 23, 24, 25
 520 };
 521
 522 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
 523         /* Analog */
 524         0, 1, 2, 3, 4, 5, 6, 7,
 525         /* ADAT 2 */
 526         16, 17, 18, 19, 20, 21, 22, 23,
 527         /* SPDIF */
 528         24, 25,
 529         -1, -1, -1, -1, -1, -1, -1, -1
 530 };
 531
 532 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
 533         /* ADAT channels are remapped */
 534         1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
 535         /* channels 12 and 13 are S/PDIF */
 536         24, 25,
 537         /* others don't exist */
 538         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 539 };
 540
 541 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
 542         /* ADAT channels */
 543         0, 1, 2, 3, 4, 5, 6, 7,
 544         /* SPDIF */
 545         8, 9,
 546         /* Analog */
 547         10, 11,
 548         /* AO4S-192 and AI4S-192 extension boards */
 549         12, 13, 14, 15,
 550         /* others don't exist */
 551         -1, -1, -1, -1, -1, -1, -1, -1,
 552         -1, -1
 553 };
 554
 555 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
 556         /* ADAT */
 557         1, 3, 5, 7,
 558         /* SPDIF */
 559         8, 9,
 560         /* Analog */
 561         10, 11,
 562         /* AO4S-192 and AI4S-192 extension boards */
 563         12, 13, 14, 15,
 564         /* others don't exist */
 565         -1, -1, -1, -1, -1, -1, -1, -1,
 566         -1, -1, -1, -1, -1, -1
 567 };
 568
 569 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
 570         /* ADAT is disabled in this mode */
 571         /* SPDIF */
 572         8, 9,
 573         /* Analog */
 574         10, 11,
 575         /* AO4S-192 and AI4S-192 extension boards */
 576         12, 13, 14, 15,
 577         /* others don't exist */
 578         -1, -1, -1, -1, -1, -1, -1, -1,
 579         -1, -1, -1, -1, -1, -1, -1, -1,
 580         -1, -1
 581 };
 582
 583 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
 584 {
 585         dmab->dev.type = SNDRV_DMA_TYPE_DEV;
 586         dmab->dev.dev = snd_dma_pci_data(pci);
 587         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
 588                                 size, dmab) < 0)
 589                 return -ENOMEM;
 590         return 0;
 591 }
 592
 593 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
 594 {
 595         if (dmab->area)
 596                 snd_dma_free_pages(dmab);
 597 }
 598
 599
 600 static const struct pci_device_id snd_hdsp_ids[] = {
 601         {
 602                 .vendor = PCI_VENDOR_ID_XILINX,
 603                 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
 604                 .subvendor = PCI_ANY_ID,
 605                 .subdevice = PCI_ANY_ID,
 606         }, /* RME Hammerfall-DSP */
 607         { 0, },
 608 };
 609
 610 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
 611
 612 /* prototypes */
 613 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
 614 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
 615 static int snd_hdsp_enable_io (struct hdsp *hdsp);
 616 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
 617 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
 618 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
 619 static int hdsp_autosync_ref(struct hdsp *hdsp);
 620 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
 621 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
 622
 623 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
 624 {
 625         switch (hdsp->io_type) {
 626         case Multiface:
 627         case Digiface:
 628         case RPM:
 629         default:
 630                 if (hdsp->firmware_rev == 0xa)
 631                         return (64 * out) + (32 + (in));
 632                 else
 633                         return (52 * out) + (26 + (in));
 634         case H9632:
 635                 return (32 * out) + (16 + (in));
 636         case H9652:
 637                 return (52 * out) + (26 + (in));
 638         }
 639 }
 640
 641 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
 642 {
 643         switch (hdsp->io_type) {
 644         case Multiface:
 645         case Digiface:
 646         case RPM:
 647         default:
 648                 if (hdsp->firmware_rev == 0xa)
 649                         return (64 * out) + in;
 650                 else
 651                         return (52 * out) + in;
 652         case H9632:
 653                 return (32 * out) + in;
 654         case H9652:
 655                 return (52 * out) + in;
 656         }
 657 }
 658
 659 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
 660 {
 661         writel(val, hdsp->iobase + reg);
 662 }
 663
 664 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
 665 {
 666         return readl (hdsp->iobase + reg);
 667 }
 668
 669 static int hdsp_check_for_iobox (struct hdsp *hdsp)
 670 {
 671         int i;
 672
 673         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
 674         for (i = 0; i < 500; i++) {
 675                 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
 676                                         HDSP_ConfigError)) {
 677                         if (i) {
 678                                 dev_dbg(hdsp->card->dev,
 679                                         "IO box found after %d ms\n",
 680                                                 (20 * i));
 681                         }
 682                         return 0;
 683                 }
 684                 msleep(20);
 685         }
 686         dev_err(hdsp->card->dev, "no IO box connected!\n");
 687         hdsp->state &= ~HDSP_FirmwareLoaded;
 688         return -EIO;
 689 }
 690
 691 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
 692                                unsigned int delay)
 693 {
 694         unsigned int i;
 695
 696         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
 697                 return 0;
 698
 699         for (i = 0; i != loops; ++i) {
 700                 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
 701                         msleep(delay);
 702                 else {
 703                         dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
 704                                    i * delay);
 705                         return 0;
 706                 }
 707         }
 708
 709         dev_info(hdsp->card->dev, "no IO box connected!\n");
 710         hdsp->state &= ~HDSP_FirmwareLoaded;
 711         return -EIO;
 712 }
 713
 714 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
 715
 716         int i;
 717         unsigned long flags;
 718         const u32 *cache;
 719
 720         if (hdsp->fw_uploaded)
 721                 cache = hdsp->fw_uploaded;
 722         else {
 723                 if (!hdsp->firmware)
 724                         return -ENODEV;
 725                 cache = (u32 *)hdsp->firmware->data;
 726                 if (!cache)
 727                         return -ENODEV;
 728         }
 729
 730         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 731
 732                 dev_info(hdsp->card->dev, "loading firmware\n");
 733
 734                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
 735                 hdsp_write (hdsp, HDSP_fifoData, 0);
 736
 737                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
 738                         dev_info(hdsp->card->dev,
 739                                  "timeout waiting for download preparation\n");
 740                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 741                         return -EIO;
 742                 }
 743
 744                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 745
 746                 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
 747                         hdsp_write(hdsp, HDSP_fifoData, cache[i]);
 748                         if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
 749                                 dev_info(hdsp->card->dev,
 750                                          "timeout during firmware loading\n");
 751                                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 752                                 return -EIO;
 753                         }
 754                 }
 755
 756                 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
 757                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 758
 759                 ssleep(3);
 760 #ifdef SNDRV_BIG_ENDIAN
 761                 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
 762 #else
 763                 hdsp->control2_register = 0;
 764 #endif
 765                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
 766                 dev_info(hdsp->card->dev, "finished firmware loading\n");
 767
 768         }
 769         if (hdsp->state & HDSP_InitializationComplete) {
 770                 dev_info(hdsp->card->dev,
 771                          "firmware loaded from cache, restoring defaults\n");
 772                 spin_lock_irqsave(&hdsp->lock, flags);
 773                 snd_hdsp_set_defaults(hdsp);
 774                 spin_unlock_irqrestore(&hdsp->lock, flags);
 775         }
 776
 777         hdsp->state |= HDSP_FirmwareLoaded;
 778
 779         return 0;
 780 }
 781
 782 static int hdsp_get_iobox_version (struct hdsp *hdsp)
 783 {
 784         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 785
 786                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 787                 hdsp_write(hdsp, HDSP_fifoData, 0);
 788
 789                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
 790                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 791                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 792                 }
 793
 794                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
 795                 hdsp_write (hdsp, HDSP_fifoData, 0);
 796                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
 797                         goto set_multi;
 798
 799                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 800                 hdsp_write(hdsp, HDSP_fifoData, 0);
 801                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
 802                         hdsp->io_type = Digiface;
 803                         dev_info(hdsp->card->dev, "Digiface found\n");
 804                         return 0;
 805                 }
 806
 807                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 808                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 809                 hdsp_write(hdsp, HDSP_fifoData, 0);
 810                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0)
 811                         goto set_multi;
 812
 813                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 814                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 815                 hdsp_write(hdsp, HDSP_fifoData, 0);
 816                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
 817                         goto set_multi;
 818
 819                 hdsp->io_type = RPM;
 820                 dev_info(hdsp->card->dev, "RPM found\n");
 821                 return 0;
 822         } else {
 823                 /* firmware was already loaded, get iobox type */
 824                 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
 825                         hdsp->io_type = RPM;
 826                 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
 827                         hdsp->io_type = Multiface;
 828                 else
 829                         hdsp->io_type = Digiface;
 830         }
 831         return 0;
 832
 833 set_multi:
 834         hdsp->io_type = Multiface;
 835         dev_info(hdsp->card->dev, "Multiface found\n");
 836         return 0;
 837 }
 838
 839
 840 static int hdsp_request_fw_loader(struct hdsp *hdsp);
 841
 842 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
 843 {
 844         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
 845                 return 0;
 846         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 847                 hdsp->state &= ~HDSP_FirmwareLoaded;
 848                 if (! load_on_demand)
 849                         return -EIO;
 850                 dev_err(hdsp->card->dev, "firmware not present.\n");
 851                 /* try to load firmware */
 852                 if (! (hdsp->state & HDSP_FirmwareCached)) {
 853                         if (! hdsp_request_fw_loader(hdsp))
 854                                 return 0;
 855                         dev_err(hdsp->card->dev,
 856                                    "No firmware loaded nor cached, please upload firmware.\n");
 857                         return -EIO;
 858                 }
 859                 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
 860                         dev_err(hdsp->card->dev,
 861                                    "Firmware loading from cache failed, please upload manually.\n");
 862                         return -EIO;
 863                 }
 864         }
 865         return 0;
 866 }
 867
 868
 869 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
 870 {
 871         int i;
 872
 873         /* the fifoStatus registers reports on how many words
 874            are available in the command FIFO.
 875         */
 876
 877         for (i = 0; i < timeout; i++) {
 878
 879                 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
 880                         return 0;
 881
 882                 /* not very friendly, but we only do this during a firmware
 883                    load and changing the mixer, so we just put up with it.
 884                 */
 885
 886                 udelay (100);
 887         }
 888
 889         dev_warn(hdsp->card->dev,
 890                  "wait for FIFO status <= %d failed after %d iterations\n",
 891                     count, timeout);
 892         return -1;
 893 }
 894
 895 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
 896 {
 897         if (addr >= HDSP_MATRIX_MIXER_SIZE)
 898                 return 0;
 899
 900         return hdsp->mixer_matrix[addr];
 901 }
 902
 903 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
 904 {
 905         unsigned int ad;
 906
 907         if (addr >= HDSP_MATRIX_MIXER_SIZE)
 908                 return -1;
 909
 910         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
 911
 912                 /* from martin bjornsen:
 913
 914                    "You can only write dwords to the
 915                    mixer memory which contain two
 916                    mixer values in the low and high
 917                    word. So if you want to change
 918                    value 0 you have to read value 1
 919                    from the cache and write both to
 920                    the first dword in the mixer
 921                    memory."
 922                 */
 923
 924                 if (hdsp->io_type == H9632 && addr >= 512)
 925                         return 0;
 926
 927                 if (hdsp->io_type == H9652 && addr >= 1352)
 928                         return 0;
 929
 930                 hdsp->mixer_matrix[addr] = data;
 931
 932
 933                 /* `addr' addresses a 16-bit wide address, but
 934                    the address space accessed via hdsp_write
 935                    uses byte offsets. put another way, addr
 936                    varies from 0 to 1351, but to access the
 937                    corresponding memory location, we need
 938                    to access 0 to 2703 ...
 939                 */
 940                 ad = addr/2;
 941
 942                 hdsp_write (hdsp, 4096 + (ad*4),
 943                             (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
 944                             hdsp->mixer_matrix[addr&0x7fe]);
 945
 946                 return 0;
 947
 948         } else {
 949
 950                 ad = (addr << 16) + data;
 951
 952                 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
 953                         return -1;
 954
 955                 hdsp_write (hdsp, HDSP_fifoData, ad);
 956                 hdsp->mixer_matrix[addr] = data;
 957
 958         }
 959
 960         return 0;
 961 }
 962
 963 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
 964 {
 965         unsigned long flags;
 966         int ret = 1;
 967
 968         spin_lock_irqsave(&hdsp->lock, flags);
 969         if ((hdsp->playback_pid != hdsp->capture_pid) &&
 970             (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
 971                 ret = 0;
 972         spin_unlock_irqrestore(&hdsp->lock, flags);
 973         return ret;
 974 }
 975
 976 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
 977 {
 978         unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
 979         unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
 980
 981         /* For the 9632, the mask is different */
 982         if (hdsp->io_type == H9632)
 983                  rate_bits = (status & HDSP_spdifFrequencyMask_9632);
 984
 985         if (status & HDSP_SPDIFErrorFlag)
 986                 return 0;
 987
 988         switch (rate_bits) {
 989         case HDSP_spdifFrequency32KHz: return 32000;
 990         case HDSP_spdifFrequency44_1KHz: return 44100;
 991         case HDSP_spdifFrequency48KHz: return 48000;
 992         case HDSP_spdifFrequency64KHz: return 64000;
 993         case HDSP_spdifFrequency88_2KHz: return 88200;
 994         case HDSP_spdifFrequency96KHz: return 96000;
 995         case HDSP_spdifFrequency128KHz:
 996                 if (hdsp->io_type == H9632) return 128000;
 997                 break;
 998         case HDSP_spdifFrequency176_4KHz:
 999                 if (hdsp->io_type == H9632) return 176400;
1000                 break;
1001         case HDSP_spdifFrequency192KHz:
1002                 if (hdsp->io_type == H9632) return 192000;
1003                 break;
1004         default:
1005                 break;
1006         }
1007         dev_warn(hdsp->card->dev,
1008                  "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
1009                  rate_bits, status);
1010         return 0;
1011 }
1012
1013 static int hdsp_external_sample_rate(struct hdsp *hdsp)
1014 {
1015         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
1016         unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
1017
1018         /* For the 9632 card, there seems to be no bit for indicating external
1019          * sample rate greater than 96kHz. The card reports the corresponding
1020          * single speed. So the best means seems to get spdif rate when
1021          * autosync reference is spdif */
1022         if (hdsp->io_type == H9632 &&
1023             hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1024                  return hdsp_spdif_sample_rate(hdsp);
1025
1026         switch (rate_bits) {
1027         case HDSP_systemFrequency32:   return 32000;
1028         case HDSP_systemFrequency44_1: return 44100;
1029         case HDSP_systemFrequency48:   return 48000;
1030         case HDSP_systemFrequency64:   return 64000;
1031         case HDSP_systemFrequency88_2: return 88200;
1032         case HDSP_systemFrequency96:   return 96000;
1033         default:
1034                 return 0;
1035         }
1036 }
1037
1038 static void hdsp_compute_period_size(struct hdsp *hdsp)
1039 {
1040         hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1041 }
1042
1043 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1044 {
1045         int position;
1046
1047         position = hdsp_read(hdsp, HDSP_statusRegister);
1048
1049         if (!hdsp->precise_ptr)
1050                 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1051
1052         position &= HDSP_BufferPositionMask;
1053         position /= 4;
1054         position &= (hdsp->period_bytes/2) - 1;
1055         return position;
1056 }
1057
1058 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1059 {
1060         hdsp_write (hdsp, HDSP_resetPointer, 0);
1061         if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1062                 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1063                  * requires (?) to write again DDS value after a reset pointer
1064                  * (at least, it works like this) */
1065                 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1066 }
1067
1068 static void hdsp_start_audio(struct hdsp *s)
1069 {
1070         s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1071         hdsp_write(s, HDSP_controlRegister, s->control_register);
1072 }
1073
1074 static void hdsp_stop_audio(struct hdsp *s)
1075 {
1076         s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1077         hdsp_write(s, HDSP_controlRegister, s->control_register);
1078 }
1079
1080 static void hdsp_silence_playback(struct hdsp *hdsp)
1081 {
1082         memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1083 }
1084
1085 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1086 {
1087         int n;
1088
1089         spin_lock_irq(&s->lock);
1090
1091         frames >>= 7;
1092         n = 0;
1093         while (frames) {
1094                 n++;
1095                 frames >>= 1;
1096         }
1097
1098         s->control_register &= ~HDSP_LatencyMask;
1099         s->control_register |= hdsp_encode_latency(n);
1100
1101         hdsp_write(s, HDSP_controlRegister, s->control_register);
1102
1103         hdsp_compute_period_size(s);
1104
1105         spin_unlock_irq(&s->lock);
1106
1107         return 0;
1108 }
1109
1110 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1111 {
1112         u64 n;
1113
1114         if (rate >= 112000)
1115                 rate /= 4;
1116         else if (rate >= 56000)
1117                 rate /= 2;
1118
1119         n = DDS_NUMERATOR;
1120         n = div_u64(n, rate);
1121         /* n should be less than 2^32 for being written to FREQ register */
1122         snd_BUG_ON(n >> 32);
1123         /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1124            value to write it after a reset */
1125         hdsp->dds_value = n;
1126         hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1127 }
1128
1129 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1130 {
1131         int reject_if_open = 0;
1132         int current_rate;
1133         int rate_bits;
1134
1135         /* ASSUMPTION: hdsp->lock is either held, or
1136            there is no need for it (e.g. during module
1137            initialization).
1138         */
1139
1140         if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1141                 if (called_internally) {
1142                         /* request from ctl or card initialization */
1143                         dev_err(hdsp->card->dev,
1144                                 "device is not running as a clock master: cannot set sample rate.\n");
1145                         return -1;
1146                 } else {
1147                         /* hw_param request while in AutoSync mode */
1148                         int external_freq = hdsp_external_sample_rate(hdsp);
1149                         int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1150
1151                         if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1152                                 dev_info(hdsp->card->dev,
1153                                          "Detected ADAT in double speed mode\n");
1154                         else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1155                                 dev_info(hdsp->card->dev,
1156                                          "Detected ADAT in quad speed mode\n");
1157                         else if (rate != external_freq) {
1158                                 dev_info(hdsp->card->dev,
1159                                          "No AutoSync source for requested rate\n");
1160                                 return -1;
1161                         }
1162                 }
1163         }
1164
1165         current_rate = hdsp->system_sample_rate;
1166
1167         /* Changing from a "single speed" to a "double speed" rate is
1168            not allowed if any substreams are open. This is because
1169            such a change causes a shift in the location of
1170            the DMA buffers and a reduction in the number of available
1171            buffers.
1172
1173            Note that a similar but essentially insoluble problem
1174            exists for externally-driven rate changes. All we can do
1175            is to flag rate changes in the read/write routines.  */
1176
1177         if (rate > 96000 && hdsp->io_type != H9632)
1178                 return -EINVAL;
1179
1180         switch (rate) {
1181         case 32000:
1182                 if (current_rate > 48000)
1183                         reject_if_open = 1;
1184                 rate_bits = HDSP_Frequency32KHz;
1185                 break;
1186         case 44100:
1187                 if (current_rate > 48000)
1188                         reject_if_open = 1;
1189                 rate_bits = HDSP_Frequency44_1KHz;
1190                 break;
1191         case 48000:
1192                 if (current_rate > 48000)
1193                         reject_if_open = 1;
1194                 rate_bits = HDSP_Frequency48KHz;
1195                 break;
1196         case 64000:
1197                 if (current_rate <= 48000 || current_rate > 96000)
1198                         reject_if_open = 1;
1199                 rate_bits = HDSP_Frequency64KHz;
1200                 break;
1201         case 88200:
1202                 if (current_rate <= 48000 || current_rate > 96000)
1203                         reject_if_open = 1;
1204                 rate_bits = HDSP_Frequency88_2KHz;
1205                 break;
1206         case 96000:
1207                 if (current_rate <= 48000 || current_rate > 96000)
1208                         reject_if_open = 1;
1209                 rate_bits = HDSP_Frequency96KHz;
1210                 break;
1211         case 128000:
1212                 if (current_rate < 128000)
1213                         reject_if_open = 1;
1214                 rate_bits = HDSP_Frequency128KHz;
1215                 break;
1216         case 176400:
1217                 if (current_rate < 128000)
1218                         reject_if_open = 1;
1219                 rate_bits = HDSP_Frequency176_4KHz;
1220                 break;
1221         case 192000:
1222                 if (current_rate < 128000)
1223                         reject_if_open = 1;
1224                 rate_bits = HDSP_Frequency192KHz;
1225                 break;
1226         default:
1227                 return -EINVAL;
1228         }
1229
1230         if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1231                 dev_warn(hdsp->card->dev,
1232                          "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1233                             hdsp->capture_pid,
1234                             hdsp->playback_pid);
1235                 return -EBUSY;
1236         }
1237
1238         hdsp->control_register &= ~HDSP_FrequencyMask;
1239         hdsp->control_register |= rate_bits;
1240         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1241
1242         /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1243         if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1244                 hdsp_set_dds_value(hdsp, rate);
1245
1246         if (rate >= 128000) {
1247                 hdsp->channel_map = channel_map_H9632_qs;
1248         } else if (rate > 48000) {
1249                 if (hdsp->io_type == H9632)
1250                         hdsp->channel_map = channel_map_H9632_ds;
1251                 else
1252                         hdsp->channel_map = channel_map_ds;
1253         } else {
1254                 switch (hdsp->io_type) {
1255                 case RPM:
1256                 case Multiface:
1257                         hdsp->channel_map = channel_map_mf_ss;
1258                         break;
1259                 case Digiface:
1260                 case H9652:
1261                         hdsp->channel_map = channel_map_df_ss;
1262                         break;
1263                 case H9632:
1264                         hdsp->channel_map = channel_map_H9632_ss;
1265                         break;
1266                 default:
1267                         /* should never happen */
1268                         break;
1269                 }
1270         }
1271
1272         hdsp->system_sample_rate = rate;
1273
1274         return 0;
1275 }
1276
1277 /*----------------------------------------------------------------------------
1278    MIDI
1279   ----------------------------------------------------------------------------*/
1280
1281 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1282 {
1283         /* the hardware already does the relevant bit-mask with 0xff */
1284         if (id)
1285                 return hdsp_read(hdsp, HDSP_midiDataIn1);
1286         else
1287                 return hdsp_read(hdsp, HDSP_midiDataIn0);
1288 }
1289
1290 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1291 {
1292         /* the hardware already does the relevant bit-mask with 0xff */
1293         if (id)
1294                 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1295         else
1296                 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1297 }
1298
1299 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1300 {
1301         if (id)
1302                 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1303         else
1304                 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1305 }
1306
1307 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1308 {
1309         int fifo_bytes_used;
1310
1311         if (id)
1312                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1313         else
1314                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1315
1316         if (fifo_bytes_used < 128)
1317                 return  128 - fifo_bytes_used;
1318         else
1319                 return 0;
1320 }
1321
1322 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1323 {
1324         while (snd_hdsp_midi_input_available (hdsp, id))
1325                 snd_hdsp_midi_read_byte (hdsp, id);
1326 }
1327
1328 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1329 {
1330         unsigned long flags;
1331         int n_pending;
1332         int to_write;
1333         int i;
1334         unsigned char buf[128];
1335
1336         /* Output is not interrupt driven */
1337
1338         spin_lock_irqsave (&hmidi->lock, flags);
1339         if (hmidi->output) {
1340                 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1341                         if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1342                                 if (n_pending > (int)sizeof (buf))
1343                                         n_pending = sizeof (buf);
1344
1345                                 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1346                                         for (i = 0; i < to_write; ++i)
1347                                                 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1348                                 }
1349                         }
1350                 }
1351         }
1352         spin_unlock_irqrestore (&hmidi->lock, flags);
1353         return 0;
1354 }
1355
1356 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1357 {
1358         unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1359         unsigned long flags;
1360         int n_pending;
1361         int i;
1362
1363         spin_lock_irqsave (&hmidi->lock, flags);
1364         if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1365                 if (hmidi->input) {
1366                         if (n_pending > (int)sizeof (buf))
1367                                 n_pending = sizeof (buf);
1368                         for (i = 0; i < n_pending; ++i)
1369                                 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1370                         if (n_pending)
1371                                 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1372                 } else {
1373                         /* flush the MIDI input FIFO */
1374                         while (--n_pending)
1375                                 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1376                 }
1377         }
1378         hmidi->pending = 0;
1379         if (hmidi->id)
1380                 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1381         else
1382                 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1383         hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1384         spin_unlock_irqrestore (&hmidi->lock, flags);
1385         return snd_hdsp_midi_output_write (hmidi);
1386 }
1387
1388 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1389 {
1390         struct hdsp *hdsp;
1391         struct hdsp_midi *hmidi;
1392         unsigned long flags;
1393         u32 ie;
1394
1395         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1396         hdsp = hmidi->hdsp;
1397         ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1398         spin_lock_irqsave (&hdsp->lock, flags);
1399         if (up) {
1400                 if (!(hdsp->control_register & ie)) {
1401                         snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1402                         hdsp->control_register |= ie;
1403                 }
1404         } else {
1405                 hdsp->control_register &= ~ie;
1406                 tasklet_kill(&hdsp->midi_tasklet);
1407         }
1408
1409         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1410         spin_unlock_irqrestore (&hdsp->lock, flags);
1411 }
1412
1413 static void snd_hdsp_midi_output_timer(struct timer_list *t)
1414 {
1415         struct hdsp_midi *hmidi = from_timer(hmidi, t, timer);
1416         unsigned long flags;
1417
1418         snd_hdsp_midi_output_write(hmidi);
1419         spin_lock_irqsave (&hmidi->lock, flags);
1420
1421         /* this does not bump hmidi->istimer, because the
1422            kernel automatically removed the timer when it
1423            expired, and we are now adding it back, thus
1424            leaving istimer wherever it was set before.
1425         */
1426
1427         if (hmidi->istimer)
1428                 mod_timer(&hmidi->timer, 1 + jiffies);
1429
1430         spin_unlock_irqrestore (&hmidi->lock, flags);
1431 }
1432
1433 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1434 {
1435         struct hdsp_midi *hmidi;
1436         unsigned long flags;
1437
1438         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1439         spin_lock_irqsave (&hmidi->lock, flags);
1440         if (up) {
1441                 if (!hmidi->istimer) {
1442                         timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer,
1443                                     0);
1444                         mod_timer(&hmidi->timer, 1 + jiffies);
1445                         hmidi->istimer++;
1446                 }
1447         } else {
1448                 if (hmidi->istimer && --hmidi->istimer <= 0)
1449                         del_timer (&hmidi->timer);
1450         }
1451         spin_unlock_irqrestore (&hmidi->lock, flags);
1452         if (up)
1453                 snd_hdsp_midi_output_write(hmidi);
1454 }
1455
1456 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1457 {
1458         struct hdsp_midi *hmidi;
1459
1460         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1461         spin_lock_irq (&hmidi->lock);
1462         snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1463         hmidi->input = substream;
1464         spin_unlock_irq (&hmidi->lock);
1465
1466         return 0;
1467 }
1468
1469 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1470 {
1471         struct hdsp_midi *hmidi;
1472
1473         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1474         spin_lock_irq (&hmidi->lock);
1475         hmidi->output = substream;
1476         spin_unlock_irq (&hmidi->lock);
1477
1478         return 0;
1479 }
1480
1481 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1482 {
1483         struct hdsp_midi *hmidi;
1484
1485         snd_hdsp_midi_input_trigger (substream, 0);
1486
1487         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1488         spin_lock_irq (&hmidi->lock);
1489         hmidi->input = NULL;
1490         spin_unlock_irq (&hmidi->lock);
1491
1492         return 0;
1493 }
1494
1495 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1496 {
1497         struct hdsp_midi *hmidi;
1498
1499         snd_hdsp_midi_output_trigger (substream, 0);
1500
1501         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1502         spin_lock_irq (&hmidi->lock);
1503         hmidi->output = NULL;
1504         spin_unlock_irq (&hmidi->lock);
1505
1506         return 0;
1507 }
1508
1509 static const struct snd_rawmidi_ops snd_hdsp_midi_output =
1510 {
1511         .open =         snd_hdsp_midi_output_open,
1512         .close =        snd_hdsp_midi_output_close,
1513         .trigger =      snd_hdsp_midi_output_trigger,
1514 };
1515
1516 static const struct snd_rawmidi_ops snd_hdsp_midi_input =
1517 {
1518         .open =         snd_hdsp_midi_input_open,
1519         .close =        snd_hdsp_midi_input_close,
1520         .trigger =      snd_hdsp_midi_input_trigger,
1521 };
1522
1523 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1524 {
1525         char buf[40];
1526
1527         hdsp->midi[id].id = id;
1528         hdsp->midi[id].rmidi = NULL;
1529         hdsp->midi[id].input = NULL;
1530         hdsp->midi[id].output = NULL;
1531         hdsp->midi[id].hdsp = hdsp;
1532         hdsp->midi[id].istimer = 0;
1533         hdsp->midi[id].pending = 0;
1534         spin_lock_init (&hdsp->midi[id].lock);
1535
1536         snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
1537         if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1538                 return -1;
1539
1540         sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1541         hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1542
1543         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1544         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1545
1546         hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1547                 SNDRV_RAWMIDI_INFO_INPUT |
1548                 SNDRV_RAWMIDI_INFO_DUPLEX;
1549
1550         return 0;
1551 }
1552
1553 /*-----------------------------------------------------------------------------
1554   Control Interface
1555   ----------------------------------------------------------------------------*/
1556
1557 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1558 {
1559         u32 val = 0;
1560         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1561         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1562         if (val & HDSP_SPDIFProfessional)
1563                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1564         else
1565                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1566         return val;
1567 }
1568
1569 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1570 {
1571         aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1572                          ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1573         if (val & HDSP_SPDIFProfessional)
1574                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1575         else
1576                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1577 }
1578
1579 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1580 {
1581         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1582         uinfo->count = 1;
1583         return 0;
1584 }
1585
1586 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1587 {
1588         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1589
1590         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1591         return 0;
1592 }
1593
1594 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1595 {
1596         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1597         int change;
1598         u32 val;
1599
1600         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1601         spin_lock_irq(&hdsp->lock);
1602         change = val != hdsp->creg_spdif;
1603         hdsp->creg_spdif = val;
1604         spin_unlock_irq(&hdsp->lock);
1605         return change;
1606 }
1607
1608 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1609 {
1610         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1611         uinfo->count = 1;
1612         return 0;
1613 }
1614
1615 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1616 {
1617         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1618
1619         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1620         return 0;
1621 }
1622
1623 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1624 {
1625         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1626         int change;
1627         u32 val;
1628
1629         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1630         spin_lock_irq(&hdsp->lock);
1631         change = val != hdsp->creg_spdif_stream;
1632         hdsp->creg_spdif_stream = val;
1633         hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1634         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1635         spin_unlock_irq(&hdsp->lock);
1636         return change;
1637 }
1638
1639 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1640 {
1641         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1642         uinfo->count = 1;
1643         return 0;
1644 }
1645
1646 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1647 {
1648         ucontrol->value.iec958.status[0] = kcontrol->private_value;
1649         return 0;
1650 }
1651
1652 #define HDSP_SPDIF_IN(xname, xindex) \
1653 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1654   .name = xname, \
1655   .index = xindex, \
1656   .info = snd_hdsp_info_spdif_in, \
1657   .get = snd_hdsp_get_spdif_in, \
1658   .put = snd_hdsp_put_spdif_in }
1659
1660 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1661 {
1662         return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1663 }
1664
1665 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1666 {
1667         hdsp->control_register &= ~HDSP_SPDIFInputMask;
1668         hdsp->control_register |= hdsp_encode_spdif_in(in);
1669         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1670         return 0;
1671 }
1672
1673 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1674 {
1675         static const char * const texts[4] = {
1676                 "Optical", "Coaxial", "Internal", "AES"
1677         };
1678         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1679
1680         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1681                                  texts);
1682 }
1683
1684 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1685 {
1686         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1687
1688         ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1689         return 0;
1690 }
1691
1692 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1693 {
1694         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1695         int change;
1696         unsigned int val;
1697
1698         if (!snd_hdsp_use_is_exclusive(hdsp))
1699                 return -EBUSY;
1700         val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1701         spin_lock_irq(&hdsp->lock);
1702         change = val != hdsp_spdif_in(hdsp);
1703         if (change)
1704                 hdsp_set_spdif_input(hdsp, val);
1705         spin_unlock_irq(&hdsp->lock);
1706         return change;
1707 }
1708
1709 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1710 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1711         .name = xname, \
1712         .private_value = xindex, \
1713         .info = snd_hdsp_info_toggle_setting, \
1714         .get = snd_hdsp_get_toggle_setting, \
1715         .put = snd_hdsp_put_toggle_setting \
1716 }
1717
1718 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1719 {
1720         return (hdsp->control_register & regmask) ? 1 : 0;
1721 }
1722
1723 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1724 {
1725         if (out)
1726                 hdsp->control_register |= regmask;
1727         else
1728                 hdsp->control_register &= ~regmask;
1729         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1730
1731         return 0;
1732 }
1733
1734 #define snd_hdsp_info_toggle_setting               snd_ctl_boolean_mono_info
1735
1736 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1737                 struct snd_ctl_elem_value *ucontrol)
1738 {
1739         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1740         u32 regmask = kcontrol->private_value;
1741
1742         spin_lock_irq(&hdsp->lock);
1743         ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1744         spin_unlock_irq(&hdsp->lock);
1745         return 0;
1746 }
1747
1748 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1749                 struct snd_ctl_elem_value *ucontrol)
1750 {
1751         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1752         u32 regmask = kcontrol->private_value;
1753         int change;
1754         unsigned int val;
1755
1756         if (!snd_hdsp_use_is_exclusive(hdsp))
1757                 return -EBUSY;
1758         val = ucontrol->value.integer.value[0] & 1;
1759         spin_lock_irq(&hdsp->lock);
1760         change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1761         if (change)
1762                 hdsp_set_toggle_setting(hdsp, regmask, val);
1763         spin_unlock_irq(&hdsp->lock);
1764         return change;
1765 }
1766
1767 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1768 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1769   .name = xname, \
1770   .index = xindex, \
1771   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1772   .info = snd_hdsp_info_spdif_sample_rate, \
1773   .get = snd_hdsp_get_spdif_sample_rate \
1774 }
1775
1776 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1777 {
1778         static const char * const texts[] = {
1779                 "32000", "44100", "48000", "64000", "88200", "96000",
1780                 "None", "128000", "176400", "192000"
1781         };
1782         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1783
1784         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1785                                  texts);
1786 }
1787
1788 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1789 {
1790         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1791
1792         switch (hdsp_spdif_sample_rate(hdsp)) {
1793         case 32000:
1794                 ucontrol->value.enumerated.item[0] = 0;
1795                 break;
1796         case 44100:
1797                 ucontrol->value.enumerated.item[0] = 1;
1798                 break;
1799         case 48000:
1800                 ucontrol->value.enumerated.item[0] = 2;
1801                 break;
1802         case 64000:
1803                 ucontrol->value.enumerated.item[0] = 3;
1804                 break;
1805         case 88200:
1806                 ucontrol->value.enumerated.item[0] = 4;
1807                 break;
1808         case 96000:
1809                 ucontrol->value.enumerated.item[0] = 5;
1810                 break;
1811         case 128000:
1812                 ucontrol->value.enumerated.item[0] = 7;
1813                 break;
1814         case 176400:
1815                 ucontrol->value.enumerated.item[0] = 8;
1816                 break;
1817         case 192000:
1818                 ucontrol->value.enumerated.item[0] = 9;
1819                 break;
1820         default:
1821                 ucontrol->value.enumerated.item[0] = 6;
1822         }
1823         return 0;
1824 }
1825
1826 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1827 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1828   .name = xname, \
1829   .index = xindex, \
1830   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1831   .info = snd_hdsp_info_system_sample_rate, \
1832   .get = snd_hdsp_get_system_sample_rate \
1833 }
1834
1835 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1836 {
1837         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1838         uinfo->count = 1;
1839         return 0;
1840 }
1841
1842 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1843 {
1844         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1845
1846         ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1847         return 0;
1848 }
1849
1850 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1851 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1852   .name = xname, \
1853   .index = xindex, \
1854   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1855   .info = snd_hdsp_info_autosync_sample_rate, \
1856   .get = snd_hdsp_get_autosync_sample_rate \
1857 }
1858
1859 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1860 {
1861         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1862         static const char * const texts[] = {
1863                 "32000", "44100", "48000", "64000", "88200", "96000",
1864                 "None", "128000", "176400", "192000"
1865         };
1866
1867         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1868                                  texts);
1869 }
1870
1871 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1872 {
1873         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1874
1875         switch (hdsp_external_sample_rate(hdsp)) {
1876         case 32000:
1877                 ucontrol->value.enumerated.item[0] = 0;
1878                 break;
1879         case 44100:
1880                 ucontrol->value.enumerated.item[0] = 1;
1881                 break;
1882         case 48000:
1883                 ucontrol->value.enumerated.item[0] = 2;
1884                 break;
1885         case 64000:
1886                 ucontrol->value.enumerated.item[0] = 3;
1887                 break;
1888         case 88200:
1889                 ucontrol->value.enumerated.item[0] = 4;
1890                 break;
1891         case 96000:
1892                 ucontrol->value.enumerated.item[0] = 5;
1893                 break;
1894         case 128000:
1895                 ucontrol->value.enumerated.item[0] = 7;
1896                 break;
1897         case 176400:
1898                 ucontrol->value.enumerated.item[0] = 8;
1899                 break;
1900         case 192000:
1901                 ucontrol->value.enumerated.item[0] = 9;
1902                 break;
1903         default:
1904                 ucontrol->value.enumerated.item[0] = 6;
1905         }
1906         return 0;
1907 }
1908
1909 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1910 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1911   .name = xname, \
1912   .index = xindex, \
1913   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1914   .info = snd_hdsp_info_system_clock_mode, \
1915   .get = snd_hdsp_get_system_clock_mode \
1916 }
1917
1918 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1919 {
1920         if (hdsp->control_register & HDSP_ClockModeMaster)
1921                 return 0;
1922         else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1923                         return 0;
1924         return 1;
1925 }
1926
1927 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1928 {
1929         static const char * const texts[] = {"Master", "Slave" };
1930
1931         return snd_ctl_enum_info(uinfo, 1, 2, texts);
1932 }
1933
1934 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1935 {
1936         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1937
1938         ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1939         return 0;
1940 }
1941
1942 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1943 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1944   .name = xname, \
1945   .index = xindex, \
1946   .info = snd_hdsp_info_clock_source, \
1947   .get = snd_hdsp_get_clock_source, \
1948   .put = snd_hdsp_put_clock_source \
1949 }
1950
1951 static int hdsp_clock_source(struct hdsp *hdsp)
1952 {
1953         if (hdsp->control_register & HDSP_ClockModeMaster) {
1954                 switch (hdsp->system_sample_rate) {
1955                 case 32000:
1956                         return 1;
1957                 case 44100:
1958                         return 2;
1959                 case 48000:
1960                         return 3;
1961                 case 64000:
1962                         return 4;
1963                 case 88200:
1964                         return 5;
1965                 case 96000:
1966                         return 6;
1967                 case 128000:
1968                         return 7;
1969                 case 176400:
1970                         return 8;
1971                 case 192000:
1972                         return 9;
1973                 default:
1974                         return 3;
1975                 }
1976         } else {
1977                 return 0;
1978         }
1979 }
1980
1981 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1982 {
1983         int rate;
1984         switch (mode) {
1985         case HDSP_CLOCK_SOURCE_AUTOSYNC:
1986                 if (hdsp_external_sample_rate(hdsp) != 0) {
1987                     if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1988                         hdsp->control_register &= ~HDSP_ClockModeMaster;
1989                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1990                         return 0;
1991                     }
1992                 }
1993                 return -1;
1994         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
1995                 rate = 32000;
1996                 break;
1997         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1998                 rate = 44100;
1999                 break;
2000         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2001                 rate = 48000;
2002                 break;
2003         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2004                 rate = 64000;
2005                 break;
2006         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2007                 rate = 88200;
2008                 break;
2009         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2010                 rate = 96000;
2011                 break;
2012         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2013                 rate = 128000;
2014                 break;
2015         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2016                 rate = 176400;
2017                 break;
2018         case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2019                 rate = 192000;
2020                 break;
2021         default:
2022                 rate = 48000;
2023         }
2024         hdsp->control_register |= HDSP_ClockModeMaster;
2025         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2026         hdsp_set_rate(hdsp, rate, 1);
2027         return 0;
2028 }
2029
2030 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2031 {
2032         static const char * const texts[] = {
2033                 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2034                 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2035                 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2036                 "Internal 192.0 KHz"
2037         };
2038         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2039
2040         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2041                                  texts);
2042 }
2043
2044 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2045 {
2046         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2047
2048         ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2049         return 0;
2050 }
2051
2052 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2053 {
2054         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2055         int change;
2056         int val;
2057
2058         if (!snd_hdsp_use_is_exclusive(hdsp))
2059                 return -EBUSY;
2060         val = ucontrol->value.enumerated.item[0];
2061         if (val < 0) val = 0;
2062         if (hdsp->io_type == H9632) {
2063                 if (val > 9)
2064                         val = 9;
2065         } else {
2066                 if (val > 6)
2067                         val = 6;
2068         }
2069         spin_lock_irq(&hdsp->lock);
2070         if (val != hdsp_clock_source(hdsp))
2071                 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2072         else
2073                 change = 0;
2074         spin_unlock_irq(&hdsp->lock);
2075         return change;
2076 }
2077
2078 #define snd_hdsp_info_clock_source_lock         snd_ctl_boolean_mono_info
2079
2080 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2081 {
2082         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2083
2084         ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2085         return 0;
2086 }
2087
2088 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2089 {
2090         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2091         int change;
2092
2093         change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2094         if (change)
2095                 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2096         return change;
2097 }
2098
2099 #define HDSP_DA_GAIN(xname, xindex) \
2100 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2101   .name = xname, \
2102   .index = xindex, \
2103   .info = snd_hdsp_info_da_gain, \
2104   .get = snd_hdsp_get_da_gain, \
2105   .put = snd_hdsp_put_da_gain \
2106 }
2107
2108 static int hdsp_da_gain(struct hdsp *hdsp)
2109 {
2110         switch (hdsp->control_register & HDSP_DAGainMask) {
2111         case HDSP_DAGainHighGain:
2112                 return 0;
2113         case HDSP_DAGainPlus4dBu:
2114                 return 1;
2115         case HDSP_DAGainMinus10dBV:
2116                 return 2;
2117         default:
2118                 return 1;
2119         }
2120 }
2121
2122 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2123 {
2124         hdsp->control_register &= ~HDSP_DAGainMask;
2125         switch (mode) {
2126         case 0:
2127                 hdsp->control_register |= HDSP_DAGainHighGain;
2128                 break;
2129         case 1:
2130                 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2131                 break;
2132         case 2:
2133                 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2134                 break;
2135         default:
2136                 return -1;
2137
2138         }
2139         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2140         return 0;
2141 }
2142
2143 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2144 {
2145         static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2146
2147         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2148 }
2149
2150 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2151 {
2152         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2153
2154         ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2155         return 0;
2156 }
2157
2158 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2159 {
2160         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2161         int change;
2162         int val;
2163
2164         if (!snd_hdsp_use_is_exclusive(hdsp))
2165                 return -EBUSY;
2166         val = ucontrol->value.enumerated.item[0];
2167         if (val < 0) val = 0;
2168         if (val > 2) val = 2;
2169         spin_lock_irq(&hdsp->lock);
2170         if (val != hdsp_da_gain(hdsp))
2171                 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2172         else
2173                 change = 0;
2174         spin_unlock_irq(&hdsp->lock);
2175         return change;
2176 }
2177
2178 #define HDSP_AD_GAIN(xname, xindex) \
2179 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2180   .name = xname, \
2181   .index = xindex, \
2182   .info = snd_hdsp_info_ad_gain, \
2183   .get = snd_hdsp_get_ad_gain, \
2184   .put = snd_hdsp_put_ad_gain \
2185 }
2186
2187 static int hdsp_ad_gain(struct hdsp *hdsp)
2188 {
2189         switch (hdsp->control_register & HDSP_ADGainMask) {
2190         case HDSP_ADGainMinus10dBV:
2191                 return 0;
2192         case HDSP_ADGainPlus4dBu:
2193                 return 1;
2194         case HDSP_ADGainLowGain:
2195                 return 2;
2196         default:
2197                 return 1;
2198         }
2199 }
2200
2201 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2202 {
2203         hdsp->control_register &= ~HDSP_ADGainMask;
2204         switch (mode) {
2205         case 0:
2206                 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2207                 break;
2208         case 1:
2209                 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2210                 break;
2211         case 2:
2212                 hdsp->control_register |= HDSP_ADGainLowGain;
2213                 break;
2214         default:
2215                 return -1;
2216
2217         }
2218         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2219         return 0;
2220 }
2221
2222 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2223 {
2224         static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2225
2226         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2227 }
2228
2229 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2230 {
2231         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2232
2233         ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2234         return 0;
2235 }
2236
2237 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2238 {
2239         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2240         int change;
2241         int val;
2242
2243         if (!snd_hdsp_use_is_exclusive(hdsp))
2244                 return -EBUSY;
2245         val = ucontrol->value.enumerated.item[0];
2246         if (val < 0) val = 0;
2247         if (val > 2) val = 2;
2248         spin_lock_irq(&hdsp->lock);
2249         if (val != hdsp_ad_gain(hdsp))
2250                 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2251         else
2252                 change = 0;
2253         spin_unlock_irq(&hdsp->lock);
2254         return change;
2255 }
2256
2257 #define HDSP_PHONE_GAIN(xname, xindex) \
2258 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2259   .name = xname, \
2260   .index = xindex, \
2261   .info = snd_hdsp_info_phone_gain, \
2262   .get = snd_hdsp_get_phone_gain, \
2263   .put = snd_hdsp_put_phone_gain \
2264 }
2265
2266 static int hdsp_phone_gain(struct hdsp *hdsp)
2267 {
2268         switch (hdsp->control_register & HDSP_PhoneGainMask) {
2269         case HDSP_PhoneGain0dB:
2270                 return 0;
2271         case HDSP_PhoneGainMinus6dB:
2272                 return 1;
2273         case HDSP_PhoneGainMinus12dB:
2274                 return 2;
2275         default:
2276                 return 0;
2277         }
2278 }
2279
2280 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2281 {
2282         hdsp->control_register &= ~HDSP_PhoneGainMask;
2283         switch (mode) {
2284         case 0:
2285                 hdsp->control_register |= HDSP_PhoneGain0dB;
2286                 break;
2287         case 1:
2288                 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2289                 break;
2290         case 2:
2291                 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2292                 break;
2293         default:
2294                 return -1;
2295
2296         }
2297         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2298         return 0;
2299 }
2300
2301 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2302 {
2303         static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2304
2305         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2306 }
2307
2308 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2309 {
2310         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2311
2312         ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2313         return 0;
2314 }
2315
2316 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2317 {
2318         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2319         int change;
2320         int val;
2321
2322         if (!snd_hdsp_use_is_exclusive(hdsp))
2323                 return -EBUSY;
2324         val = ucontrol->value.enumerated.item[0];
2325         if (val < 0) val = 0;
2326         if (val > 2) val = 2;
2327         spin_lock_irq(&hdsp->lock);
2328         if (val != hdsp_phone_gain(hdsp))
2329                 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2330         else
2331                 change = 0;
2332         spin_unlock_irq(&hdsp->lock);
2333         return change;
2334 }
2335
2336 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2337 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2338   .name = xname, \
2339   .index = xindex, \
2340   .info = snd_hdsp_info_pref_sync_ref, \
2341   .get = snd_hdsp_get_pref_sync_ref, \
2342   .put = snd_hdsp_put_pref_sync_ref \
2343 }
2344
2345 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2346 {
2347         /* Notice that this looks at the requested sync source,
2348            not the one actually in use.
2349         */
2350
2351         switch (hdsp->control_register & HDSP_SyncRefMask) {
2352         case HDSP_SyncRef_ADAT1:
2353                 return HDSP_SYNC_FROM_ADAT1;
2354         case HDSP_SyncRef_ADAT2:
2355                 return HDSP_SYNC_FROM_ADAT2;
2356         case HDSP_SyncRef_ADAT3:
2357                 return HDSP_SYNC_FROM_ADAT3;
2358         case HDSP_SyncRef_SPDIF:
2359                 return HDSP_SYNC_FROM_SPDIF;
2360         case HDSP_SyncRef_WORD:
2361                 return HDSP_SYNC_FROM_WORD;
2362         case HDSP_SyncRef_ADAT_SYNC:
2363                 return HDSP_SYNC_FROM_ADAT_SYNC;
2364         default:
2365                 return HDSP_SYNC_FROM_WORD;
2366         }
2367         return 0;
2368 }
2369
2370 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2371 {
2372         hdsp->control_register &= ~HDSP_SyncRefMask;
2373         switch (pref) {
2374         case HDSP_SYNC_FROM_ADAT1:
2375                 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2376                 break;
2377         case HDSP_SYNC_FROM_ADAT2:
2378                 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2379                 break;
2380         case HDSP_SYNC_FROM_ADAT3:
2381                 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2382                 break;
2383         case HDSP_SYNC_FROM_SPDIF:
2384                 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2385                 break;
2386         case HDSP_SYNC_FROM_WORD:
2387                 hdsp->control_register |= HDSP_SyncRef_WORD;
2388                 break;
2389         case HDSP_SYNC_FROM_ADAT_SYNC:
2390                 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2391                 break;
2392         default:
2393                 return -1;
2394         }
2395         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2396         return 0;
2397 }
2398
2399 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2400 {
2401         static const char * const texts[] = {
2402                 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2403         };
2404         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2405         int num_items;
2406
2407         switch (hdsp->io_type) {
2408         case Digiface:
2409         case H9652:
2410                 num_items = 6;
2411                 break;
2412         case Multiface:
2413                 num_items = 4;
2414                 break;
2415         case H9632:
2416                 num_items = 3;
2417                 break;
2418         default:
2419                 return -EINVAL;
2420         }
2421
2422         return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2423 }
2424
2425 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2426 {
2427         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2428
2429         ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2430         return 0;
2431 }
2432
2433 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2434 {
2435         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2436         int change, max;
2437         unsigned int val;
2438
2439         if (!snd_hdsp_use_is_exclusive(hdsp))
2440                 return -EBUSY;
2441
2442         switch (hdsp->io_type) {
2443         case Digiface:
2444         case H9652:
2445                 max = 6;
2446                 break;
2447         case Multiface:
2448                 max = 4;
2449                 break;
2450         case H9632:
2451                 max = 3;
2452                 break;
2453         default:
2454                 return -EIO;
2455         }
2456
2457         val = ucontrol->value.enumerated.item[0] % max;
2458         spin_lock_irq(&hdsp->lock);
2459         change = (int)val != hdsp_pref_sync_ref(hdsp);
2460         hdsp_set_pref_sync_ref(hdsp, val);
2461         spin_unlock_irq(&hdsp->lock);
2462         return change;
2463 }
2464
2465 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2466 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2467   .name = xname, \
2468   .index = xindex, \
2469   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2470   .info = snd_hdsp_info_autosync_ref, \
2471   .get = snd_hdsp_get_autosync_ref, \
2472 }
2473
2474 static int hdsp_autosync_ref(struct hdsp *hdsp)
2475 {
2476         /* This looks at the autosync selected sync reference */
2477         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2478
2479         switch (status2 & HDSP_SelSyncRefMask) {
2480         case HDSP_SelSyncRef_WORD:
2481                 return HDSP_AUTOSYNC_FROM_WORD;
2482         case HDSP_SelSyncRef_ADAT_SYNC:
2483                 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2484         case HDSP_SelSyncRef_SPDIF:
2485                 return HDSP_AUTOSYNC_FROM_SPDIF;
2486         case HDSP_SelSyncRefMask:
2487                 return HDSP_AUTOSYNC_FROM_NONE;
2488         case HDSP_SelSyncRef_ADAT1:
2489                 return HDSP_AUTOSYNC_FROM_ADAT1;
2490         case HDSP_SelSyncRef_ADAT2:
2491                 return HDSP_AUTOSYNC_FROM_ADAT2;
2492         case HDSP_SelSyncRef_ADAT3:
2493                 return HDSP_AUTOSYNC_FROM_ADAT3;
2494         default:
2495                 return HDSP_AUTOSYNC_FROM_WORD;
2496         }
2497         return 0;
2498 }
2499
2500 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2501 {
2502         static const char * const texts[] = {
2503                 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2504         };
2505
2506         return snd_ctl_enum_info(uinfo, 1, 7, texts);
2507 }
2508
2509 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2510 {
2511         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2512
2513         ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2514         return 0;
2515 }
2516
2517 #define HDSP_PRECISE_POINTER(xname, xindex) \
2518 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2519   .name = xname, \
2520   .index = xindex, \
2521   .info = snd_hdsp_info_precise_pointer, \
2522   .get = snd_hdsp_get_precise_pointer, \
2523   .put = snd_hdsp_put_precise_pointer \
2524 }
2525
2526 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2527 {
2528         if (precise)
2529                 hdsp->precise_ptr = 1;
2530         else
2531                 hdsp->precise_ptr = 0;
2532         return 0;
2533 }
2534
2535 #define snd_hdsp_info_precise_pointer           snd_ctl_boolean_mono_info
2536
2537 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2538 {
2539         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2540
2541         spin_lock_irq(&hdsp->lock);
2542         ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2543         spin_unlock_irq(&hdsp->lock);
2544         return 0;
2545 }
2546
2547 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2548 {
2549         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2550         int change;
2551         unsigned int val;
2552
2553         if (!snd_hdsp_use_is_exclusive(hdsp))
2554                 return -EBUSY;
2555         val = ucontrol->value.integer.value[0] & 1;
2556         spin_lock_irq(&hdsp->lock);
2557         change = (int)val != hdsp->precise_ptr;
2558         hdsp_set_precise_pointer(hdsp, val);
2559         spin_unlock_irq(&hdsp->lock);
2560         return change;
2561 }
2562
2563 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2564 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2565   .name = xname, \
2566   .index = xindex, \
2567   .info = snd_hdsp_info_use_midi_tasklet, \
2568   .get = snd_hdsp_get_use_midi_tasklet, \
2569   .put = snd_hdsp_put_use_midi_tasklet \
2570 }
2571
2572 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2573 {
2574         if (use_tasklet)
2575                 hdsp->use_midi_tasklet = 1;
2576         else
2577                 hdsp->use_midi_tasklet = 0;
2578         return 0;
2579 }
2580
2581 #define snd_hdsp_info_use_midi_tasklet          snd_ctl_boolean_mono_info
2582
2583 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2584 {
2585         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2586
2587         spin_lock_irq(&hdsp->lock);
2588         ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2589         spin_unlock_irq(&hdsp->lock);
2590         return 0;
2591 }
2592
2593 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2594 {
2595         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2596         int change;
2597         unsigned int val;
2598
2599         if (!snd_hdsp_use_is_exclusive(hdsp))
2600                 return -EBUSY;
2601         val = ucontrol->value.integer.value[0] & 1;
2602         spin_lock_irq(&hdsp->lock);
2603         change = (int)val != hdsp->use_midi_tasklet;
2604         hdsp_set_use_midi_tasklet(hdsp, val);
2605         spin_unlock_irq(&hdsp->lock);
2606         return change;
2607 }
2608
2609 #define HDSP_MIXER(xname, xindex) \
2610 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2611   .name = xname, \
2612   .index = xindex, \
2613   .device = 0, \
2614   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2615                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2616   .info = snd_hdsp_info_mixer, \
2617   .get = snd_hdsp_get_mixer, \
2618   .put = snd_hdsp_put_mixer \
2619 }
2620
2621 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2622 {
2623         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2624         uinfo->count = 3;
2625         uinfo->value.integer.min = 0;
2626         uinfo->value.integer.max = 65536;
2627         uinfo->value.integer.step = 1;
2628         return 0;
2629 }
2630
2631 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2632 {
2633         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2634         int source;
2635         int destination;
2636         int addr;
2637
2638         source = ucontrol->value.integer.value[0];
2639         destination = ucontrol->value.integer.value[1];
2640
2641         if (source >= hdsp->max_channels)
2642                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2643         else
2644                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2645
2646         spin_lock_irq(&hdsp->lock);
2647         ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2648         spin_unlock_irq(&hdsp->lock);
2649         return 0;
2650 }
2651
2652 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2653 {
2654         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2655         int change;
2656         int source;
2657         int destination;
2658         int gain;
2659         int addr;
2660
2661         if (!snd_hdsp_use_is_exclusive(hdsp))
2662                 return -EBUSY;
2663
2664         source = ucontrol->value.integer.value[0];
2665         destination = ucontrol->value.integer.value[1];
2666
2667         if (source >= hdsp->max_channels)
2668                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2669         else
2670                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2671
2672         gain = ucontrol->value.integer.value[2];
2673
2674         spin_lock_irq(&hdsp->lock);
2675         change = gain != hdsp_read_gain(hdsp, addr);
2676         if (change)
2677                 hdsp_write_gain(hdsp, addr, gain);
2678         spin_unlock_irq(&hdsp->lock);
2679         return change;
2680 }
2681
2682 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2683 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2684   .name = xname, \
2685   .index = xindex, \
2686   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2687   .info = snd_hdsp_info_sync_check, \
2688   .get = snd_hdsp_get_wc_sync_check \
2689 }
2690
2691 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2692 {
2693         static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2694
2695         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2696 }
2697
2698 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2699 {
2700         int status2 = hdsp_read(hdsp, HDSP_status2Register);
2701         if (status2 & HDSP_wc_lock) {
2702                 if (status2 & HDSP_wc_sync)
2703                         return 2;
2704                 else
2705                          return 1;
2706         } else
2707                 return 0;
2708         return 0;
2709 }
2710
2711 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2712 {
2713         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2714
2715         ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2716         return 0;
2717 }
2718
2719 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2720 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2721   .name = xname, \
2722   .index = xindex, \
2723   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2724   .info = snd_hdsp_info_sync_check, \
2725   .get = snd_hdsp_get_spdif_sync_check \
2726 }
2727
2728 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2729 {
2730         int status = hdsp_read(hdsp, HDSP_statusRegister);
2731         if (status & HDSP_SPDIFErrorFlag)
2732                 return 0;
2733         else {
2734                 if (status & HDSP_SPDIFSync)
2735                         return 2;
2736                 else
2737                         return 1;
2738         }
2739         return 0;
2740 }
2741
2742 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2743 {
2744         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2745
2746         ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2747         return 0;
2748 }
2749
2750 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2751 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2752   .name = xname, \
2753   .index = xindex, \
2754   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2755   .info = snd_hdsp_info_sync_check, \
2756   .get = snd_hdsp_get_adatsync_sync_check \
2757 }
2758
2759 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2760 {
2761         int status = hdsp_read(hdsp, HDSP_statusRegister);
2762         if (status & HDSP_TimecodeLock) {
2763                 if (status & HDSP_TimecodeSync)
2764                         return 2;
2765                 else
2766                         return 1;
2767         } else
2768                 return 0;
2769 }
2770
2771 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2772 {
2773         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2774
2775         ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2776         return 0;
2777 }
2778
2779 #define HDSP_ADAT_SYNC_CHECK \
2780 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2781   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2782   .info = snd_hdsp_info_sync_check, \
2783   .get = snd_hdsp_get_adat_sync_check \
2784 }
2785
2786 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2787 {
2788         int status = hdsp_read(hdsp, HDSP_statusRegister);
2789
2790         if (status & (HDSP_Lock0>>idx)) {
2791                 if (status & (HDSP_Sync0>>idx))
2792                         return 2;
2793                 else
2794                         return 1;
2795         } else
2796                 return 0;
2797 }
2798
2799 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2800 {
2801         int offset;
2802         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2803
2804         offset = ucontrol->id.index - 1;
2805         if (snd_BUG_ON(offset < 0))
2806                 return -EINVAL;
2807
2808         switch (hdsp->io_type) {
2809         case Digiface:
2810         case H9652:
2811                 if (offset >= 3)
2812                         return -EINVAL;
2813                 break;
2814         case Multiface:
2815         case H9632:
2816                 if (offset >= 1)
2817                         return -EINVAL;
2818                 break;
2819         default:
2820                 return -EIO;
2821         }
2822
2823         ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2824         return 0;
2825 }
2826
2827 #define HDSP_DDS_OFFSET(xname, xindex) \
2828 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2829   .name = xname, \
2830   .index = xindex, \
2831   .info = snd_hdsp_info_dds_offset, \
2832   .get = snd_hdsp_get_dds_offset, \
2833   .put = snd_hdsp_put_dds_offset \
2834 }
2835
2836 static int hdsp_dds_offset(struct hdsp *hdsp)
2837 {
2838         u64 n;
2839         unsigned int dds_value = hdsp->dds_value;
2840         int system_sample_rate = hdsp->system_sample_rate;
2841
2842         if (!dds_value)
2843                 return 0;
2844
2845         n = DDS_NUMERATOR;
2846         /*
2847          * dds_value = n / rate
2848          * rate = n / dds_value
2849          */
2850         n = div_u64(n, dds_value);
2851         if (system_sample_rate >= 112000)
2852                 n *= 4;
2853         else if (system_sample_rate >= 56000)
2854                 n *= 2;
2855         return ((int)n) - system_sample_rate;
2856 }
2857
2858 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2859 {
2860         int rate = hdsp->system_sample_rate + offset_hz;
2861         hdsp_set_dds_value(hdsp, rate);
2862         return 0;
2863 }
2864
2865 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2866 {
2867         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2868         uinfo->count = 1;
2869         uinfo->value.integer.min = -5000;
2870         uinfo->value.integer.max = 5000;
2871         return 0;
2872 }
2873
2874 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2875 {
2876         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2877
2878         ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2879         return 0;
2880 }
2881
2882 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2883 {
2884         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2885         int change;
2886         int val;
2887
2888         if (!snd_hdsp_use_is_exclusive(hdsp))
2889                 return -EBUSY;
2890         val = ucontrol->value.integer.value[0];
2891         spin_lock_irq(&hdsp->lock);
2892         if (val != hdsp_dds_offset(hdsp))
2893                 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2894         else
2895                 change = 0;
2896         spin_unlock_irq(&hdsp->lock);
2897         return change;
2898 }
2899
2900 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2901 HDSP_DA_GAIN("DA Gain", 0),
2902 HDSP_AD_GAIN("AD Gain", 0),
2903 HDSP_PHONE_GAIN("Phones Gain", 0),
2904 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2905 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2906 };
2907
2908 static struct snd_kcontrol_new snd_hdsp_controls[] = {
2909 {
2910         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2911         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2912         .info =         snd_hdsp_control_spdif_info,
2913         .get =          snd_hdsp_control_spdif_get,
2914         .put =          snd_hdsp_control_spdif_put,
2915 },
2916 {
2917         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2918         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2919         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2920         .info =         snd_hdsp_control_spdif_stream_info,
2921         .get =          snd_hdsp_control_spdif_stream_get,
2922         .put =          snd_hdsp_control_spdif_stream_put,
2923 },
2924 {
2925         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2926         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2927         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2928         .info =         snd_hdsp_control_spdif_mask_info,
2929         .get =          snd_hdsp_control_spdif_mask_get,
2930         .private_value = IEC958_AES0_NONAUDIO |
2931                          IEC958_AES0_PROFESSIONAL |
2932                          IEC958_AES0_CON_EMPHASIS,
2933 },
2934 {
2935         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2936         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2937         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2938         .info =         snd_hdsp_control_spdif_mask_info,
2939         .get =          snd_hdsp_control_spdif_mask_get,
2940         .private_value = IEC958_AES0_NONAUDIO |
2941                          IEC958_AES0_PROFESSIONAL |
2942                          IEC958_AES0_PRO_EMPHASIS,
2943 },
2944 HDSP_MIXER("Mixer", 0),
2945 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2946 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2947 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2948 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2949 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2950 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2951 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2952 {
2953         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2954         .name = "Sample Clock Source Locking",
2955         .info = snd_hdsp_info_clock_source_lock,
2956         .get = snd_hdsp_get_clock_source_lock,
2957         .put = snd_hdsp_put_clock_source_lock,
2958 },
2959 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2960 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2961 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2962 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2963 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2964 /* 'External Rate' complies with the alsa control naming scheme */
2965 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2966 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2967 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2968 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2969 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2970 HDSP_PRECISE_POINTER("Precise Pointer", 0),
2971 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
2972 };
2973
2974
2975 static int hdsp_rpm_input12(struct hdsp *hdsp)
2976 {
2977         switch (hdsp->control_register & HDSP_RPM_Inp12) {
2978         case HDSP_RPM_Inp12_Phon_6dB:
2979                 return 0;
2980         case HDSP_RPM_Inp12_Phon_n6dB:
2981                 return 2;
2982         case HDSP_RPM_Inp12_Line_0dB:
2983                 return 3;
2984         case HDSP_RPM_Inp12_Line_n6dB:
2985                 return 4;
2986         }
2987         return 1;
2988 }
2989
2990
2991 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2992 {
2993         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2994
2995         ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
2996         return 0;
2997 }
2998
2999
3000 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
3001 {
3002         hdsp->control_register &= ~HDSP_RPM_Inp12;
3003         switch (mode) {
3004         case 0:
3005                 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
3006                 break;
3007         case 1:
3008                 break;
3009         case 2:
3010                 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
3011                 break;
3012         case 3:
3013                 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
3014                 break;
3015         case 4:
3016                 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
3017                 break;
3018         default:
3019                 return -1;
3020         }
3021
3022         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3023         return 0;
3024 }
3025
3026
3027 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3028 {
3029         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3030         int change;
3031         int val;
3032
3033         if (!snd_hdsp_use_is_exclusive(hdsp))
3034                 return -EBUSY;
3035         val = ucontrol->value.enumerated.item[0];
3036         if (val < 0)
3037                 val = 0;
3038         if (val > 4)
3039                 val = 4;
3040         spin_lock_irq(&hdsp->lock);
3041         if (val != hdsp_rpm_input12(hdsp))
3042                 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3043         else
3044                 change = 0;
3045         spin_unlock_irq(&hdsp->lock);
3046         return change;
3047 }
3048
3049
3050 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3051 {
3052         static const char * const texts[] = {
3053                 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3054         };
3055
3056         return snd_ctl_enum_info(uinfo, 1, 5, texts);
3057 }
3058
3059
3060 static int hdsp_rpm_input34(struct hdsp *hdsp)
3061 {
3062         switch (hdsp->control_register & HDSP_RPM_Inp34) {
3063         case HDSP_RPM_Inp34_Phon_6dB:
3064                 return 0;
3065         case HDSP_RPM_Inp34_Phon_n6dB:
3066                 return 2;
3067         case HDSP_RPM_Inp34_Line_0dB:
3068                 return 3;
3069         case HDSP_RPM_Inp34_Line_n6dB:
3070                 return 4;
3071         }
3072         return 1;
3073 }
3074
3075
3076 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3077 {
3078         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3079
3080         ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3081         return 0;
3082 }
3083
3084
3085 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3086 {
3087         hdsp->control_register &= ~HDSP_RPM_Inp34;
3088         switch (mode) {
3089         case 0:
3090                 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3091                 break;
3092         case 1:
3093                 break;
3094         case 2:
3095                 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3096                 break;
3097         case 3:
3098                 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3099                 break;
3100         case 4:
3101                 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3102                 break;
3103         default:
3104                 return -1;
3105         }
3106
3107         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3108         return 0;
3109 }
3110
3111
3112 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3113 {
3114         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3115         int change;
3116         int val;
3117
3118         if (!snd_hdsp_use_is_exclusive(hdsp))
3119                 return -EBUSY;
3120         val = ucontrol->value.enumerated.item[0];
3121         if (val < 0)
3122                 val = 0;
3123         if (val > 4)
3124                 val = 4;
3125         spin_lock_irq(&hdsp->lock);
3126         if (val != hdsp_rpm_input34(hdsp))
3127                 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3128         else
3129                 change = 0;
3130         spin_unlock_irq(&hdsp->lock);
3131         return change;
3132 }
3133
3134
3135 /* RPM Bypass switch */
3136 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3137 {
3138         return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3139 }
3140
3141
3142 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3143 {
3144         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3145
3146         ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3147         return 0;
3148 }
3149
3150
3151 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3152 {
3153         if (on)
3154                 hdsp->control_register |= HDSP_RPM_Bypass;
3155         else
3156                 hdsp->control_register &= ~HDSP_RPM_Bypass;
3157         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3158         return 0;
3159 }
3160
3161
3162 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3163 {
3164         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3165         int change;
3166         unsigned int val;
3167
3168         if (!snd_hdsp_use_is_exclusive(hdsp))
3169                 return -EBUSY;
3170         val = ucontrol->value.integer.value[0] & 1;
3171         spin_lock_irq(&hdsp->lock);
3172         change = (int)val != hdsp_rpm_bypass(hdsp);
3173         hdsp_set_rpm_bypass(hdsp, val);
3174         spin_unlock_irq(&hdsp->lock);
3175         return change;
3176 }
3177
3178
3179 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3180 {
3181         static const char * const texts[] = {"On", "Off"};
3182
3183         return snd_ctl_enum_info(uinfo, 1, 2, texts);
3184 }
3185
3186
3187 /* RPM Disconnect switch */
3188 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3189 {
3190         return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3191 }
3192
3193
3194 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3195 {
3196         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3197
3198         ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3199         return 0;
3200 }
3201
3202
3203 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3204 {
3205         if (on)
3206                 hdsp->control_register |= HDSP_RPM_Disconnect;
3207         else
3208                 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3209         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3210         return 0;
3211 }
3212
3213
3214 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3215 {
3216         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3217         int change;
3218         unsigned int val;
3219
3220         if (!snd_hdsp_use_is_exclusive(hdsp))
3221                 return -EBUSY;
3222         val = ucontrol->value.integer.value[0] & 1;
3223         spin_lock_irq(&hdsp->lock);
3224         change = (int)val != hdsp_rpm_disconnect(hdsp);
3225         hdsp_set_rpm_disconnect(hdsp, val);
3226         spin_unlock_irq(&hdsp->lock);
3227         return change;
3228 }
3229
3230 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3231 {
3232         static const char * const texts[] = {"On", "Off"};
3233
3234         return snd_ctl_enum_info(uinfo, 1, 2, texts);
3235 }
3236
3237 static struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3238         {
3239                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3240                 .name = "RPM Bypass",
3241                 .get = snd_hdsp_get_rpm_bypass,
3242                 .put = snd_hdsp_put_rpm_bypass,
3243                 .info = snd_hdsp_info_rpm_bypass
3244         },
3245         {
3246                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3247                 .name = "RPM Disconnect",
3248                 .get = snd_hdsp_get_rpm_disconnect,
3249                 .put = snd_hdsp_put_rpm_disconnect,
3250                 .info = snd_hdsp_info_rpm_disconnect
3251         },
3252         {
3253                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3254                 .name = "Input 1/2",
3255                 .get = snd_hdsp_get_rpm_input12,
3256                 .put = snd_hdsp_put_rpm_input12,
3257                 .info = snd_hdsp_info_rpm_input
3258         },
3259         {
3260                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3261                 .name = "Input 3/4",
3262                 .get = snd_hdsp_get_rpm_input34,
3263                 .put = snd_hdsp_put_rpm_input34,
3264                 .info = snd_hdsp_info_rpm_input
3265         },
3266         HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3267         HDSP_MIXER("Mixer", 0)
3268 };
3269
3270 static struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3271         HDSP_TOGGLE_SETTING("Analog Extension Board",
3272                         HDSP_AnalogExtensionBoard);
3273 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3274
3275 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3276 {
3277         unsigned int idx;
3278         int err;
3279         struct snd_kcontrol *kctl;
3280
3281         if (hdsp->io_type == RPM) {
3282                 /* RPM Bypass, Disconnect and Input switches */
3283                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3284                         err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3285                         if (err < 0)
3286                                 return err;
3287                 }
3288                 return 0;
3289         }
3290
3291         for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3292                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3293                         return err;
3294                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
3295                         hdsp->spdif_ctl = kctl;
3296         }
3297
3298         /* ADAT SyncCheck status */
3299         snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3300         snd_hdsp_adat_sync_check.index = 1;
3301         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3302                 return err;
3303         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3304                 for (idx = 1; idx < 3; ++idx) {
3305                         snd_hdsp_adat_sync_check.index = idx+1;
3306                         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3307                                 return err;
3308                 }
3309         }
3310
3311         /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3312         if (hdsp->io_type == H9632) {
3313                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3314                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3315                                 return err;
3316                 }
3317         }
3318
3319         /* AEB control for H96xx card */
3320         if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3321                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3322                                 return err;
3323         }
3324
3325         return 0;
3326 }
3327
3328 /*------------------------------------------------------------
3329    /proc interface
3330  ------------------------------------------------------------*/
3331
3332 static void
3333 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3334 {
3335         struct hdsp *hdsp = entry->private_data;
3336         unsigned int status;
3337         unsigned int status2;
3338         char *pref_sync_ref;
3339         char *autosync_ref;
3340         char *system_clock_mode;
3341         char *clock_source;
3342         int x;
3343
3344         status = hdsp_read(hdsp, HDSP_statusRegister);
3345         status2 = hdsp_read(hdsp, HDSP_status2Register);
3346
3347         snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3348                     hdsp->card->number + 1);
3349         snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3350                     hdsp->capture_buffer, hdsp->playback_buffer);
3351         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3352                     hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3353         snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3354         snd_iprintf(buffer, "Control2 register: 0x%x\n",
3355                     hdsp->control2_register);
3356         snd_iprintf(buffer, "Status register: 0x%x\n", status);
3357         snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3358
3359         if (hdsp_check_for_iobox(hdsp)) {
3360                 snd_iprintf(buffer, "No I/O box connected.\n"
3361                             "Please connect one and upload firmware.\n");
3362                 return;
3363         }
3364
3365         if (hdsp_check_for_firmware(hdsp, 0)) {
3366                 if (hdsp->state & HDSP_FirmwareCached) {
3367                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3368                                 snd_iprintf(buffer, "Firmware loading from "
3369                                             "cache failed, "
3370                                             "please upload manually.\n");
3371                                 return;
3372                         }
3373                 } else {
3374                         int err = -EINVAL;
3375                         err = hdsp_request_fw_loader(hdsp);
3376                         if (err < 0) {
3377                                 snd_iprintf(buffer,
3378                                             "No firmware loaded nor cached, "
3379                                             "please upload firmware.\n");
3380                                 return;
3381                         }
3382                 }
3383         }
3384
3385         snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3386         snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3387         snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3388         snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3389         snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3390         snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3391
3392         snd_iprintf(buffer, "\n");
3393
3394         x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3395
3396         snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3397         snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3398         snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3399         snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3400
3401         snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3402
3403         snd_iprintf(buffer, "\n");
3404
3405         switch (hdsp_clock_source(hdsp)) {
3406         case HDSP_CLOCK_SOURCE_AUTOSYNC:
3407                 clock_source = "AutoSync";
3408                 break;
3409         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3410                 clock_source = "Internal 32 kHz";
3411                 break;
3412         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3413                 clock_source = "Internal 44.1 kHz";
3414                 break;
3415         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3416                 clock_source = "Internal 48 kHz";
3417                 break;
3418         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3419                 clock_source = "Internal 64 kHz";
3420                 break;
3421         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3422                 clock_source = "Internal 88.2 kHz";
3423                 break;
3424         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3425                 clock_source = "Internal 96 kHz";
3426                 break;
3427         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3428                 clock_source = "Internal 128 kHz";
3429                 break;
3430         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3431                 clock_source = "Internal 176.4 kHz";
3432                 break;
3433                 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3434                 clock_source = "Internal 192 kHz";
3435                 break;
3436         default:
3437                 clock_source = "Error";
3438         }
3439         snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3440
3441         if (hdsp_system_clock_mode(hdsp))
3442                 system_clock_mode = "Slave";
3443         else
3444                 system_clock_mode = "Master";
3445
3446         switch (hdsp_pref_sync_ref (hdsp)) {
3447         case HDSP_SYNC_FROM_WORD:
3448                 pref_sync_ref = "Word Clock";
3449                 break;
3450         case HDSP_SYNC_FROM_ADAT_SYNC:
3451                 pref_sync_ref = "ADAT Sync";
3452                 break;
3453         case HDSP_SYNC_FROM_SPDIF:
3454                 pref_sync_ref = "SPDIF";
3455                 break;
3456         case HDSP_SYNC_FROM_ADAT1:
3457                 pref_sync_ref = "ADAT1";
3458                 break;
3459         case HDSP_SYNC_FROM_ADAT2:
3460                 pref_sync_ref = "ADAT2";
3461                 break;
3462         case HDSP_SYNC_FROM_ADAT3:
3463                 pref_sync_ref = "ADAT3";
3464                 break;
3465         default:
3466                 pref_sync_ref = "Word Clock";
3467                 break;
3468         }
3469         snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3470
3471         switch (hdsp_autosync_ref (hdsp)) {
3472         case HDSP_AUTOSYNC_FROM_WORD:
3473                 autosync_ref = "Word Clock";
3474                 break;
3475         case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3476                 autosync_ref = "ADAT Sync";
3477                 break;
3478         case HDSP_AUTOSYNC_FROM_SPDIF:
3479                 autosync_ref = "SPDIF";
3480                 break;
3481         case HDSP_AUTOSYNC_FROM_NONE:
3482                 autosync_ref = "None";
3483                 break;
3484         case HDSP_AUTOSYNC_FROM_ADAT1:
3485                 autosync_ref = "ADAT1";
3486                 break;
3487         case HDSP_AUTOSYNC_FROM_ADAT2:
3488                 autosync_ref = "ADAT2";
3489                 break;
3490         case HDSP_AUTOSYNC_FROM_ADAT3:
3491                 autosync_ref = "ADAT3";
3492                 break;
3493         default:
3494                 autosync_ref = "---";
3495                 break;
3496         }
3497         snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3498
3499         snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3500
3501         snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3502
3503         snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3504         snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3505
3506         snd_iprintf(buffer, "\n");
3507
3508         if (hdsp->io_type != RPM) {
3509                 switch (hdsp_spdif_in(hdsp)) {
3510                 case HDSP_SPDIFIN_OPTICAL:
3511                         snd_iprintf(buffer, "IEC958 input: Optical\n");
3512                         break;
3513                 case HDSP_SPDIFIN_COAXIAL:
3514                         snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3515                         break;
3516                 case HDSP_SPDIFIN_INTERNAL:
3517                         snd_iprintf(buffer, "IEC958 input: Internal\n");
3518                         break;
3519                 case HDSP_SPDIFIN_AES:
3520                         snd_iprintf(buffer, "IEC958 input: AES\n");
3521                         break;
3522                 default:
3523                         snd_iprintf(buffer, "IEC958 input: ???\n");
3524                         break;
3525                 }
3526         }
3527
3528         if (RPM == hdsp->io_type) {
3529                 if (hdsp->control_register & HDSP_RPM_Bypass)
3530                         snd_iprintf(buffer, "RPM Bypass: disabled\n");
3531                 else
3532                         snd_iprintf(buffer, "RPM Bypass: enabled\n");
3533                 if (hdsp->control_register & HDSP_RPM_Disconnect)
3534                         snd_iprintf(buffer, "RPM disconnected\n");
3535                 else
3536                         snd_iprintf(buffer, "RPM connected\n");
3537
3538                 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3539                 case HDSP_RPM_Inp12_Phon_6dB:
3540                         snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3541                         break;
3542                 case HDSP_RPM_Inp12_Phon_0dB:
3543                         snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3544                         break;
3545                 case HDSP_RPM_Inp12_Phon_n6dB:
3546                         snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3547                         break;
3548                 case HDSP_RPM_Inp12_Line_0dB:
3549                         snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3550                         break;
3551                 case HDSP_RPM_Inp12_Line_n6dB:
3552                         snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3553                         break;
3554                 default:
3555                         snd_iprintf(buffer, "Input 1/2: ???\n");
3556                 }
3557
3558                 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3559                 case HDSP_RPM_Inp34_Phon_6dB:
3560                         snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3561                         break;
3562                 case HDSP_RPM_Inp34_Phon_0dB:
3563                         snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3564                         break;
3565                 case HDSP_RPM_Inp34_Phon_n6dB:
3566                         snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3567                         break;
3568                 case HDSP_RPM_Inp34_Line_0dB:
3569                         snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3570                         break;
3571                 case HDSP_RPM_Inp34_Line_n6dB:
3572                         snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3573                         break;
3574                 default:
3575                         snd_iprintf(buffer, "Input 3/4: ???\n");
3576                 }
3577
3578         } else {
3579                 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3580                         snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3581                 else
3582                         snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3583
3584                 if (hdsp->control_register & HDSP_SPDIFProfessional)
3585                         snd_iprintf(buffer, "IEC958 quality: Professional\n");
3586                 else
3587                         snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3588
3589                 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3590                         snd_iprintf(buffer, "IEC958 emphasis: on\n");
3591                 else
3592                         snd_iprintf(buffer, "IEC958 emphasis: off\n");
3593
3594                 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3595                         snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3596                 else
3597                         snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3598                 x = hdsp_spdif_sample_rate(hdsp);
3599                 if (x != 0)
3600                         snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3601                 else
3602                         snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3603         }
3604         snd_iprintf(buffer, "\n");
3605
3606         /* Sync Check */
3607         x = status & HDSP_Sync0;
3608         if (status & HDSP_Lock0)
3609                 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3610         else
3611                 snd_iprintf(buffer, "ADAT1: No Lock\n");
3612
3613         switch (hdsp->io_type) {
3614         case Digiface:
3615         case H9652:
3616                 x = status & HDSP_Sync1;
3617                 if (status & HDSP_Lock1)
3618                         snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3619                 else
3620                         snd_iprintf(buffer, "ADAT2: No Lock\n");
3621                 x = status & HDSP_Sync2;
3622                 if (status & HDSP_Lock2)
3623                         snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3624                 else
3625                         snd_iprintf(buffer, "ADAT3: No Lock\n");
3626                 break;
3627         default:
3628                 /* relax */
3629                 break;
3630         }
3631
3632         x = status & HDSP_SPDIFSync;
3633         if (status & HDSP_SPDIFErrorFlag)
3634                 snd_iprintf (buffer, "SPDIF: No Lock\n");
3635         else
3636                 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3637
3638         x = status2 & HDSP_wc_sync;
3639         if (status2 & HDSP_wc_lock)
3640                 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3641         else
3642                 snd_iprintf (buffer, "Word Clock: No Lock\n");
3643
3644         x = status & HDSP_TimecodeSync;
3645         if (status & HDSP_TimecodeLock)
3646                 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3647         else
3648                 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3649
3650         snd_iprintf(buffer, "\n");
3651
3652         /* Informations about H9632 specific controls */
3653         if (hdsp->io_type == H9632) {
3654                 char *tmp;
3655
3656                 switch (hdsp_ad_gain(hdsp)) {
3657                 case 0:
3658                         tmp = "-10 dBV";
3659                         break;
3660                 case 1:
3661                         tmp = "+4 dBu";
3662                         break;
3663                 default:
3664                         tmp = "Lo Gain";
3665                         break;
3666                 }
3667                 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3668
3669                 switch (hdsp_da_gain(hdsp)) {
3670                 case 0:
3671                         tmp = "Hi Gain";
3672                         break;
3673                 case 1:
3674                         tmp = "+4 dBu";
3675                         break;
3676                 default:
3677                         tmp = "-10 dBV";
3678                         break;
3679                 }
3680                 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3681
3682                 switch (hdsp_phone_gain(hdsp)) {
3683                 case 0:
3684                         tmp = "0 dB";
3685                         break;
3686                 case 1:
3687                         tmp = "-6 dB";
3688                         break;
3689                 default:
3690                         tmp = "-12 dB";
3691                         break;
3692                 }
3693                 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3694
3695                 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3696                         hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3697                         "yes" : "no");
3698
3699                 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3700                         snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3701                 else
3702                         snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3703                 snd_iprintf(buffer, "\n");
3704         }
3705
3706 }
3707
3708 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3709 {
3710         struct snd_info_entry *entry;
3711
3712         if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3713                 snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read);
3714 }
3715
3716 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3717 {
3718         snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3719         snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3720 }
3721
3722 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3723 {
3724         unsigned long pb_bus, cb_bus;
3725
3726         if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3727             snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3728                 if (hdsp->capture_dma_buf.area)
3729                         snd_dma_free_pages(&hdsp->capture_dma_buf);
3730                 dev_err(hdsp->card->dev,
3731                         "%s: no buffers available\n", hdsp->card_name);
3732                 return -ENOMEM;
3733         }
3734
3735         /* Align to bus-space 64K boundary */
3736
3737         cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3738         pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3739
3740         /* Tell the card where it is */
3741
3742         hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3743         hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3744
3745         hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3746         hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3747
3748         return 0;
3749 }
3750
3751 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3752 {
3753         unsigned int i;
3754
3755         /* ASSUMPTION: hdsp->lock is either held, or
3756            there is no need to hold it (e.g. during module
3757            initialization).
3758          */
3759
3760         /* set defaults:
3761
3762            SPDIF Input via Coax
3763            Master clock mode
3764            maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3765                             which implies 2 4096 sample, 32Kbyte periods).
3766            Enable line out.
3767          */
3768
3769         hdsp->control_register = HDSP_ClockModeMaster |
3770                                  HDSP_SPDIFInputCoaxial |
3771                                  hdsp_encode_latency(7) |
3772                                  HDSP_LineOut;
3773
3774
3775         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3776
3777 #ifdef SNDRV_BIG_ENDIAN
3778         hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3779 #else
3780         hdsp->control2_register = 0;
3781 #endif
3782         if (hdsp->io_type == H9652)
3783                 snd_hdsp_9652_enable_mixer (hdsp);
3784         else
3785                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3786
3787         hdsp_reset_hw_pointer(hdsp);
3788         hdsp_compute_period_size(hdsp);
3789
3790         /* silence everything */
3791
3792         for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3793                 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3794
3795         for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3796                 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3797                         return -EIO;
3798         }
3799
3800         /* H9632 specific defaults */
3801         if (hdsp->io_type == H9632) {
3802                 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3803                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3804         }
3805
3806         /* set a default rate so that the channel map is set up.
3807          */
3808
3809         hdsp_set_rate(hdsp, 48000, 1);
3810
3811         return 0;
3812 }
3813
3814 static void hdsp_midi_tasklet(unsigned long arg)
3815 {
3816         struct hdsp *hdsp = (struct hdsp *)arg;
3817
3818         if (hdsp->midi[0].pending)
3819                 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3820         if (hdsp->midi[1].pending)
3821                 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3822 }
3823
3824 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3825 {
3826         struct hdsp *hdsp = (struct hdsp *) dev_id;
3827         unsigned int status;
3828         int audio;
3829         int midi0;
3830         int midi1;
3831         unsigned int midi0status;
3832         unsigned int midi1status;
3833         int schedule = 0;
3834
3835         status = hdsp_read(hdsp, HDSP_statusRegister);
3836
3837         audio = status & HDSP_audioIRQPending;
3838         midi0 = status & HDSP_midi0IRQPending;
3839         midi1 = status & HDSP_midi1IRQPending;
3840
3841         if (!audio && !midi0 && !midi1)
3842                 return IRQ_NONE;
3843
3844         hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3845
3846         midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3847         midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3848
3849         if (!(hdsp->state & HDSP_InitializationComplete))
3850                 return IRQ_HANDLED;
3851
3852         if (audio) {
3853                 if (hdsp->capture_substream)
3854                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3855
3856                 if (hdsp->playback_substream)
3857                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3858         }
3859
3860         if (midi0 && midi0status) {
3861                 if (hdsp->use_midi_tasklet) {
3862                         /* we disable interrupts for this input until processing is done */
3863                         hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3864                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3865                         hdsp->midi[0].pending = 1;
3866                         schedule = 1;
3867                 } else {
3868                         snd_hdsp_midi_input_read (&hdsp->midi[0]);
3869                 }
3870         }
3871         if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3872                 if (hdsp->use_midi_tasklet) {
3873                         /* we disable interrupts for this input until processing is done */
3874                         hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3875                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3876                         hdsp->midi[1].pending = 1;
3877                         schedule = 1;
3878                 } else {
3879                         snd_hdsp_midi_input_read (&hdsp->midi[1]);
3880                 }
3881         }
3882         if (hdsp->use_midi_tasklet && schedule)
3883                 tasklet_schedule(&hdsp->midi_tasklet);
3884         return IRQ_HANDLED;
3885 }
3886
3887 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3888 {
3889         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3890         return hdsp_hw_pointer(hdsp);
3891 }
3892
3893 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3894                                              int stream,
3895                                              int channel)
3896
3897 {
3898         int mapped_channel;
3899
3900         if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3901                 return NULL;
3902
3903         if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3904                 return NULL;
3905
3906         if (stream == SNDRV_PCM_STREAM_CAPTURE)
3907                 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3908         else
3909                 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3910 }
3911
3912 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream,
3913                                   int channel, unsigned long pos,
3914                                   void __user *src, unsigned long count)
3915 {
3916         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3917         char *channel_buf;
3918
3919         if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3920                 return -EINVAL;
3921
3922         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3923         if (snd_BUG_ON(!channel_buf))
3924                 return -EIO;
3925         if (copy_from_user(channel_buf + pos, src, count))
3926                 return -EFAULT;
3927         return 0;
3928 }
3929
3930 static int snd_hdsp_playback_copy_kernel(struct snd_pcm_substream *substream,
3931                                          int channel, unsigned long pos,
3932                                          void *src, unsigned long count)
3933 {
3934         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3935         char *channel_buf;
3936
3937         channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3938         if (snd_BUG_ON(!channel_buf))
3939                 return -EIO;
3940         memcpy(channel_buf + pos, src, count);
3941         return 0;
3942 }
3943
3944 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream,
3945                                  int channel, unsigned long pos,
3946                                  void __user *dst, unsigned long count)
3947 {
3948         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3949         char *channel_buf;
3950
3951         if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3952                 return -EINVAL;
3953
3954         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3955         if (snd_BUG_ON(!channel_buf))
3956                 return -EIO;
3957         if (copy_to_user(dst, channel_buf + pos, count))
3958                 return -EFAULT;
3959         return 0;
3960 }
3961
3962 static int snd_hdsp_capture_copy_kernel(struct snd_pcm_substream *substream,
3963                                         int channel, unsigned long pos,
3964                                         void *dst, unsigned long count)
3965 {
3966         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3967         char *channel_buf;
3968
3969         channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3970         if (snd_BUG_ON(!channel_buf))
3971                 return -EIO;
3972         memcpy(dst, channel_buf + pos, count);
3973         return 0;
3974 }
3975
3976 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream,
3977                                int channel, unsigned long pos,
3978                                unsigned long count)
3979 {
3980         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3981         char *channel_buf;
3982
3983         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3984         if (snd_BUG_ON(!channel_buf))
3985                 return -EIO;
3986         memset(channel_buf + pos, 0, count);
3987         return 0;
3988 }
3989
3990 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
3991 {
3992         struct snd_pcm_runtime *runtime = substream->runtime;
3993         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3994         struct snd_pcm_substream *other;
3995         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3996                 other = hdsp->capture_substream;
3997         else
3998                 other = hdsp->playback_substream;
3999         if (hdsp->running)
4000                 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
4001         else
4002                 runtime->status->hw_ptr = 0;
4003         if (other) {
4004                 struct snd_pcm_substream *s;
4005                 struct snd_pcm_runtime *oruntime = other->runtime;
4006                 snd_pcm_group_for_each_entry(s, substream) {
4007                         if (s == other) {
4008                                 oruntime->status->hw_ptr = runtime->status->hw_ptr;
4009                                 break;
4010                         }
4011                 }
4012         }
4013         return 0;
4014 }
4015
4016 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
4017                                  struct snd_pcm_hw_params *params)
4018 {
4019         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4020         int err;
4021         pid_t this_pid;
4022         pid_t other_pid;
4023
4024         if (hdsp_check_for_iobox (hdsp))
4025                 return -EIO;
4026
4027         if (hdsp_check_for_firmware(hdsp, 1))
4028                 return -EIO;
4029
4030         spin_lock_irq(&hdsp->lock);
4031
4032         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4033                 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4034                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4035                 this_pid = hdsp->playback_pid;
4036                 other_pid = hdsp->capture_pid;
4037         } else {
4038                 this_pid = hdsp->capture_pid;
4039                 other_pid = hdsp->playback_pid;
4040         }
4041
4042         if ((other_pid > 0) && (this_pid != other_pid)) {
4043
4044                 /* The other stream is open, and not by the same
4045                    task as this one. Make sure that the parameters
4046                    that matter are the same.
4047                  */
4048
4049                 if (params_rate(params) != hdsp->system_sample_rate) {
4050                         spin_unlock_irq(&hdsp->lock);
4051                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4052                         return -EBUSY;
4053                 }
4054
4055                 if (params_period_size(params) != hdsp->period_bytes / 4) {
4056                         spin_unlock_irq(&hdsp->lock);
4057                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4058                         return -EBUSY;
4059                 }
4060
4061                 /* We're fine. */
4062
4063                 spin_unlock_irq(&hdsp->lock);
4064                 return 0;
4065
4066         } else {
4067                 spin_unlock_irq(&hdsp->lock);
4068         }
4069
4070         /* how to make sure that the rate matches an externally-set one ?
4071          */
4072
4073         spin_lock_irq(&hdsp->lock);
4074         if (! hdsp->clock_source_locked) {
4075                 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
4076                         spin_unlock_irq(&hdsp->lock);
4077                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4078                         return err;
4079                 }
4080         }
4081         spin_unlock_irq(&hdsp->lock);
4082
4083         if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
4084                 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4085                 return err;
4086         }
4087
4088         return 0;
4089 }
4090
4091 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4092                                     struct snd_pcm_channel_info *info)
4093 {
4094         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4095         int mapped_channel;
4096
4097         if (snd_BUG_ON(info->channel >= hdsp->max_channels))
4098                 return -EINVAL;
4099
4100         if ((mapped_channel = hdsp->channel_map[info->channel]) < 0)
4101                 return -EINVAL;
4102
4103         info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
4104         info->first = 0;
4105         info->step = 32;
4106         return 0;
4107 }
4108
4109 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4110                              unsigned int cmd, void *arg)
4111 {
4112         switch (cmd) {
4113         case SNDRV_PCM_IOCTL1_RESET:
4114                 return snd_hdsp_reset(substream);
4115         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4116                 return snd_hdsp_channel_info(substream, arg);
4117         default:
4118                 break;
4119         }
4120
4121         return snd_pcm_lib_ioctl(substream, cmd, arg);
4122 }
4123
4124 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4125 {
4126         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4127         struct snd_pcm_substream *other;
4128         int running;
4129
4130         if (hdsp_check_for_iobox (hdsp))
4131                 return -EIO;
4132
4133         if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4134                 return -EIO;
4135
4136         spin_lock(&hdsp->lock);
4137         running = hdsp->running;
4138         switch (cmd) {
4139         case SNDRV_PCM_TRIGGER_START:
4140                 running |= 1 << substream->stream;
4141                 break;
4142         case SNDRV_PCM_TRIGGER_STOP:
4143                 running &= ~(1 << substream->stream);
4144                 break;
4145         default:
4146                 snd_BUG();
4147                 spin_unlock(&hdsp->lock);
4148                 return -EINVAL;
4149         }
4150         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4151                 other = hdsp->capture_substream;
4152         else
4153                 other = hdsp->playback_substream;
4154
4155         if (other) {
4156                 struct snd_pcm_substream *s;
4157                 snd_pcm_group_for_each_entry(s, substream) {
4158                         if (s == other) {
4159                                 snd_pcm_trigger_done(s, substream);
4160                                 if (cmd == SNDRV_PCM_TRIGGER_START)
4161                                         running |= 1 << s->stream;
4162                                 else
4163                                         running &= ~(1 << s->stream);
4164                                 goto _ok;
4165                         }
4166                 }
4167                 if (cmd == SNDRV_PCM_TRIGGER_START) {
4168                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4169                             substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4170                                 hdsp_silence_playback(hdsp);
4171                 } else {
4172                         if (running &&
4173                             substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4174                                 hdsp_silence_playback(hdsp);
4175                 }
4176         } else {
4177                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4178                                 hdsp_silence_playback(hdsp);
4179         }
4180  _ok:
4181         snd_pcm_trigger_done(substream, substream);
4182         if (!hdsp->running && running)
4183                 hdsp_start_audio(hdsp);
4184         else if (hdsp->running && !running)
4185                 hdsp_stop_audio(hdsp);
4186         hdsp->running = running;
4187         spin_unlock(&hdsp->lock);
4188
4189         return 0;
4190 }
4191
4192 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4193 {
4194         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4195         int result = 0;
4196
4197         if (hdsp_check_for_iobox (hdsp))
4198                 return -EIO;
4199
4200         if (hdsp_check_for_firmware(hdsp, 1))
4201                 return -EIO;
4202
4203         spin_lock_irq(&hdsp->lock);
4204         if (!hdsp->running)
4205                 hdsp_reset_hw_pointer(hdsp);
4206         spin_unlock_irq(&hdsp->lock);
4207         return result;
4208 }
4209
4210 static const struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4211 {
4212         .info =                 (SNDRV_PCM_INFO_MMAP |
4213                                  SNDRV_PCM_INFO_MMAP_VALID |
4214                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4215                                  SNDRV_PCM_INFO_SYNC_START |
4216                                  SNDRV_PCM_INFO_DOUBLE),
4217 #ifdef SNDRV_BIG_ENDIAN
4218         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4219 #else
4220         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4221 #endif
4222         .rates =                (SNDRV_PCM_RATE_32000 |
4223                                  SNDRV_PCM_RATE_44100 |
4224                                  SNDRV_PCM_RATE_48000 |
4225                                  SNDRV_PCM_RATE_64000 |
4226                                  SNDRV_PCM_RATE_88200 |
4227                                  SNDRV_PCM_RATE_96000),
4228         .rate_min =             32000,
4229         .rate_max =             96000,
4230         .channels_min =         6,
4231         .channels_max =         HDSP_MAX_CHANNELS,
4232         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4233         .period_bytes_min =     (64 * 4) * 10,
4234         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4235         .periods_min =          2,
4236         .periods_max =          2,
4237         .fifo_size =            0
4238 };
4239
4240 static const struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4241 {
4242         .info =                 (SNDRV_PCM_INFO_MMAP |
4243                                  SNDRV_PCM_INFO_MMAP_VALID |
4244                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4245                                  SNDRV_PCM_INFO_SYNC_START),
4246 #ifdef SNDRV_BIG_ENDIAN
4247         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4248 #else
4249         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4250 #endif
4251         .rates =                (SNDRV_PCM_RATE_32000 |
4252                                  SNDRV_PCM_RATE_44100 |
4253                                  SNDRV_PCM_RATE_48000 |
4254                                  SNDRV_PCM_RATE_64000 |
4255                                  SNDRV_PCM_RATE_88200 |
4256                                  SNDRV_PCM_RATE_96000),
4257         .rate_min =             32000,
4258         .rate_max =             96000,
4259         .channels_min =         5,
4260         .channels_max =         HDSP_MAX_CHANNELS,
4261         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4262         .period_bytes_min =     (64 * 4) * 10,
4263         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4264         .periods_min =          2,
4265         .periods_max =          2,
4266         .fifo_size =            0
4267 };
4268
4269 static const unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4270
4271 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4272         .count = ARRAY_SIZE(hdsp_period_sizes),
4273         .list = hdsp_period_sizes,
4274         .mask = 0
4275 };
4276
4277 static const unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4278
4279 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4280         .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4281         .list = hdsp_9632_sample_rates,
4282         .mask = 0
4283 };
4284
4285 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4286                                         struct snd_pcm_hw_rule *rule)
4287 {
4288         struct hdsp *hdsp = rule->private;
4289         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4290         if (hdsp->io_type == H9632) {
4291                 unsigned int list[3];
4292                 list[0] = hdsp->qs_in_channels;
4293                 list[1] = hdsp->ds_in_channels;
4294                 list[2] = hdsp->ss_in_channels;
4295                 return snd_interval_list(c, 3, list, 0);
4296         } else {
4297                 unsigned int list[2];
4298                 list[0] = hdsp->ds_in_channels;
4299                 list[1] = hdsp->ss_in_channels;
4300                 return snd_interval_list(c, 2, list, 0);
4301         }
4302 }
4303
4304 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4305                                         struct snd_pcm_hw_rule *rule)
4306 {
4307         unsigned int list[3];
4308         struct hdsp *hdsp = rule->private;
4309         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4310         if (hdsp->io_type == H9632) {
4311                 list[0] = hdsp->qs_out_channels;
4312                 list[1] = hdsp->ds_out_channels;
4313                 list[2] = hdsp->ss_out_channels;
4314                 return snd_interval_list(c, 3, list, 0);
4315         } else {
4316                 list[0] = hdsp->ds_out_channels;
4317                 list[1] = hdsp->ss_out_channels;
4318         }
4319         return snd_interval_list(c, 2, list, 0);
4320 }
4321
4322 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4323                                              struct snd_pcm_hw_rule *rule)
4324 {
4325         struct hdsp *hdsp = rule->private;
4326         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4327         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4328         if (r->min > 96000 && hdsp->io_type == H9632) {
4329                 struct snd_interval t = {
4330                         .min = hdsp->qs_in_channels,
4331                         .max = hdsp->qs_in_channels,
4332                         .integer = 1,
4333                 };
4334                 return snd_interval_refine(c, &t);
4335         } else if (r->min > 48000 && r->max <= 96000) {
4336                 struct snd_interval t = {
4337                         .min = hdsp->ds_in_channels,
4338                         .max = hdsp->ds_in_channels,
4339                         .integer = 1,
4340                 };
4341                 return snd_interval_refine(c, &t);
4342         } else if (r->max < 64000) {
4343                 struct snd_interval t = {
4344                         .min = hdsp->ss_in_channels,
4345                         .max = hdsp->ss_in_channels,
4346                         .integer = 1,
4347                 };
4348                 return snd_interval_refine(c, &t);
4349         }
4350         return 0;
4351 }
4352
4353 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4354                                              struct snd_pcm_hw_rule *rule)
4355 {
4356         struct hdsp *hdsp = rule->private;
4357         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4358         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4359         if (r->min > 96000 && hdsp->io_type == H9632) {
4360                 struct snd_interval t = {
4361                         .min = hdsp->qs_out_channels,
4362                         .max = hdsp->qs_out_channels,
4363                         .integer = 1,
4364                 };
4365                 return snd_interval_refine(c, &t);
4366         } else if (r->min > 48000 && r->max <= 96000) {
4367                 struct snd_interval t = {
4368                         .min = hdsp->ds_out_channels,
4369                         .max = hdsp->ds_out_channels,
4370                         .integer = 1,
4371                 };
4372                 return snd_interval_refine(c, &t);
4373         } else if (r->max < 64000) {
4374                 struct snd_interval t = {
4375                         .min = hdsp->ss_out_channels,
4376                         .max = hdsp->ss_out_channels,
4377                         .integer = 1,
4378                 };
4379                 return snd_interval_refine(c, &t);
4380         }
4381         return 0;
4382 }
4383
4384 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4385                                              struct snd_pcm_hw_rule *rule)
4386 {
4387         struct hdsp *hdsp = rule->private;
4388         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4389         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4390         if (c->min >= hdsp->ss_out_channels) {
4391                 struct snd_interval t = {
4392                         .min = 32000,
4393                         .max = 48000,
4394                         .integer = 1,
4395                 };
4396                 return snd_interval_refine(r, &t);
4397         } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4398                 struct snd_interval t = {
4399                         .min = 128000,
4400                         .max = 192000,
4401                         .integer = 1,
4402                 };
4403                 return snd_interval_refine(r, &t);
4404         } else if (c->max <= hdsp->ds_out_channels) {
4405                 struct snd_interval t = {
4406                         .min = 64000,
4407                         .max = 96000,
4408                         .integer = 1,
4409                 };
4410                 return snd_interval_refine(r, &t);
4411         }
4412         return 0;
4413 }
4414
4415 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4416                                              struct snd_pcm_hw_rule *rule)
4417 {
4418         struct hdsp *hdsp = rule->private;
4419         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4420         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4421         if (c->min >= hdsp->ss_in_channels) {
4422                 struct snd_interval t = {
4423                         .min = 32000,
4424                         .max = 48000,
4425                         .integer = 1,
4426                 };
4427                 return snd_interval_refine(r, &t);
4428         } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4429                 struct snd_interval t = {
4430                         .min = 128000,
4431                         .max = 192000,
4432                         .integer = 1,
4433                 };
4434                 return snd_interval_refine(r, &t);
4435         } else if (c->max <= hdsp->ds_in_channels) {
4436                 struct snd_interval t = {
4437                         .min = 64000,
4438                         .max = 96000,
4439                         .integer = 1,
4440                 };
4441                 return snd_interval_refine(r, &t);
4442         }
4443         return 0;
4444 }
4445
4446 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4447 {
4448         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4449         struct snd_pcm_runtime *runtime = substream->runtime;
4450
4451         if (hdsp_check_for_iobox (hdsp))
4452                 return -EIO;
4453
4454         if (hdsp_check_for_firmware(hdsp, 1))
4455                 return -EIO;
4456
4457         spin_lock_irq(&hdsp->lock);
4458
4459         snd_pcm_set_sync(substream);
4460
4461         runtime->hw = snd_hdsp_playback_subinfo;
4462         runtime->dma_area = hdsp->playback_buffer;
4463         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4464
4465         hdsp->playback_pid = current->pid;
4466         hdsp->playback_substream = substream;
4467
4468         spin_unlock_irq(&hdsp->lock);
4469
4470         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4471         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4472         if (hdsp->clock_source_locked) {
4473                 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4474         } else if (hdsp->io_type == H9632) {
4475                 runtime->hw.rate_max = 192000;
4476                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4477                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4478         }
4479         if (hdsp->io_type == H9632) {
4480                 runtime->hw.channels_min = hdsp->qs_out_channels;
4481                 runtime->hw.channels_max = hdsp->ss_out_channels;
4482         }
4483
4484         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4485                              snd_hdsp_hw_rule_out_channels, hdsp,
4486                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4487         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4488                              snd_hdsp_hw_rule_out_channels_rate, hdsp,
4489                              SNDRV_PCM_HW_PARAM_RATE, -1);
4490         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4491                              snd_hdsp_hw_rule_rate_out_channels, hdsp,
4492                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4493
4494         if (RPM != hdsp->io_type) {
4495                 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4496                 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4497                 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4498                         SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4499         }
4500         return 0;
4501 }
4502
4503 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4504 {
4505         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4506
4507         spin_lock_irq(&hdsp->lock);
4508
4509         hdsp->playback_pid = -1;
4510         hdsp->playback_substream = NULL;
4511
4512         spin_unlock_irq(&hdsp->lock);
4513
4514         if (RPM != hdsp->io_type) {
4515                 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4516                 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4517                         SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4518         }
4519         return 0;
4520 }
4521
4522
4523 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4524 {
4525         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4526         struct snd_pcm_runtime *runtime = substream->runtime;
4527
4528         if (hdsp_check_for_iobox (hdsp))
4529                 return -EIO;
4530
4531         if (hdsp_check_for_firmware(hdsp, 1))
4532                 return -EIO;
4533
4534         spin_lock_irq(&hdsp->lock);
4535
4536         snd_pcm_set_sync(substream);
4537
4538         runtime->hw = snd_hdsp_capture_subinfo;
4539         runtime->dma_area = hdsp->capture_buffer;
4540         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4541
4542         hdsp->capture_pid = current->pid;
4543         hdsp->capture_substream = substream;
4544
4545         spin_unlock_irq(&hdsp->lock);
4546
4547         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4548         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4549         if (hdsp->io_type == H9632) {
4550                 runtime->hw.channels_min = hdsp->qs_in_channels;
4551                 runtime->hw.channels_max = hdsp->ss_in_channels;
4552                 runtime->hw.rate_max = 192000;
4553                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4554                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4555         }
4556         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4557                              snd_hdsp_hw_rule_in_channels, hdsp,
4558                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4559         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4560                              snd_hdsp_hw_rule_in_channels_rate, hdsp,
4561                              SNDRV_PCM_HW_PARAM_RATE, -1);
4562         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4563                              snd_hdsp_hw_rule_rate_in_channels, hdsp,
4564                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4565         return 0;
4566 }
4567
4568 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4569 {
4570         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4571
4572         spin_lock_irq(&hdsp->lock);
4573
4574         hdsp->capture_pid = -1;
4575         hdsp->capture_substream = NULL;
4576
4577         spin_unlock_irq(&hdsp->lock);
4578         return 0;
4579 }
4580
4581 /* helper functions for copying meter values */
4582 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4583 {
4584         u32 val = readl(src);
4585         return copy_to_user(dest, &val, 4);
4586 }
4587
4588 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4589 {
4590         u32 rms_low, rms_high;
4591         u64 rms;
4592         rms_low = readl(src_low);
4593         rms_high = readl(src_high);
4594         rms = ((u64)rms_high << 32) | rms_low;
4595         return copy_to_user(dest, &rms, 8);
4596 }
4597
4598 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4599 {
4600         u32 rms_low, rms_high;
4601         u64 rms;
4602         rms_low = readl(src_low) & 0xffffff00;
4603         rms_high = readl(src_high) & 0xffffff00;
4604         rms = ((u64)rms_high << 32) | rms_low;
4605         return copy_to_user(dest, &rms, 8);
4606 }
4607
4608 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4609 {
4610         int doublespeed = 0;
4611         int i, j, channels, ofs;
4612
4613         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4614                 doublespeed = 1;
4615         channels = doublespeed ? 14 : 26;
4616         for (i = 0, j = 0; i < 26; ++i) {
4617                 if (doublespeed && (i & 4))
4618                         continue;
4619                 ofs = HDSP_9652_peakBase - j * 4;
4620                 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4621                         return -EFAULT;
4622                 ofs -= channels * 4;
4623                 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4624                         return -EFAULT;
4625                 ofs -= channels * 4;
4626                 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4627                         return -EFAULT;
4628                 ofs = HDSP_9652_rmsBase + j * 8;
4629                 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4630                                 hdsp->iobase + ofs + 4))
4631                         return -EFAULT;
4632                 ofs += channels * 8;
4633                 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4634                                 hdsp->iobase + ofs + 4))
4635                         return -EFAULT;
4636                 ofs += channels * 8;
4637                 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4638                                 hdsp->iobase + ofs + 4))
4639                         return -EFAULT;
4640                 j++;
4641         }
4642         return 0;
4643 }
4644
4645 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4646 {
4647         int i, j;
4648         struct hdsp_9632_meters __iomem *m;
4649         int doublespeed = 0;
4650
4651         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4652                 doublespeed = 1;
4653         m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4654         for (i = 0, j = 0; i < 16; ++i, ++j) {
4655                 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4656                         return -EFAULT;
4657                 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4658                         return -EFAULT;
4659                 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4660                         return -EFAULT;
4661                 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4662                                 &m->input_rms_high[j]))
4663                         return -EFAULT;
4664                 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4665                                 &m->playback_rms_high[j]))
4666                         return -EFAULT;
4667                 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4668                                 &m->output_rms_high[j]))
4669                         return -EFAULT;
4670                 if (doublespeed && i == 3) i += 4;
4671         }
4672         return 0;
4673 }
4674
4675 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4676 {
4677         int i;
4678
4679         for (i = 0; i < 26; i++) {
4680                 if (copy_u32_le(&peak_rms->playback_peaks[i],
4681                                 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4682                         return -EFAULT;
4683                 if (copy_u32_le(&peak_rms->input_peaks[i],
4684                                 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4685                         return -EFAULT;
4686         }
4687         for (i = 0; i < 28; i++) {
4688                 if (copy_u32_le(&peak_rms->output_peaks[i],
4689                                 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4690                         return -EFAULT;
4691         }
4692         for (i = 0; i < 26; ++i) {
4693                 if (copy_u64_le(&peak_rms->playback_rms[i],
4694                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4695                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4696                         return -EFAULT;
4697                 if (copy_u64_le(&peak_rms->input_rms[i],
4698                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4699                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4700                         return -EFAULT;
4701         }
4702         return 0;
4703 }
4704
4705 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4706 {
4707         struct hdsp *hdsp = hw->private_data;
4708         void __user *argp = (void __user *)arg;
4709         int err;
4710
4711         switch (cmd) {
4712         case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4713                 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4714
4715                 err = hdsp_check_for_iobox(hdsp);
4716                 if (err < 0)
4717                         return err;
4718
4719                 err = hdsp_check_for_firmware(hdsp, 1);
4720                 if (err < 0)
4721                         return err;
4722
4723                 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4724                         dev_err(hdsp->card->dev,
4725                                 "firmware needs to be uploaded to the card.\n");
4726                         return -EINVAL;
4727                 }
4728
4729                 switch (hdsp->io_type) {
4730                 case H9652:
4731                         return hdsp_9652_get_peak(hdsp, peak_rms);
4732                 case H9632:
4733                         return hdsp_9632_get_peak(hdsp, peak_rms);
4734                 default:
4735                         return hdsp_get_peak(hdsp, peak_rms);
4736                 }
4737         }
4738         case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4739                 struct hdsp_config_info info;
4740                 unsigned long flags;
4741                 int i;
4742
4743                 err = hdsp_check_for_iobox(hdsp);
4744                 if (err < 0)
4745                         return err;
4746
4747                 err = hdsp_check_for_firmware(hdsp, 1);
4748                 if (err < 0)
4749                         return err;
4750
4751                 memset(&info, 0, sizeof(info));
4752                 spin_lock_irqsave(&hdsp->lock, flags);
4753                 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4754                 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4755                 if (hdsp->io_type != H9632)
4756                     info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4757                 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4758                 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4759                         info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4760                 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4761                 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4762                                 HDSP_SPDIFOpticalOut);
4763                 info.spdif_professional = (unsigned char)
4764                         hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4765                 info.spdif_emphasis = (unsigned char)
4766                         hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4767                 info.spdif_nonaudio = (unsigned char)
4768                         hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4769                 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4770                 info.system_sample_rate = hdsp->system_sample_rate;
4771                 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4772                 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4773                 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4774                 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4775                 info.line_out = (unsigned char)
4776                         hdsp_toggle_setting(hdsp, HDSP_LineOut);
4777                 if (hdsp->io_type == H9632) {
4778                         info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4779                         info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4780                         info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4781                         info.xlr_breakout_cable =
4782                                 (unsigned char)hdsp_toggle_setting(hdsp,
4783                                         HDSP_XLRBreakoutCable);
4784
4785                 } else if (hdsp->io_type == RPM) {
4786                         info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4787                         info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4788                 }
4789                 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4790                         info.analog_extension_board =
4791                                 (unsigned char)hdsp_toggle_setting(hdsp,
4792                                             HDSP_AnalogExtensionBoard);
4793                 spin_unlock_irqrestore(&hdsp->lock, flags);
4794                 if (copy_to_user(argp, &info, sizeof(info)))
4795                         return -EFAULT;
4796                 break;
4797         }
4798         case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4799                 struct hdsp_9632_aeb h9632_aeb;
4800
4801                 if (hdsp->io_type != H9632) return -EINVAL;
4802                 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4803                 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4804                 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4805                         return -EFAULT;
4806                 break;
4807         }
4808         case SNDRV_HDSP_IOCTL_GET_VERSION: {
4809                 struct hdsp_version hdsp_version;
4810                 int err;
4811
4812                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4813                 if (hdsp->io_type == Undefined) {
4814                         if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4815                                 return err;
4816                 }
4817                 memset(&hdsp_version, 0, sizeof(hdsp_version));
4818                 hdsp_version.io_type = hdsp->io_type;
4819                 hdsp_version.firmware_rev = hdsp->firmware_rev;
4820                 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4821                         return -EFAULT;
4822                 break;
4823         }
4824         case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4825                 struct hdsp_firmware __user *firmware;
4826                 u32 __user *firmware_data;
4827                 int err;
4828
4829                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4830                 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4831                 if (hdsp->io_type == Undefined) return -EINVAL;
4832
4833                 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4834                         return -EBUSY;
4835
4836                 dev_info(hdsp->card->dev,
4837                          "initializing firmware upload\n");
4838                 firmware = (struct hdsp_firmware __user *)argp;
4839
4840                 if (get_user(firmware_data, &firmware->firmware_data))
4841                         return -EFAULT;
4842
4843                 if (hdsp_check_for_iobox (hdsp))
4844                         return -EIO;
4845
4846                 if (!hdsp->fw_uploaded) {
4847                         hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4848                         if (!hdsp->fw_uploaded)
4849                                 return -ENOMEM;
4850                 }
4851
4852                 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4853                                    HDSP_FIRMWARE_SIZE)) {
4854                         vfree(hdsp->fw_uploaded);
4855                         hdsp->fw_uploaded = NULL;
4856                         return -EFAULT;
4857                 }
4858
4859                 hdsp->state |= HDSP_FirmwareCached;
4860
4861                 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4862                         return err;
4863
4864                 if (!(hdsp->state & HDSP_InitializationComplete)) {
4865                         if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4866                                 return err;
4867
4868                         snd_hdsp_initialize_channels(hdsp);
4869                         snd_hdsp_initialize_midi_flush(hdsp);
4870
4871                         if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4872                                 dev_err(hdsp->card->dev,
4873                                         "error creating alsa devices\n");
4874                                 return err;
4875                         }
4876                 }
4877                 break;
4878         }
4879         case SNDRV_HDSP_IOCTL_GET_MIXER: {
4880                 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4881                 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4882                         return -EFAULT;
4883                 break;
4884         }
4885         default:
4886                 return -EINVAL;
4887         }
4888         return 0;
4889 }
4890
4891 static const struct snd_pcm_ops snd_hdsp_playback_ops = {
4892         .open =         snd_hdsp_playback_open,
4893         .close =        snd_hdsp_playback_release,
4894         .ioctl =        snd_hdsp_ioctl,
4895         .hw_params =    snd_hdsp_hw_params,
4896         .prepare =      snd_hdsp_prepare,
4897         .trigger =      snd_hdsp_trigger,
4898         .pointer =      snd_hdsp_hw_pointer,
4899         .copy_user =    snd_hdsp_playback_copy,
4900         .copy_kernel =  snd_hdsp_playback_copy_kernel,
4901         .fill_silence = snd_hdsp_hw_silence,
4902 };
4903
4904 static const struct snd_pcm_ops snd_hdsp_capture_ops = {
4905         .open =         snd_hdsp_capture_open,
4906         .close =        snd_hdsp_capture_release,
4907         .ioctl =        snd_hdsp_ioctl,
4908         .hw_params =    snd_hdsp_hw_params,
4909         .prepare =      snd_hdsp_prepare,
4910         .trigger =      snd_hdsp_trigger,
4911         .pointer =      snd_hdsp_hw_pointer,
4912         .copy_user =    snd_hdsp_capture_copy,
4913         .copy_kernel =  snd_hdsp_capture_copy_kernel,
4914 };
4915
4916 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4917 {
4918         struct snd_hwdep *hw;
4919         int err;
4920
4921         if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4922                 return err;
4923
4924         hdsp->hwdep = hw;
4925         hw->private_data = hdsp;
4926         strcpy(hw->name, "HDSP hwdep interface");
4927
4928         hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4929         hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4930
4931         return 0;
4932 }
4933
4934 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4935 {
4936         struct snd_pcm *pcm;
4937         int err;
4938
4939         if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4940                 return err;
4941
4942         hdsp->pcm = pcm;
4943         pcm->private_data = hdsp;
4944         strcpy(pcm->name, hdsp->card_name);
4945
4946         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4947         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4948
4949         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4950
4951         return 0;
4952 }
4953
4954 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4955 {
4956         hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4957         hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4958 }
4959
4960 static int snd_hdsp_enable_io (struct hdsp *hdsp)
4961 {
4962         int i;
4963
4964         if (hdsp_fifo_wait (hdsp, 0, 100)) {
4965                 dev_err(hdsp->card->dev,
4966                         "enable_io fifo_wait failed\n");
4967                 return -EIO;
4968         }
4969
4970         for (i = 0; i < hdsp->max_channels; ++i) {
4971                 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4972                 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4973         }
4974
4975         return 0;
4976 }
4977
4978 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
4979 {
4980         int status, aebi_channels, aebo_channels;
4981
4982         switch (hdsp->io_type) {
4983         case Digiface:
4984                 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4985                 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4986                 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4987                 break;
4988
4989         case H9652:
4990                 hdsp->card_name = "RME Hammerfall HDSP 9652";
4991                 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4992                 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4993                 break;
4994
4995         case H9632:
4996                 status = hdsp_read(hdsp, HDSP_statusRegister);
4997                 /* HDSP_AEBx bits are low when AEB are connected */
4998                 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4999                 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
5000                 hdsp->card_name = "RME Hammerfall HDSP 9632";
5001                 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
5002                 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
5003                 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
5004                 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
5005                 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
5006                 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
5007                 break;
5008
5009         case Multiface:
5010                 hdsp->card_name = "RME Hammerfall DSP + Multiface";
5011                 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
5012                 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
5013                 break;
5014
5015         case RPM:
5016                 hdsp->card_name = "RME Hammerfall DSP + RPM";
5017                 hdsp->ss_in_channels = RPM_CHANNELS-1;
5018                 hdsp->ss_out_channels = RPM_CHANNELS;
5019                 hdsp->ds_in_channels = RPM_CHANNELS-1;
5020                 hdsp->ds_out_channels = RPM_CHANNELS;
5021                 break;
5022
5023         default:
5024                 /* should never get here */
5025                 break;
5026         }
5027 }
5028
5029 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5030 {
5031         snd_hdsp_flush_midi_input (hdsp, 0);
5032         snd_hdsp_flush_midi_input (hdsp, 1);
5033 }
5034
5035 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5036 {
5037         int err;
5038
5039         if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
5040                 dev_err(card->dev,
5041                         "Error creating pcm interface\n");
5042                 return err;
5043         }
5044
5045
5046         if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
5047                 dev_err(card->dev,
5048                         "Error creating first midi interface\n");
5049                 return err;
5050         }
5051
5052         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5053                 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
5054                         dev_err(card->dev,
5055                                 "Error creating second midi interface\n");
5056                         return err;
5057                 }
5058         }
5059
5060         if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
5061                 dev_err(card->dev,
5062                         "Error creating ctl interface\n");
5063                 return err;
5064         }
5065
5066         snd_hdsp_proc_init(hdsp);
5067
5068         hdsp->system_sample_rate = -1;
5069         hdsp->playback_pid = -1;
5070         hdsp->capture_pid = -1;
5071         hdsp->capture_substream = NULL;
5072         hdsp->playback_substream = NULL;
5073
5074         if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
5075                 dev_err(card->dev,
5076                         "Error setting default values\n");
5077                 return err;
5078         }
5079
5080         if (!(hdsp->state & HDSP_InitializationComplete)) {
5081                 strcpy(card->shortname, "Hammerfall DSP");
5082                 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5083                         hdsp->port, hdsp->irq);
5084
5085                 if ((err = snd_card_register(card)) < 0) {
5086                         dev_err(card->dev,
5087                                 "error registering card\n");
5088                         return err;
5089                 }
5090                 hdsp->state |= HDSP_InitializationComplete;
5091         }
5092
5093         return 0;
5094 }
5095
5096 /* load firmware via hotplug fw loader */
5097 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5098 {
5099         const char *fwfile;
5100         const struct firmware *fw;
5101         int err;
5102
5103         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5104                 return 0;
5105         if (hdsp->io_type == Undefined) {
5106                 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
5107                         return err;
5108                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5109                         return 0;
5110         }
5111
5112         /* caution: max length of firmware filename is 30! */
5113         switch (hdsp->io_type) {
5114         case RPM:
5115                 fwfile = "rpm_firmware.bin";
5116                 break;
5117         case Multiface:
5118                 if (hdsp->firmware_rev == 0xa)
5119                         fwfile = "multiface_firmware.bin";
5120                 else
5121                         fwfile = "multiface_firmware_rev11.bin";
5122                 break;
5123         case Digiface:
5124                 if (hdsp->firmware_rev == 0xa)
5125                         fwfile = "digiface_firmware.bin";
5126                 else
5127                         fwfile = "digiface_firmware_rev11.bin";
5128                 break;
5129         default:
5130                 dev_err(hdsp->card->dev,
5131                         "invalid io_type %d\n", hdsp->io_type);
5132                 return -EINVAL;
5133         }
5134
5135         if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5136                 dev_err(hdsp->card->dev,
5137                         "cannot load firmware %s\n", fwfile);
5138                 return -ENOENT;
5139         }
5140         if (fw->size < HDSP_FIRMWARE_SIZE) {
5141                 dev_err(hdsp->card->dev,
5142                         "too short firmware size %d (expected %d)\n",
5143                            (int)fw->size, HDSP_FIRMWARE_SIZE);
5144                 release_firmware(fw);
5145                 return -EINVAL;
5146         }
5147
5148         hdsp->firmware = fw;
5149
5150         hdsp->state |= HDSP_FirmwareCached;
5151
5152         if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
5153                 return err;
5154
5155         if (!(hdsp->state & HDSP_InitializationComplete)) {
5156                 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
5157                         return err;
5158
5159                 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
5160                         dev_err(hdsp->card->dev,
5161                                 "error creating hwdep device\n");
5162                         return err;
5163                 }
5164                 snd_hdsp_initialize_channels(hdsp);
5165                 snd_hdsp_initialize_midi_flush(hdsp);
5166                 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
5167                         dev_err(hdsp->card->dev,
5168                                 "error creating alsa devices\n");
5169                         return err;
5170                 }
5171         }
5172         return 0;
5173 }
5174
5175 static int snd_hdsp_create(struct snd_card *card,
5176                            struct hdsp *hdsp)
5177 {
5178         struct pci_dev *pci = hdsp->pci;
5179         int err;
5180         int is_9652 = 0;
5181         int is_9632 = 0;
5182
5183         hdsp->irq = -1;
5184         hdsp->state = 0;
5185         hdsp->midi[0].rmidi = NULL;
5186         hdsp->midi[1].rmidi = NULL;
5187         hdsp->midi[0].input = NULL;
5188         hdsp->midi[1].input = NULL;
5189         hdsp->midi[0].output = NULL;
5190         hdsp->midi[1].output = NULL;
5191         hdsp->midi[0].pending = 0;
5192         hdsp->midi[1].pending = 0;
5193         spin_lock_init(&hdsp->midi[0].lock);
5194         spin_lock_init(&hdsp->midi[1].lock);
5195         hdsp->iobase = NULL;
5196         hdsp->control_register = 0;
5197         hdsp->control2_register = 0;
5198         hdsp->io_type = Undefined;
5199         hdsp->max_channels = 26;
5200
5201         hdsp->card = card;
5202
5203         spin_lock_init(&hdsp->lock);
5204
5205         tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
5206
5207         pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5208         hdsp->firmware_rev &= 0xff;
5209
5210         /* From Martin Bjoernsen :
5211             "It is important that the card's latency timer register in
5212             the PCI configuration space is set to a value much larger
5213             than 0 by the computer's BIOS or the driver.
5214             The windows driver always sets this 8 bit register [...]
5215             to its maximum 255 to avoid problems with some computers."
5216         */
5217         pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5218
5219         strcpy(card->driver, "H-DSP");
5220         strcpy(card->mixername, "Xilinx FPGA");
5221
5222         if (hdsp->firmware_rev < 0xa)
5223                 return -ENODEV;
5224         else if (hdsp->firmware_rev < 0x64)
5225                 hdsp->card_name = "RME Hammerfall DSP";
5226         else if (hdsp->firmware_rev < 0x96) {
5227                 hdsp->card_name = "RME HDSP 9652";
5228                 is_9652 = 1;
5229         } else {
5230                 hdsp->card_name = "RME HDSP 9632";
5231                 hdsp->max_channels = 16;
5232                 is_9632 = 1;
5233         }
5234
5235         if ((err = pci_enable_device(pci)) < 0)
5236                 return err;
5237
5238         pci_set_master(hdsp->pci);
5239
5240         if ((err = pci_request_regions(pci, "hdsp")) < 0)
5241                 return err;
5242         hdsp->port = pci_resource_start(pci, 0);
5243         if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5244                 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5245                         hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5246                 return -EBUSY;
5247         }
5248
5249         if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5250                         KBUILD_MODNAME, hdsp)) {
5251                 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5252                 return -EBUSY;
5253         }
5254
5255         hdsp->irq = pci->irq;
5256         hdsp->precise_ptr = 0;
5257         hdsp->use_midi_tasklet = 1;
5258         hdsp->dds_value = 0;
5259
5260         if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5261                 return err;
5262
5263         if (!is_9652 && !is_9632) {
5264                 /* we wait a maximum of 10 seconds to let freshly
5265                  * inserted cardbus cards do their hardware init */
5266                 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5267
5268                 if (err < 0)
5269                         return err;
5270
5271                 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5272                         if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5273                                 /* we don't fail as this can happen
5274                                    if userspace is not ready for
5275                                    firmware upload
5276                                 */
5277                                 dev_err(hdsp->card->dev,
5278                                         "couldn't get firmware from userspace. try using hdsploader\n");
5279                         else
5280                                 /* init is complete, we return */
5281                                 return 0;
5282                         /* we defer initialization */
5283                         dev_info(hdsp->card->dev,
5284                                  "card initialization pending : waiting for firmware\n");
5285                         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5286                                 return err;
5287                         return 0;
5288                 } else {
5289                         dev_info(hdsp->card->dev,
5290                                  "Firmware already present, initializing card.\n");
5291                         if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5292                                 hdsp->io_type = RPM;
5293                         else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5294                                 hdsp->io_type = Multiface;
5295                         else
5296                                 hdsp->io_type = Digiface;
5297                 }
5298         }
5299
5300         if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5301                 return err;
5302
5303         if (is_9652)
5304                 hdsp->io_type = H9652;
5305
5306         if (is_9632)
5307                 hdsp->io_type = H9632;
5308
5309         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5310                 return err;
5311
5312         snd_hdsp_initialize_channels(hdsp);
5313         snd_hdsp_initialize_midi_flush(hdsp);
5314
5315         hdsp->state |= HDSP_FirmwareLoaded;
5316
5317         if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5318                 return err;
5319
5320         return 0;
5321 }
5322
5323 static int snd_hdsp_free(struct hdsp *hdsp)
5324 {
5325         if (hdsp->port) {
5326                 /* stop the audio, and cancel all interrupts */
5327                 tasklet_kill(&hdsp->midi_tasklet);
5328                 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5329                 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5330         }
5331
5332         if (hdsp->irq >= 0)
5333                 free_irq(hdsp->irq, (void *)hdsp);
5334
5335         snd_hdsp_free_buffers(hdsp);
5336
5337         release_firmware(hdsp->firmware);
5338         vfree(hdsp->fw_uploaded);
5339         iounmap(hdsp->iobase);
5340
5341         if (hdsp->port)
5342                 pci_release_regions(hdsp->pci);
5343
5344         pci_disable_device(hdsp->pci);
5345         return 0;
5346 }
5347
5348 static void snd_hdsp_card_free(struct snd_card *card)
5349 {
5350         struct hdsp *hdsp = card->private_data;
5351
5352         if (hdsp)
5353                 snd_hdsp_free(hdsp);
5354 }
5355
5356 static int snd_hdsp_probe(struct pci_dev *pci,
5357                           const struct pci_device_id *pci_id)
5358 {
5359         static int dev;
5360         struct hdsp *hdsp;
5361         struct snd_card *card;
5362         int err;
5363
5364         if (dev >= SNDRV_CARDS)
5365                 return -ENODEV;
5366         if (!enable[dev]) {
5367                 dev++;
5368                 return -ENOENT;
5369         }
5370
5371         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5372                            sizeof(struct hdsp), &card);
5373         if (err < 0)
5374                 return err;
5375
5376         hdsp = card->private_data;
5377         card->private_free = snd_hdsp_card_free;
5378         hdsp->dev = dev;
5379         hdsp->pci = pci;
5380         err = snd_hdsp_create(card, hdsp);
5381         if (err)
5382                 goto free_card;
5383
5384         strcpy(card->shortname, "Hammerfall DSP");
5385         sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5386                 hdsp->port, hdsp->irq);
5387         err = snd_card_register(card);
5388         if (err) {
5389 free_card:
5390                 snd_card_free(card);
5391                 return err;
5392         }
5393         pci_set_drvdata(pci, card);
5394         dev++;
5395         return 0;
5396 }
5397
5398 static void snd_hdsp_remove(struct pci_dev *pci)
5399 {
5400         snd_card_free(pci_get_drvdata(pci));
5401 }
5402
5403 static struct pci_driver hdsp_driver = {
5404         .name =     KBUILD_MODNAME,
5405         .id_table = snd_hdsp_ids,
5406         .probe =    snd_hdsp_probe,
5407         .remove = snd_hdsp_remove,
5408 };
5409
5410 module_pci_driver(hdsp_driver);