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[PATCH] aic7xxx_osm build fix
[cris-mirror.git] / drivers / infiniband / hw / mthca / mthca_cmd.c
blobcd9ed958d92fedc8b993b24347c00d2f57336247
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 * $Id: mthca_cmd.c 1349 2004-12-16 21:09:43Z roland $
33 */
34
35 #include <linux/sched.h>
36 #include <linux/pci.h>
37 #include <linux/errno.h>
38 #include <asm/io.h>
39 #include <ib_mad.h>
40
41 #include "mthca_dev.h"
42 #include "mthca_config_reg.h"
43 #include "mthca_cmd.h"
44 #include "mthca_memfree.h"
45
46 #define CMD_POLL_TOKEN 0xffff
47
48 enum {
49 HCR_IN_PARAM_OFFSET = 0x00,
50 HCR_IN_MODIFIER_OFFSET = 0x08,
51 HCR_OUT_PARAM_OFFSET = 0x0c,
52 HCR_TOKEN_OFFSET = 0x14,
53 HCR_STATUS_OFFSET = 0x18,
54
55 HCR_OPMOD_SHIFT = 12,
56 HCA_E_BIT = 22,
57 HCR_GO_BIT = 23
58 };
59
60 enum {
61 /* initialization and general commands */
62 CMD_SYS_EN = 0x1,
63 CMD_SYS_DIS = 0x2,
64 CMD_MAP_FA = 0xfff,
65 CMD_UNMAP_FA = 0xffe,
66 CMD_RUN_FW = 0xff6,
67 CMD_MOD_STAT_CFG = 0x34,
68 CMD_QUERY_DEV_LIM = 0x3,
69 CMD_QUERY_FW = 0x4,
70 CMD_ENABLE_LAM = 0xff8,
71 CMD_DISABLE_LAM = 0xff7,
72 CMD_QUERY_DDR = 0x5,
73 CMD_QUERY_ADAPTER = 0x6,
74 CMD_INIT_HCA = 0x7,
75 CMD_CLOSE_HCA = 0x8,
76 CMD_INIT_IB = 0x9,
77 CMD_CLOSE_IB = 0xa,
78 CMD_QUERY_HCA = 0xb,
79 CMD_SET_IB = 0xc,
80 CMD_ACCESS_DDR = 0x2e,
81 CMD_MAP_ICM = 0xffa,
82 CMD_UNMAP_ICM = 0xff9,
83 CMD_MAP_ICM_AUX = 0xffc,
84 CMD_UNMAP_ICM_AUX = 0xffb,
85 CMD_SET_ICM_SIZE = 0xffd,
86
87 /* TPT commands */
88 CMD_SW2HW_MPT = 0xd,
89 CMD_QUERY_MPT = 0xe,
90 CMD_HW2SW_MPT = 0xf,
91 CMD_READ_MTT = 0x10,
92 CMD_WRITE_MTT = 0x11,
93 CMD_SYNC_TPT = 0x2f,
94
95 /* EQ commands */
96 CMD_MAP_EQ = 0x12,
97 CMD_SW2HW_EQ = 0x13,
98 CMD_HW2SW_EQ = 0x14,
99 CMD_QUERY_EQ = 0x15,
100
101 /* CQ commands */
102 CMD_SW2HW_CQ = 0x16,
103 CMD_HW2SW_CQ = 0x17,
104 CMD_QUERY_CQ = 0x18,
105 CMD_RESIZE_CQ = 0x2c,
106
107 /* SRQ commands */
108 CMD_SW2HW_SRQ = 0x35,
109 CMD_HW2SW_SRQ = 0x36,
110 CMD_QUERY_SRQ = 0x37,
111
112 /* QP/EE commands */
113 CMD_RST2INIT_QPEE = 0x19,
114 CMD_INIT2RTR_QPEE = 0x1a,
115 CMD_RTR2RTS_QPEE = 0x1b,
116 CMD_RTS2RTS_QPEE = 0x1c,
117 CMD_SQERR2RTS_QPEE = 0x1d,
118 CMD_2ERR_QPEE = 0x1e,
119 CMD_RTS2SQD_QPEE = 0x1f,
120 CMD_SQD2SQD_QPEE = 0x38,
121 CMD_SQD2RTS_QPEE = 0x20,
122 CMD_ERR2RST_QPEE = 0x21,
123 CMD_QUERY_QPEE = 0x22,
124 CMD_INIT2INIT_QPEE = 0x2d,
125 CMD_SUSPEND_QPEE = 0x32,
126 CMD_UNSUSPEND_QPEE = 0x33,
127 /* special QPs and management commands */
128 CMD_CONF_SPECIAL_QP = 0x23,
129 CMD_MAD_IFC = 0x24,
130
131 /* multicast commands */
132 CMD_READ_MGM = 0x25,
133 CMD_WRITE_MGM = 0x26,
134 CMD_MGID_HASH = 0x27,
135
136 /* miscellaneous commands */
137 CMD_DIAG_RPRT = 0x30,
138 CMD_NOP = 0x31,
139
140 /* debug commands */
141 CMD_QUERY_DEBUG_MSG = 0x2a,
142 CMD_SET_DEBUG_MSG = 0x2b,
143 };
144
145 /*
146 * According to Mellanox code, FW may be starved and never complete
147 * commands. So we can't use strict timeouts described in PRM -- we
148 * just arbitrarily select 60 seconds for now.
149 */
150 #if 0
151 /*
152 * Round up and add 1 to make sure we get the full wait time (since we
153 * will be starting in the middle of a jiffy)
154 */
155 enum {
156 CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1,
157 CMD_TIME_CLASS_B = (HZ + 99) / 100 + 1,
158 CMD_TIME_CLASS_C = (HZ + 9) / 10 + 1
159 };
160 #else
161 enum {
162 CMD_TIME_CLASS_A = 60 * HZ,
163 CMD_TIME_CLASS_B = 60 * HZ,
164 CMD_TIME_CLASS_C = 60 * HZ
165 };
166 #endif
167
168 enum {
169 GO_BIT_TIMEOUT = HZ * 10
170 };
171
172 struct mthca_cmd_context {
173 struct completion done;
174 struct timer_list timer;
175 int result;
176 int next;
177 u64 out_param;
178 u16 token;
179 u8 status;
180 };
181
182 static inline int go_bit(struct mthca_dev *dev)
183 {
184 return readl(dev->hcr + HCR_STATUS_OFFSET) &
185 swab32(1 << HCR_GO_BIT);
186 }
187
188 static int mthca_cmd_post(struct mthca_dev *dev,
189 u64 in_param,
190 u64 out_param,
191 u32 in_modifier,
192 u8 op_modifier,
193 u16 op,
194 u16 token,
195 int event)
196 {
197 int err = 0;
198
199 if (down_interruptible(&dev->cmd.hcr_sem))
200 return -EINTR;
201
202 if (event) {
203 unsigned long end = jiffies + GO_BIT_TIMEOUT;
204
205 while (go_bit(dev) && time_before(jiffies, end)) {
206 set_current_state(TASK_RUNNING);
207 schedule();
208 }
209 }
210
211 if (go_bit(dev)) {
212 err = -EAGAIN;
213 goto out;
214 }
215
216 /*
217 * We use writel (instead of something like memcpy_toio)
218 * because writes of less than 32 bits to the HCR don't work
219 * (and some architectures such as ia64 implement memcpy_toio
220 * in terms of writeb).
221 */
222 __raw_writel(cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4);
223 __raw_writel(cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4);
224 __raw_writel(cpu_to_be32(in_modifier), dev->hcr + 2 * 4);
225 __raw_writel(cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4);
226 __raw_writel(cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4);
227 __raw_writel(cpu_to_be32(token << 16), dev->hcr + 5 * 4);
228
229 /* __raw_writel may not order writes. */
230 wmb();
231
232 __raw_writel(cpu_to_be32((1 << HCR_GO_BIT) |
233 (event ? (1 << HCA_E_BIT) : 0) |
234 (op_modifier << HCR_OPMOD_SHIFT) |
235 op), dev->hcr + 6 * 4);
236
237 out:
238 up(&dev->cmd.hcr_sem);
239 return err;
240 }
241
242 static int mthca_cmd_poll(struct mthca_dev *dev,
243 u64 in_param,
244 u64 *out_param,
245 int out_is_imm,
246 u32 in_modifier,
247 u8 op_modifier,
248 u16 op,
249 unsigned long timeout,
250 u8 *status)
251 {
252 int err = 0;
253 unsigned long end;
254
255 if (down_interruptible(&dev->cmd.poll_sem))
256 return -EINTR;
257
258 err = mthca_cmd_post(dev, in_param,
259 out_param ? *out_param : 0,
260 in_modifier, op_modifier,
261 op, CMD_POLL_TOKEN, 0);
262 if (err)
263 goto out;
264
265 end = timeout + jiffies;
266 while (go_bit(dev) && time_before(jiffies, end)) {
267 set_current_state(TASK_RUNNING);
268 schedule();
269 }
270
271 if (go_bit(dev)) {
272 err = -EBUSY;
273 goto out;
274 }
275
276 if (out_is_imm) {
277 memcpy_fromio(out_param, dev->hcr + HCR_OUT_PARAM_OFFSET, sizeof (u64));
278 be64_to_cpus(out_param);
279 }
280
281 *status = be32_to_cpu(__raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24;
282
283 out:
284 up(&dev->cmd.poll_sem);
285 return err;
286 }
287
288 void mthca_cmd_event(struct mthca_dev *dev,
289 u16 token,
290 u8 status,
291 u64 out_param)
292 {
293 struct mthca_cmd_context *context =
294 &dev->cmd.context[token & dev->cmd.token_mask];
295
296 /* previously timed out command completing at long last */
297 if (token != context->token)
298 return;
299
300 context->result = 0;
301 context->status = status;
302 context->out_param = out_param;
303
304 context->token += dev->cmd.token_mask + 1;
305
306 complete(&context->done);
307 }
308
309 static void event_timeout(unsigned long context_ptr)
310 {
311 struct mthca_cmd_context *context =
312 (struct mthca_cmd_context *) context_ptr;
313
314 context->result = -EBUSY;
315 complete(&context->done);
316 }
317
318 static int mthca_cmd_wait(struct mthca_dev *dev,
319 u64 in_param,
320 u64 *out_param,
321 int out_is_imm,
322 u32 in_modifier,
323 u8 op_modifier,
324 u16 op,
325 unsigned long timeout,
326 u8 *status)
327 {
328 int err = 0;
329 struct mthca_cmd_context *context;
330
331 if (down_interruptible(&dev->cmd.event_sem))
332 return -EINTR;
333
334 spin_lock(&dev->cmd.context_lock);
335 BUG_ON(dev->cmd.free_head < 0);
336 context = &dev->cmd.context[dev->cmd.free_head];
337 dev->cmd.free_head = context->next;
338 spin_unlock(&dev->cmd.context_lock);
339
340 init_completion(&context->done);
341
342 err = mthca_cmd_post(dev, in_param,
343 out_param ? *out_param : 0,
344 in_modifier, op_modifier,
345 op, context->token, 1);
346 if (err)
347 goto out;
348
349 context->timer.expires = jiffies + timeout;
350 add_timer(&context->timer);
351
352 wait_for_completion(&context->done);
353 del_timer_sync(&context->timer);
354
355 err = context->result;
356 if (err)
357 goto out;
358
359 *status = context->status;
360 if (*status)
361 mthca_dbg(dev, "Command %02x completed with status %02x\n",
362 op, *status);
363
364 if (out_is_imm)
365 *out_param = context->out_param;
366
367 out:
368 spin_lock(&dev->cmd.context_lock);
369 context->next = dev->cmd.free_head;
370 dev->cmd.free_head = context - dev->cmd.context;
371 spin_unlock(&dev->cmd.context_lock);
372
373 up(&dev->cmd.event_sem);
374 return err;
375 }
376
377 /* Invoke a command with an output mailbox */
378 static int mthca_cmd_box(struct mthca_dev *dev,
379 u64 in_param,
380 u64 out_param,
381 u32 in_modifier,
382 u8 op_modifier,
383 u16 op,
384 unsigned long timeout,
385 u8 *status)
386 {
387 if (dev->cmd.use_events)
388 return mthca_cmd_wait(dev, in_param, &out_param, 0,
389 in_modifier, op_modifier, op,
390 timeout, status);
391 else
392 return mthca_cmd_poll(dev, in_param, &out_param, 0,
393 in_modifier, op_modifier, op,
394 timeout, status);
395 }
396
397 /* Invoke a command with no output parameter */
398 static int mthca_cmd(struct mthca_dev *dev,
399 u64 in_param,
400 u32 in_modifier,
401 u8 op_modifier,
402 u16 op,
403 unsigned long timeout,
404 u8 *status)
405 {
406 return mthca_cmd_box(dev, in_param, 0, in_modifier,
407 op_modifier, op, timeout, status);
408 }
409
410 /*
411 * Invoke a command with an immediate output parameter (and copy the
412 * output into the caller's out_param pointer after the command
413 * executes).
414 */
415 static int mthca_cmd_imm(struct mthca_dev *dev,
416 u64 in_param,
417 u64 *out_param,
418 u32 in_modifier,
419 u8 op_modifier,
420 u16 op,
421 unsigned long timeout,
422 u8 *status)
423 {
424 if (dev->cmd.use_events)
425 return mthca_cmd_wait(dev, in_param, out_param, 1,
426 in_modifier, op_modifier, op,
427 timeout, status);
428 else
429 return mthca_cmd_poll(dev, in_param, out_param, 1,
430 in_modifier, op_modifier, op,
431 timeout, status);
432 }
433
434 /*
435 * Switch to using events to issue FW commands (should be called after
436 * event queue to command events has been initialized).
437 */
438 int mthca_cmd_use_events(struct mthca_dev *dev)
439 {
440 int i;
441
442 dev->cmd.context = kmalloc(dev->cmd.max_cmds *
443 sizeof (struct mthca_cmd_context),
444 GFP_KERNEL);
445 if (!dev->cmd.context)
446 return -ENOMEM;
447
448 for (i = 0; i < dev->cmd.max_cmds; ++i) {
449 dev->cmd.context[i].token = i;
450 dev->cmd.context[i].next = i + 1;
451 init_timer(&dev->cmd.context[i].timer);
452 dev->cmd.context[i].timer.data =
453 (unsigned long) &dev->cmd.context[i];
454 dev->cmd.context[i].timer.function = event_timeout;
455 }
456
457 dev->cmd.context[dev->cmd.max_cmds - 1].next = -1;
458 dev->cmd.free_head = 0;
459
460 sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds);
461 spin_lock_init(&dev->cmd.context_lock);
462
463 for (dev->cmd.token_mask = 1;
464 dev->cmd.token_mask < dev->cmd.max_cmds;
465 dev->cmd.token_mask <<= 1)
466 ; /* nothing */
467 --dev->cmd.token_mask;
468
469 dev->cmd.use_events = 1;
470 down(&dev->cmd.poll_sem);
471
472 return 0;
473 }
474
475 /*
476 * Switch back to polling (used when shutting down the device)
477 */
478 void mthca_cmd_use_polling(struct mthca_dev *dev)
479 {
480 int i;
481
482 dev->cmd.use_events = 0;
483
484 for (i = 0; i < dev->cmd.max_cmds; ++i)
485 down(&dev->cmd.event_sem);
486
487 kfree(dev->cmd.context);
488
489 up(&dev->cmd.poll_sem);
490 }
491
492 int mthca_SYS_EN(struct mthca_dev *dev, u8 *status)
493 {
494 u64 out;
495 int ret;
496
497 ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, HZ, status);
498
499 if (*status == MTHCA_CMD_STAT_DDR_MEM_ERR)
500 mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, "
501 "sladdr=%d, SPD source=%s\n",
502 (int) (out >> 6) & 0xf, (int) (out >> 4) & 3,
503 (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM");
504
505 return ret;
506 }
507
508 int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status)
509 {
510 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, HZ, status);
511 }
512
513 static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm,
514 u64 virt, u8 *status)
515 {
516 u32 *inbox;
517 dma_addr_t indma;
518 struct mthca_icm_iter iter;
519 int lg;
520 int nent = 0;
521 int i;
522 int err = 0;
523 int ts = 0, tc = 0;
524
525 inbox = pci_alloc_consistent(dev->pdev, PAGE_SIZE, &indma);
526 if (!inbox)
527 return -ENOMEM;
528
529 memset(inbox, 0, PAGE_SIZE);
530
531 for (mthca_icm_first(icm, &iter);
532 !mthca_icm_last(&iter);
533 mthca_icm_next(&iter)) {
534 /*
535 * We have to pass pages that are aligned to their
536 * size, so find the least significant 1 in the
537 * address or size and use that as our log2 size.
538 */
539 lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1;
540 if (lg < 12) {
541 mthca_warn(dev, "Got FW area not aligned to 4K (%llx/%lx).\n",
542 (unsigned long long) mthca_icm_addr(&iter),
543 mthca_icm_size(&iter));
544 err = -EINVAL;
545 goto out;
546 }
547 for (i = 0; i < mthca_icm_size(&iter) / (1 << lg); ++i, ++nent) {
548 if (virt != -1) {
549 *((__be64 *) (inbox + nent * 4)) =
550 cpu_to_be64(virt);
551 virt += 1 << lg;
552 }
553
554 *((__be64 *) (inbox + nent * 4 + 2)) =
555 cpu_to_be64((mthca_icm_addr(&iter) +
556 (i << lg)) | (lg - 12));
557 ts += 1 << (lg - 10);
558 ++tc;
559
560 if (nent == PAGE_SIZE / 16) {
561 err = mthca_cmd(dev, indma, nent, 0, op,
562 CMD_TIME_CLASS_B, status);
563 if (err || *status)
564 goto out;
565 nent = 0;
566 }
567 }
568 }
569
570 if (nent)
571 err = mthca_cmd(dev, indma, nent, 0, op,
572 CMD_TIME_CLASS_B, status);
573
574 switch (op) {
575 case CMD_MAP_FA:
576 mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
577 break;
578 case CMD_MAP_ICM_AUX:
579 mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
580 break;
581 case CMD_MAP_ICM:
582 mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
583 tc, ts, (unsigned long long) virt - (ts << 10));
584 break;
585 }
586
587 out:
588 pci_free_consistent(dev->pdev, PAGE_SIZE, inbox, indma);
589 return err;
590 }
591
592 int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
593 {
594 return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1, status);
595 }
596
597 int mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status)
598 {
599 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B, status);
600 }
601
602 int mthca_RUN_FW(struct mthca_dev *dev, u8 *status)
603 {
604 return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A, status);
605 }
606
607 int mthca_QUERY_FW(struct mthca_dev *dev, u8 *status)
608 {
609 u32 *outbox;
610 dma_addr_t outdma;
611 int err = 0;
612 u8 lg;
613
614 #define QUERY_FW_OUT_SIZE 0x100
615 #define QUERY_FW_VER_OFFSET 0x00
616 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
617 #define QUERY_FW_ERR_START_OFFSET 0x30
618 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
619
620 #define QUERY_FW_START_OFFSET 0x20
621 #define QUERY_FW_END_OFFSET 0x28
622
623 #define QUERY_FW_SIZE_OFFSET 0x00
624 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
625 #define QUERY_FW_EQ_ARM_BASE_OFFSET 0x40
626 #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48
627
628 outbox = pci_alloc_consistent(dev->pdev, QUERY_FW_OUT_SIZE, &outdma);
629 if (!outbox) {
630 return -ENOMEM;
631 }
632
633 err = mthca_cmd_box(dev, 0, outdma, 0, 0, CMD_QUERY_FW,
634 CMD_TIME_CLASS_A, status);
635
636 if (err)
637 goto out;
638
639 MTHCA_GET(dev->fw_ver, outbox, QUERY_FW_VER_OFFSET);
640 /*
641 * FW subminor version is at more signifant bits than minor
642 * version, so swap here.
643 */
644 dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) |
645 ((dev->fw_ver & 0xffff0000ull) >> 16) |
646 ((dev->fw_ver & 0x0000ffffull) << 16);
647
648 MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
649 dev->cmd.max_cmds = 1 << lg;
650
651 mthca_dbg(dev, "FW version %012llx, max commands %d\n",
652 (unsigned long long) dev->fw_ver, dev->cmd.max_cmds);
653
654 if (mthca_is_memfree(dev)) {
655 MTHCA_GET(dev->fw.arbel.fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
656 MTHCA_GET(dev->fw.arbel.clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
657 MTHCA_GET(dev->fw.arbel.eq_arm_base, outbox, QUERY_FW_EQ_ARM_BASE_OFFSET);
658 MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET);
659 mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2);
660
661 /*
662 * Arbel page size is always 4 KB; round up number of
663 * system pages needed.
664 */
665 dev->fw.arbel.fw_pages =
666 (dev->fw.arbel.fw_pages + (1 << (PAGE_SHIFT - 12)) - 1) >>
667 (PAGE_SHIFT - 12);
668
669 mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n",
670 (unsigned long long) dev->fw.arbel.clr_int_base,
671 (unsigned long long) dev->fw.arbel.eq_arm_base,
672 (unsigned long long) dev->fw.arbel.eq_set_ci_base);
673 } else {
674 MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET);
675 MTHCA_GET(dev->fw.tavor.fw_end, outbox, QUERY_FW_END_OFFSET);
676
677 mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n",
678 (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10),
679 (unsigned long long) dev->fw.tavor.fw_start,
680 (unsigned long long) dev->fw.tavor.fw_end);
681 }
682
683 out:
684 pci_free_consistent(dev->pdev, QUERY_FW_OUT_SIZE, outbox, outdma);
685 return err;
686 }
687
688 int mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status)
689 {
690 u8 info;
691 u32 *outbox;
692 dma_addr_t outdma;
693 int err = 0;
694
695 #define ENABLE_LAM_OUT_SIZE 0x100
696 #define ENABLE_LAM_START_OFFSET 0x00
697 #define ENABLE_LAM_END_OFFSET 0x08
698 #define ENABLE_LAM_INFO_OFFSET 0x13
699
700 #define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4)
701 #define ENABLE_LAM_INFO_ECC_MASK 0x3
702
703 outbox = pci_alloc_consistent(dev->pdev, ENABLE_LAM_OUT_SIZE, &outdma);
704 if (!outbox)
705 return -ENOMEM;
706
707 err = mthca_cmd_box(dev, 0, outdma, 0, 0, CMD_ENABLE_LAM,
708 CMD_TIME_CLASS_C, status);
709
710 if (err)
711 goto out;
712
713 if (*status == MTHCA_CMD_STAT_LAM_NOT_PRE)
714 goto out;
715
716 MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET);
717 MTHCA_GET(dev->ddr_end, outbox, ENABLE_LAM_END_OFFSET);
718 MTHCA_GET(info, outbox, ENABLE_LAM_INFO_OFFSET);
719
720 if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) !=
721 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
722 mthca_info(dev, "FW reports that HCA-attached memory "
723 "is %s hidden; does not match PCI config\n",
724 (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ?
725 "" : "not");
726 }
727 if (info & ENABLE_LAM_INFO_HIDDEN_FLAG)
728 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
729
730 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
731 (int) ((dev->ddr_end - dev->ddr_start) >> 10),
732 (unsigned long long) dev->ddr_start,
733 (unsigned long long) dev->ddr_end);
734
735 out:
736 pci_free_consistent(dev->pdev, ENABLE_LAM_OUT_SIZE, outbox, outdma);
737 return err;
738 }
739
740 int mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status)
741 {
742 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status);
743 }
744
745 int mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status)
746 {
747 u8 info;
748 u32 *outbox;
749 dma_addr_t outdma;
750 int err = 0;
751
752 #define QUERY_DDR_OUT_SIZE 0x100
753 #define QUERY_DDR_START_OFFSET 0x00
754 #define QUERY_DDR_END_OFFSET 0x08
755 #define QUERY_DDR_INFO_OFFSET 0x13
756
757 #define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4)
758 #define QUERY_DDR_INFO_ECC_MASK 0x3
759
760 outbox = pci_alloc_consistent(dev->pdev, QUERY_DDR_OUT_SIZE, &outdma);
761 if (!outbox)
762 return -ENOMEM;
763
764 err = mthca_cmd_box(dev, 0, outdma, 0, 0, CMD_QUERY_DDR,
765 CMD_TIME_CLASS_A, status);
766
767 if (err)
768 goto out;
769
770 MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET);
771 MTHCA_GET(dev->ddr_end, outbox, QUERY_DDR_END_OFFSET);
772 MTHCA_GET(info, outbox, QUERY_DDR_INFO_OFFSET);
773
774 if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) !=
775 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
776 mthca_info(dev, "FW reports that HCA-attached memory "
777 "is %s hidden; does not match PCI config\n",
778 (info & QUERY_DDR_INFO_HIDDEN_FLAG) ?
779 "" : "not");
780 }
781 if (info & QUERY_DDR_INFO_HIDDEN_FLAG)
782 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
783
784 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
785 (int) ((dev->ddr_end - dev->ddr_start) >> 10),
786 (unsigned long long) dev->ddr_start,
787 (unsigned long long) dev->ddr_end);
788
789 out:
790 pci_free_consistent(dev->pdev, QUERY_DDR_OUT_SIZE, outbox, outdma);
791 return err;
792 }
793
794 int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
795 struct mthca_dev_lim *dev_lim, u8 *status)
796 {
797 u32 *outbox;
798 dma_addr_t outdma;
799 u8 field;
800 u16 size;
801 int err;
802
803 #define QUERY_DEV_LIM_OUT_SIZE 0x100
804 #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET 0x10
805 #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET 0x11
806 #define QUERY_DEV_LIM_RSVD_QP_OFFSET 0x12
807 #define QUERY_DEV_LIM_MAX_QP_OFFSET 0x13
808 #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET 0x14
809 #define QUERY_DEV_LIM_MAX_SRQ_OFFSET 0x15
810 #define QUERY_DEV_LIM_RSVD_EEC_OFFSET 0x16
811 #define QUERY_DEV_LIM_MAX_EEC_OFFSET 0x17
812 #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET 0x19
813 #define QUERY_DEV_LIM_RSVD_CQ_OFFSET 0x1a
814 #define QUERY_DEV_LIM_MAX_CQ_OFFSET 0x1b
815 #define QUERY_DEV_LIM_MAX_MPT_OFFSET 0x1d
816 #define QUERY_DEV_LIM_RSVD_EQ_OFFSET 0x1e
817 #define QUERY_DEV_LIM_MAX_EQ_OFFSET 0x1f
818 #define QUERY_DEV_LIM_RSVD_MTT_OFFSET 0x20
819 #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET 0x21
820 #define QUERY_DEV_LIM_RSVD_MRW_OFFSET 0x22
821 #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET 0x23
822 #define QUERY_DEV_LIM_MAX_AV_OFFSET 0x27
823 #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET 0x29
824 #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET 0x2b
825 #define QUERY_DEV_LIM_MAX_RDMA_OFFSET 0x2f
826 #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET 0x33
827 #define QUERY_DEV_LIM_ACK_DELAY_OFFSET 0x35
828 #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET 0x36
829 #define QUERY_DEV_LIM_VL_PORT_OFFSET 0x37
830 #define QUERY_DEV_LIM_MAX_GID_OFFSET 0x3b
831 #define QUERY_DEV_LIM_MAX_PKEY_OFFSET 0x3f
832 #define QUERY_DEV_LIM_FLAGS_OFFSET 0x44
833 #define QUERY_DEV_LIM_RSVD_UAR_OFFSET 0x48
834 #define QUERY_DEV_LIM_UAR_SZ_OFFSET 0x49
835 #define QUERY_DEV_LIM_PAGE_SZ_OFFSET 0x4b
836 #define QUERY_DEV_LIM_MAX_SG_OFFSET 0x51
837 #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET 0x52
838 #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET 0x55
839 #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56
840 #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET 0x61
841 #define QUERY_DEV_LIM_RSVD_MCG_OFFSET 0x62
842 #define QUERY_DEV_LIM_MAX_MCG_OFFSET 0x63
843 #define QUERY_DEV_LIM_RSVD_PD_OFFSET 0x64
844 #define QUERY_DEV_LIM_MAX_PD_OFFSET 0x65
845 #define QUERY_DEV_LIM_RSVD_RDD_OFFSET 0x66
846 #define QUERY_DEV_LIM_MAX_RDD_OFFSET 0x67
847 #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET 0x80
848 #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET 0x82
849 #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET 0x84
850 #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET 0x86
851 #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET 0x88
852 #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET 0x8a
853 #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET 0x8c
854 #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET 0x8e
855 #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET 0x90
856 #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET 0x92
857 #define QUERY_DEV_LIM_PBL_SZ_OFFSET 0x96
858 #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET 0x97
859 #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET 0x98
860 #define QUERY_DEV_LIM_LAMR_OFFSET 0x9f
861 #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET 0xa0
862
863 outbox = pci_alloc_consistent(dev->pdev, QUERY_DEV_LIM_OUT_SIZE, &outdma);
864 if (!outbox)
865 return -ENOMEM;
866
867 err = mthca_cmd_box(dev, 0, outdma, 0, 0, CMD_QUERY_DEV_LIM,
868 CMD_TIME_CLASS_A, status);
869
870 if (err)
871 goto out;
872
873 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
874 dev_lim->max_srq_sz = 1 << field;
875 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
876 dev_lim->max_qp_sz = 1 << field;
877 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET);
878 dev_lim->reserved_qps = 1 << (field & 0xf);
879 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET);
880 dev_lim->max_qps = 1 << (field & 0x1f);
881 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET);
882 dev_lim->reserved_srqs = 1 << (field >> 4);
883 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET);
884 dev_lim->max_srqs = 1 << (field & 0x1f);
885 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET);
886 dev_lim->reserved_eecs = 1 << (field & 0xf);
887 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET);
888 dev_lim->max_eecs = 1 << (field & 0x1f);
889 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET);
890 dev_lim->max_cq_sz = 1 << field;
891 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET);
892 dev_lim->reserved_cqs = 1 << (field & 0xf);
893 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET);
894 dev_lim->max_cqs = 1 << (field & 0x1f);
895 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET);
896 dev_lim->max_mpts = 1 << (field & 0x3f);
897 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET);
898 dev_lim->reserved_eqs = 1 << (field & 0xf);
899 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET);
900 dev_lim->max_eqs = 1 << (field & 0x7);
901 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET);
902 dev_lim->reserved_mtts = 1 << (field >> 4);
903 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET);
904 dev_lim->max_mrw_sz = 1 << field;
905 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET);
906 dev_lim->reserved_mrws = 1 << (field & 0xf);
907 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET);
908 dev_lim->max_mtt_seg = 1 << (field & 0x3f);
909 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET);
910 dev_lim->max_requester_per_qp = 1 << (field & 0x3f);
911 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET);
912 dev_lim->max_responder_per_qp = 1 << (field & 0x3f);
913 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET);
914 dev_lim->max_rdma_global = 1 << (field & 0x3f);
915 MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET);
916 dev_lim->local_ca_ack_delay = field & 0x1f;
917 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET);
918 dev_lim->max_mtu = field >> 4;
919 dev_lim->max_port_width = field & 0xf;
920 MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET);
921 dev_lim->max_vl = field >> 4;
922 dev_lim->num_ports = field & 0xf;
923 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET);
924 dev_lim->max_gids = 1 << (field & 0xf);
925 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET);
926 dev_lim->max_pkeys = 1 << (field & 0xf);
927 MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET);
928 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET);
929 dev_lim->reserved_uars = field >> 4;
930 MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET);
931 dev_lim->uar_size = 1 << ((field & 0x3f) + 20);
932 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET);
933 dev_lim->min_page_sz = 1 << field;
934 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET);
935 dev_lim->max_sg = field;
936
937 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET);
938 dev_lim->max_desc_sz = size;
939
940 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET);
941 dev_lim->max_qp_per_mcg = 1 << field;
942 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET);
943 dev_lim->reserved_mgms = field & 0xf;
944 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET);
945 dev_lim->max_mcgs = 1 << field;
946 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET);
947 dev_lim->reserved_pds = field >> 4;
948 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET);
949 dev_lim->max_pds = 1 << (field & 0x3f);
950 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET);
951 dev_lim->reserved_rdds = field >> 4;
952 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET);
953 dev_lim->max_rdds = 1 << (field & 0x3f);
954
955 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET);
956 dev_lim->eec_entry_sz = size;
957 MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET);
958 dev_lim->qpc_entry_sz = size;
959 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET);
960 dev_lim->eeec_entry_sz = size;
961 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET);
962 dev_lim->eqpc_entry_sz = size;
963 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET);
964 dev_lim->eqc_entry_sz = size;
965 MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET);
966 dev_lim->cqc_entry_sz = size;
967 MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET);
968 dev_lim->srq_entry_sz = size;
969 MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET);
970 dev_lim->uar_scratch_entry_sz = size;
971
972 mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
973 dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz);
974 mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
975 dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz);
976 mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
977 dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz);
978 mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
979 dev_lim->reserved_mrws, dev_lim->reserved_mtts);
980 mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
981 dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars);
982 mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
983 dev_lim->max_pds, dev_lim->reserved_mgms);
984
985 mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags);
986
987 if (mthca_is_memfree(dev)) {
988 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET);
989 dev_lim->hca.arbel.resize_srq = field & 1;
990 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET);
991 dev_lim->max_sg = min_t(int, field, dev_lim->max_sg);
992 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET);
993 dev_lim->mpt_entry_sz = size;
994 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET);
995 dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f);
996 MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox,
997 QUERY_DEV_LIM_BMME_FLAGS_OFFSET);
998 MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox,
999 QUERY_DEV_LIM_RSVD_LKEY_OFFSET);
1000 MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET);
1001 dev_lim->hca.arbel.lam_required = field & 1;
1002 MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox,
1003 QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET);
1004
1005 if (dev_lim->hca.arbel.bmme_flags & 1)
1006 mthca_dbg(dev, "Base MM extensions: yes "
1007 "(flags %d, max PBL %d, rsvd L_Key %08x)\n",
1008 dev_lim->hca.arbel.bmme_flags,
1009 dev_lim->hca.arbel.max_pbl_sz,
1010 dev_lim->hca.arbel.reserved_lkey);
1011 else
1012 mthca_dbg(dev, "Base MM extensions: no\n");
1013
1014 mthca_dbg(dev, "Max ICM size %lld MB\n",
1015 (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20);
1016 } else {
1017 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET);
1018 dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f);
1019 dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE;
1020 }
1021
1022 out:
1023 pci_free_consistent(dev->pdev, QUERY_DEV_LIM_OUT_SIZE, outbox, outdma);
1024 return err;
1025 }
1026
1027 int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
1028 struct mthca_adapter *adapter, u8 *status)
1029 {
1030 u32 *outbox;
1031 dma_addr_t outdma;
1032 int err;
1033
1034 #define QUERY_ADAPTER_OUT_SIZE 0x100
1035 #define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00
1036 #define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04
1037 #define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08
1038 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1039
1040 outbox = pci_alloc_consistent(dev->pdev, QUERY_ADAPTER_OUT_SIZE, &outdma);
1041 if (!outbox)
1042 return -ENOMEM;
1043
1044 err = mthca_cmd_box(dev, 0, outdma, 0, 0, CMD_QUERY_ADAPTER,
1045 CMD_TIME_CLASS_A, status);
1046
1047 if (err)
1048 goto out;
1049
1050 MTHCA_GET(adapter->vendor_id, outbox, QUERY_ADAPTER_VENDOR_ID_OFFSET);
1051 MTHCA_GET(adapter->device_id, outbox, QUERY_ADAPTER_DEVICE_ID_OFFSET);
1052 MTHCA_GET(adapter->revision_id, outbox, QUERY_ADAPTER_REVISION_ID_OFFSET);
1053 MTHCA_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1054
1055 out:
1056 pci_free_consistent(dev->pdev, QUERY_DEV_LIM_OUT_SIZE, outbox, outdma);
1057 return err;
1058 }
1059
1060 int mthca_INIT_HCA(struct mthca_dev *dev,
1061 struct mthca_init_hca_param *param,
1062 u8 *status)
1063 {
1064 u32 *inbox;
1065 dma_addr_t indma;
1066 int err;
1067
1068 #define INIT_HCA_IN_SIZE 0x200
1069 #define INIT_HCA_FLAGS_OFFSET 0x014
1070 #define INIT_HCA_QPC_OFFSET 0x020
1071 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1072 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1073 #define INIT_HCA_EEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x20)
1074 #define INIT_HCA_LOG_EEC_OFFSET (INIT_HCA_QPC_OFFSET + 0x27)
1075 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1076 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1077 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1078 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1079 #define INIT_HCA_EQPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1080 #define INIT_HCA_EEEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1081 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1082 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1083 #define INIT_HCA_RDB_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1084 #define INIT_HCA_UDAV_OFFSET 0x0b0
1085 #define INIT_HCA_UDAV_LKEY_OFFSET (INIT_HCA_UDAV_OFFSET + 0x0)
1086 #define INIT_HCA_UDAV_PD_OFFSET (INIT_HCA_UDAV_OFFSET + 0x4)
1087 #define INIT_HCA_MCAST_OFFSET 0x0c0
1088 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1089 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1090 #define INIT_HCA_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1091 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1092 #define INIT_HCA_TPT_OFFSET 0x0f0
1093 #define INIT_HCA_MPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1094 #define INIT_HCA_MTT_SEG_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x09)
1095 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1096 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1097 #define INIT_HCA_UAR_OFFSET 0x120
1098 #define INIT_HCA_UAR_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x00)
1099 #define INIT_HCA_UARC_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x09)
1100 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1101 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1102 #define INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10)
1103 #define INIT_HCA_UAR_CTX_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x18)
1104
1105 inbox = pci_alloc_consistent(dev->pdev, INIT_HCA_IN_SIZE, &indma);
1106 if (!inbox)
1107 return -ENOMEM;
1108
1109 memset(inbox, 0, INIT_HCA_IN_SIZE);
1110
1111 #if defined(__LITTLE_ENDIAN)
1112 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1113 #elif defined(__BIG_ENDIAN)
1114 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1115 #else
1116 #error Host endianness not defined
1117 #endif
1118 /* Check port for UD address vector: */
1119 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1120
1121 /* We leave wqe_quota, responder_exu, etc as 0 (default) */
1122
1123 /* QPC/EEC/CQC/EQC/RDB attributes */
1124
1125 MTHCA_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1126 MTHCA_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1127 MTHCA_PUT(inbox, param->eec_base, INIT_HCA_EEC_BASE_OFFSET);
1128 MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET);
1129 MTHCA_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1130 MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1131 MTHCA_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1132 MTHCA_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1133 MTHCA_PUT(inbox, param->eqpc_base, INIT_HCA_EQPC_BASE_OFFSET);
1134 MTHCA_PUT(inbox, param->eeec_base, INIT_HCA_EEEC_BASE_OFFSET);
1135 MTHCA_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1136 MTHCA_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1137 MTHCA_PUT(inbox, param->rdb_base, INIT_HCA_RDB_BASE_OFFSET);
1138
1139 /* UD AV attributes */
1140
1141 /* multicast attributes */
1142
1143 MTHCA_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1144 MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1145 MTHCA_PUT(inbox, param->mc_hash_sz, INIT_HCA_MC_HASH_SZ_OFFSET);
1146 MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1147
1148 /* TPT attributes */
1149
1150 MTHCA_PUT(inbox, param->mpt_base, INIT_HCA_MPT_BASE_OFFSET);
1151 if (!mthca_is_memfree(dev))
1152 MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET);
1153 MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1154 MTHCA_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1155
1156 /* UAR attributes */
1157 {
1158 u8 uar_page_sz = PAGE_SHIFT - 12;
1159 MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1160 }
1161
1162 MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET);
1163
1164 if (mthca_is_memfree(dev)) {
1165 MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET);
1166 MTHCA_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1167 MTHCA_PUT(inbox, param->uarc_base, INIT_HCA_UAR_CTX_BASE_OFFSET);
1168 }
1169
1170 err = mthca_cmd(dev, indma, 0, 0, CMD_INIT_HCA,
1171 HZ, status);
1172
1173 pci_free_consistent(dev->pdev, INIT_HCA_IN_SIZE, inbox, indma);
1174 return err;
1175 }
1176
1177 int mthca_INIT_IB(struct mthca_dev *dev,
1178 struct mthca_init_ib_param *param,
1179 int port, u8 *status)
1180 {
1181 u32 *inbox;
1182 dma_addr_t indma;
1183 int err;
1184 u32 flags;
1185
1186 #define INIT_IB_IN_SIZE 56
1187 #define INIT_IB_FLAGS_OFFSET 0x00
1188 #define INIT_IB_FLAG_SIG (1 << 18)
1189 #define INIT_IB_FLAG_NG (1 << 17)
1190 #define INIT_IB_FLAG_G0 (1 << 16)
1191 #define INIT_IB_FLAG_1X (1 << 8)
1192 #define INIT_IB_FLAG_4X (1 << 9)
1193 #define INIT_IB_FLAG_12X (1 << 11)
1194 #define INIT_IB_VL_SHIFT 4
1195 #define INIT_IB_MTU_SHIFT 12
1196 #define INIT_IB_MAX_GID_OFFSET 0x06
1197 #define INIT_IB_MAX_PKEY_OFFSET 0x0a
1198 #define INIT_IB_GUID0_OFFSET 0x10
1199 #define INIT_IB_NODE_GUID_OFFSET 0x18
1200 #define INIT_IB_SI_GUID_OFFSET 0x20
1201
1202 inbox = pci_alloc_consistent(dev->pdev, INIT_IB_IN_SIZE, &indma);
1203 if (!inbox)
1204 return -ENOMEM;
1205
1206 memset(inbox, 0, INIT_IB_IN_SIZE);
1207
1208 flags = 0;
1209 flags |= param->enable_1x ? INIT_IB_FLAG_1X : 0;
1210 flags |= param->enable_4x ? INIT_IB_FLAG_4X : 0;
1211 flags |= param->set_guid0 ? INIT_IB_FLAG_G0 : 0;
1212 flags |= param->set_node_guid ? INIT_IB_FLAG_NG : 0;
1213 flags |= param->set_si_guid ? INIT_IB_FLAG_SIG : 0;
1214 flags |= param->vl_cap << INIT_IB_VL_SHIFT;
1215 flags |= param->mtu_cap << INIT_IB_MTU_SHIFT;
1216 MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET);
1217
1218 MTHCA_PUT(inbox, param->gid_cap, INIT_IB_MAX_GID_OFFSET);
1219 MTHCA_PUT(inbox, param->pkey_cap, INIT_IB_MAX_PKEY_OFFSET);
1220 MTHCA_PUT(inbox, param->guid0, INIT_IB_GUID0_OFFSET);
1221 MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET);
1222 MTHCA_PUT(inbox, param->si_guid, INIT_IB_SI_GUID_OFFSET);
1223
1224 err = mthca_cmd(dev, indma, port, 0, CMD_INIT_IB,
1225 CMD_TIME_CLASS_A, status);
1226
1227 pci_free_consistent(dev->pdev, INIT_HCA_IN_SIZE, inbox, indma);
1228 return err;
1229 }
1230
1231 int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status)
1232 {
1233 return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, HZ, status);
1234 }
1235
1236 int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status)
1237 {
1238 return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, HZ, status);
1239 }
1240
1241 int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
1242 int port, u8 *status)
1243 {
1244 u32 *inbox;
1245 dma_addr_t indma;
1246 int err;
1247 u32 flags = 0;
1248
1249 #define SET_IB_IN_SIZE 0x40
1250 #define SET_IB_FLAGS_OFFSET 0x00
1251 #define SET_IB_FLAG_SIG (1 << 18)
1252 #define SET_IB_FLAG_RQK (1 << 0)
1253 #define SET_IB_CAP_MASK_OFFSET 0x04
1254 #define SET_IB_SI_GUID_OFFSET 0x08
1255
1256 inbox = pci_alloc_consistent(dev->pdev, SET_IB_IN_SIZE, &indma);
1257 if (!inbox)
1258 return -ENOMEM;
1259
1260 memset(inbox, 0, SET_IB_IN_SIZE);
1261
1262 flags |= param->set_si_guid ? SET_IB_FLAG_SIG : 0;
1263 flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0;
1264 MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET);
1265
1266 MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET);
1267 MTHCA_PUT(inbox, param->si_guid, SET_IB_SI_GUID_OFFSET);
1268
1269 err = mthca_cmd(dev, indma, port, 0, CMD_SET_IB,
1270 CMD_TIME_CLASS_B, status);
1271
1272 pci_free_consistent(dev->pdev, INIT_HCA_IN_SIZE, inbox, indma);
1273 return err;
1274 }
1275
1276 int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status)
1277 {
1278 return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt, status);
1279 }
1280
1281 int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status)
1282 {
1283 u64 *inbox;
1284 dma_addr_t indma;
1285 int err;
1286
1287 inbox = pci_alloc_consistent(dev->pdev, 16, &indma);
1288 if (!inbox)
1289 return -ENOMEM;
1290
1291 inbox[0] = cpu_to_be64(virt);
1292 inbox[1] = cpu_to_be64(dma_addr);
1293
1294 err = mthca_cmd(dev, indma, 1, 0, CMD_MAP_ICM, CMD_TIME_CLASS_B, status);
1295
1296 pci_free_consistent(dev->pdev, 16, inbox, indma);
1297
1298 if (!err)
1299 mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n",
1300 (unsigned long long) dma_addr, (unsigned long long) virt);
1301
1302 return err;
1303 }
1304
1305 int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status)
1306 {
1307 mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n",
1308 page_count, (unsigned long long) virt);
1309
1310 return mthca_cmd(dev, virt, page_count, 0, CMD_UNMAP_ICM, CMD_TIME_CLASS_B, status);
1311 }
1312
1313 int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
1314 {
1315 return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1, status);
1316 }
1317
1318 int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status)
1319 {
1320 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B, status);
1321 }
1322
1323 int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages,
1324 u8 *status)
1325 {
1326 int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0, 0, CMD_SET_ICM_SIZE,
1327 CMD_TIME_CLASS_A, status);
1328
1329 if (ret || status)
1330 return ret;
1331
1332 /*
1333 * Arbel page size is always 4 KB; round up number of system
1334 * pages needed.
1335 */
1336 *aux_pages = (*aux_pages + (1 << (PAGE_SHIFT - 12)) - 1) >> (PAGE_SHIFT - 12);
1337
1338 return 0;
1339 }
1340
1341 int mthca_SW2HW_MPT(struct mthca_dev *dev, void *mpt_entry,
1342 int mpt_index, u8 *status)
1343 {
1344 dma_addr_t indma;
1345 int err;
1346
1347 indma = pci_map_single(dev->pdev, mpt_entry,
1348 MTHCA_MPT_ENTRY_SIZE,
1349 PCI_DMA_TODEVICE);
1350 if (pci_dma_mapping_error(indma))
1351 return -ENOMEM;
1352
1353 err = mthca_cmd(dev, indma, mpt_index, 0, CMD_SW2HW_MPT,
1354 CMD_TIME_CLASS_B, status);
1355
1356 pci_unmap_single(dev->pdev, indma,
1357 MTHCA_MPT_ENTRY_SIZE, PCI_DMA_TODEVICE);
1358 return err;
1359 }
1360
1361 int mthca_HW2SW_MPT(struct mthca_dev *dev, void *mpt_entry,
1362 int mpt_index, u8 *status)
1363 {
1364 dma_addr_t outdma = 0;
1365 int err;
1366
1367 if (mpt_entry) {
1368 outdma = pci_map_single(dev->pdev, mpt_entry,
1369 MTHCA_MPT_ENTRY_SIZE,
1370 PCI_DMA_FROMDEVICE);
1371 if (pci_dma_mapping_error(outdma))
1372 return -ENOMEM;
1373 }
1374
1375 err = mthca_cmd_box(dev, 0, outdma, mpt_index, !mpt_entry,
1376 CMD_HW2SW_MPT,
1377 CMD_TIME_CLASS_B, status);
1378
1379 if (mpt_entry)
1380 pci_unmap_single(dev->pdev, outdma,
1381 MTHCA_MPT_ENTRY_SIZE,
1382 PCI_DMA_FROMDEVICE);
1383 return err;
1384 }
1385
1386 int mthca_WRITE_MTT(struct mthca_dev *dev, u64 *mtt_entry,
1387 int num_mtt, u8 *status)
1388 {
1389 dma_addr_t indma;
1390 int err;
1391
1392 indma = pci_map_single(dev->pdev, mtt_entry,
1393 (num_mtt + 2) * 8,
1394 PCI_DMA_TODEVICE);
1395 if (pci_dma_mapping_error(indma))
1396 return -ENOMEM;
1397
1398 err = mthca_cmd(dev, indma, num_mtt, 0, CMD_WRITE_MTT,
1399 CMD_TIME_CLASS_B, status);
1400
1401 pci_unmap_single(dev->pdev, indma,
1402 (num_mtt + 2) * 8, PCI_DMA_TODEVICE);
1403 return err;
1404 }
1405
1406 int mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status)
1407 {
1408 return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B, status);
1409 }
1410
1411 int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
1412 int eq_num, u8 *status)
1413 {
1414 mthca_dbg(dev, "%s mask %016llx for eqn %d\n",
1415 unmap ? "Clearing" : "Setting",
1416 (unsigned long long) event_mask, eq_num);
1417 return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num,
1418 0, CMD_MAP_EQ, CMD_TIME_CLASS_B, status);
1419 }
1420
1421 int mthca_SW2HW_EQ(struct mthca_dev *dev, void *eq_context,
1422 int eq_num, u8 *status)
1423 {
1424 dma_addr_t indma;
1425 int err;
1426
1427 indma = pci_map_single(dev->pdev, eq_context,
1428 MTHCA_EQ_CONTEXT_SIZE,
1429 PCI_DMA_TODEVICE);
1430 if (pci_dma_mapping_error(indma))
1431 return -ENOMEM;
1432
1433 err = mthca_cmd(dev, indma, eq_num, 0, CMD_SW2HW_EQ,
1434 CMD_TIME_CLASS_A, status);
1435
1436 pci_unmap_single(dev->pdev, indma,
1437 MTHCA_EQ_CONTEXT_SIZE, PCI_DMA_TODEVICE);
1438 return err;
1439 }
1440
1441 int mthca_HW2SW_EQ(struct mthca_dev *dev, void *eq_context,
1442 int eq_num, u8 *status)
1443 {
1444 dma_addr_t outdma = 0;
1445 int err;
1446
1447 outdma = pci_map_single(dev->pdev, eq_context,
1448 MTHCA_EQ_CONTEXT_SIZE,
1449 PCI_DMA_FROMDEVICE);
1450 if (pci_dma_mapping_error(outdma))
1451 return -ENOMEM;
1452
1453 err = mthca_cmd_box(dev, 0, outdma, eq_num, 0,
1454 CMD_HW2SW_EQ,
1455 CMD_TIME_CLASS_A, status);
1456
1457 pci_unmap_single(dev->pdev, outdma,
1458 MTHCA_EQ_CONTEXT_SIZE,
1459 PCI_DMA_FROMDEVICE);
1460 return err;
1461 }
1462
1463 int mthca_SW2HW_CQ(struct mthca_dev *dev, void *cq_context,
1464 int cq_num, u8 *status)
1465 {
1466 dma_addr_t indma;
1467 int err;
1468
1469 indma = pci_map_single(dev->pdev, cq_context,
1470 MTHCA_CQ_CONTEXT_SIZE,
1471 PCI_DMA_TODEVICE);
1472 if (pci_dma_mapping_error(indma))
1473 return -ENOMEM;
1474
1475 err = mthca_cmd(dev, indma, cq_num, 0, CMD_SW2HW_CQ,
1476 CMD_TIME_CLASS_A, status);
1477
1478 pci_unmap_single(dev->pdev, indma,
1479 MTHCA_CQ_CONTEXT_SIZE, PCI_DMA_TODEVICE);
1480 return err;
1481 }
1482
1483 int mthca_HW2SW_CQ(struct mthca_dev *dev, void *cq_context,
1484 int cq_num, u8 *status)
1485 {
1486 dma_addr_t outdma = 0;
1487 int err;
1488
1489 outdma = pci_map_single(dev->pdev, cq_context,
1490 MTHCA_CQ_CONTEXT_SIZE,
1491 PCI_DMA_FROMDEVICE);
1492 if (pci_dma_mapping_error(outdma))
1493 return -ENOMEM;
1494
1495 err = mthca_cmd_box(dev, 0, outdma, cq_num, 0,
1496 CMD_HW2SW_CQ,
1497 CMD_TIME_CLASS_A, status);
1498
1499 pci_unmap_single(dev->pdev, outdma,
1500 MTHCA_CQ_CONTEXT_SIZE,
1501 PCI_DMA_FROMDEVICE);
1502 return err;
1503 }
1504
1505 int mthca_MODIFY_QP(struct mthca_dev *dev, int trans, u32 num,
1506 int is_ee, void *qp_context, u32 optmask,
1507 u8 *status)
1508 {
1509 static const u16 op[] = {
1510 [MTHCA_TRANS_RST2INIT] = CMD_RST2INIT_QPEE,
1511 [MTHCA_TRANS_INIT2INIT] = CMD_INIT2INIT_QPEE,
1512 [MTHCA_TRANS_INIT2RTR] = CMD_INIT2RTR_QPEE,
1513 [MTHCA_TRANS_RTR2RTS] = CMD_RTR2RTS_QPEE,
1514 [MTHCA_TRANS_RTS2RTS] = CMD_RTS2RTS_QPEE,
1515 [MTHCA_TRANS_SQERR2RTS] = CMD_SQERR2RTS_QPEE,
1516 [MTHCA_TRANS_ANY2ERR] = CMD_2ERR_QPEE,
1517 [MTHCA_TRANS_RTS2SQD] = CMD_RTS2SQD_QPEE,
1518 [MTHCA_TRANS_SQD2SQD] = CMD_SQD2SQD_QPEE,
1519 [MTHCA_TRANS_SQD2RTS] = CMD_SQD2RTS_QPEE,
1520 [MTHCA_TRANS_ANY2RST] = CMD_ERR2RST_QPEE
1521 };
1522 u8 op_mod = 0;
1523
1524 dma_addr_t indma;
1525 int err;
1526
1527 if (trans < 0 || trans >= ARRAY_SIZE(op))
1528 return -EINVAL;
1529
1530 if (trans == MTHCA_TRANS_ANY2RST) {
1531 indma = 0;
1532 op_mod = 3; /* don't write outbox, any->reset */
1533
1534 /* For debugging */
1535 qp_context = pci_alloc_consistent(dev->pdev, MTHCA_QP_CONTEXT_SIZE,
1536 &indma);
1537 op_mod = 2; /* write outbox, any->reset */
1538 } else {
1539 indma = pci_map_single(dev->pdev, qp_context,
1540 MTHCA_QP_CONTEXT_SIZE,
1541 PCI_DMA_TODEVICE);
1542 if (pci_dma_mapping_error(indma))
1543 return -ENOMEM;
1544
1545 if (0) {
1546 int i;
1547 mthca_dbg(dev, "Dumping QP context:\n");
1548 printk(" opt param mask: %08x\n", be32_to_cpup(qp_context));
1549 for (i = 0; i < 0x100 / 4; ++i) {
1550 if (i % 8 == 0)
1551 printk(" [%02x] ", i * 4);
1552 printk(" %08x", be32_to_cpu(((u32 *) qp_context)[i + 2]));
1553 if ((i + 1) % 8 == 0)
1554 printk("\n");
1555 }
1556 }
1557 }
1558
1559 if (trans == MTHCA_TRANS_ANY2RST) {
1560 err = mthca_cmd_box(dev, 0, indma, (!!is_ee << 24) | num,
1561 op_mod, op[trans], CMD_TIME_CLASS_C, status);
1562
1563 if (0) {
1564 int i;
1565 mthca_dbg(dev, "Dumping QP context:\n");
1566 printk(" %08x\n", be32_to_cpup(qp_context));
1567 for (i = 0; i < 0x100 / 4; ++i) {
1568 if (i % 8 == 0)
1569 printk("[%02x] ", i * 4);
1570 printk(" %08x", be32_to_cpu(((u32 *) qp_context)[i + 2]));
1571 if ((i + 1) % 8 == 0)
1572 printk("\n");
1573 }
1574 }
1575
1576 } else
1577 err = mthca_cmd(dev, indma, (!!is_ee << 24) | num,
1578 op_mod, op[trans], CMD_TIME_CLASS_C, status);
1579
1580 if (trans != MTHCA_TRANS_ANY2RST)
1581 pci_unmap_single(dev->pdev, indma,
1582 MTHCA_QP_CONTEXT_SIZE, PCI_DMA_TODEVICE);
1583 else
1584 pci_free_consistent(dev->pdev, MTHCA_QP_CONTEXT_SIZE,
1585 qp_context, indma);
1586 return err;
1587 }
1588
1589 int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
1590 void *qp_context, u8 *status)
1591 {
1592 dma_addr_t outdma = 0;
1593 int err;
1594
1595 outdma = pci_map_single(dev->pdev, qp_context,
1596 MTHCA_QP_CONTEXT_SIZE,
1597 PCI_DMA_FROMDEVICE);
1598 if (pci_dma_mapping_error(outdma))
1599 return -ENOMEM;
1600
1601 err = mthca_cmd_box(dev, 0, outdma, (!!is_ee << 24) | num, 0,
1602 CMD_QUERY_QPEE,
1603 CMD_TIME_CLASS_A, status);
1604
1605 pci_unmap_single(dev->pdev, outdma,
1606 MTHCA_QP_CONTEXT_SIZE,
1607 PCI_DMA_FROMDEVICE);
1608 return err;
1609 }
1610
1611 int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn,
1612 u8 *status)
1613 {
1614 u8 op_mod;
1615
1616 switch (type) {
1617 case IB_QPT_SMI:
1618 op_mod = 0;
1619 break;
1620 case IB_QPT_GSI:
1621 op_mod = 1;
1622 break;
1623 case IB_QPT_RAW_IPV6:
1624 op_mod = 2;
1625 break;
1626 case IB_QPT_RAW_ETY:
1627 op_mod = 3;
1628 break;
1629 default:
1630 return -EINVAL;
1631 }
1632
1633 return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP,
1634 CMD_TIME_CLASS_B, status);
1635 }
1636
1637 int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
1638 int port, struct ib_wc* in_wc, struct ib_grh* in_grh,
1639 void *in_mad, void *response_mad, u8 *status)
1640 {
1641 void *box;
1642 dma_addr_t dma;
1643 int err;
1644 u32 in_modifier = port;
1645 u8 op_modifier = 0;
1646
1647 #define MAD_IFC_BOX_SIZE 0x400
1648 #define MAD_IFC_MY_QPN_OFFSET 0x100
1649 #define MAD_IFC_RQPN_OFFSET 0x104
1650 #define MAD_IFC_SL_OFFSET 0x108
1651 #define MAD_IFC_G_PATH_OFFSET 0x109
1652 #define MAD_IFC_RLID_OFFSET 0x10a
1653 #define MAD_IFC_PKEY_OFFSET 0x10e
1654 #define MAD_IFC_GRH_OFFSET 0x140
1655
1656 box = pci_alloc_consistent(dev->pdev, MAD_IFC_BOX_SIZE, &dma);
1657 if (!box)
1658 return -ENOMEM;
1659
1660 memcpy(box, in_mad, 256);
1661
1662 /*
1663 * Key check traps can't be generated unless we have in_wc to
1664 * tell us where to send the trap.
1665 */
1666 if (ignore_mkey || !in_wc)
1667 op_modifier |= 0x1;
1668 if (ignore_bkey || !in_wc)
1669 op_modifier |= 0x2;
1670
1671 if (in_wc) {
1672 u8 val;
1673
1674 memset(box + 256, 0, 256);
1675
1676 MTHCA_PUT(box, in_wc->qp_num, MAD_IFC_MY_QPN_OFFSET);
1677 MTHCA_PUT(box, in_wc->src_qp, MAD_IFC_RQPN_OFFSET);
1678
1679 val = in_wc->sl << 4;
1680 MTHCA_PUT(box, val, MAD_IFC_SL_OFFSET);
1681
1682 val = in_wc->dlid_path_bits |
1683 (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
1684 MTHCA_PUT(box, val, MAD_IFC_GRH_OFFSET);
1685
1686 MTHCA_PUT(box, in_wc->slid, MAD_IFC_RLID_OFFSET);
1687 MTHCA_PUT(box, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET);
1688
1689 if (in_grh)
1690 memcpy((u8 *) box + MAD_IFC_GRH_OFFSET, in_grh, 40);
1691
1692 op_modifier |= 0x10;
1693
1694 in_modifier |= in_wc->slid << 16;
1695 }
1696
1697 err = mthca_cmd_box(dev, dma, dma + 512, in_modifier, op_modifier,
1698 CMD_MAD_IFC, CMD_TIME_CLASS_C, status);
1699
1700 if (!err && !*status)
1701 memcpy(response_mad, box + 512, 256);
1702
1703 pci_free_consistent(dev->pdev, MAD_IFC_BOX_SIZE, box, dma);
1704 return err;
1705 }
1706
1707 int mthca_READ_MGM(struct mthca_dev *dev, int index, void *mgm,
1708 u8 *status)
1709 {
1710 dma_addr_t outdma = 0;
1711 int err;
1712
1713 outdma = pci_map_single(dev->pdev, mgm,
1714 MTHCA_MGM_ENTRY_SIZE,
1715 PCI_DMA_FROMDEVICE);
1716 if (pci_dma_mapping_error(outdma))
1717 return -ENOMEM;
1718
1719 err = mthca_cmd_box(dev, 0, outdma, index, 0,
1720 CMD_READ_MGM,
1721 CMD_TIME_CLASS_A, status);
1722
1723 pci_unmap_single(dev->pdev, outdma,
1724 MTHCA_MGM_ENTRY_SIZE,
1725 PCI_DMA_FROMDEVICE);
1726 return err;
1727 }
1728
1729 int mthca_WRITE_MGM(struct mthca_dev *dev, int index, void *mgm,
1730 u8 *status)
1731 {
1732 dma_addr_t indma;
1733 int err;
1734
1735 indma = pci_map_single(dev->pdev, mgm,
1736 MTHCA_MGM_ENTRY_SIZE,
1737 PCI_DMA_TODEVICE);
1738 if (pci_dma_mapping_error(indma))
1739 return -ENOMEM;
1740
1741 err = mthca_cmd(dev, indma, index, 0, CMD_WRITE_MGM,
1742 CMD_TIME_CLASS_A, status);
1743
1744 pci_unmap_single(dev->pdev, indma,
1745 MTHCA_MGM_ENTRY_SIZE, PCI_DMA_TODEVICE);
1746 return err;
1747 }
1748
1749 int mthca_MGID_HASH(struct mthca_dev *dev, void *gid, u16 *hash,
1750 u8 *status)
1751 {
1752 dma_addr_t indma;
1753 u64 imm;
1754 int err;
1755
1756 indma = pci_map_single(dev->pdev, gid, 16, PCI_DMA_TODEVICE);
1757 if (pci_dma_mapping_error(indma))
1758 return -ENOMEM;
1759
1760 err = mthca_cmd_imm(dev, indma, &imm, 0, 0, CMD_MGID_HASH,
1761 CMD_TIME_CLASS_A, status);
1762 *hash = imm;
1763
1764 pci_unmap_single(dev->pdev, indma, 16, PCI_DMA_TODEVICE);
1765 return err;
1766 }
1767
1768 int mthca_NOP(struct mthca_dev *dev, u8 *status)
1769 {
1770 return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100), status);
1771 }
CRIS linux kernel tree