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[PATCH] aic7xxx_osm build fix
[cris-mirror.git] / drivers / isdn / hisax / isar.c
blobee081321efb25e6e9741ded87490ac0bc6dab641
1 /* $Id: isar.c,v 1.22.2.6 2004/02/11 13:21:34 keil Exp $
2 *
3 * isar.c ISAR (Siemens PSB 7110) specific routines
4 *
5 * Author Karsten Keil (keil@isdn4linux.de)
6 *
7 * This file is (c) under GNU General Public License
8 *
9 */
10
11 #include <linux/init.h>
12 #include "hisax.h"
13 #include "isar.h"
14 #include "isdnl1.h"
15 #include <linux/interrupt.h>
16
17 #define DBG_LOADFIRM 0
18 #define DUMP_MBOXFRAME 2
19
20 #define DLE 0x10
21 #define ETX 0x03
22
23 #define FAXMODCNT 13
24 const u_char faxmodulation[] = {3,24,48,72,73,74,96,97,98,121,122,145,146};
25 static u_int modmask = 0x1fff;
26 static int frm_extra_delay = 2;
27 static int para_TOA = 6;
28 const u_char *FC1_CMD[] = {"FAE", "FTS", "FRS", "FTM", "FRM", "FTH", "FRH", "CTRL" };
29
30 void isar_setup(struct IsdnCardState *cs);
31 static void isar_pump_cmd(struct BCState *bcs, u_char cmd, u_char para);
32 static void ll_deliver_faxstat(struct BCState *bcs, u_char status);
33
34 static inline int
35 waitforHIA(struct IsdnCardState *cs, int timeout)
36 {
37
38 while ((cs->BC_Read_Reg(cs, 0, ISAR_HIA) & 1) && timeout) {
39 udelay(1);
40 timeout--;
41 }
42 if (!timeout)
43 printk(KERN_WARNING "HiSax: ISAR waitforHIA timeout\n");
44 return(timeout);
45 }
46
47
48 int
49 sendmsg(struct IsdnCardState *cs, u_char his, u_char creg, u_char len,
50 u_char *msg)
51 {
52 int i;
53
54 if (!waitforHIA(cs, 4000))
55 return(0);
56 #if DUMP_MBOXFRAME
57 if (cs->debug & L1_DEB_HSCX)
58 debugl1(cs, "sendmsg(%02x,%02x,%d)", his, creg, len);
59 #endif
60 cs->BC_Write_Reg(cs, 0, ISAR_CTRL_H, creg);
61 cs->BC_Write_Reg(cs, 0, ISAR_CTRL_L, len);
62 cs->BC_Write_Reg(cs, 0, ISAR_WADR, 0);
63 if (msg && len) {
64 cs->BC_Write_Reg(cs, 1, ISAR_MBOX, msg[0]);
65 for (i=1; i<len; i++)
66 cs->BC_Write_Reg(cs, 2, ISAR_MBOX, msg[i]);
67 #if DUMP_MBOXFRAME>1
68 if (cs->debug & L1_DEB_HSCX_FIFO) {
69 char tmp[256], *t;
70
71 i = len;
72 while (i>0) {
73 t = tmp;
74 t += sprintf(t, "sendmbox cnt %d", len);
75 QuickHex(t, &msg[len-i], (i>64) ? 64:i);
76 debugl1(cs, tmp);
77 i -= 64;
78 }
79 }
80 #endif
81 }
82 cs->BC_Write_Reg(cs, 1, ISAR_HIS, his);
83 waitforHIA(cs, 10000);
84 return(1);
85 }
86
87 /* Call only with IRQ disabled !!! */
88 inline void
89 rcv_mbox(struct IsdnCardState *cs, struct isar_reg *ireg, u_char *msg)
90 {
91 int i;
92
93 cs->BC_Write_Reg(cs, 1, ISAR_RADR, 0);
94 if (msg && ireg->clsb) {
95 msg[0] = cs->BC_Read_Reg(cs, 1, ISAR_MBOX);
96 for (i=1; i < ireg->clsb; i++)
97 msg[i] = cs->BC_Read_Reg(cs, 2, ISAR_MBOX);
98 #if DUMP_MBOXFRAME>1
99 if (cs->debug & L1_DEB_HSCX_FIFO) {
100 char tmp[256], *t;
101
102 i = ireg->clsb;
103 while (i>0) {
104 t = tmp;
105 t += sprintf(t, "rcv_mbox cnt %d", ireg->clsb);
106 QuickHex(t, &msg[ireg->clsb-i], (i>64) ? 64:i);
107 debugl1(cs, tmp);
108 i -= 64;
109 }
110 }
111 #endif
112 }
113 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
114 }
115
116 /* Call only with IRQ disabled !!! */
117 inline void
118 get_irq_infos(struct IsdnCardState *cs, struct isar_reg *ireg)
119 {
120 ireg->iis = cs->BC_Read_Reg(cs, 1, ISAR_IIS);
121 ireg->cmsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_H);
122 ireg->clsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_L);
123 #if DUMP_MBOXFRAME
124 if (cs->debug & L1_DEB_HSCX)
125 debugl1(cs, "irq_stat(%02x,%02x,%d)", ireg->iis, ireg->cmsb,
126 ireg->clsb);
127 #endif
128 }
129
130 int
131 waitrecmsg(struct IsdnCardState *cs, u_char *len,
132 u_char *msg, int maxdelay)
133 {
134 int timeout = 0;
135 struct isar_reg *ir = cs->bcs[0].hw.isar.reg;
136
137
138 while((!(cs->BC_Read_Reg(cs, 0, ISAR_IRQBIT) & ISAR_IRQSTA)) &&
139 (timeout++ < maxdelay))
140 udelay(1);
141 if (timeout >= maxdelay) {
142 printk(KERN_WARNING"isar recmsg IRQSTA timeout\n");
143 return(0);
144 }
145 get_irq_infos(cs, ir);
146 rcv_mbox(cs, ir, msg);
147 *len = ir->clsb;
148 return(1);
149 }
150
151 int
152 ISARVersion(struct IsdnCardState *cs, char *s)
153 {
154 int ver;
155 u_char msg[] = ISAR_MSG_HWVER;
156 u_char tmp[64];
157 u_char len;
158 u_long flags;
159 int debug;
160
161 cs->cardmsg(cs, CARD_RESET, NULL);
162 spin_lock_irqsave(&cs->lock, flags);
163 /* disable ISAR IRQ */
164 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
165 debug = cs->debug;
166 cs->debug &= ~(L1_DEB_HSCX | L1_DEB_HSCX_FIFO);
167 if (!sendmsg(cs, ISAR_HIS_VNR, 0, 3, msg)) {
168 spin_unlock_irqrestore(&cs->lock, flags);
169 return(-1);
170 }
171 if (!waitrecmsg(cs, &len, tmp, 100000)) {
172 spin_unlock_irqrestore(&cs->lock, flags);
173 return(-2);
174 }
175 cs->debug = debug;
176 if (cs->bcs[0].hw.isar.reg->iis == ISAR_IIS_VNR) {
177 if (len == 1) {
178 ver = tmp[0] & 0xf;
179 printk(KERN_INFO "%s ISAR version %d\n", s, ver);
180 } else
181 ver = -3;
182 } else
183 ver = -4;
184 spin_unlock_irqrestore(&cs->lock, flags);
185 return(ver);
186 }
187
188 int
189 isar_load_firmware(struct IsdnCardState *cs, u_char __user *buf)
190 {
191 int ret, size, cnt, debug;
192 u_char len, nom, noc;
193 u_short sadr, left, *sp;
194 u_char __user *p = buf;
195 u_char *msg, *tmpmsg, *mp, tmp[64];
196 u_long flags;
197 struct isar_reg *ireg = cs->bcs[0].hw.isar.reg;
198
199 struct {u_short sadr;
200 u_short len;
201 u_short d_key;
202 } blk_head;
203
204 #define BLK_HEAD_SIZE 6
205 if (1 != (ret = ISARVersion(cs, "Testing"))) {
206 printk(KERN_ERR"isar_load_firmware wrong isar version %d\n", ret);
207 return(1);
208 }
209 debug = cs->debug;
210 #if DBG_LOADFIRM<2
211 cs->debug &= ~(L1_DEB_HSCX | L1_DEB_HSCX_FIFO);
212 #endif
213
214 if ((ret = copy_from_user(&size, p, sizeof(int)))) {
215 printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret);
216 return ret;
217 }
218 p += sizeof(int);
219 printk(KERN_DEBUG"isar_load_firmware size: %d\n", size);
220 cnt = 0;
221 /* disable ISAR IRQ */
222 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
223 if (!(msg = kmalloc(256, GFP_KERNEL))) {
224 printk(KERN_ERR"isar_load_firmware no buffer\n");
225 return (1);
226 }
227 if (!(tmpmsg = kmalloc(256, GFP_KERNEL))) {
228 printk(KERN_ERR"isar_load_firmware no tmp buffer\n");
229 kfree(msg);
230 return (1);
231 }
232 spin_lock_irqsave(&cs->lock, flags);
233 /* disable ISAR IRQ */
234 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
235 spin_unlock_irqrestore(&cs->lock, flags);
236 while (cnt < size) {
237 if ((ret = copy_from_user(&blk_head, p, BLK_HEAD_SIZE))) {
238 printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret);
239 goto reterror;
240 }
241 #ifdef __BIG_ENDIAN
242 sadr = (blk_head.sadr & 0xff)*256 + blk_head.sadr/256;
243 blk_head.sadr = sadr;
244 sadr = (blk_head.len & 0xff)*256 + blk_head.len/256;
245 blk_head.len = sadr;
246 sadr = (blk_head.d_key & 0xff)*256 + blk_head.d_key/256;
247 blk_head.d_key = sadr;
248 #endif /* __BIG_ENDIAN */
249 cnt += BLK_HEAD_SIZE;
250 p += BLK_HEAD_SIZE;
251 printk(KERN_DEBUG"isar firmware block (%#x,%5d,%#x)\n",
252 blk_head.sadr, blk_head.len, blk_head.d_key & 0xff);
253 sadr = blk_head.sadr;
254 left = blk_head.len;
255 spin_lock_irqsave(&cs->lock, flags);
256 if (!sendmsg(cs, ISAR_HIS_DKEY, blk_head.d_key & 0xff, 0, NULL)) {
257 printk(KERN_ERR"isar sendmsg dkey failed\n");
258 ret = 1;goto reterr_unlock;
259 }
260 if (!waitrecmsg(cs, &len, tmp, 100000)) {
261 printk(KERN_ERR"isar waitrecmsg dkey failed\n");
262 ret = 1;goto reterr_unlock;
263 }
264 if ((ireg->iis != ISAR_IIS_DKEY) || ireg->cmsb || len) {
265 printk(KERN_ERR"isar wrong dkey response (%x,%x,%x)\n",
266 ireg->iis, ireg->cmsb, len);
267 ret = 1;goto reterr_unlock;
268 }
269 spin_unlock_irqrestore(&cs->lock, flags);
270 while (left>0) {
271 if (left > 126)
272 noc = 126;
273 else
274 noc = left;
275 nom = 2*noc;
276 mp = msg;
277 *mp++ = sadr / 256;
278 *mp++ = sadr % 256;
279 left -= noc;
280 *mp++ = noc;
281 if ((ret = copy_from_user(tmpmsg, p, nom))) {
282 printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret);
283 goto reterror;
284 }
285 p += nom;
286 cnt += nom;
287 nom += 3;
288 sp = (u_short *)tmpmsg;
289 #if DBG_LOADFIRM
290 printk(KERN_DEBUG"isar: load %3d words at %04x left %d\n",
291 noc, sadr, left);
292 #endif
293 sadr += noc;
294 while(noc) {
295 #ifdef __BIG_ENDIAN
296 *mp++ = *sp % 256;
297 *mp++ = *sp / 256;
298 #else
299 *mp++ = *sp / 256;
300 *mp++ = *sp % 256;
301 #endif /* __BIG_ENDIAN */
302 sp++;
303 noc--;
304 }
305 spin_lock_irqsave(&cs->lock, flags);
306 if (!sendmsg(cs, ISAR_HIS_FIRM, 0, nom, msg)) {
307 printk(KERN_ERR"isar sendmsg prog failed\n");
308 ret = 1;goto reterr_unlock;
309 }
310 if (!waitrecmsg(cs, &len, tmp, 100000)) {
311 printk(KERN_ERR"isar waitrecmsg prog failed\n");
312 ret = 1;goto reterr_unlock;
313 }
314 if ((ireg->iis != ISAR_IIS_FIRM) || ireg->cmsb || len) {
315 printk(KERN_ERR"isar wrong prog response (%x,%x,%x)\n",
316 ireg->iis, ireg->cmsb, len);
317 ret = 1;goto reterr_unlock;
318 }
319 spin_unlock_irqrestore(&cs->lock, flags);
320 }
321 printk(KERN_DEBUG"isar firmware block %5d words loaded\n",
322 blk_head.len);
323 }
324 /* 10ms delay */
325 cnt = 10;
326 while (cnt--)
327 udelay(1000);
328 msg[0] = 0xff;
329 msg[1] = 0xfe;
330 ireg->bstat = 0;
331 spin_lock_irqsave(&cs->lock, flags);
332 if (!sendmsg(cs, ISAR_HIS_STDSP, 0, 2, msg)) {
333 printk(KERN_ERR"isar sendmsg start dsp failed\n");
334 ret = 1;goto reterr_unlock;
335 }
336 if (!waitrecmsg(cs, &len, tmp, 100000)) {
337 printk(KERN_ERR"isar waitrecmsg start dsp failed\n");
338 ret = 1;goto reterr_unlock;
339 }
340 if ((ireg->iis != ISAR_IIS_STDSP) || ireg->cmsb || len) {
341 printk(KERN_ERR"isar wrong start dsp response (%x,%x,%x)\n",
342 ireg->iis, ireg->cmsb, len);
343 ret = 1;goto reterr_unlock;
344 } else
345 printk(KERN_DEBUG"isar start dsp success\n");
346 /* NORMAL mode entered */
347 /* Enable IRQs of ISAR */
348 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, ISAR_IRQSTA);
349 spin_unlock_irqrestore(&cs->lock, flags);
350 cnt = 1000; /* max 1s */
351 while ((!ireg->bstat) && cnt) {
352 udelay(1000);
353 cnt--;
354 }
355 if (!cnt) {
356 printk(KERN_ERR"isar no general status event received\n");
357 ret = 1;goto reterror;
358 } else {
359 printk(KERN_DEBUG"isar general status event %x\n",
360 ireg->bstat);
361 }
362 /* 10ms delay */
363 cnt = 10;
364 while (cnt--)
365 udelay(1000);
366 spin_lock_irqsave(&cs->lock, flags);
367 ireg->iis = 0;
368 if (!sendmsg(cs, ISAR_HIS_DIAG, ISAR_CTRL_STST, 0, NULL)) {
369 printk(KERN_ERR"isar sendmsg self tst failed\n");
370 ret = 1;goto reterr_unlock;
371 }
372 cnt = 10000; /* max 100 ms */
373 spin_unlock_irqrestore(&cs->lock, flags);
374 while ((ireg->iis != ISAR_IIS_DIAG) && cnt) {
375 udelay(10);
376 cnt--;
377 }
378 udelay(1000);
379 if (!cnt) {
380 printk(KERN_ERR"isar no self tst response\n");
381 ret = 1;goto reterror;
382 }
383 if ((ireg->cmsb == ISAR_CTRL_STST) && (ireg->clsb == 1)
384 && (ireg->par[0] == 0)) {
385 printk(KERN_DEBUG"isar selftest OK\n");
386 } else {
387 printk(KERN_DEBUG"isar selftest not OK %x/%x/%x\n",
388 ireg->cmsb, ireg->clsb, ireg->par[0]);
389 ret = 1;goto reterror;
390 }
391 spin_lock_irqsave(&cs->lock, flags);
392 ireg->iis = 0;
393 if (!sendmsg(cs, ISAR_HIS_DIAG, ISAR_CTRL_SWVER, 0, NULL)) {
394 printk(KERN_ERR"isar RQST SVN failed\n");
395 ret = 1;goto reterr_unlock;
396 }
397 spin_unlock_irqrestore(&cs->lock, flags);
398 cnt = 30000; /* max 300 ms */
399 while ((ireg->iis != ISAR_IIS_DIAG) && cnt) {
400 udelay(10);
401 cnt--;
402 }
403 udelay(1000);
404 if (!cnt) {
405 printk(KERN_ERR"isar no SVN response\n");
406 ret = 1;goto reterror;
407 } else {
408 if ((ireg->cmsb == ISAR_CTRL_SWVER) && (ireg->clsb == 1))
409 printk(KERN_DEBUG"isar software version %#x\n",
410 ireg->par[0]);
411 else {
412 printk(KERN_ERR"isar wrong swver response (%x,%x) cnt(%d)\n",
413 ireg->cmsb, ireg->clsb, cnt);
414 ret = 1;goto reterror;
415 }
416 }
417 spin_lock_irqsave(&cs->lock, flags);
418 cs->debug = debug;
419 isar_setup(cs);
420
421 ret = 0;
422 reterr_unlock:
423 spin_unlock_irqrestore(&cs->lock, flags);
424 reterror:
425 cs->debug = debug;
426 if (ret)
427 /* disable ISAR IRQ */
428 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
429 kfree(msg);
430 kfree(tmpmsg);
431 return(ret);
432 }
433
434 extern void BChannel_bh(struct BCState *);
435 #define B_LL_NOCARRIER 8
436 #define B_LL_CONNECT 9
437 #define B_LL_OK 10
438
439 static void
440 isar_bh(struct BCState *bcs)
441 {
442 BChannel_bh(bcs);
443 if (test_and_clear_bit(B_LL_NOCARRIER, &bcs->event))
444 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_NOCARR);
445 if (test_and_clear_bit(B_LL_CONNECT, &bcs->event))
446 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
447 if (test_and_clear_bit(B_LL_OK, &bcs->event))
448 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_OK);
449 }
450
451 static void
452 send_DLE_ETX(struct BCState *bcs)
453 {
454 u_char dleetx[2] = {DLE,ETX};
455 struct sk_buff *skb;
456
457 if ((skb = dev_alloc_skb(2))) {
458 memcpy(skb_put(skb, 2), dleetx, 2);
459 skb_queue_tail(&bcs->rqueue, skb);
460 schedule_event(bcs, B_RCVBUFREADY);
461 } else {
462 printk(KERN_WARNING "HiSax: skb out of memory\n");
463 }
464 }
465
466 static inline int
467 dle_count(unsigned char *buf, int len)
468 {
469 int count = 0;
470
471 while (len--)
472 if (*buf++ == DLE)
473 count++;
474 return count;
475 }
476
477 static inline void
478 insert_dle(unsigned char *dest, unsigned char *src, int count) {
479 /* <DLE> in input stream have to be flagged as <DLE><DLE> */
480 while (count--) {
481 *dest++ = *src;
482 if (*src++ == DLE)
483 *dest++ = DLE;
484 }
485 }
486
487 static void
488 isar_rcv_frame(struct IsdnCardState *cs, struct BCState *bcs)
489 {
490 u_char *ptr;
491 struct sk_buff *skb;
492 struct isar_reg *ireg = bcs->hw.isar.reg;
493
494 if (!ireg->clsb) {
495 debugl1(cs, "isar zero len frame");
496 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
497 return;
498 }
499 switch (bcs->mode) {
500 case L1_MODE_NULL:
501 debugl1(cs, "isar mode 0 spurious IIS_RDATA %x/%x/%x",
502 ireg->iis, ireg->cmsb, ireg->clsb);
503 printk(KERN_WARNING"isar mode 0 spurious IIS_RDATA %x/%x/%x\n",
504 ireg->iis, ireg->cmsb, ireg->clsb);
505 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
506 break;
507 case L1_MODE_TRANS:
508 case L1_MODE_V32:
509 if ((skb = dev_alloc_skb(ireg->clsb))) {
510 rcv_mbox(cs, ireg, (u_char *)skb_put(skb, ireg->clsb));
511 skb_queue_tail(&bcs->rqueue, skb);
512 schedule_event(bcs, B_RCVBUFREADY);
513 } else {
514 printk(KERN_WARNING "HiSax: skb out of memory\n");
515 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
516 }
517 break;
518 case L1_MODE_HDLC:
519 if ((bcs->hw.isar.rcvidx + ireg->clsb) > HSCX_BUFMAX) {
520 if (cs->debug & L1_DEB_WARN)
521 debugl1(cs, "isar_rcv_frame: incoming packet too large");
522 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
523 bcs->hw.isar.rcvidx = 0;
524 } else if (ireg->cmsb & HDLC_ERROR) {
525 if (cs->debug & L1_DEB_WARN)
526 debugl1(cs, "isar frame error %x len %d",
527 ireg->cmsb, ireg->clsb);
528 #ifdef ERROR_STATISTIC
529 if (ireg->cmsb & HDLC_ERR_RER)
530 bcs->err_inv++;
531 if (ireg->cmsb & HDLC_ERR_CER)
532 bcs->err_crc++;
533 #endif
534 bcs->hw.isar.rcvidx = 0;
535 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
536 } else {
537 if (ireg->cmsb & HDLC_FSD)
538 bcs->hw.isar.rcvidx = 0;
539 ptr = bcs->hw.isar.rcvbuf + bcs->hw.isar.rcvidx;
540 bcs->hw.isar.rcvidx += ireg->clsb;
541 rcv_mbox(cs, ireg, ptr);
542 if (ireg->cmsb & HDLC_FED) {
543 if (bcs->hw.isar.rcvidx < 3) { /* last 2 bytes are the FCS */
544 if (cs->debug & L1_DEB_WARN)
545 debugl1(cs, "isar frame to short %d",
546 bcs->hw.isar.rcvidx);
547 } else if (!(skb = dev_alloc_skb(bcs->hw.isar.rcvidx-2))) {
548 printk(KERN_WARNING "ISAR: receive out of memory\n");
549 } else {
550 memcpy(skb_put(skb, bcs->hw.isar.rcvidx-2),
551 bcs->hw.isar.rcvbuf, bcs->hw.isar.rcvidx-2);
552 skb_queue_tail(&bcs->rqueue, skb);
553 schedule_event(bcs, B_RCVBUFREADY);
554 }
555 bcs->hw.isar.rcvidx = 0;
556 }
557 }
558 break;
559 case L1_MODE_FAX:
560 if (bcs->hw.isar.state != STFAX_ACTIV) {
561 if (cs->debug & L1_DEB_WARN)
562 debugl1(cs, "isar_rcv_frame: not ACTIV");
563 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
564 bcs->hw.isar.rcvidx = 0;
565 break;
566 }
567 if (bcs->hw.isar.cmd == PCTRL_CMD_FRM) {
568 rcv_mbox(cs, ireg, bcs->hw.isar.rcvbuf);
569 bcs->hw.isar.rcvidx = ireg->clsb +
570 dle_count(bcs->hw.isar.rcvbuf, ireg->clsb);
571 if (cs->debug & L1_DEB_HSCX)
572 debugl1(cs, "isar_rcv_frame: raw(%d) dle(%d)",
573 ireg->clsb, bcs->hw.isar.rcvidx);
574 if ((skb = dev_alloc_skb(bcs->hw.isar.rcvidx))) {
575 insert_dle((u_char *)skb_put(skb, bcs->hw.isar.rcvidx),
576 bcs->hw.isar.rcvbuf, ireg->clsb);
577 skb_queue_tail(&bcs->rqueue, skb);
578 schedule_event(bcs, B_RCVBUFREADY);
579 if (ireg->cmsb & SART_NMD) { /* ABORT */
580 if (cs->debug & L1_DEB_WARN)
581 debugl1(cs, "isar_rcv_frame: no more data");
582 bcs->hw.isar.rcvidx = 0;
583 send_DLE_ETX(bcs);
584 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) |
585 ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC,
586 0, NULL);
587 bcs->hw.isar.state = STFAX_ESCAPE;
588 schedule_event(bcs, B_LL_NOCARRIER);
589 }
590 } else {
591 printk(KERN_WARNING "HiSax: skb out of memory\n");
592 }
593 break;
594 }
595 if (bcs->hw.isar.cmd != PCTRL_CMD_FRH) {
596 if (cs->debug & L1_DEB_WARN)
597 debugl1(cs, "isar_rcv_frame: unknown fax mode %x",
598 bcs->hw.isar.cmd);
599 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
600 bcs->hw.isar.rcvidx = 0;
601 break;
602 }
603 /* PCTRL_CMD_FRH */
604 if ((bcs->hw.isar.rcvidx + ireg->clsb) > HSCX_BUFMAX) {
605 if (cs->debug & L1_DEB_WARN)
606 debugl1(cs, "isar_rcv_frame: incoming packet too large");
607 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
608 bcs->hw.isar.rcvidx = 0;
609 } else if (ireg->cmsb & HDLC_ERROR) {
610 if (cs->debug & L1_DEB_WARN)
611 debugl1(cs, "isar frame error %x len %d",
612 ireg->cmsb, ireg->clsb);
613 bcs->hw.isar.rcvidx = 0;
614 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
615 } else {
616 if (ireg->cmsb & HDLC_FSD) {
617 bcs->hw.isar.rcvidx = 0;
618 }
619 ptr = bcs->hw.isar.rcvbuf + bcs->hw.isar.rcvidx;
620 bcs->hw.isar.rcvidx += ireg->clsb;
621 rcv_mbox(cs, ireg, ptr);
622 if (ireg->cmsb & HDLC_FED) {
623 int len = bcs->hw.isar.rcvidx +
624 dle_count(bcs->hw.isar.rcvbuf, bcs->hw.isar.rcvidx);
625 if (bcs->hw.isar.rcvidx < 3) { /* last 2 bytes are the FCS */
626 if (cs->debug & L1_DEB_WARN)
627 debugl1(cs, "isar frame to short %d",
628 bcs->hw.isar.rcvidx);
629 printk(KERN_WARNING "ISAR: frame to short %d\n",
630 bcs->hw.isar.rcvidx);
631 } else if (!(skb = dev_alloc_skb(len))) {
632 printk(KERN_WARNING "ISAR: receive out of memory\n");
633 } else {
634 insert_dle((u_char *)skb_put(skb, len),
635 bcs->hw.isar.rcvbuf,
636 bcs->hw.isar.rcvidx);
637 skb_queue_tail(&bcs->rqueue, skb);
638 schedule_event(bcs, B_RCVBUFREADY);
639 send_DLE_ETX(bcs);
640 schedule_event(bcs, B_LL_OK);
641 test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
642 }
643 bcs->hw.isar.rcvidx = 0;
644 }
645 }
646 if (ireg->cmsb & SART_NMD) { /* ABORT */
647 if (cs->debug & L1_DEB_WARN)
648 debugl1(cs, "isar_rcv_frame: no more data");
649 bcs->hw.isar.rcvidx = 0;
650 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) |
651 ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC, 0, NULL);
652 bcs->hw.isar.state = STFAX_ESCAPE;
653 if (test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag)) {
654 send_DLE_ETX(bcs);
655 schedule_event(bcs, B_LL_NOCARRIER);
656 }
657 }
658 break;
659 default:
660 printk(KERN_ERR"isar_rcv_frame mode (%x)error\n", bcs->mode);
661 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
662 break;
663 }
664 }
665
666 void
667 isar_fill_fifo(struct BCState *bcs)
668 {
669 struct IsdnCardState *cs = bcs->cs;
670 int count;
671 u_char msb;
672 u_char *ptr;
673
674 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
675 debugl1(cs, "isar_fill_fifo");
676 if (!bcs->tx_skb)
677 return;
678 if (bcs->tx_skb->len <= 0)
679 return;
680 if (!(bcs->hw.isar.reg->bstat &
681 (bcs->hw.isar.dpath == 1 ? BSTAT_RDM1 : BSTAT_RDM2)))
682 return;
683 if (bcs->tx_skb->len > bcs->hw.isar.mml) {
684 msb = 0;
685 count = bcs->hw.isar.mml;
686 } else {
687 count = bcs->tx_skb->len;
688 msb = HDLC_FED;
689 }
690 ptr = bcs->tx_skb->data;
691 if (!bcs->hw.isar.txcnt) {
692 msb |= HDLC_FST;
693 if ((bcs->mode == L1_MODE_FAX) &&
694 (bcs->hw.isar.cmd == PCTRL_CMD_FTH)) {
695 if (bcs->tx_skb->len > 1) {
696 if ((ptr[0]== 0xff) && (ptr[1] == 0x13))
697 /* last frame */
698 test_and_set_bit(BC_FLG_LASTDATA,
699 &bcs->Flag);
700 }
701 }
702 }
703 skb_pull(bcs->tx_skb, count);
704 bcs->tx_cnt -= count;
705 bcs->hw.isar.txcnt += count;
706 switch (bcs->mode) {
707 case L1_MODE_NULL:
708 printk(KERN_ERR"isar_fill_fifo wrong mode 0\n");
709 break;
710 case L1_MODE_TRANS:
711 case L1_MODE_V32:
712 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
713 0, count, ptr);
714 break;
715 case L1_MODE_HDLC:
716 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
717 msb, count, ptr);
718 break;
719 case L1_MODE_FAX:
720 if (bcs->hw.isar.state != STFAX_ACTIV) {
721 if (cs->debug & L1_DEB_WARN)
722 debugl1(cs, "isar_fill_fifo: not ACTIV");
723 } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) {
724 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
725 msb, count, ptr);
726 } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTM) {
727 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
728 0, count, ptr);
729 } else {
730 if (cs->debug & L1_DEB_WARN)
731 debugl1(cs, "isar_fill_fifo: not FTH/FTM");
732 }
733 break;
734 default:
735 if (cs->debug)
736 debugl1(cs, "isar_fill_fifo mode(%x) error", bcs->mode);
737 printk(KERN_ERR"isar_fill_fifo mode(%x) error\n", bcs->mode);
738 break;
739 }
740 }
741
742 inline
743 struct BCState *sel_bcs_isar(struct IsdnCardState *cs, u_char dpath)
744 {
745 if ((!dpath) || (dpath == 3))
746 return(NULL);
747 if (cs->bcs[0].hw.isar.dpath == dpath)
748 return(&cs->bcs[0]);
749 if (cs->bcs[1].hw.isar.dpath == dpath)
750 return(&cs->bcs[1]);
751 return(NULL);
752 }
753
754 void
755 send_frames(struct BCState *bcs)
756 {
757 if (bcs->tx_skb) {
758 if (bcs->tx_skb->len) {
759 isar_fill_fifo(bcs);
760 return;
761 } else {
762 if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
763 (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
764 u_long flags;
765 spin_lock_irqsave(&bcs->aclock, flags);
766 bcs->ackcnt += bcs->hw.isar.txcnt;
767 spin_unlock_irqrestore(&bcs->aclock, flags);
768 schedule_event(bcs, B_ACKPENDING);
769 }
770 if (bcs->mode == L1_MODE_FAX) {
771 if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) {
772 if (test_bit(BC_FLG_LASTDATA, &bcs->Flag)) {
773 test_and_set_bit(BC_FLG_NMD_DATA, &bcs->Flag);
774 }
775 } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTM) {
776 if (test_bit(BC_FLG_DLEETX, &bcs->Flag)) {
777 test_and_set_bit(BC_FLG_LASTDATA, &bcs->Flag);
778 test_and_set_bit(BC_FLG_NMD_DATA, &bcs->Flag);
779 }
780 }
781 }
782 dev_kfree_skb_any(bcs->tx_skb);
783 bcs->hw.isar.txcnt = 0;
784 bcs->tx_skb = NULL;
785 }
786 }
787 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
788 bcs->hw.isar.txcnt = 0;
789 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
790 isar_fill_fifo(bcs);
791 } else {
792 if (test_and_clear_bit(BC_FLG_DLEETX, &bcs->Flag)) {
793 if (test_and_clear_bit(BC_FLG_LASTDATA, &bcs->Flag)) {
794 if (test_and_clear_bit(BC_FLG_NMD_DATA, &bcs->Flag)) {
795 u_char dummy = 0;
796 sendmsg(bcs->cs, SET_DPS(bcs->hw.isar.dpath) |
797 ISAR_HIS_SDATA, 0x01, 1, &dummy);
798 }
799 test_and_set_bit(BC_FLG_LL_OK, &bcs->Flag);
800 } else {
801 schedule_event(bcs, B_LL_CONNECT);
802 }
803 }
804 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
805 schedule_event(bcs, B_XMTBUFREADY);
806 }
807 }
808
809 inline void
810 check_send(struct IsdnCardState *cs, u_char rdm)
811 {
812 struct BCState *bcs;
813
814 if (rdm & BSTAT_RDM1) {
815 if ((bcs = sel_bcs_isar(cs, 1))) {
816 if (bcs->mode) {
817 send_frames(bcs);
818 }
819 }
820 }
821 if (rdm & BSTAT_RDM2) {
822 if ((bcs = sel_bcs_isar(cs, 2))) {
823 if (bcs->mode) {
824 send_frames(bcs);
825 }
826 }
827 }
828
829 }
830
831 const char *dmril[] = {"NO SPEED", "1200/75", "NODEF2", "75/1200", "NODEF4",
832 "300", "600", "1200", "2400", "4800", "7200",
833 "9600nt", "9600t", "12000", "14400", "WRONG"};
834 const char *dmrim[] = {"NO MOD", "NO DEF", "V32/V32b", "V22", "V21",
835 "Bell103", "V23", "Bell202", "V17", "V29", "V27ter"};
836
837 static void
838 isar_pump_status_rsp(struct BCState *bcs, struct isar_reg *ireg) {
839 struct IsdnCardState *cs = bcs->cs;
840 u_char ril = ireg->par[0];
841 u_char rim;
842
843 if (!test_and_clear_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags))
844 return;
845 if (ril > 14) {
846 if (cs->debug & L1_DEB_WARN)
847 debugl1(cs, "wrong pstrsp ril=%d",ril);
848 ril = 15;
849 }
850 switch(ireg->par[1]) {
851 case 0:
852 rim = 0;
853 break;
854 case 0x20:
855 rim = 2;
856 break;
857 case 0x40:
858 rim = 3;
859 break;
860 case 0x41:
861 rim = 4;
862 break;
863 case 0x51:
864 rim = 5;
865 break;
866 case 0x61:
867 rim = 6;
868 break;
869 case 0x71:
870 rim = 7;
871 break;
872 case 0x82:
873 rim = 8;
874 break;
875 case 0x92:
876 rim = 9;
877 break;
878 case 0xa2:
879 rim = 10;
880 break;
881 default:
882 rim = 1;
883 break;
884 }
885 sprintf(bcs->hw.isar.conmsg,"%s %s", dmril[ril], dmrim[rim]);
886 bcs->conmsg = bcs->hw.isar.conmsg;
887 if (cs->debug & L1_DEB_HSCX)
888 debugl1(cs, "pump strsp %s", bcs->conmsg);
889 }
890
891 static void
892 isar_pump_statev_modem(struct BCState *bcs, u_char devt) {
893 struct IsdnCardState *cs = bcs->cs;
894 u_char dps = SET_DPS(bcs->hw.isar.dpath);
895
896 switch(devt) {
897 case PSEV_10MS_TIMER:
898 if (cs->debug & L1_DEB_HSCX)
899 debugl1(cs, "pump stev TIMER");
900 break;
901 case PSEV_CON_ON:
902 if (cs->debug & L1_DEB_HSCX)
903 debugl1(cs, "pump stev CONNECT");
904 l1_msg_b(bcs->st, PH_ACTIVATE | REQUEST, NULL);
905 break;
906 case PSEV_CON_OFF:
907 if (cs->debug & L1_DEB_HSCX)
908 debugl1(cs, "pump stev NO CONNECT");
909 sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
910 l1_msg_b(bcs->st, PH_DEACTIVATE | REQUEST, NULL);
911 break;
912 case PSEV_V24_OFF:
913 if (cs->debug & L1_DEB_HSCX)
914 debugl1(cs, "pump stev V24 OFF");
915 break;
916 case PSEV_CTS_ON:
917 if (cs->debug & L1_DEB_HSCX)
918 debugl1(cs, "pump stev CTS ON");
919 break;
920 case PSEV_CTS_OFF:
921 if (cs->debug & L1_DEB_HSCX)
922 debugl1(cs, "pump stev CTS OFF");
923 break;
924 case PSEV_DCD_ON:
925 if (cs->debug & L1_DEB_HSCX)
926 debugl1(cs, "pump stev CARRIER ON");
927 test_and_set_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags);
928 sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
929 break;
930 case PSEV_DCD_OFF:
931 if (cs->debug & L1_DEB_HSCX)
932 debugl1(cs, "pump stev CARRIER OFF");
933 break;
934 case PSEV_DSR_ON:
935 if (cs->debug & L1_DEB_HSCX)
936 debugl1(cs, "pump stev DSR ON");
937 break;
938 case PSEV_DSR_OFF:
939 if (cs->debug & L1_DEB_HSCX)
940 debugl1(cs, "pump stev DSR_OFF");
941 break;
942 case PSEV_REM_RET:
943 if (cs->debug & L1_DEB_HSCX)
944 debugl1(cs, "pump stev REMOTE RETRAIN");
945 break;
946 case PSEV_REM_REN:
947 if (cs->debug & L1_DEB_HSCX)
948 debugl1(cs, "pump stev REMOTE RENEGOTIATE");
949 break;
950 case PSEV_GSTN_CLR:
951 if (cs->debug & L1_DEB_HSCX)
952 debugl1(cs, "pump stev GSTN CLEAR", devt);
953 break;
954 default:
955 if (cs->debug & L1_DEB_HSCX)
956 debugl1(cs, "unknown pump stev %x", devt);
957 break;
958 }
959 }
960
961 static void
962 ll_deliver_faxstat(struct BCState *bcs, u_char status)
963 {
964 isdn_ctrl ic;
965 struct Channel *chanp = (struct Channel *) bcs->st->lli.userdata;
966
967 if (bcs->cs->debug & L1_DEB_HSCX)
968 debugl1(bcs->cs, "HL->LL FAXIND %x", status);
969 ic.driver = bcs->cs->myid;
970 ic.command = ISDN_STAT_FAXIND;
971 ic.arg = chanp->chan;
972 ic.parm.aux.cmd = status;
973 bcs->cs->iif.statcallb(&ic);
974 }
975
976 static void
977 isar_pump_statev_fax(struct BCState *bcs, u_char devt) {
978 struct IsdnCardState *cs = bcs->cs;
979 u_char dps = SET_DPS(bcs->hw.isar.dpath);
980 u_char p1;
981
982 switch(devt) {
983 case PSEV_10MS_TIMER:
984 if (cs->debug & L1_DEB_HSCX)
985 debugl1(cs, "pump stev TIMER");
986 break;
987 case PSEV_RSP_READY:
988 if (cs->debug & L1_DEB_HSCX)
989 debugl1(cs, "pump stev RSP_READY");
990 bcs->hw.isar.state = STFAX_READY;
991 l1_msg_b(bcs->st, PH_ACTIVATE | REQUEST, NULL);
992 if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
993 isar_pump_cmd(bcs, ISDN_FAX_CLASS1_FRH, 3);
994 } else {
995 isar_pump_cmd(bcs, ISDN_FAX_CLASS1_FTH, 3);
996 }
997 break;
998 case PSEV_LINE_TX_H:
999 if (bcs->hw.isar.state == STFAX_LINE) {
1000 if (cs->debug & L1_DEB_HSCX)
1001 debugl1(cs, "pump stev LINE_TX_H");
1002 bcs->hw.isar.state = STFAX_CONT;
1003 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
1004 } else {
1005 if (cs->debug & L1_DEB_WARN)
1006 debugl1(cs, "pump stev LINE_TX_H wrong st %x",
1007 bcs->hw.isar.state);
1008 }
1009 break;
1010 case PSEV_LINE_RX_H:
1011 if (bcs->hw.isar.state == STFAX_LINE) {
1012 if (cs->debug & L1_DEB_HSCX)
1013 debugl1(cs, "pump stev LINE_RX_H");
1014 bcs->hw.isar.state = STFAX_CONT;
1015 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
1016 } else {
1017 if (cs->debug & L1_DEB_WARN)
1018 debugl1(cs, "pump stev LINE_RX_H wrong st %x",
1019 bcs->hw.isar.state);
1020 }
1021 break;
1022 case PSEV_LINE_TX_B:
1023 if (bcs->hw.isar.state == STFAX_LINE) {
1024 if (cs->debug & L1_DEB_HSCX)
1025 debugl1(cs, "pump stev LINE_TX_B");
1026 bcs->hw.isar.state = STFAX_CONT;
1027 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
1028 } else {
1029 if (cs->debug & L1_DEB_WARN)
1030 debugl1(cs, "pump stev LINE_TX_B wrong st %x",
1031 bcs->hw.isar.state);
1032 }
1033 break;
1034 case PSEV_LINE_RX_B:
1035 if (bcs->hw.isar.state == STFAX_LINE) {
1036 if (cs->debug & L1_DEB_HSCX)
1037 debugl1(cs, "pump stev LINE_RX_B");
1038 bcs->hw.isar.state = STFAX_CONT;
1039 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
1040 } else {
1041 if (cs->debug & L1_DEB_WARN)
1042 debugl1(cs, "pump stev LINE_RX_B wrong st %x",
1043 bcs->hw.isar.state);
1044 }
1045 break;
1046 case PSEV_RSP_CONN:
1047 if (bcs->hw.isar.state == STFAX_CONT) {
1048 if (cs->debug & L1_DEB_HSCX)
1049 debugl1(cs, "pump stev RSP_CONN");
1050 bcs->hw.isar.state = STFAX_ACTIV;
1051 test_and_set_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags);
1052 sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
1053 if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) {
1054 /* 1s Flags before data */
1055 if (test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag))
1056 del_timer(&bcs->hw.isar.ftimer);
1057 /* 1000 ms */
1058 bcs->hw.isar.ftimer.expires =
1059 jiffies + ((1000 * HZ)/1000);
1060 test_and_set_bit(BC_FLG_LL_CONN,
1061 &bcs->Flag);
1062 add_timer(&bcs->hw.isar.ftimer);
1063 } else {
1064 schedule_event(bcs, B_LL_CONNECT);
1065 }
1066 } else {
1067 if (cs->debug & L1_DEB_WARN)
1068 debugl1(cs, "pump stev RSP_CONN wrong st %x",
1069 bcs->hw.isar.state);
1070 }
1071 break;
1072 case PSEV_FLAGS_DET:
1073 if (cs->debug & L1_DEB_HSCX)
1074 debugl1(cs, "pump stev FLAGS_DET");
1075 break;
1076 case PSEV_RSP_DISC:
1077 if (cs->debug & L1_DEB_HSCX)
1078 debugl1(cs, "pump stev RSP_DISC");
1079 if (bcs->hw.isar.state == STFAX_ESCAPE) {
1080 p1 = 5;
1081 switch(bcs->hw.isar.newcmd) {
1082 case 0:
1083 bcs->hw.isar.state = STFAX_READY;
1084 break;
1085 case PCTRL_CMD_FTM:
1086 p1 = 2;
1087 case PCTRL_CMD_FTH:
1088 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
1089 PCTRL_CMD_SILON, 1, &p1);
1090 bcs->hw.isar.state = STFAX_SILDET;
1091 break;
1092 case PCTRL_CMD_FRM:
1093 if (frm_extra_delay)
1094 mdelay(frm_extra_delay);
1095 case PCTRL_CMD_FRH:
1096 p1 = bcs->hw.isar.mod = bcs->hw.isar.newmod;
1097 bcs->hw.isar.newmod = 0;
1098 bcs->hw.isar.cmd = bcs->hw.isar.newcmd;
1099 bcs->hw.isar.newcmd = 0;
1100 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
1101 bcs->hw.isar.cmd, 1, &p1);
1102 bcs->hw.isar.state = STFAX_LINE;
1103 bcs->hw.isar.try_mod = 3;
1104 break;
1105 default:
1106 if (cs->debug & L1_DEB_HSCX)
1107 debugl1(cs, "RSP_DISC unknown newcmd %x", bcs->hw.isar.newcmd);
1108 break;
1109 }
1110 } else if (bcs->hw.isar.state == STFAX_ACTIV) {
1111 if (test_and_clear_bit(BC_FLG_LL_OK, &bcs->Flag)) {
1112 schedule_event(bcs, B_LL_OK);
1113 } else if (bcs->hw.isar.cmd == PCTRL_CMD_FRM) {
1114 send_DLE_ETX(bcs);
1115 schedule_event(bcs, B_LL_NOCARRIER);
1116 } else {
1117 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR);
1118 }
1119 bcs->hw.isar.state = STFAX_READY;
1120 } else {
1121 bcs->hw.isar.state = STFAX_READY;
1122 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR);
1123 }
1124 break;
1125 case PSEV_RSP_SILDET:
1126 if (cs->debug & L1_DEB_HSCX)
1127 debugl1(cs, "pump stev RSP_SILDET");
1128 if (bcs->hw.isar.state == STFAX_SILDET) {
1129 p1 = bcs->hw.isar.mod = bcs->hw.isar.newmod;
1130 bcs->hw.isar.newmod = 0;
1131 bcs->hw.isar.cmd = bcs->hw.isar.newcmd;
1132 bcs->hw.isar.newcmd = 0;
1133 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
1134 bcs->hw.isar.cmd, 1, &p1);
1135 bcs->hw.isar.state = STFAX_LINE;
1136 bcs->hw.isar.try_mod = 3;
1137 }
1138 break;
1139 case PSEV_RSP_SILOFF:
1140 if (cs->debug & L1_DEB_HSCX)
1141 debugl1(cs, "pump stev RSP_SILOFF");
1142 break;
1143 case PSEV_RSP_FCERR:
1144 if (bcs->hw.isar.state == STFAX_LINE) {
1145 if (cs->debug & L1_DEB_HSCX)
1146 debugl1(cs, "pump stev RSP_FCERR try %d",
1147 bcs->hw.isar.try_mod);
1148 if (bcs->hw.isar.try_mod--) {
1149 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
1150 bcs->hw.isar.cmd, 1,
1151 &bcs->hw.isar.mod);
1152 break;
1153 }
1154 }
1155 if (cs->debug & L1_DEB_HSCX)
1156 debugl1(cs, "pump stev RSP_FCERR");
1157 bcs->hw.isar.state = STFAX_ESCAPE;
1158 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC, 0, NULL);
1159 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR);
1160 break;
1161 default:
1162 break;
1163 }
1164 }
1165
1166 static char debbuf[128];
1167
1168 void
1169 isar_int_main(struct IsdnCardState *cs)
1170 {
1171 struct isar_reg *ireg = cs->bcs[0].hw.isar.reg;
1172 struct BCState *bcs;
1173
1174 get_irq_infos(cs, ireg);
1175 switch (ireg->iis & ISAR_IIS_MSCMSD) {
1176 case ISAR_IIS_RDATA:
1177 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1178 isar_rcv_frame(cs, bcs);
1179 } else {
1180 debugl1(cs, "isar spurious IIS_RDATA %x/%x/%x",
1181 ireg->iis, ireg->cmsb, ireg->clsb);
1182 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
1183 }
1184 break;
1185 case ISAR_IIS_GSTEV:
1186 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
1187 ireg->bstat |= ireg->cmsb;
1188 check_send(cs, ireg->cmsb);
1189 break;
1190 case ISAR_IIS_BSTEV:
1191 #ifdef ERROR_STATISTIC
1192 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1193 if (ireg->cmsb == BSTEV_TBO)
1194 bcs->err_tx++;
1195 if (ireg->cmsb == BSTEV_RBO)
1196 bcs->err_rdo++;
1197 }
1198 #endif
1199 if (cs->debug & L1_DEB_WARN)
1200 debugl1(cs, "Buffer STEV dpath%d msb(%x)",
1201 ireg->iis>>6, ireg->cmsb);
1202 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
1203 break;
1204 case ISAR_IIS_PSTEV:
1205 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1206 rcv_mbox(cs, ireg, (u_char *)ireg->par);
1207 if (bcs->mode == L1_MODE_V32) {
1208 isar_pump_statev_modem(bcs, ireg->cmsb);
1209 } else if (bcs->mode == L1_MODE_FAX) {
1210 isar_pump_statev_fax(bcs, ireg->cmsb);
1211 } else if (ireg->cmsb == PSEV_10MS_TIMER) {
1212 if (cs->debug & L1_DEB_HSCX)
1213 debugl1(cs, "pump stev TIMER");
1214 } else {
1215 if (cs->debug & L1_DEB_WARN)
1216 debugl1(cs, "isar IIS_PSTEV pmode %d stat %x",
1217 bcs->mode, ireg->cmsb);
1218 }
1219 } else {
1220 debugl1(cs, "isar spurious IIS_PSTEV %x/%x/%x",
1221 ireg->iis, ireg->cmsb, ireg->clsb);
1222 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
1223 }
1224 break;
1225 case ISAR_IIS_PSTRSP:
1226 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1227 rcv_mbox(cs, ireg, (u_char *)ireg->par);
1228 isar_pump_status_rsp(bcs, ireg);
1229 } else {
1230 debugl1(cs, "isar spurious IIS_PSTRSP %x/%x/%x",
1231 ireg->iis, ireg->cmsb, ireg->clsb);
1232 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
1233 }
1234 break;
1235 case ISAR_IIS_DIAG:
1236 case ISAR_IIS_BSTRSP:
1237 case ISAR_IIS_IOM2RSP:
1238 rcv_mbox(cs, ireg, (u_char *)ireg->par);
1239 if ((cs->debug & (L1_DEB_HSCX | L1_DEB_HSCX_FIFO))
1240 == L1_DEB_HSCX) {
1241 u_char *tp=debbuf;
1242
1243 tp += sprintf(debbuf, "msg iis(%x) msb(%x)",
1244 ireg->iis, ireg->cmsb);
1245 QuickHex(tp, (u_char *)ireg->par, ireg->clsb);
1246 debugl1(cs, debbuf);
1247 }
1248 break;
1249 case ISAR_IIS_INVMSG:
1250 rcv_mbox(cs, ireg, debbuf);
1251 if (cs->debug & L1_DEB_WARN)
1252 debugl1(cs, "invalid msg his:%x",
1253 ireg->cmsb);
1254 break;
1255 default:
1256 rcv_mbox(cs, ireg, debbuf);
1257 if (cs->debug & L1_DEB_WARN)
1258 debugl1(cs, "unhandled msg iis(%x) ctrl(%x/%x)",
1259 ireg->iis, ireg->cmsb, ireg->clsb);
1260 break;
1261 }
1262 }
1263
1264 static void
1265 ftimer_handler(struct BCState *bcs) {
1266 if (bcs->cs->debug)
1267 debugl1(bcs->cs, "ftimer flags %04x",
1268 bcs->Flag);
1269 test_and_clear_bit(BC_FLG_FTI_RUN, &bcs->Flag);
1270 if (test_and_clear_bit(BC_FLG_LL_CONN, &bcs->Flag)) {
1271 schedule_event(bcs, B_LL_CONNECT);
1272 }
1273 if (test_and_clear_bit(BC_FLG_FTI_FTS, &bcs->Flag)) {
1274 schedule_event(bcs, B_LL_OK);
1275 }
1276 }
1277
1278 static void
1279 setup_pump(struct BCState *bcs) {
1280 struct IsdnCardState *cs = bcs->cs;
1281 u_char dps = SET_DPS(bcs->hw.isar.dpath);
1282 u_char ctrl, param[6];
1283
1284 switch (bcs->mode) {
1285 case L1_MODE_NULL:
1286 case L1_MODE_TRANS:
1287 case L1_MODE_HDLC:
1288 sendmsg(cs, dps | ISAR_HIS_PUMPCFG, PMOD_BYPASS, 0, NULL);
1289 break;
1290 case L1_MODE_V32:
1291 ctrl = PMOD_DATAMODEM;
1292 if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
1293 ctrl |= PCTRL_ORIG;
1294 param[5] = PV32P6_CTN;
1295 } else {
1296 param[5] = PV32P6_ATN;
1297 }
1298 param[0] = para_TOA; /* 6 db */
1299 param[1] = PV32P2_V23R | PV32P2_V22A | PV32P2_V22B |
1300 PV32P2_V22C | PV32P2_V21 | PV32P2_BEL;
1301 param[2] = PV32P3_AMOD | PV32P3_V32B | PV32P3_V23B;
1302 param[3] = PV32P4_UT144;
1303 param[4] = PV32P5_UT144;
1304 sendmsg(cs, dps | ISAR_HIS_PUMPCFG, ctrl, 6, param);
1305 break;
1306 case L1_MODE_FAX:
1307 ctrl = PMOD_FAX;
1308 if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
1309 ctrl |= PCTRL_ORIG;
1310 param[1] = PFAXP2_CTN;
1311 } else {
1312 param[1] = PFAXP2_ATN;
1313 }
1314 param[0] = para_TOA; /* 6 db */
1315 sendmsg(cs, dps | ISAR_HIS_PUMPCFG, ctrl, 2, param);
1316 bcs->hw.isar.state = STFAX_NULL;
1317 bcs->hw.isar.newcmd = 0;
1318 bcs->hw.isar.newmod = 0;
1319 test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag);
1320 break;
1321 }
1322 udelay(1000);
1323 sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
1324 udelay(1000);
1325 }
1326
1327 static void
1328 setup_sart(struct BCState *bcs) {
1329 struct IsdnCardState *cs = bcs->cs;
1330 u_char dps = SET_DPS(bcs->hw.isar.dpath);
1331 u_char ctrl, param[2];
1332
1333 switch (bcs->mode) {
1334 case L1_MODE_NULL:
1335 sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_DISABLE, 0,
1336 NULL);
1337 break;
1338 case L1_MODE_TRANS:
1339 sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_BINARY, 2,
1340 "\0\0");
1341 break;
1342 case L1_MODE_HDLC:
1343 param[0] = 0;
1344 sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_HDLC, 1,
1345 param);
1346 break;
1347 case L1_MODE_V32:
1348 ctrl = SMODE_V14 | SCTRL_HDMC_BOTH;
1349 param[0] = S_P1_CHS_8;
1350 param[1] = S_P2_BFT_DEF;
1351 sendmsg(cs, dps | ISAR_HIS_SARTCFG, ctrl, 2,
1352 param);
1353 break;
1354 case L1_MODE_FAX:
1355 /* SART must not configured with FAX */
1356 break;
1357 }
1358 udelay(1000);
1359 sendmsg(cs, dps | ISAR_HIS_BSTREQ, 0, 0, NULL);
1360 udelay(1000);
1361 }
1362
1363 static void
1364 setup_iom2(struct BCState *bcs) {
1365 struct IsdnCardState *cs = bcs->cs;
1366 u_char dps = SET_DPS(bcs->hw.isar.dpath);
1367 u_char cmsb = IOM_CTRL_ENA, msg[5] = {IOM_P1_TXD,0,0,0,0};
1368
1369 if (bcs->channel)
1370 msg[1] = msg[3] = 1;
1371 switch (bcs->mode) {
1372 case L1_MODE_NULL:
1373 cmsb = 0;
1374 /* dummy slot */
1375 msg[1] = msg[3] = bcs->hw.isar.dpath + 2;
1376 break;
1377 case L1_MODE_TRANS:
1378 case L1_MODE_HDLC:
1379 break;
1380 case L1_MODE_V32:
1381 case L1_MODE_FAX:
1382 cmsb |= IOM_CTRL_ALAW | IOM_CTRL_RCV;
1383 break;
1384 }
1385 sendmsg(cs, dps | ISAR_HIS_IOM2CFG, cmsb, 5, msg);
1386 udelay(1000);
1387 sendmsg(cs, dps | ISAR_HIS_IOM2REQ, 0, 0, NULL);
1388 udelay(1000);
1389 }
1390
1391 int
1392 modeisar(struct BCState *bcs, int mode, int bc)
1393 {
1394 struct IsdnCardState *cs = bcs->cs;
1395
1396 /* Here we are selecting the best datapath for requested mode */
1397 if(bcs->mode == L1_MODE_NULL) { /* New Setup */
1398 bcs->channel = bc;
1399 switch (mode) {
1400 case L1_MODE_NULL: /* init */
1401 if (!bcs->hw.isar.dpath)
1402 /* no init for dpath 0 */
1403 return(0);
1404 break;
1405 case L1_MODE_TRANS:
1406 case L1_MODE_HDLC:
1407 /* best is datapath 2 */
1408 if (!test_and_set_bit(ISAR_DP2_USE,
1409 &bcs->hw.isar.reg->Flags))
1410 bcs->hw.isar.dpath = 2;
1411 else if (!test_and_set_bit(ISAR_DP1_USE,
1412 &bcs->hw.isar.reg->Flags))
1413 bcs->hw.isar.dpath = 1;
1414 else {
1415 printk(KERN_WARNING"isar modeisar both pathes in use\n");
1416 return(1);
1417 }
1418 break;
1419 case L1_MODE_V32:
1420 case L1_MODE_FAX:
1421 /* only datapath 1 */
1422 if (!test_and_set_bit(ISAR_DP1_USE,
1423 &bcs->hw.isar.reg->Flags))
1424 bcs->hw.isar.dpath = 1;
1425 else {
1426 printk(KERN_WARNING"isar modeisar analog funktions only with DP1\n");
1427 debugl1(cs, "isar modeisar analog funktions only with DP1");
1428 return(1);
1429 }
1430 break;
1431 }
1432 }
1433 if (cs->debug & L1_DEB_HSCX)
1434 debugl1(cs, "isar dp%d mode %d->%d ichan %d",
1435 bcs->hw.isar.dpath, bcs->mode, mode, bc);
1436 bcs->mode = mode;
1437 setup_pump(bcs);
1438 setup_iom2(bcs);
1439 setup_sart(bcs);
1440 if (bcs->mode == L1_MODE_NULL) {
1441 /* Clear resources */
1442 if (bcs->hw.isar.dpath == 1)
1443 test_and_clear_bit(ISAR_DP1_USE, &bcs->hw.isar.reg->Flags);
1444 else if (bcs->hw.isar.dpath == 2)
1445 test_and_clear_bit(ISAR_DP2_USE, &bcs->hw.isar.reg->Flags);
1446 bcs->hw.isar.dpath = 0;
1447 }
1448 return(0);
1449 }
1450
1451 static void
1452 isar_pump_cmd(struct BCState *bcs, u_char cmd, u_char para)
1453 {
1454 struct IsdnCardState *cs = bcs->cs;
1455 u_char dps = SET_DPS(bcs->hw.isar.dpath);
1456 u_char ctrl = 0, nom = 0, p1 = 0;
1457
1458 switch(cmd) {
1459 case ISDN_FAX_CLASS1_FTM:
1460 test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
1461 if (bcs->hw.isar.state == STFAX_READY) {
1462 p1 = para;
1463 ctrl = PCTRL_CMD_FTM;
1464 nom = 1;
1465 bcs->hw.isar.state = STFAX_LINE;
1466 bcs->hw.isar.cmd = ctrl;
1467 bcs->hw.isar.mod = para;
1468 bcs->hw.isar.newmod = 0;
1469 bcs->hw.isar.newcmd = 0;
1470 bcs->hw.isar.try_mod = 3;
1471 } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
1472 (bcs->hw.isar.cmd == PCTRL_CMD_FTM) &&
1473 (bcs->hw.isar.mod == para)) {
1474 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
1475 } else {
1476 bcs->hw.isar.newmod = para;
1477 bcs->hw.isar.newcmd = PCTRL_CMD_FTM;
1478 nom = 0;
1479 ctrl = PCTRL_CMD_ESC;
1480 bcs->hw.isar.state = STFAX_ESCAPE;
1481 }
1482 break;
1483 case ISDN_FAX_CLASS1_FTH:
1484 test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
1485 if (bcs->hw.isar.state == STFAX_READY) {
1486 p1 = para;
1487 ctrl = PCTRL_CMD_FTH;
1488 nom = 1;
1489 bcs->hw.isar.state = STFAX_LINE;
1490 bcs->hw.isar.cmd = ctrl;
1491 bcs->hw.isar.mod = para;
1492 bcs->hw.isar.newmod = 0;
1493 bcs->hw.isar.newcmd = 0;
1494 bcs->hw.isar.try_mod = 3;
1495 } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
1496 (bcs->hw.isar.cmd == PCTRL_CMD_FTH) &&
1497 (bcs->hw.isar.mod == para)) {
1498 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
1499 } else {
1500 bcs->hw.isar.newmod = para;
1501 bcs->hw.isar.newcmd = PCTRL_CMD_FTH;
1502 nom = 0;
1503 ctrl = PCTRL_CMD_ESC;
1504 bcs->hw.isar.state = STFAX_ESCAPE;
1505 }
1506 break;
1507 case ISDN_FAX_CLASS1_FRM:
1508 test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
1509 if (bcs->hw.isar.state == STFAX_READY) {
1510 p1 = para;
1511 ctrl = PCTRL_CMD_FRM;
1512 nom = 1;
1513 bcs->hw.isar.state = STFAX_LINE;
1514 bcs->hw.isar.cmd = ctrl;
1515 bcs->hw.isar.mod = para;
1516 bcs->hw.isar.newmod = 0;
1517 bcs->hw.isar.newcmd = 0;
1518 bcs->hw.isar.try_mod = 3;
1519 } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
1520 (bcs->hw.isar.cmd == PCTRL_CMD_FRM) &&
1521 (bcs->hw.isar.mod == para)) {
1522 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
1523 } else {
1524 bcs->hw.isar.newmod = para;
1525 bcs->hw.isar.newcmd = PCTRL_CMD_FRM;
1526 nom = 0;
1527 ctrl = PCTRL_CMD_ESC;
1528 bcs->hw.isar.state = STFAX_ESCAPE;
1529 }
1530 break;
1531 case ISDN_FAX_CLASS1_FRH:
1532 test_and_set_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
1533 if (bcs->hw.isar.state == STFAX_READY) {
1534 p1 = para;
1535 ctrl = PCTRL_CMD_FRH;
1536 nom = 1;
1537 bcs->hw.isar.state = STFAX_LINE;
1538 bcs->hw.isar.cmd = ctrl;
1539 bcs->hw.isar.mod = para;
1540 bcs->hw.isar.newmod = 0;
1541 bcs->hw.isar.newcmd = 0;
1542 bcs->hw.isar.try_mod = 3;
1543 } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
1544 (bcs->hw.isar.cmd == PCTRL_CMD_FRH) &&
1545 (bcs->hw.isar.mod == para)) {
1546 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
1547 } else {
1548 bcs->hw.isar.newmod = para;
1549 bcs->hw.isar.newcmd = PCTRL_CMD_FRH;
1550 nom = 0;
1551 ctrl = PCTRL_CMD_ESC;
1552 bcs->hw.isar.state = STFAX_ESCAPE;
1553 }
1554 break;
1555 case ISDN_FAXPUMP_HALT:
1556 bcs->hw.isar.state = STFAX_NULL;
1557 nom = 0;
1558 ctrl = PCTRL_CMD_HALT;
1559 break;
1560 }
1561 if (ctrl)
1562 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, ctrl, nom, &p1);
1563 }
1564
1565 void
1566 isar_setup(struct IsdnCardState *cs)
1567 {
1568 u_char msg;
1569 int i;
1570
1571 /* Dpath 1, 2 */
1572 msg = 61;
1573 for (i=0; i<2; i++) {
1574 /* Buffer Config */
1575 sendmsg(cs, (i ? ISAR_HIS_DPS2 : ISAR_HIS_DPS1) |
1576 ISAR_HIS_P12CFG, 4, 1, &msg);
1577 cs->bcs[i].hw.isar.mml = msg;
1578 cs->bcs[i].mode = 0;
1579 cs->bcs[i].hw.isar.dpath = i + 1;
1580 modeisar(&cs->bcs[i], 0, 0);
1581 INIT_WORK(&cs->bcs[i].tqueue, (void *)(void *) isar_bh, &cs->bcs[i]);
1582 }
1583 }
1584
1585 void
1586 isar_l2l1(struct PStack *st, int pr, void *arg)
1587 {
1588 struct BCState *bcs = st->l1.bcs;
1589 struct sk_buff *skb = arg;
1590 int ret;
1591 u_long flags;
1592
1593 switch (pr) {
1594 case (PH_DATA | REQUEST):
1595 spin_lock_irqsave(&bcs->cs->lock, flags);
1596 if (bcs->tx_skb) {
1597 skb_queue_tail(&bcs->squeue, skb);
1598 } else {
1599 bcs->tx_skb = skb;
1600 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1601 if (bcs->cs->debug & L1_DEB_HSCX)
1602 debugl1(bcs->cs, "DRQ set BC_FLG_BUSY");
1603 bcs->hw.isar.txcnt = 0;
1604 bcs->cs->BC_Send_Data(bcs);
1605 }
1606 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1607 break;
1608 case (PH_PULL | INDICATION):
1609 spin_lock_irqsave(&bcs->cs->lock, flags);
1610 if (bcs->tx_skb) {
1611 printk(KERN_WARNING "isar_l2l1: this shouldn't happen\n");
1612 } else {
1613 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1614 if (bcs->cs->debug & L1_DEB_HSCX)
1615 debugl1(bcs->cs, "PUI set BC_FLG_BUSY");
1616 bcs->tx_skb = skb;
1617 bcs->hw.isar.txcnt = 0;
1618 bcs->cs->BC_Send_Data(bcs);
1619 }
1620 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1621 break;
1622 case (PH_PULL | REQUEST):
1623 if (!bcs->tx_skb) {
1624 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1625 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1626 } else
1627 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1628 break;
1629 case (PH_ACTIVATE | REQUEST):
1630 spin_lock_irqsave(&bcs->cs->lock, flags);
1631 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
1632 bcs->hw.isar.conmsg[0] = 0;
1633 if (test_bit(FLG_ORIG, &st->l2.flag))
1634 test_and_set_bit(BC_FLG_ORIG, &bcs->Flag);
1635 else
1636 test_and_clear_bit(BC_FLG_ORIG, &bcs->Flag);
1637 switch(st->l1.mode) {
1638 case L1_MODE_TRANS:
1639 case L1_MODE_HDLC:
1640 ret = modeisar(bcs, st->l1.mode, st->l1.bc);
1641 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1642 if (ret)
1643 l1_msg_b(st, PH_DEACTIVATE | REQUEST, arg);
1644 else
1645 l1_msg_b(st, PH_ACTIVATE | REQUEST, arg);
1646 break;
1647 case L1_MODE_V32:
1648 case L1_MODE_FAX:
1649 ret = modeisar(bcs, st->l1.mode, st->l1.bc);
1650 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1651 if (ret)
1652 l1_msg_b(st, PH_DEACTIVATE | REQUEST, arg);
1653 break;
1654 default:
1655 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1656 break;
1657 }
1658 break;
1659 case (PH_DEACTIVATE | REQUEST):
1660 l1_msg_b(st, pr, arg);
1661 break;
1662 case (PH_DEACTIVATE | CONFIRM):
1663 spin_lock_irqsave(&bcs->cs->lock, flags);
1664 switch(st->l1.mode) {
1665 case L1_MODE_TRANS:
1666 case L1_MODE_HDLC:
1667 case L1_MODE_V32:
1668 break;
1669 case L1_MODE_FAX:
1670 isar_pump_cmd(bcs, ISDN_FAXPUMP_HALT, 0);
1671 break;
1672 }
1673 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
1674 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1675 if (bcs->cs->debug & L1_DEB_HSCX)
1676 debugl1(bcs->cs, "PDAC clear BC_FLG_BUSY");
1677 modeisar(bcs, 0, st->l1.bc);
1678 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1679 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
1680 break;
1681 }
1682 }
1683
1684 void
1685 close_isarstate(struct BCState *bcs)
1686 {
1687 modeisar(bcs, 0, bcs->channel);
1688 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
1689 if (bcs->hw.isar.rcvbuf) {
1690 kfree(bcs->hw.isar.rcvbuf);
1691 bcs->hw.isar.rcvbuf = NULL;
1692 }
1693 skb_queue_purge(&bcs->rqueue);
1694 skb_queue_purge(&bcs->squeue);
1695 if (bcs->tx_skb) {
1696 dev_kfree_skb_any(bcs->tx_skb);
1697 bcs->tx_skb = NULL;
1698 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1699 if (bcs->cs->debug & L1_DEB_HSCX)
1700 debugl1(bcs->cs, "closeisar clear BC_FLG_BUSY");
1701 }
1702 }
1703 del_timer(&bcs->hw.isar.ftimer);
1704 }
1705
1706 int
1707 open_isarstate(struct IsdnCardState *cs, struct BCState *bcs)
1708 {
1709 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
1710 if (!(bcs->hw.isar.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
1711 printk(KERN_WARNING
1712 "HiSax: No memory for isar.rcvbuf\n");
1713 return (1);
1714 }
1715 skb_queue_head_init(&bcs->rqueue);
1716 skb_queue_head_init(&bcs->squeue);
1717 }
1718 bcs->tx_skb = NULL;
1719 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1720 if (cs->debug & L1_DEB_HSCX)
1721 debugl1(cs, "openisar clear BC_FLG_BUSY");
1722 bcs->event = 0;
1723 bcs->hw.isar.rcvidx = 0;
1724 bcs->tx_cnt = 0;
1725 return (0);
1726 }
1727
1728 int
1729 setstack_isar(struct PStack *st, struct BCState *bcs)
1730 {
1731 bcs->channel = st->l1.bc;
1732 if (open_isarstate(st->l1.hardware, bcs))
1733 return (-1);
1734 st->l1.bcs = bcs;
1735 st->l2.l2l1 = isar_l2l1;
1736 setstack_manager(st);
1737 bcs->st = st;
1738 setstack_l1_B(st);
1739 return (0);
1740 }
1741
1742 int
1743 isar_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic) {
1744 u_long adr;
1745 int features, i;
1746 struct BCState *bcs;
1747
1748 if (cs->debug & L1_DEB_HSCX)
1749 debugl1(cs, "isar_auxcmd cmd/ch %x/%d", ic->command, ic->arg);
1750 switch (ic->command) {
1751 case (ISDN_CMD_FAXCMD):
1752 bcs = cs->channel[ic->arg].bcs;
1753 if (cs->debug & L1_DEB_HSCX)
1754 debugl1(cs, "isar_auxcmd cmd/subcmd %d/%d",
1755 ic->parm.aux.cmd, ic->parm.aux.subcmd);
1756 switch(ic->parm.aux.cmd) {
1757 case ISDN_FAX_CLASS1_CTRL:
1758 if (ic->parm.aux.subcmd == ETX)
1759 test_and_set_bit(BC_FLG_DLEETX,
1760 &bcs->Flag);
1761 break;
1762 case ISDN_FAX_CLASS1_FTS:
1763 if (ic->parm.aux.subcmd == AT_QUERY) {
1764 ic->command = ISDN_STAT_FAXIND;
1765 ic->parm.aux.cmd = ISDN_FAX_CLASS1_OK;
1766 cs->iif.statcallb(ic);
1767 return(0);
1768 } else if (ic->parm.aux.subcmd == AT_EQ_QUERY) {
1769 strcpy(ic->parm.aux.para, "0-255");
1770 ic->command = ISDN_STAT_FAXIND;
1771 ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY;
1772 cs->iif.statcallb(ic);
1773 return(0);
1774 } else if (ic->parm.aux.subcmd == AT_EQ_VALUE) {
1775 if (cs->debug & L1_DEB_HSCX)
1776 debugl1(cs, "isar_auxcmd %s=%d",
1777 FC1_CMD[ic->parm.aux.cmd], ic->parm.aux.para[0]);
1778 if (bcs->hw.isar.state == STFAX_READY) {
1779 if (! ic->parm.aux.para[0]) {
1780 ic->command = ISDN_STAT_FAXIND;
1781 ic->parm.aux.cmd = ISDN_FAX_CLASS1_OK;
1782 cs->iif.statcallb(ic);
1783 return(0);
1784 }
1785 if (! test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag)) {
1786 /* n*10 ms */
1787 bcs->hw.isar.ftimer.expires =
1788 jiffies + ((ic->parm.aux.para[0] * 10 * HZ)/1000);
1789 test_and_set_bit(BC_FLG_FTI_FTS, &bcs->Flag);
1790 add_timer(&bcs->hw.isar.ftimer);
1791 return(0);
1792 } else {
1793 if (cs->debug)
1794 debugl1(cs, "isar FTS=%d and FTI busy",
1795 ic->parm.aux.para[0]);
1796 }
1797 } else {
1798 if (cs->debug)
1799 debugl1(cs, "isar FTS=%d and isar.state not ready(%x)",
1800 ic->parm.aux.para[0],bcs->hw.isar.state);
1801 }
1802 ic->command = ISDN_STAT_FAXIND;
1803 ic->parm.aux.cmd = ISDN_FAX_CLASS1_ERROR;
1804 cs->iif.statcallb(ic);
1805 }
1806 break;
1807 case ISDN_FAX_CLASS1_FRM:
1808 case ISDN_FAX_CLASS1_FRH:
1809 case ISDN_FAX_CLASS1_FTM:
1810 case ISDN_FAX_CLASS1_FTH:
1811 if (ic->parm.aux.subcmd == AT_QUERY) {
1812 sprintf(ic->parm.aux.para,
1813 "%d", bcs->hw.isar.mod);
1814 ic->command = ISDN_STAT_FAXIND;
1815 ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY;
1816 cs->iif.statcallb(ic);
1817 return(0);
1818 } else if (ic->parm.aux.subcmd == AT_EQ_QUERY) {
1819 char *p = ic->parm.aux.para;
1820 for(i=0;i<FAXMODCNT;i++)
1821 if ((1<<i) & modmask)
1822 p += sprintf(p, "%d,", faxmodulation[i]);
1823 p--;
1824 *p=0;
1825 ic->command = ISDN_STAT_FAXIND;
1826 ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY;
1827 cs->iif.statcallb(ic);
1828 return(0);
1829 } else if (ic->parm.aux.subcmd == AT_EQ_VALUE) {
1830 if (cs->debug & L1_DEB_HSCX)
1831 debugl1(cs, "isar_auxcmd %s=%d",
1832 FC1_CMD[ic->parm.aux.cmd], ic->parm.aux.para[0]);
1833 for(i=0;i<FAXMODCNT;i++)
1834 if (faxmodulation[i]==ic->parm.aux.para[0])
1835 break;
1836 if ((i < FAXMODCNT) && ((1<<i) & modmask) &&
1837 test_bit(BC_FLG_INIT, &bcs->Flag)) {
1838 isar_pump_cmd(bcs,
1839 ic->parm.aux.cmd,
1840 ic->parm.aux.para[0]);
1841 return(0);
1842 }
1843 }
1844 /* wrong modulation or not activ */
1845 /* fall through */
1846 default:
1847 ic->command = ISDN_STAT_FAXIND;
1848 ic->parm.aux.cmd = ISDN_FAX_CLASS1_ERROR;
1849 cs->iif.statcallb(ic);
1850 }
1851 break;
1852 case (ISDN_CMD_IOCTL):
1853 switch (ic->arg) {
1854 case 9: /* load firmware */
1855 features = ISDN_FEATURE_L2_MODEM |
1856 ISDN_FEATURE_L2_FAX |
1857 ISDN_FEATURE_L3_FCLASS1;
1858 memcpy(&adr, ic->parm.num, sizeof(ulong));
1859 if (isar_load_firmware(cs, (u_char __user *)adr))
1860 return(1);
1861 else
1862 ll_run(cs, features);
1863 break;
1864 case 20:
1865 features = *(unsigned int *) ic->parm.num;
1866 printk(KERN_DEBUG "HiSax: max modulation old(%04x) new(%04x)\n",
1867 modmask, features);
1868 modmask = features;
1869 break;
1870 case 21:
1871 features = *(unsigned int *) ic->parm.num;
1872 printk(KERN_DEBUG "HiSax: FRM extra delay old(%d) new(%d) ms\n",
1873 frm_extra_delay, features);
1874 if (features >= 0)
1875 frm_extra_delay = features;
1876 break;
1877 case 22:
1878 features = *(unsigned int *) ic->parm.num;
1879 printk(KERN_DEBUG "HiSax: TOA old(%d) new(%d) db\n",
1880 para_TOA, features);
1881 if (features >= 0 && features < 32)
1882 para_TOA = features;
1883 break;
1884 default:
1885 printk(KERN_DEBUG "HiSax: invalid ioctl %d\n",
1886 (int) ic->arg);
1887 return(-EINVAL);
1888 }
1889 break;
1890 default:
1891 return(-EINVAL);
1892 }
1893 return(0);
1894 }
1895
1896 void __devinit
1897 initisar(struct IsdnCardState *cs)
1898 {
1899 cs->bcs[0].BC_SetStack = setstack_isar;
1900 cs->bcs[1].BC_SetStack = setstack_isar;
1901 cs->bcs[0].BC_Close = close_isarstate;
1902 cs->bcs[1].BC_Close = close_isarstate;
1903 cs->bcs[0].hw.isar.ftimer.function = (void *) ftimer_handler;
1904 cs->bcs[0].hw.isar.ftimer.data = (long) &cs->bcs[0];
1905 init_timer(&cs->bcs[0].hw.isar.ftimer);
1906 cs->bcs[1].hw.isar.ftimer.function = (void *) ftimer_handler;
1907 cs->bcs[1].hw.isar.ftimer.data = (long) &cs->bcs[1];
1908 init_timer(&cs->bcs[1].hw.isar.ftimer);
1909 }
CRIS linux kernel tree