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[PATCH] aic7xxx_osm build fix
[cris-mirror.git] / drivers / mtd / nand / s3c2410.c
blobd05e9b97947d575a79300ea1526f9b95541813d3
1 /* linux/drivers/mtd/nand/s3c2410.c
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C2410 NAND driver
7 *
8 * Changelog:
9 * 21-Sep-2004 BJD Initial version
10 * 23-Sep-2004 BJD Mulitple device support
11 * 28-Sep-2004 BJD Fixed ECC placement for Hardware mode
12 * 12-Oct-2004 BJD Fixed errors in use of platform data
13 *
14 * $Id: s3c2410.c,v 1.7 2005/01/05 18:05:14 dwmw2 Exp $
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 */
30
31 #include <config/mtd/nand/s3c2410/hwecc.h>
32 #include <config/mtd/nand/s3c2410/debug.h>
33
34 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
35 #define DEBUG
36 #endif
37
38 #include <linux/module.h>
39 #include <linux/types.h>
40 #include <linux/init.h>
41 #include <linux/kernel.h>
42 #include <linux/string.h>
43 #include <linux/ioport.h>
44 #include <linux/device.h>
45 #include <linux/delay.h>
46 #include <linux/err.h>
47
48 #include <linux/mtd/mtd.h>
49 #include <linux/mtd/nand.h>
50 #include <linux/mtd/nand_ecc.h>
51 #include <linux/mtd/partitions.h>
52
53 #include <asm/io.h>
54 #include <asm/mach-types.h>
55 #include <asm/hardware/clock.h>
56
57 #include <asm/arch/regs-nand.h>
58 #include <asm/arch/nand.h>
59
60 #define PFX "s3c2410-nand: "
61
62 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
63 static int hardware_ecc = 1;
64 #else
65 static int hardware_ecc = 0;
66 #endif
67
68 /* new oob placement block for use with hardware ecc generation
69 */
70
71 static struct nand_oobinfo nand_hw_eccoob = {
72 .useecc = MTD_NANDECC_AUTOPLACE,
73 .eccbytes = 3,
74 .eccpos = {0, 1, 2 },
75 .oobfree = { {8, 8} }
76 };
77
78 /* controller and mtd information */
79
80 struct s3c2410_nand_info;
81
82 struct s3c2410_nand_mtd {
83 struct mtd_info mtd;
84 struct nand_chip chip;
85 struct s3c2410_nand_set *set;
86 struct s3c2410_nand_info *info;
87 int scan_res;
88 };
89
90 /* overview of the s3c2410 nand state */
91
92 struct s3c2410_nand_info {
93 /* mtd info */
94 struct nand_hw_control controller;
95 struct s3c2410_nand_mtd *mtds;
96 struct s3c2410_platform_nand *platform;
97
98 /* device info */
99 struct device *device;
100 struct resource *area;
101 struct clk *clk;
102 void *regs;
103 int mtd_count;
104 };
105
106 /* conversion functions */
107
108 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
109 {
110 return container_of(mtd, struct s3c2410_nand_mtd, mtd);
111 }
112
113 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
114 {
115 return s3c2410_nand_mtd_toours(mtd)->info;
116 }
117
118 static struct s3c2410_nand_info *to_nand_info(struct device *dev)
119 {
120 return dev_get_drvdata(dev);
121 }
122
123 static struct s3c2410_platform_nand *to_nand_plat(struct device *dev)
124 {
125 return dev->platform_data;
126 }
127
128 /* timing calculations */
129
130 #define NS_IN_KHZ 10000000
131
132 static int s3c2410_nand_calc_rate(int wanted, unsigned long clk, int max)
133 {
134 int result;
135
136 result = (wanted * NS_IN_KHZ) / clk;
137 result++;
138
139 pr_debug("result %d from %ld, %d\n", result, clk, wanted);
140
141 if (result > max) {
142 printk("%d ns is too big for current clock rate %ld\n",
143 wanted, clk);
144 return -1;
145 }
146
147 if (result < 1)
148 result = 1;
149
150 return result;
151 }
152
153 #define to_ns(ticks,clk) (((clk) * (ticks)) / NS_IN_KHZ)
154
155 /* controller setup */
156
157 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info,
158 struct device *dev)
159 {
160 struct s3c2410_platform_nand *plat = to_nand_plat(dev);
161 unsigned int tacls, twrph0, twrph1;
162 unsigned long clkrate = clk_get_rate(info->clk);
163 unsigned long cfg;
164
165 /* calculate the timing information for the controller */
166
167 if (plat != NULL) {
168 tacls = s3c2410_nand_calc_rate(plat->tacls, clkrate, 8);
169 twrph0 = s3c2410_nand_calc_rate(plat->twrph0, clkrate, 8);
170 twrph1 = s3c2410_nand_calc_rate(plat->twrph1, clkrate, 8);
171 } else {
172 /* default timings */
173 tacls = 8;
174 twrph0 = 8;
175 twrph1 = 8;
176 }
177
178 if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
179 printk(KERN_ERR PFX "cannot get timings suitable for board\n");
180 return -EINVAL;
181 }
182
183 printk(KERN_INFO PFX "timing: Tacls %ldns, Twrph0 %ldns, Twrph1 %ldns\n",
184 to_ns(tacls, clkrate),
185 to_ns(twrph0, clkrate),
186 to_ns(twrph1, clkrate));
187
188 cfg = S3C2410_NFCONF_EN;
189 cfg |= S3C2410_NFCONF_TACLS(tacls-1);
190 cfg |= S3C2410_NFCONF_TWRPH0(twrph0-1);
191 cfg |= S3C2410_NFCONF_TWRPH1(twrph1-1);
192
193 pr_debug(PFX "NF_CONF is 0x%lx\n", cfg);
194
195 writel(cfg, info->regs + S3C2410_NFCONF);
196 return 0;
197 }
198
199 /* select chip */
200
201 static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
202 {
203 struct s3c2410_nand_info *info;
204 struct s3c2410_nand_mtd *nmtd;
205 struct nand_chip *this = mtd->priv;
206 unsigned long cur;
207
208 nmtd = this->priv;
209 info = nmtd->info;
210
211 cur = readl(info->regs + S3C2410_NFCONF);
212
213 if (chip == -1) {
214 cur |= S3C2410_NFCONF_nFCE;
215 } else {
216 if (chip > nmtd->set->nr_chips) {
217 printk(KERN_ERR PFX "chip %d out of range\n", chip);
218 return;
219 }
220
221 if (info->platform != NULL) {
222 if (info->platform->select_chip != NULL)
223 (info->platform->select_chip)(nmtd->set, chip);
224 }
225
226 cur &= ~S3C2410_NFCONF_nFCE;
227 }
228
229 writel(cur, info->regs + S3C2410_NFCONF);
230 }
231
232 /* command and control functions */
233
234 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd)
235 {
236 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
237 unsigned long cur;
238
239 switch (cmd) {
240 case NAND_CTL_SETNCE:
241 cur = readl(info->regs + S3C2410_NFCONF);
242 cur &= ~S3C2410_NFCONF_nFCE;
243 writel(cur, info->regs + S3C2410_NFCONF);
244 break;
245
246 case NAND_CTL_CLRNCE:
247 cur = readl(info->regs + S3C2410_NFCONF);
248 cur |= S3C2410_NFCONF_nFCE;
249 writel(cur, info->regs + S3C2410_NFCONF);
250 break;
251
252 /* we don't need to implement these */
253 case NAND_CTL_SETCLE:
254 case NAND_CTL_CLRCLE:
255 case NAND_CTL_SETALE:
256 case NAND_CTL_CLRALE:
257 pr_debug(PFX "s3c2410_nand_hwcontrol(%d) unusedn", cmd);
258 break;
259 }
260 }
261
262 /* s3c2410_nand_command
263 *
264 * This function implements sending commands and the relevant address
265 * information to the chip, via the hardware controller. Since the
266 * S3C2410 generates the correct ALE/CLE signaling automatically, we
267 * do not need to use hwcontrol.
268 */
269
270 static void s3c2410_nand_command (struct mtd_info *mtd, unsigned command,
271 int column, int page_addr)
272 {
273 register struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
274 register struct nand_chip *this = mtd->priv;
275
276 /*
277 * Write out the command to the device.
278 */
279 if (command == NAND_CMD_SEQIN) {
280 int readcmd;
281
282 if (column >= mtd->oobblock) {
283 /* OOB area */
284 column -= mtd->oobblock;
285 readcmd = NAND_CMD_READOOB;
286 } else if (column < 256) {
287 /* First 256 bytes --> READ0 */
288 readcmd = NAND_CMD_READ0;
289 } else {
290 column -= 256;
291 readcmd = NAND_CMD_READ1;
292 }
293
294 writeb(readcmd, info->regs + S3C2410_NFCMD);
295 }
296 writeb(command, info->regs + S3C2410_NFCMD);
297
298 /* Set ALE and clear CLE to start address cycle */
299
300 if (column != -1 || page_addr != -1) {
301
302 /* Serially input address */
303 if (column != -1) {
304 /* Adjust columns for 16 bit buswidth */
305 if (this->options & NAND_BUSWIDTH_16)
306 column >>= 1;
307 writeb(column, info->regs + S3C2410_NFADDR);
308 }
309 if (page_addr != -1) {
310 writeb((unsigned char) (page_addr), info->regs + S3C2410_NFADDR);
311 writeb((unsigned char) (page_addr >> 8), info->regs + S3C2410_NFADDR);
312 /* One more address cycle for higher density devices */
313 if (this->chipsize & 0x0c000000)
314 writeb((unsigned char) ((page_addr >> 16) & 0x0f),
315 info->regs + S3C2410_NFADDR);
316 }
317 /* Latch in address */
318 }
319
320 /*
321 * program and erase have their own busy handlers
322 * status and sequential in needs no delay
323 */
324 switch (command) {
325
326 case NAND_CMD_PAGEPROG:
327 case NAND_CMD_ERASE1:
328 case NAND_CMD_ERASE2:
329 case NAND_CMD_SEQIN:
330 case NAND_CMD_STATUS:
331 return;
332
333 case NAND_CMD_RESET:
334 if (this->dev_ready)
335 break;
336
337 udelay(this->chip_delay);
338 writeb(NAND_CMD_STATUS, info->regs + S3C2410_NFCMD);
339
340 while ( !(this->read_byte(mtd) & 0x40));
341 return;
342
343 /* This applies to read commands */
344 default:
345 /*
346 * If we don't have access to the busy pin, we apply the given
347 * command delay
348 */
349 if (!this->dev_ready) {
350 udelay (this->chip_delay);
351 return;
352 }
353 }
354
355 /* Apply this short delay always to ensure that we do wait tWB in
356 * any case on any machine. */
357 ndelay (100);
358 /* wait until command is processed */
359 while (!this->dev_ready(mtd));
360 }
361
362
363 /* s3c2410_nand_devready()
364 *
365 * returns 0 if the nand is busy, 1 if it is ready
366 */
367
368 static int s3c2410_nand_devready(struct mtd_info *mtd)
369 {
370 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
371
372 return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
373 }
374
375 /* ECC handling functions */
376
377 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
378 u_char *read_ecc, u_char *calc_ecc)
379 {
380 pr_debug("s3c2410_nand_correct_data(%p,%p,%p,%p)\n",
381 mtd, dat, read_ecc, calc_ecc);
382
383 pr_debug("eccs: read %02x,%02x,%02x vs calc %02x,%02x,%02x\n",
384 read_ecc[0], read_ecc[1], read_ecc[2],
385 calc_ecc[0], calc_ecc[1], calc_ecc[2]);
386
387 if (read_ecc[0] == calc_ecc[0] &&
388 read_ecc[1] == calc_ecc[1] &&
389 read_ecc[2] == calc_ecc[2])
390 return 0;
391
392 /* we curently have no method for correcting the error */
393
394 return -1;
395 }
396
397 static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
398 {
399 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
400 unsigned long ctrl;
401
402 ctrl = readl(info->regs + S3C2410_NFCONF);
403 ctrl |= S3C2410_NFCONF_INITECC;
404 writel(ctrl, info->regs + S3C2410_NFCONF);
405 }
406
407 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd,
408 const u_char *dat, u_char *ecc_code)
409 {
410 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
411
412 ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
413 ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
414 ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
415
416 pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n",
417 ecc_code[0], ecc_code[1], ecc_code[2]);
418
419 return 0;
420 }
421
422
423 /* over-ride the standard functions for a little more speed? */
424
425 static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
426 {
427 struct nand_chip *this = mtd->priv;
428 readsb(this->IO_ADDR_R, buf, len);
429 }
430
431 static void s3c2410_nand_write_buf(struct mtd_info *mtd,
432 const u_char *buf, int len)
433 {
434 struct nand_chip *this = mtd->priv;
435 writesb(this->IO_ADDR_W, buf, len);
436 }
437
438 /* device management functions */
439
440 static int s3c2410_nand_remove(struct device *dev)
441 {
442 struct s3c2410_nand_info *info = to_nand_info(dev);
443
444 dev_set_drvdata(dev, NULL);
445
446 if (info == NULL)
447 return 0;
448
449 /* first thing we need to do is release all our mtds
450 * and their partitions, then go through freeing the
451 * resources used
452 */
453
454 if (info->mtds != NULL) {
455 struct s3c2410_nand_mtd *ptr = info->mtds;
456 int mtdno;
457
458 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
459 pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
460 nand_release(&ptr->mtd);
461 }
462
463 kfree(info->mtds);
464 }
465
466 /* free the common resources */
467
468 if (info->clk != NULL && !IS_ERR(info->clk)) {
469 clk_disable(info->clk);
470 clk_unuse(info->clk);
471 clk_put(info->clk);
472 }
473
474 if (info->regs != NULL) {
475 iounmap(info->regs);
476 info->regs = NULL;
477 }
478
479 if (info->area != NULL) {
480 release_resource(info->area);
481 kfree(info->area);
482 info->area = NULL;
483 }
484
485 kfree(info);
486
487 return 0;
488 }
489
490 #ifdef CONFIG_MTD_PARTITIONS
491 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
492 struct s3c2410_nand_mtd *mtd,
493 struct s3c2410_nand_set *set)
494 {
495 if (set == NULL)
496 return add_mtd_device(&mtd->mtd);
497
498 if (set->nr_partitions > 0 && set->partitions != NULL) {
499 return add_mtd_partitions(&mtd->mtd,
500 set->partitions,
501 set->nr_partitions);
502 }
503
504 return add_mtd_device(&mtd->mtd);
505 }
506 #else
507 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
508 struct s3c2410_nand_mtd *mtd,
509 struct s3c2410_nand_set *set)
510 {
511 return add_mtd_device(&mtd->mtd);
512 }
513 #endif
514
515 /* s3c2410_nand_init_chip
516 *
517 * init a single instance of an chip
518 */
519
520 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
521 struct s3c2410_nand_mtd *nmtd,
522 struct s3c2410_nand_set *set)
523 {
524 struct nand_chip *chip = &nmtd->chip;
525
526 chip->IO_ADDR_R = (char *)info->regs + S3C2410_NFDATA;
527 chip->IO_ADDR_W = (char *)info->regs + S3C2410_NFDATA;
528 chip->hwcontrol = s3c2410_nand_hwcontrol;
529 chip->dev_ready = s3c2410_nand_devready;
530 chip->cmdfunc = s3c2410_nand_command;
531 chip->write_buf = s3c2410_nand_write_buf;
532 chip->read_buf = s3c2410_nand_read_buf;
533 chip->select_chip = s3c2410_nand_select_chip;
534 chip->chip_delay = 50;
535 chip->priv = nmtd;
536 chip->options = 0;
537 chip->controller = &info->controller;
538
539 nmtd->info = info;
540 nmtd->mtd.priv = chip;
541 nmtd->set = set;
542
543 if (hardware_ecc) {
544 chip->correct_data = s3c2410_nand_correct_data;
545 chip->enable_hwecc = s3c2410_nand_enable_hwecc;
546 chip->calculate_ecc = s3c2410_nand_calculate_ecc;
547 chip->eccmode = NAND_ECC_HW3_512;
548 chip->autooob = &nand_hw_eccoob;
549 } else {
550 chip->eccmode = NAND_ECC_SOFT;
551 }
552 }
553
554 /* s3c2410_nand_probe
555 *
556 * called by device layer when it finds a device matching
557 * one our driver can handled. This code checks to see if
558 * it can allocate all necessary resources then calls the
559 * nand layer to look for devices
560 */
561
562 static int s3c2410_nand_probe(struct device *dev)
563 {
564 struct platform_device *pdev = to_platform_device(dev);
565 struct s3c2410_platform_nand *plat = to_nand_plat(dev);
566 struct s3c2410_nand_info *info;
567 struct s3c2410_nand_mtd *nmtd;
568 struct s3c2410_nand_set *sets;
569 struct resource *res;
570 int err = 0;
571 int size;
572 int nr_sets;
573 int setno;
574
575 pr_debug("s3c2410_nand_probe(%p)\n", dev);
576
577 info = kmalloc(sizeof(*info), GFP_KERNEL);
578 if (info == NULL) {
579 printk(KERN_ERR PFX "no memory for flash info\n");
580 err = -ENOMEM;
581 goto exit_error;
582 }
583
584 memzero(info, sizeof(*info));
585 dev_set_drvdata(dev, info);
586
587 spin_lock_init(&info->controller.lock);
588
589 /* get the clock source and enable it */
590
591 info->clk = clk_get(dev, "nand");
592 if (IS_ERR(info->clk)) {
593 printk(KERN_ERR PFX "failed to get clock");
594 err = -ENOENT;
595 goto exit_error;
596 }
597
598 clk_use(info->clk);
599 clk_enable(info->clk);
600
601 /* allocate and map the resource */
602
603 res = pdev->resource; /* assume that the flash has one resource */
604 size = res->end - res->start + 1;
605
606 info->area = request_mem_region(res->start, size, pdev->name);
607
608 if (info->area == NULL) {
609 printk(KERN_ERR PFX "cannot reserve register region\n");
610 err = -ENOENT;
611 goto exit_error;
612 }
613
614 info->device = dev;
615 info->platform = plat;
616 info->regs = ioremap(res->start, size);
617
618 if (info->regs == NULL) {
619 printk(KERN_ERR PFX "cannot reserve register region\n");
620 err = -EIO;
621 goto exit_error;
622 }
623
624 printk(KERN_INFO PFX "mapped registers at %p\n", info->regs);
625
626 /* initialise the hardware */
627
628 err = s3c2410_nand_inithw(info, dev);
629 if (err != 0)
630 goto exit_error;
631
632 sets = (plat != NULL) ? plat->sets : NULL;
633 nr_sets = (plat != NULL) ? plat->nr_sets : 1;
634
635 info->mtd_count = nr_sets;
636
637 /* allocate our information */
638
639 size = nr_sets * sizeof(*info->mtds);
640 info->mtds = kmalloc(size, GFP_KERNEL);
641 if (info->mtds == NULL) {
642 printk(KERN_ERR PFX "failed to allocate mtd storage\n");
643 err = -ENOMEM;
644 goto exit_error;
645 }
646
647 memzero(info->mtds, size);
648
649 /* initialise all possible chips */
650
651 nmtd = info->mtds;
652
653 for (setno = 0; setno < nr_sets; setno++, nmtd++) {
654 pr_debug("initialising set %d (%p, info %p)\n",
655 setno, nmtd, info);
656
657 s3c2410_nand_init_chip(info, nmtd, sets);
658
659 nmtd->scan_res = nand_scan(&nmtd->mtd,
660 (sets) ? sets->nr_chips : 1);
661
662 if (nmtd->scan_res == 0) {
663 s3c2410_nand_add_partition(info, nmtd, sets);
664 }
665
666 if (sets != NULL)
667 sets++;
668 }
669
670 pr_debug("initialised ok\n");
671 return 0;
672
673 exit_error:
674 s3c2410_nand_remove(dev);
675
676 if (err == 0)
677 err = -EINVAL;
678 return err;
679 }
680
681 static struct device_driver s3c2410_nand_driver = {
682 .name = "s3c2410-nand",
683 .bus = &platform_bus_type,
684 .probe = s3c2410_nand_probe,
685 .remove = s3c2410_nand_remove,
686 };
687
688 static int __init s3c2410_nand_init(void)
689 {
690 printk("S3C2410 NAND Driver, (c) 2004 Simtec Electronics\n");
691 return driver_register(&s3c2410_nand_driver);
692 }
693
694 static void __exit s3c2410_nand_exit(void)
695 {
696 driver_unregister(&s3c2410_nand_driver);
697 }
698
699 module_init(s3c2410_nand_init);
700 module_exit(s3c2410_nand_exit);
701
702 MODULE_LICENSE("GPL");
703 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
704 MODULE_DESCRIPTION("S3C2410 MTD NAND driver");
CRIS linux kernel tree