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[PATCH] aic7xxx_osm build fix
[cris-mirror.git] / drivers / net / 8139too.c
blobd4bd20c21a1f26a0a9e928d609d00817f9d1fc0f
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.27"
94
95
96 #include <linux/config.h>
97 #include <linux/module.h>
98 #include <linux/kernel.h>
99 #include <linux/compiler.h>
100 #include <linux/pci.h>
101 #include <linux/init.h>
102 #include <linux/ioport.h>
103 #include <linux/netdevice.h>
104 #include <linux/etherdevice.h>
105 #include <linux/rtnetlink.h>
106 #include <linux/delay.h>
107 #include <linux/ethtool.h>
108 #include <linux/mii.h>
109 #include <linux/completion.h>
110 #include <linux/crc32.h>
111 #include <asm/io.h>
112 #include <asm/uaccess.h>
113 #include <asm/irq.h>
114
115 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
116 #define PFX DRV_NAME ": "
117
118 /* Default Message level */
119 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
120 NETIF_MSG_PROBE | \
121 NETIF_MSG_LINK)
122
123
124 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
125 #ifdef CONFIG_8139TOO_PIO
126 #define USE_IO_OPS 1
127 #endif
128
129 /* define to 1 to enable copious debugging info */
130 #undef RTL8139_DEBUG
131
132 /* define to 1 to disable lightweight runtime debugging checks */
133 #undef RTL8139_NDEBUG
134
135
136 #ifdef RTL8139_DEBUG
137 /* note: prints function name for you */
138 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
139 #else
140 # define DPRINTK(fmt, args...)
141 #endif
142
143 #ifdef RTL8139_NDEBUG
144 # define assert(expr) do {} while (0)
145 #else
146 # define assert(expr) \
147 if(unlikely(!(expr))) { \
148 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
149 #expr,__FILE__,__FUNCTION__,__LINE__); \
150 }
151 #endif
152
153
154 /* A few user-configurable values. */
155 /* media options */
156 #define MAX_UNITS 8
157 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
158 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
159
160 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
161 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
162 static int multicast_filter_limit = 32;
163
164 /* bitmapped message enable number */
165 static int debug = -1;
166
167 /*
168 * Receive ring size
169 * Warning: 64K ring has hardware issues and may lock up.
170 */
171 #if defined(CONFIG_SH_DREAMCAST)
172 #define RX_BUF_IDX 1 /* 16K ring */
173 #else
174 #define RX_BUF_IDX 2 /* 32K ring */
175 #endif
176 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
177 #define RX_BUF_PAD 16
178 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
179
180 #if RX_BUF_LEN == 65536
181 #define RX_BUF_TOT_LEN RX_BUF_LEN
182 #else
183 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
184 #endif
185
186 /* Number of Tx descriptor registers. */
187 #define NUM_TX_DESC 4
188
189 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
190 #define MAX_ETH_FRAME_SIZE 1536
191
192 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
193 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
194 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
195
196 /* PCI Tuning Parameters
197 Threshold is bytes transferred to chip before transmission starts. */
198 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
199
200 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
201 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
202 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
203 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
204 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
205
206 /* Operational parameters that usually are not changed. */
207 /* Time in jiffies before concluding the transmitter is hung. */
208 #define TX_TIMEOUT (6*HZ)
209
210
211 enum {
212 HAS_MII_XCVR = 0x010000,
213 HAS_CHIP_XCVR = 0x020000,
214 HAS_LNK_CHNG = 0x040000,
215 };
216
217 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
218 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
219 #define RTL_MIN_IO_SIZE 0x80
220 #define RTL8139B_IO_SIZE 256
221
222 #define RTL8129_CAPS HAS_MII_XCVR
223 #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
224
225 typedef enum {
226 RTL8139 = 0,
227 RTL8129,
228 } board_t;
229
230
231 /* indexed by board_t, above */
232 static struct {
233 const char *name;
234 u32 hw_flags;
235 } board_info[] __devinitdata = {
236 { "RealTek RTL8139", RTL8139_CAPS },
237 { "RealTek RTL8129", RTL8129_CAPS },
238 };
239
240
241 static struct pci_device_id rtl8139_pci_tbl[] = {
242 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
261
262 #ifdef CONFIG_SH_SECUREEDGE5410
263 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
264 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
265 #endif
266 #ifdef CONFIG_8139TOO_8129
267 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
268 #endif
269
270 /* some crazy cards report invalid vendor ids like
271 * 0x0001 here. The other ids are valid and constant,
272 * so we simply don't match on the main vendor id.
273 */
274 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
275 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
276 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
277
278 {0,}
279 };
280 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
281
282 static struct {
283 const char str[ETH_GSTRING_LEN];
284 } ethtool_stats_keys[] = {
285 { "early_rx" },
286 { "tx_buf_mapped" },
287 { "tx_timeouts" },
288 { "rx_lost_in_ring" },
289 };
290
291 /* The rest of these values should never change. */
292
293 /* Symbolic offsets to registers. */
294 enum RTL8139_registers {
295 MAC0 = 0, /* Ethernet hardware address. */
296 MAR0 = 8, /* Multicast filter. */
297 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
298 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
299 RxBuf = 0x30,
300 ChipCmd = 0x37,
301 RxBufPtr = 0x38,
302 RxBufAddr = 0x3A,
303 IntrMask = 0x3C,
304 IntrStatus = 0x3E,
305 TxConfig = 0x40,
306 RxConfig = 0x44,
307 Timer = 0x48, /* A general-purpose counter. */
308 RxMissed = 0x4C, /* 24 bits valid, write clears. */
309 Cfg9346 = 0x50,
310 Config0 = 0x51,
311 Config1 = 0x52,
312 FlashReg = 0x54,
313 MediaStatus = 0x58,
314 Config3 = 0x59,
315 Config4 = 0x5A, /* absent on RTL-8139A */
316 HltClk = 0x5B,
317 MultiIntr = 0x5C,
318 TxSummary = 0x60,
319 BasicModeCtrl = 0x62,
320 BasicModeStatus = 0x64,
321 NWayAdvert = 0x66,
322 NWayLPAR = 0x68,
323 NWayExpansion = 0x6A,
324 /* Undocumented registers, but required for proper operation. */
325 FIFOTMS = 0x70, /* FIFO Control and test. */
326 CSCR = 0x74, /* Chip Status and Configuration Register. */
327 PARA78 = 0x78,
328 PARA7c = 0x7c, /* Magic transceiver parameter register. */
329 Config5 = 0xD8, /* absent on RTL-8139A */
330 };
331
332 enum ClearBitMasks {
333 MultiIntrClear = 0xF000,
334 ChipCmdClear = 0xE2,
335 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
336 };
337
338 enum ChipCmdBits {
339 CmdReset = 0x10,
340 CmdRxEnb = 0x08,
341 CmdTxEnb = 0x04,
342 RxBufEmpty = 0x01,
343 };
344
345 /* Interrupt register bits, using my own meaningful names. */
346 enum IntrStatusBits {
347 PCIErr = 0x8000,
348 PCSTimeout = 0x4000,
349 RxFIFOOver = 0x40,
350 RxUnderrun = 0x20,
351 RxOverflow = 0x10,
352 TxErr = 0x08,
353 TxOK = 0x04,
354 RxErr = 0x02,
355 RxOK = 0x01,
356
357 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
358 };
359
360 enum TxStatusBits {
361 TxHostOwns = 0x2000,
362 TxUnderrun = 0x4000,
363 TxStatOK = 0x8000,
364 TxOutOfWindow = 0x20000000,
365 TxAborted = 0x40000000,
366 TxCarrierLost = 0x80000000,
367 };
368 enum RxStatusBits {
369 RxMulticast = 0x8000,
370 RxPhysical = 0x4000,
371 RxBroadcast = 0x2000,
372 RxBadSymbol = 0x0020,
373 RxRunt = 0x0010,
374 RxTooLong = 0x0008,
375 RxCRCErr = 0x0004,
376 RxBadAlign = 0x0002,
377 RxStatusOK = 0x0001,
378 };
379
380 /* Bits in RxConfig. */
381 enum rx_mode_bits {
382 AcceptErr = 0x20,
383 AcceptRunt = 0x10,
384 AcceptBroadcast = 0x08,
385 AcceptMulticast = 0x04,
386 AcceptMyPhys = 0x02,
387 AcceptAllPhys = 0x01,
388 };
389
390 /* Bits in TxConfig. */
391 enum tx_config_bits {
392
393 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
394 TxIFGShift = 24,
395 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
396 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
397 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
398 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
399
400 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
401 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
402 TxClearAbt = (1 << 0), /* Clear abort (WO) */
403 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
404 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
405
406 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
407 };
408
409 /* Bits in Config1 */
410 enum Config1Bits {
411 Cfg1_PM_Enable = 0x01,
412 Cfg1_VPD_Enable = 0x02,
413 Cfg1_PIO = 0x04,
414 Cfg1_MMIO = 0x08,
415 LWAKE = 0x10, /* not on 8139, 8139A */
416 Cfg1_Driver_Load = 0x20,
417 Cfg1_LED0 = 0x40,
418 Cfg1_LED1 = 0x80,
419 SLEEP = (1 << 1), /* only on 8139, 8139A */
420 PWRDN = (1 << 0), /* only on 8139, 8139A */
421 };
422
423 /* Bits in Config3 */
424 enum Config3Bits {
425 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
426 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
427 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
428 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
429 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
430 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
431 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
432 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
433 };
434
435 /* Bits in Config4 */
436 enum Config4Bits {
437 LWPTN = (1 << 2), /* not on 8139, 8139A */
438 };
439
440 /* Bits in Config5 */
441 enum Config5Bits {
442 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
443 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
444 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
445 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
446 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
447 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
448 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
449 };
450
451 enum RxConfigBits {
452 /* rx fifo threshold */
453 RxCfgFIFOShift = 13,
454 RxCfgFIFONone = (7 << RxCfgFIFOShift),
455
456 /* Max DMA burst */
457 RxCfgDMAShift = 8,
458 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
459
460 /* rx ring buffer length */
461 RxCfgRcv8K = 0,
462 RxCfgRcv16K = (1 << 11),
463 RxCfgRcv32K = (1 << 12),
464 RxCfgRcv64K = (1 << 11) | (1 << 12),
465
466 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
467 RxNoWrap = (1 << 7),
468 };
469
470 /* Twister tuning parameters from RealTek.
471 Completely undocumented, but required to tune bad links on some boards. */
472 enum CSCRBits {
473 CSCR_LinkOKBit = 0x0400,
474 CSCR_LinkChangeBit = 0x0800,
475 CSCR_LinkStatusBits = 0x0f000,
476 CSCR_LinkDownOffCmd = 0x003c0,
477 CSCR_LinkDownCmd = 0x0f3c0,
478 };
479
480 enum Cfg9346Bits {
481 Cfg9346_Lock = 0x00,
482 Cfg9346_Unlock = 0xC0,
483 };
484
485 typedef enum {
486 CH_8139 = 0,
487 CH_8139_K,
488 CH_8139A,
489 CH_8139A_G,
490 CH_8139B,
491 CH_8130,
492 CH_8139C,
493 CH_8100,
494 CH_8100B_8139D,
495 CH_8101,
496 } chip_t;
497
498 enum chip_flags {
499 HasHltClk = (1 << 0),
500 HasLWake = (1 << 1),
501 };
502
503 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
504 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
505 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
506
507 /* directly indexed by chip_t, above */
508 const static struct {
509 const char *name;
510 u32 version; /* from RTL8139C/RTL8139D docs */
511 u32 flags;
512 } rtl_chip_info[] = {
513 { "RTL-8139",
514 HW_REVID(1, 0, 0, 0, 0, 0, 0),
515 HasHltClk,
516 },
517
518 { "RTL-8139 rev K",
519 HW_REVID(1, 1, 0, 0, 0, 0, 0),
520 HasHltClk,
521 },
522
523 { "RTL-8139A",
524 HW_REVID(1, 1, 1, 0, 0, 0, 0),
525 HasHltClk, /* XXX undocumented? */
526 },
527
528 { "RTL-8139A rev G",
529 HW_REVID(1, 1, 1, 0, 0, 1, 0),
530 HasHltClk, /* XXX undocumented? */
531 },
532
533 { "RTL-8139B",
534 HW_REVID(1, 1, 1, 1, 0, 0, 0),
535 HasLWake,
536 },
537
538 { "RTL-8130",
539 HW_REVID(1, 1, 1, 1, 1, 0, 0),
540 HasLWake,
541 },
542
543 { "RTL-8139C",
544 HW_REVID(1, 1, 1, 0, 1, 0, 0),
545 HasLWake,
546 },
547
548 { "RTL-8100",
549 HW_REVID(1, 1, 1, 1, 0, 1, 0),
550 HasLWake,
551 },
552
553 { "RTL-8100B/8139D",
554 HW_REVID(1, 1, 1, 0, 1, 0, 1),
555 HasLWake,
556 },
557
558 { "RTL-8101",
559 HW_REVID(1, 1, 1, 0, 1, 1, 1),
560 HasLWake,
561 },
562 };
563
564 struct rtl_extra_stats {
565 unsigned long early_rx;
566 unsigned long tx_buf_mapped;
567 unsigned long tx_timeouts;
568 unsigned long rx_lost_in_ring;
569 };
570
571 struct rtl8139_private {
572 void *mmio_addr;
573 int drv_flags;
574 struct pci_dev *pci_dev;
575 u32 msg_enable;
576 struct net_device_stats stats;
577 unsigned char *rx_ring;
578 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
579 unsigned int tx_flag;
580 unsigned long cur_tx;
581 unsigned long dirty_tx;
582 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
583 unsigned char *tx_bufs; /* Tx bounce buffer region. */
584 dma_addr_t rx_ring_dma;
585 dma_addr_t tx_bufs_dma;
586 signed char phys[4]; /* MII device addresses. */
587 char twistie, twist_row, twist_col; /* Twister tune state. */
588 unsigned int default_port:4; /* Last dev->if_port value. */
589 spinlock_t lock;
590 spinlock_t rx_lock;
591 chip_t chipset;
592 pid_t thr_pid;
593 wait_queue_head_t thr_wait;
594 struct completion thr_exited;
595 u32 rx_config;
596 struct rtl_extra_stats xstats;
597 int time_to_die;
598 struct mii_if_info mii;
599 unsigned int regs_len;
600 unsigned long fifo_copy_timeout;
601 };
602
603 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
604 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
605 MODULE_LICENSE("GPL");
606 MODULE_VERSION(DRV_VERSION);
607
608 module_param(multicast_filter_limit, int, 0);
609 module_param_array(media, int, NULL, 0);
610 module_param_array(full_duplex, int, NULL, 0);
611 module_param(debug, int, 0);
612 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
613 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
614 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
615 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
616
617 static int read_eeprom (void *ioaddr, int location, int addr_len);
618 static int rtl8139_open (struct net_device *dev);
619 static int mdio_read (struct net_device *dev, int phy_id, int location);
620 static void mdio_write (struct net_device *dev, int phy_id, int location,
621 int val);
622 static void rtl8139_start_thread(struct net_device *dev);
623 static void rtl8139_tx_timeout (struct net_device *dev);
624 static void rtl8139_init_ring (struct net_device *dev);
625 static int rtl8139_start_xmit (struct sk_buff *skb,
626 struct net_device *dev);
627 static int rtl8139_poll(struct net_device *dev, int *budget);
628 #ifdef CONFIG_NET_POLL_CONTROLLER
629 static void rtl8139_poll_controller(struct net_device *dev);
630 #endif
631 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
632 struct pt_regs *regs);
633 static int rtl8139_close (struct net_device *dev);
634 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
635 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
636 static void rtl8139_set_rx_mode (struct net_device *dev);
637 static void __set_rx_mode (struct net_device *dev);
638 static void rtl8139_hw_start (struct net_device *dev);
639 static struct ethtool_ops rtl8139_ethtool_ops;
640
641 #ifdef USE_IO_OPS
642
643 #define RTL_R8(reg) inb (((unsigned long)ioaddr) + (reg))
644 #define RTL_R16(reg) inw (((unsigned long)ioaddr) + (reg))
645 #define RTL_R32(reg) ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
646 #define RTL_W8(reg, val8) outb ((val8), ((unsigned long)ioaddr) + (reg))
647 #define RTL_W16(reg, val16) outw ((val16), ((unsigned long)ioaddr) + (reg))
648 #define RTL_W32(reg, val32) outl ((val32), ((unsigned long)ioaddr) + (reg))
649 #define RTL_W8_F RTL_W8
650 #define RTL_W16_F RTL_W16
651 #define RTL_W32_F RTL_W32
652 #undef readb
653 #undef readw
654 #undef readl
655 #undef writeb
656 #undef writew
657 #undef writel
658 #define readb(addr) inb((unsigned long)(addr))
659 #define readw(addr) inw((unsigned long)(addr))
660 #define readl(addr) inl((unsigned long)(addr))
661 #define writeb(val,addr) outb((val),(unsigned long)(addr))
662 #define writew(val,addr) outw((val),(unsigned long)(addr))
663 #define writel(val,addr) outl((val),(unsigned long)(addr))
664
665 #else
666
667 /* write MMIO register, with flush */
668 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
669 #define RTL_W8_F(reg, val8) do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
670 #define RTL_W16_F(reg, val16) do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
671 #define RTL_W32_F(reg, val32) do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
672
673
674 #define MMIO_FLUSH_AUDIT_COMPLETE 1
675 #if MMIO_FLUSH_AUDIT_COMPLETE
676
677 /* write MMIO register */
678 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
679 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
680 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
681
682 #else
683
684 /* write MMIO register, then flush */
685 #define RTL_W8 RTL_W8_F
686 #define RTL_W16 RTL_W16_F
687 #define RTL_W32 RTL_W32_F
688
689 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
690
691 /* read MMIO register */
692 #define RTL_R8(reg) readb (ioaddr + (reg))
693 #define RTL_R16(reg) readw (ioaddr + (reg))
694 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
695
696 #endif /* USE_IO_OPS */
697
698
699 static const u16 rtl8139_intr_mask =
700 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
701 TxErr | TxOK | RxErr | RxOK;
702
703 static const u16 rtl8139_norx_intr_mask =
704 PCIErr | PCSTimeout | RxUnderrun |
705 TxErr | TxOK | RxErr ;
706
707 #if RX_BUF_IDX == 0
708 static const unsigned int rtl8139_rx_config =
709 RxCfgRcv8K | RxNoWrap |
710 (RX_FIFO_THRESH << RxCfgFIFOShift) |
711 (RX_DMA_BURST << RxCfgDMAShift);
712 #elif RX_BUF_IDX == 1
713 static const unsigned int rtl8139_rx_config =
714 RxCfgRcv16K | RxNoWrap |
715 (RX_FIFO_THRESH << RxCfgFIFOShift) |
716 (RX_DMA_BURST << RxCfgDMAShift);
717 #elif RX_BUF_IDX == 2
718 static const unsigned int rtl8139_rx_config =
719 RxCfgRcv32K | RxNoWrap |
720 (RX_FIFO_THRESH << RxCfgFIFOShift) |
721 (RX_DMA_BURST << RxCfgDMAShift);
722 #elif RX_BUF_IDX == 3
723 static const unsigned int rtl8139_rx_config =
724 RxCfgRcv64K |
725 (RX_FIFO_THRESH << RxCfgFIFOShift) |
726 (RX_DMA_BURST << RxCfgDMAShift);
727 #else
728 #error "Invalid configuration for 8139_RXBUF_IDX"
729 #endif
730
731 static const unsigned int rtl8139_tx_config =
732 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
733
734 static void __rtl8139_cleanup_dev (struct net_device *dev)
735 {
736 struct rtl8139_private *tp = netdev_priv(dev);
737 struct pci_dev *pdev;
738
739 assert (dev != NULL);
740 assert (tp->pci_dev != NULL);
741 pdev = tp->pci_dev;
742
743 #ifndef USE_IO_OPS
744 if (tp->mmio_addr)
745 iounmap (tp->mmio_addr);
746 #endif /* !USE_IO_OPS */
747
748 /* it's ok to call this even if we have no regions to free */
749 pci_release_regions (pdev);
750
751 free_netdev(dev);
752 pci_set_drvdata (pdev, NULL);
753 }
754
755
756 static void rtl8139_chip_reset (void *ioaddr)
757 {
758 int i;
759
760 /* Soft reset the chip. */
761 RTL_W8 (ChipCmd, CmdReset);
762
763 /* Check that the chip has finished the reset. */
764 for (i = 1000; i > 0; i--) {
765 barrier();
766 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
767 break;
768 udelay (10);
769 }
770 }
771
772
773 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
774 struct net_device **dev_out)
775 {
776 void *ioaddr;
777 struct net_device *dev;
778 struct rtl8139_private *tp;
779 u8 tmp8;
780 int rc, disable_dev_on_err = 0;
781 unsigned int i;
782 unsigned long pio_start, pio_end, pio_flags, pio_len;
783 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
784 u32 version;
785
786 assert (pdev != NULL);
787
788 *dev_out = NULL;
789
790 /* dev and priv zeroed in alloc_etherdev */
791 dev = alloc_etherdev (sizeof (*tp));
792 if (dev == NULL) {
793 printk (KERN_ERR PFX "%s: Unable to alloc new net device\n", pci_name(pdev));
794 return -ENOMEM;
795 }
796 SET_MODULE_OWNER(dev);
797 SET_NETDEV_DEV(dev, &pdev->dev);
798
799 tp = netdev_priv(dev);
800 tp->pci_dev = pdev;
801
802 /* enable device (incl. PCI PM wakeup and hotplug setup) */
803 rc = pci_enable_device (pdev);
804 if (rc)
805 goto err_out;
806
807 pio_start = pci_resource_start (pdev, 0);
808 pio_end = pci_resource_end (pdev, 0);
809 pio_flags = pci_resource_flags (pdev, 0);
810 pio_len = pci_resource_len (pdev, 0);
811
812 mmio_start = pci_resource_start (pdev, 1);
813 mmio_end = pci_resource_end (pdev, 1);
814 mmio_flags = pci_resource_flags (pdev, 1);
815 mmio_len = pci_resource_len (pdev, 1);
816
817 /* set this immediately, we need to know before
818 * we talk to the chip directly */
819 DPRINTK("PIO region size == 0x%02X\n", pio_len);
820 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
821
822 #ifdef USE_IO_OPS
823 /* make sure PCI base addr 0 is PIO */
824 if (!(pio_flags & IORESOURCE_IO)) {
825 printk (KERN_ERR PFX "%s: region #0 not a PIO resource, aborting\n", pci_name(pdev));
826 rc = -ENODEV;
827 goto err_out;
828 }
829 /* check for weird/broken PCI region reporting */
830 if (pio_len < RTL_MIN_IO_SIZE) {
831 printk (KERN_ERR PFX "%s: Invalid PCI I/O region size(s), aborting\n", pci_name(pdev));
832 rc = -ENODEV;
833 goto err_out;
834 }
835 #else
836 /* make sure PCI base addr 1 is MMIO */
837 if (!(mmio_flags & IORESOURCE_MEM)) {
838 printk (KERN_ERR PFX "%s: region #1 not an MMIO resource, aborting\n", pci_name(pdev));
839 rc = -ENODEV;
840 goto err_out;
841 }
842 if (mmio_len < RTL_MIN_IO_SIZE) {
843 printk (KERN_ERR PFX "%s: Invalid PCI mem region size(s), aborting\n", pci_name(pdev));
844 rc = -ENODEV;
845 goto err_out;
846 }
847 #endif
848
849 rc = pci_request_regions (pdev, "8139too");
850 if (rc)
851 goto err_out;
852 disable_dev_on_err = 1;
853
854 /* enable PCI bus-mastering */
855 pci_set_master (pdev);
856
857 #ifdef USE_IO_OPS
858 ioaddr = (void *) pio_start;
859 dev->base_addr = pio_start;
860 tp->mmio_addr = ioaddr;
861 tp->regs_len = pio_len;
862 #else
863 /* ioremap MMIO region */
864 ioaddr = ioremap (mmio_start, mmio_len);
865 if (ioaddr == NULL) {
866 printk (KERN_ERR PFX "%s: cannot remap MMIO, aborting\n", pci_name(pdev));
867 rc = -EIO;
868 goto err_out;
869 }
870 dev->base_addr = (long) ioaddr;
871 tp->mmio_addr = ioaddr;
872 tp->regs_len = mmio_len;
873 #endif /* USE_IO_OPS */
874
875 /* Bring old chips out of low-power mode. */
876 RTL_W8 (HltClk, 'R');
877
878 /* check for missing/broken hardware */
879 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
880 printk (KERN_ERR PFX "%s: Chip not responding, ignoring board\n",
881 pci_name(pdev));
882 rc = -EIO;
883 goto err_out;
884 }
885
886 /* identify chip attached to board */
887 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
888 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
889 if (version == rtl_chip_info[i].version) {
890 tp->chipset = i;
891 goto match;
892 }
893
894 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
895 printk (KERN_DEBUG PFX "%s: unknown chip version, assuming RTL-8139\n",
896 pci_name(pdev));
897 printk (KERN_DEBUG PFX "%s: TxConfig = 0x%lx\n", pci_name(pdev), RTL_R32 (TxConfig));
898 tp->chipset = 0;
899
900 match:
901 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
902 version, i, rtl_chip_info[i].name);
903
904 if (tp->chipset >= CH_8139B) {
905 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
906 DPRINTK("PCI PM wakeup\n");
907 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
908 (tmp8 & LWAKE))
909 new_tmp8 &= ~LWAKE;
910 new_tmp8 |= Cfg1_PM_Enable;
911 if (new_tmp8 != tmp8) {
912 RTL_W8 (Cfg9346, Cfg9346_Unlock);
913 RTL_W8 (Config1, tmp8);
914 RTL_W8 (Cfg9346, Cfg9346_Lock);
915 }
916 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
917 tmp8 = RTL_R8 (Config4);
918 if (tmp8 & LWPTN) {
919 RTL_W8 (Cfg9346, Cfg9346_Unlock);
920 RTL_W8 (Config4, tmp8 & ~LWPTN);
921 RTL_W8 (Cfg9346, Cfg9346_Lock);
922 }
923 }
924 } else {
925 DPRINTK("Old chip wakeup\n");
926 tmp8 = RTL_R8 (Config1);
927 tmp8 &= ~(SLEEP | PWRDN);
928 RTL_W8 (Config1, tmp8);
929 }
930
931 rtl8139_chip_reset (ioaddr);
932
933 *dev_out = dev;
934 return 0;
935
936 err_out:
937 __rtl8139_cleanup_dev (dev);
938 if (disable_dev_on_err)
939 pci_disable_device (pdev);
940 return rc;
941 }
942
943
944 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
945 const struct pci_device_id *ent)
946 {
947 struct net_device *dev = NULL;
948 struct rtl8139_private *tp;
949 int i, addr_len, option;
950 void *ioaddr;
951 static int board_idx = -1;
952 u8 pci_rev;
953
954 assert (pdev != NULL);
955 assert (ent != NULL);
956
957 board_idx++;
958
959 /* when we're built into the kernel, the driver version message
960 * is only printed if at least one 8139 board has been found
961 */
962 #ifndef MODULE
963 {
964 static int printed_version;
965 if (!printed_version++)
966 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
967 }
968 #endif
969
970 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
971
972 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
973 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {
974 printk(KERN_INFO PFX "pci dev %s (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
975 pci_name(pdev), pdev->vendor, pdev->device, pci_rev);
976 printk(KERN_INFO PFX "Use the \"8139cp\" driver for improved performance and stability.\n");
977 }
978
979 i = rtl8139_init_board (pdev, &dev);
980 if (i < 0)
981 return i;
982
983 assert (dev != NULL);
984 tp = netdev_priv(dev);
985
986 ioaddr = tp->mmio_addr;
987 assert (ioaddr != NULL);
988
989 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
990 for (i = 0; i < 3; i++)
991 ((u16 *) (dev->dev_addr))[i] =
992 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
993
994 /* The Rtl8139-specific entries in the device structure. */
995 dev->open = rtl8139_open;
996 dev->hard_start_xmit = rtl8139_start_xmit;
997 dev->poll = rtl8139_poll;
998 dev->weight = 64;
999 dev->stop = rtl8139_close;
1000 dev->get_stats = rtl8139_get_stats;
1001 dev->set_multicast_list = rtl8139_set_rx_mode;
1002 dev->do_ioctl = netdev_ioctl;
1003 dev->ethtool_ops = &rtl8139_ethtool_ops;
1004 dev->tx_timeout = rtl8139_tx_timeout;
1005 dev->watchdog_timeo = TX_TIMEOUT;
1006 #ifdef CONFIG_NET_POLL_CONTROLLER
1007 dev->poll_controller = rtl8139_poll_controller;
1008 #endif
1009
1010 /* note: the hardware is not capable of sg/csum/highdma, however
1011 * through the use of skb_copy_and_csum_dev we enable these
1012 * features
1013 */
1014 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1015
1016 dev->irq = pdev->irq;
1017
1018 /* tp zeroed and aligned in alloc_etherdev */
1019 tp = netdev_priv(dev);
1020
1021 /* note: tp->chipset set in rtl8139_init_board */
1022 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1023 tp->mmio_addr = ioaddr;
1024 tp->msg_enable =
1025 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1026 spin_lock_init (&tp->lock);
1027 spin_lock_init (&tp->rx_lock);
1028 init_waitqueue_head (&tp->thr_wait);
1029 init_completion (&tp->thr_exited);
1030 tp->mii.dev = dev;
1031 tp->mii.mdio_read = mdio_read;
1032 tp->mii.mdio_write = mdio_write;
1033 tp->mii.phy_id_mask = 0x3f;
1034 tp->mii.reg_num_mask = 0x1f;
1035
1036 /* dev is fully set up and ready to use now */
1037 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1038 i = register_netdev (dev);
1039 if (i) goto err_out;
1040
1041 pci_set_drvdata (pdev, dev);
1042
1043 printk (KERN_INFO "%s: %s at 0x%lx, "
1044 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1045 "IRQ %d\n",
1046 dev->name,
1047 board_info[ent->driver_data].name,
1048 dev->base_addr,
1049 dev->dev_addr[0], dev->dev_addr[1],
1050 dev->dev_addr[2], dev->dev_addr[3],
1051 dev->dev_addr[4], dev->dev_addr[5],
1052 dev->irq);
1053
1054 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1055 dev->name, rtl_chip_info[tp->chipset].name);
1056
1057 /* Find the connected MII xcvrs.
1058 Doing this in open() would allow detecting external xcvrs later, but
1059 takes too much time. */
1060 #ifdef CONFIG_8139TOO_8129
1061 if (tp->drv_flags & HAS_MII_XCVR) {
1062 int phy, phy_idx = 0;
1063 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1064 int mii_status = mdio_read(dev, phy, 1);
1065 if (mii_status != 0xffff && mii_status != 0x0000) {
1066 u16 advertising = mdio_read(dev, phy, 4);
1067 tp->phys[phy_idx++] = phy;
1068 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1069 "advertising %4.4x.\n",
1070 dev->name, phy, mii_status, advertising);
1071 }
1072 }
1073 if (phy_idx == 0) {
1074 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1075 "transceiver.\n",
1076 dev->name);
1077 tp->phys[0] = 32;
1078 }
1079 } else
1080 #endif
1081 tp->phys[0] = 32;
1082 tp->mii.phy_id = tp->phys[0];
1083
1084 /* The lower four bits are the media type. */
1085 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1086 if (option > 0) {
1087 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1088 tp->default_port = option & 0xFF;
1089 if (tp->default_port)
1090 tp->mii.force_media = 1;
1091 }
1092 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1093 tp->mii.full_duplex = full_duplex[board_idx];
1094 if (tp->mii.full_duplex) {
1095 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1096 /* Changing the MII-advertised media because might prevent
1097 re-connection. */
1098 tp->mii.force_media = 1;
1099 }
1100 if (tp->default_port) {
1101 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1102 (option & 0x20 ? 100 : 10),
1103 (option & 0x10 ? "full" : "half"));
1104 mdio_write(dev, tp->phys[0], 0,
1105 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1106 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1107 }
1108
1109 /* Put the chip into low-power mode. */
1110 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1111 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1112
1113 return 0;
1114
1115 err_out:
1116 __rtl8139_cleanup_dev (dev);
1117 pci_disable_device (pdev);
1118 return i;
1119 }
1120
1121
1122 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1123 {
1124 struct net_device *dev = pci_get_drvdata (pdev);
1125
1126 assert (dev != NULL);
1127
1128 unregister_netdev (dev);
1129
1130 __rtl8139_cleanup_dev (dev);
1131 pci_disable_device (pdev);
1132 }
1133
1134
1135 /* Serial EEPROM section. */
1136
1137 /* EEPROM_Ctrl bits. */
1138 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1139 #define EE_CS 0x08 /* EEPROM chip select. */
1140 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1141 #define EE_WRITE_0 0x00
1142 #define EE_WRITE_1 0x02
1143 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1144 #define EE_ENB (0x80 | EE_CS)
1145
1146 /* Delay between EEPROM clock transitions.
1147 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1148 */
1149
1150 #define eeprom_delay() readl(ee_addr)
1151
1152 /* The EEPROM commands include the alway-set leading bit. */
1153 #define EE_WRITE_CMD (5)
1154 #define EE_READ_CMD (6)
1155 #define EE_ERASE_CMD (7)
1156
1157 static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
1158 {
1159 int i;
1160 unsigned retval = 0;
1161 void *ee_addr = ioaddr + Cfg9346;
1162 int read_cmd = location | (EE_READ_CMD << addr_len);
1163
1164 writeb (EE_ENB & ~EE_CS, ee_addr);
1165 writeb (EE_ENB, ee_addr);
1166 eeprom_delay ();
1167
1168 /* Shift the read command bits out. */
1169 for (i = 4 + addr_len; i >= 0; i--) {
1170 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1171 writeb (EE_ENB | dataval, ee_addr);
1172 eeprom_delay ();
1173 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1174 eeprom_delay ();
1175 }
1176 writeb (EE_ENB, ee_addr);
1177 eeprom_delay ();
1178
1179 for (i = 16; i > 0; i--) {
1180 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1181 eeprom_delay ();
1182 retval =
1183 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1184 0);
1185 writeb (EE_ENB, ee_addr);
1186 eeprom_delay ();
1187 }
1188
1189 /* Terminate the EEPROM access. */
1190 writeb (~EE_CS, ee_addr);
1191 eeprom_delay ();
1192
1193 return retval;
1194 }
1195
1196 /* MII serial management: mostly bogus for now. */
1197 /* Read and write the MII management registers using software-generated
1198 serial MDIO protocol.
1199 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1200 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1201 "overclocking" issues. */
1202 #define MDIO_DIR 0x80
1203 #define MDIO_DATA_OUT 0x04
1204 #define MDIO_DATA_IN 0x02
1205 #define MDIO_CLK 0x01
1206 #define MDIO_WRITE0 (MDIO_DIR)
1207 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1208
1209 #define mdio_delay(mdio_addr) readb(mdio_addr)
1210
1211
1212 static char mii_2_8139_map[8] = {
1213 BasicModeCtrl,
1214 BasicModeStatus,
1215 0,
1216 0,
1217 NWayAdvert,
1218 NWayLPAR,
1219 NWayExpansion,
1220 0
1221 };
1222
1223
1224 #ifdef CONFIG_8139TOO_8129
1225 /* Syncronize the MII management interface by shifting 32 one bits out. */
1226 static void mdio_sync (void *mdio_addr)
1227 {
1228 int i;
1229
1230 for (i = 32; i >= 0; i--) {
1231 writeb (MDIO_WRITE1, mdio_addr);
1232 mdio_delay (mdio_addr);
1233 writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
1234 mdio_delay (mdio_addr);
1235 }
1236 }
1237 #endif
1238
1239 static int mdio_read (struct net_device *dev, int phy_id, int location)
1240 {
1241 struct rtl8139_private *tp = netdev_priv(dev);
1242 int retval = 0;
1243 #ifdef CONFIG_8139TOO_8129
1244 void *mdio_addr = tp->mmio_addr + Config4;
1245 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1246 int i;
1247 #endif
1248
1249 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1250 return location < 8 && mii_2_8139_map[location] ?
1251 readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
1252 }
1253
1254 #ifdef CONFIG_8139TOO_8129
1255 mdio_sync (mdio_addr);
1256 /* Shift the read command bits out. */
1257 for (i = 15; i >= 0; i--) {
1258 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1259
1260 writeb (MDIO_DIR | dataval, mdio_addr);
1261 mdio_delay (mdio_addr);
1262 writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
1263 mdio_delay (mdio_addr);
1264 }
1265
1266 /* Read the two transition, 16 data, and wire-idle bits. */
1267 for (i = 19; i > 0; i--) {
1268 writeb (0, mdio_addr);
1269 mdio_delay (mdio_addr);
1270 retval = (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1 : 0);
1271 writeb (MDIO_CLK, mdio_addr);
1272 mdio_delay (mdio_addr);
1273 }
1274 #endif
1275
1276 return (retval >> 1) & 0xffff;
1277 }
1278
1279
1280 static void mdio_write (struct net_device *dev, int phy_id, int location,
1281 int value)
1282 {
1283 struct rtl8139_private *tp = netdev_priv(dev);
1284 #ifdef CONFIG_8139TOO_8129
1285 void *mdio_addr = tp->mmio_addr + Config4;
1286 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1287 int i;
1288 #endif
1289
1290 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1291 void *ioaddr = tp->mmio_addr;
1292 if (location == 0) {
1293 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1294 RTL_W16 (BasicModeCtrl, value);
1295 RTL_W8 (Cfg9346, Cfg9346_Lock);
1296 } else if (location < 8 && mii_2_8139_map[location])
1297 RTL_W16 (mii_2_8139_map[location], value);
1298 return;
1299 }
1300
1301 #ifdef CONFIG_8139TOO_8129
1302 mdio_sync (mdio_addr);
1303
1304 /* Shift the command bits out. */
1305 for (i = 31; i >= 0; i--) {
1306 int dataval =
1307 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1308 writeb (dataval, mdio_addr);
1309 mdio_delay (mdio_addr);
1310 writeb (dataval | MDIO_CLK, mdio_addr);
1311 mdio_delay (mdio_addr);
1312 }
1313 /* Clear out extra bits. */
1314 for (i = 2; i > 0; i--) {
1315 writeb (0, mdio_addr);
1316 mdio_delay (mdio_addr);
1317 writeb (MDIO_CLK, mdio_addr);
1318 mdio_delay (mdio_addr);
1319 }
1320 #endif
1321 }
1322
1323
1324 static int rtl8139_open (struct net_device *dev)
1325 {
1326 struct rtl8139_private *tp = netdev_priv(dev);
1327 int retval;
1328 void *ioaddr = tp->mmio_addr;
1329
1330 retval = request_irq (dev->irq, rtl8139_interrupt, SA_SHIRQ, dev->name, dev);
1331 if (retval)
1332 return retval;
1333
1334 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1335 &tp->tx_bufs_dma);
1336 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1337 &tp->rx_ring_dma);
1338 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1339 free_irq(dev->irq, dev);
1340
1341 if (tp->tx_bufs)
1342 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1343 tp->tx_bufs, tp->tx_bufs_dma);
1344 if (tp->rx_ring)
1345 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1346 tp->rx_ring, tp->rx_ring_dma);
1347
1348 return -ENOMEM;
1349
1350 }
1351
1352 tp->mii.full_duplex = tp->mii.force_media;
1353 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1354
1355 rtl8139_init_ring (dev);
1356 rtl8139_hw_start (dev);
1357 netif_start_queue (dev);
1358
1359 if (netif_msg_ifup(tp))
1360 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#lx IRQ %d"
1361 " GP Pins %2.2x %s-duplex.\n",
1362 dev->name, pci_resource_start (tp->pci_dev, 1),
1363 dev->irq, RTL_R8 (MediaStatus),
1364 tp->mii.full_duplex ? "full" : "half");
1365
1366 rtl8139_start_thread(dev);
1367
1368 return 0;
1369 }
1370
1371
1372 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1373 {
1374 struct rtl8139_private *tp = netdev_priv(dev);
1375
1376 if (tp->phys[0] >= 0) {
1377 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1378 }
1379 }
1380
1381 /* Start the hardware at open or resume. */
1382 static void rtl8139_hw_start (struct net_device *dev)
1383 {
1384 struct rtl8139_private *tp = netdev_priv(dev);
1385 void *ioaddr = tp->mmio_addr;
1386 u32 i;
1387 u8 tmp;
1388
1389 /* Bring old chips out of low-power mode. */
1390 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1391 RTL_W8 (HltClk, 'R');
1392
1393 rtl8139_chip_reset (ioaddr);
1394
1395 /* unlock Config[01234] and BMCR register writes */
1396 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1397 /* Restore our idea of the MAC address. */
1398 RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1399 RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1400
1401 /* Must enable Tx/Rx before setting transfer thresholds! */
1402 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1403
1404 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1405 RTL_W32 (RxConfig, tp->rx_config);
1406 RTL_W32 (TxConfig, rtl8139_tx_config);
1407
1408 tp->cur_rx = 0;
1409
1410 rtl_check_media (dev, 1);
1411
1412 if (tp->chipset >= CH_8139B) {
1413 /* Disable magic packet scanning, which is enabled
1414 * when PM is enabled in Config1. It can be reenabled
1415 * via ETHTOOL_SWOL if desired. */
1416 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1417 }
1418
1419 DPRINTK("init buffer addresses\n");
1420
1421 /* Lock Config[01234] and BMCR register writes */
1422 RTL_W8 (Cfg9346, Cfg9346_Lock);
1423
1424 /* init Rx ring buffer DMA address */
1425 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1426
1427 /* init Tx buffer DMA addresses */
1428 for (i = 0; i < NUM_TX_DESC; i++)
1429 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1430
1431 RTL_W32 (RxMissed, 0);
1432
1433 rtl8139_set_rx_mode (dev);
1434
1435 /* no early-rx interrupts */
1436 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1437
1438 /* make sure RxTx has started */
1439 tmp = RTL_R8 (ChipCmd);
1440 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1441 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1442
1443 /* Enable all known interrupts by setting the interrupt mask. */
1444 RTL_W16 (IntrMask, rtl8139_intr_mask);
1445 }
1446
1447
1448 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1449 static void rtl8139_init_ring (struct net_device *dev)
1450 {
1451 struct rtl8139_private *tp = netdev_priv(dev);
1452 int i;
1453
1454 tp->cur_rx = 0;
1455 tp->cur_tx = 0;
1456 tp->dirty_tx = 0;
1457
1458 for (i = 0; i < NUM_TX_DESC; i++)
1459 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1460 }
1461
1462
1463 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1464 static int next_tick = 3 * HZ;
1465
1466 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1467 static inline void rtl8139_tune_twister (struct net_device *dev,
1468 struct rtl8139_private *tp) {}
1469 #else
1470 enum TwisterParamVals {
1471 PARA78_default = 0x78fa8388,
1472 PARA7c_default = 0xcb38de43, /* param[0][3] */
1473 PARA7c_xxx = 0xcb38de43,
1474 };
1475
1476 static const unsigned long param[4][4] = {
1477 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1478 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1479 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1480 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1481 };
1482
1483 static void rtl8139_tune_twister (struct net_device *dev,
1484 struct rtl8139_private *tp)
1485 {
1486 int linkcase;
1487 void *ioaddr = tp->mmio_addr;
1488
1489 /* This is a complicated state machine to configure the "twister" for
1490 impedance/echos based on the cable length.
1491 All of this is magic and undocumented.
1492 */
1493 switch (tp->twistie) {
1494 case 1:
1495 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1496 /* We have link beat, let us tune the twister. */
1497 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1498 tp->twistie = 2; /* Change to state 2. */
1499 next_tick = HZ / 10;
1500 } else {
1501 /* Just put in some reasonable defaults for when beat returns. */
1502 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1503 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1504 RTL_W32 (PARA78, PARA78_default);
1505 RTL_W32 (PARA7c, PARA7c_default);
1506 tp->twistie = 0; /* Bail from future actions. */
1507 }
1508 break;
1509 case 2:
1510 /* Read how long it took to hear the echo. */
1511 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1512 if (linkcase == 0x7000)
1513 tp->twist_row = 3;
1514 else if (linkcase == 0x3000)
1515 tp->twist_row = 2;
1516 else if (linkcase == 0x1000)
1517 tp->twist_row = 1;
1518 else
1519 tp->twist_row = 0;
1520 tp->twist_col = 0;
1521 tp->twistie = 3; /* Change to state 2. */
1522 next_tick = HZ / 10;
1523 break;
1524 case 3:
1525 /* Put out four tuning parameters, one per 100msec. */
1526 if (tp->twist_col == 0)
1527 RTL_W16 (FIFOTMS, 0);
1528 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1529 [(int) tp->twist_col]);
1530 next_tick = HZ / 10;
1531 if (++tp->twist_col >= 4) {
1532 /* For short cables we are done.
1533 For long cables (row == 3) check for mistune. */
1534 tp->twistie =
1535 (tp->twist_row == 3) ? 4 : 0;
1536 }
1537 break;
1538 case 4:
1539 /* Special case for long cables: check for mistune. */
1540 if ((RTL_R16 (CSCR) &
1541 CSCR_LinkStatusBits) == 0x7000) {
1542 tp->twistie = 0;
1543 break;
1544 } else {
1545 RTL_W32 (PARA7c, 0xfb38de03);
1546 tp->twistie = 5;
1547 next_tick = HZ / 10;
1548 }
1549 break;
1550 case 5:
1551 /* Retune for shorter cable (column 2). */
1552 RTL_W32 (FIFOTMS, 0x20);
1553 RTL_W32 (PARA78, PARA78_default);
1554 RTL_W32 (PARA7c, PARA7c_default);
1555 RTL_W32 (FIFOTMS, 0x00);
1556 tp->twist_row = 2;
1557 tp->twist_col = 0;
1558 tp->twistie = 3;
1559 next_tick = HZ / 10;
1560 break;
1561
1562 default:
1563 /* do nothing */
1564 break;
1565 }
1566 }
1567 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1568
1569 static inline void rtl8139_thread_iter (struct net_device *dev,
1570 struct rtl8139_private *tp,
1571 void *ioaddr)
1572 {
1573 int mii_lpa;
1574
1575 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1576
1577 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1578 int duplex = (mii_lpa & LPA_100FULL)
1579 || (mii_lpa & 0x01C0) == 0x0040;
1580 if (tp->mii.full_duplex != duplex) {
1581 tp->mii.full_duplex = duplex;
1582
1583 if (mii_lpa) {
1584 printk (KERN_INFO
1585 "%s: Setting %s-duplex based on MII #%d link"
1586 " partner ability of %4.4x.\n",
1587 dev->name,
1588 tp->mii.full_duplex ? "full" : "half",
1589 tp->phys[0], mii_lpa);
1590 } else {
1591 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1592 dev->name);
1593 }
1594 #if 0
1595 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1596 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1597 RTL_W8 (Cfg9346, Cfg9346_Lock);
1598 #endif
1599 }
1600 }
1601
1602 next_tick = HZ * 60;
1603
1604 rtl8139_tune_twister (dev, tp);
1605
1606 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1607 dev->name, RTL_R16 (NWayLPAR));
1608 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1609 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1610 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1611 dev->name, RTL_R8 (Config0),
1612 RTL_R8 (Config1));
1613 }
1614
1615 static int rtl8139_thread (void *data)
1616 {
1617 struct net_device *dev = data;
1618 struct rtl8139_private *tp = netdev_priv(dev);
1619 unsigned long timeout;
1620
1621 daemonize("%s", dev->name);
1622 allow_signal(SIGTERM);
1623
1624 while (1) {
1625 timeout = next_tick;
1626 do {
1627 timeout = interruptible_sleep_on_timeout (&tp->thr_wait, timeout);
1628 /* make swsusp happy with our thread */
1629 try_to_freeze(PF_FREEZE);
1630 } while (!signal_pending (current) && (timeout > 0));
1631
1632 if (signal_pending (current)) {
1633 flush_signals(current);
1634 }
1635
1636 if (tp->time_to_die)
1637 break;
1638
1639 if (rtnl_lock_interruptible ())
1640 break;
1641 rtl8139_thread_iter (dev, tp, tp->mmio_addr);
1642 rtnl_unlock ();
1643 }
1644
1645 complete_and_exit (&tp->thr_exited, 0);
1646 }
1647
1648 static void rtl8139_start_thread(struct net_device *dev)
1649 {
1650 struct rtl8139_private *tp = netdev_priv(dev);
1651
1652 tp->thr_pid = -1;
1653 tp->twistie = 0;
1654 tp->time_to_die = 0;
1655 if (tp->chipset == CH_8139_K)
1656 tp->twistie = 1;
1657 else if (tp->drv_flags & HAS_LNK_CHNG)
1658 return;
1659
1660 tp->thr_pid = kernel_thread(rtl8139_thread, dev, CLONE_FS|CLONE_FILES);
1661 if (tp->thr_pid < 0) {
1662 printk (KERN_WARNING "%s: unable to start kernel thread\n",
1663 dev->name);
1664 }
1665 }
1666
1667 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1668 {
1669 tp->cur_tx = 0;
1670 tp->dirty_tx = 0;
1671
1672 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1673 }
1674
1675
1676 static void rtl8139_tx_timeout (struct net_device *dev)
1677 {
1678 struct rtl8139_private *tp = netdev_priv(dev);
1679 void *ioaddr = tp->mmio_addr;
1680 int i;
1681 u8 tmp8;
1682 unsigned long flags;
1683
1684 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1685 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1686 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1687 /* Emit info to figure out what went wrong. */
1688 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1689 dev->name, tp->cur_tx, tp->dirty_tx);
1690 for (i = 0; i < NUM_TX_DESC; i++)
1691 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1692 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1693 i == tp->dirty_tx % NUM_TX_DESC ?
1694 " (queue head)" : "");
1695
1696 tp->xstats.tx_timeouts++;
1697
1698 /* disable Tx ASAP, if not already */
1699 tmp8 = RTL_R8 (ChipCmd);
1700 if (tmp8 & CmdTxEnb)
1701 RTL_W8 (ChipCmd, CmdRxEnb);
1702
1703 spin_lock(&tp->rx_lock);
1704 /* Disable interrupts by clearing the interrupt mask. */
1705 RTL_W16 (IntrMask, 0x0000);
1706
1707 /* Stop a shared interrupt from scavenging while we are. */
1708 spin_lock_irqsave (&tp->lock, flags);
1709 rtl8139_tx_clear (tp);
1710 spin_unlock_irqrestore (&tp->lock, flags);
1711
1712 /* ...and finally, reset everything */
1713 if (netif_running(dev)) {
1714 rtl8139_hw_start (dev);
1715 netif_wake_queue (dev);
1716 }
1717 spin_unlock(&tp->rx_lock);
1718 }
1719
1720
1721 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1722 {
1723 struct rtl8139_private *tp = netdev_priv(dev);
1724 void *ioaddr = tp->mmio_addr;
1725 unsigned int entry;
1726 unsigned int len = skb->len;
1727
1728 /* Calculate the next Tx descriptor entry. */
1729 entry = tp->cur_tx % NUM_TX_DESC;
1730
1731 /* Note: the chip doesn't have auto-pad! */
1732 if (likely(len < TX_BUF_SIZE)) {
1733 if (len < ETH_ZLEN)
1734 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1735 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1736 dev_kfree_skb(skb);
1737 } else {
1738 dev_kfree_skb(skb);
1739 tp->stats.tx_dropped++;
1740 return 0;
1741 }
1742
1743 spin_lock_irq(&tp->lock);
1744 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1745 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1746
1747 dev->trans_start = jiffies;
1748
1749 tp->cur_tx++;
1750 wmb();
1751
1752 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1753 netif_stop_queue (dev);
1754 spin_unlock_irq(&tp->lock);
1755
1756 if (netif_msg_tx_queued(tp))
1757 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1758 dev->name, len, entry);
1759
1760 return 0;
1761 }
1762
1763
1764 static void rtl8139_tx_interrupt (struct net_device *dev,
1765 struct rtl8139_private *tp,
1766 void *ioaddr)
1767 {
1768 unsigned long dirty_tx, tx_left;
1769
1770 assert (dev != NULL);
1771 assert (ioaddr != NULL);
1772
1773 dirty_tx = tp->dirty_tx;
1774 tx_left = tp->cur_tx - dirty_tx;
1775 while (tx_left > 0) {
1776 int entry = dirty_tx % NUM_TX_DESC;
1777 int txstatus;
1778
1779 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1780
1781 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1782 break; /* It still hasn't been Txed */
1783
1784 /* Note: TxCarrierLost is always asserted at 100mbps. */
1785 if (txstatus & (TxOutOfWindow | TxAborted)) {
1786 /* There was an major error, log it. */
1787 if (netif_msg_tx_err(tp))
1788 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1789 dev->name, txstatus);
1790 tp->stats.tx_errors++;
1791 if (txstatus & TxAborted) {
1792 tp->stats.tx_aborted_errors++;
1793 RTL_W32 (TxConfig, TxClearAbt);
1794 RTL_W16 (IntrStatus, TxErr);
1795 wmb();
1796 }
1797 if (txstatus & TxCarrierLost)
1798 tp->stats.tx_carrier_errors++;
1799 if (txstatus & TxOutOfWindow)
1800 tp->stats.tx_window_errors++;
1801 } else {
1802 if (txstatus & TxUnderrun) {
1803 /* Add 64 to the Tx FIFO threshold. */
1804 if (tp->tx_flag < 0x00300000)
1805 tp->tx_flag += 0x00020000;
1806 tp->stats.tx_fifo_errors++;
1807 }
1808 tp->stats.collisions += (txstatus >> 24) & 15;
1809 tp->stats.tx_bytes += txstatus & 0x7ff;
1810 tp->stats.tx_packets++;
1811 }
1812
1813 dirty_tx++;
1814 tx_left--;
1815 }
1816
1817 #ifndef RTL8139_NDEBUG
1818 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1819 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1820 dev->name, dirty_tx, tp->cur_tx);
1821 dirty_tx += NUM_TX_DESC;
1822 }
1823 #endif /* RTL8139_NDEBUG */
1824
1825 /* only wake the queue if we did work, and the queue is stopped */
1826 if (tp->dirty_tx != dirty_tx) {
1827 tp->dirty_tx = dirty_tx;
1828 mb();
1829 netif_wake_queue (dev);
1830 }
1831 }
1832
1833
1834 /* TODO: clean this up! Rx reset need not be this intensive */
1835 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1836 struct rtl8139_private *tp, void *ioaddr)
1837 {
1838 u8 tmp8;
1839 #ifdef CONFIG_8139_OLD_RX_RESET
1840 int tmp_work;
1841 #endif
1842
1843 if (netif_msg_rx_err (tp))
1844 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1845 dev->name, rx_status);
1846 tp->stats.rx_errors++;
1847 if (!(rx_status & RxStatusOK)) {
1848 if (rx_status & RxTooLong) {
1849 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1850 dev->name, rx_status);
1851 /* A.C.: The chip hangs here. */
1852 }
1853 if (rx_status & (RxBadSymbol | RxBadAlign))
1854 tp->stats.rx_frame_errors++;
1855 if (rx_status & (RxRunt | RxTooLong))
1856 tp->stats.rx_length_errors++;
1857 if (rx_status & RxCRCErr)
1858 tp->stats.rx_crc_errors++;
1859 } else {
1860 tp->xstats.rx_lost_in_ring++;
1861 }
1862
1863 #ifndef CONFIG_8139_OLD_RX_RESET
1864 tmp8 = RTL_R8 (ChipCmd);
1865 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1866 RTL_W8 (ChipCmd, tmp8);
1867 RTL_W32 (RxConfig, tp->rx_config);
1868 tp->cur_rx = 0;
1869 #else
1870 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1871
1872 /* disable receive */
1873 RTL_W8_F (ChipCmd, CmdTxEnb);
1874 tmp_work = 200;
1875 while (--tmp_work > 0) {
1876 udelay(1);
1877 tmp8 = RTL_R8 (ChipCmd);
1878 if (!(tmp8 & CmdRxEnb))
1879 break;
1880 }
1881 if (tmp_work <= 0)
1882 printk (KERN_WARNING PFX "rx stop wait too long\n");
1883 /* restart receive */
1884 tmp_work = 200;
1885 while (--tmp_work > 0) {
1886 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1887 udelay(1);
1888 tmp8 = RTL_R8 (ChipCmd);
1889 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1890 break;
1891 }
1892 if (tmp_work <= 0)
1893 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1894
1895 /* and reinitialize all rx related registers */
1896 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1897 /* Must enable Tx/Rx before setting transfer thresholds! */
1898 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1899
1900 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1901 RTL_W32 (RxConfig, tp->rx_config);
1902 tp->cur_rx = 0;
1903
1904 DPRINTK("init buffer addresses\n");
1905
1906 /* Lock Config[01234] and BMCR register writes */
1907 RTL_W8 (Cfg9346, Cfg9346_Lock);
1908
1909 /* init Rx ring buffer DMA address */
1910 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1911
1912 /* A.C.: Reset the multicast list. */
1913 __set_rx_mode (dev);
1914 #endif
1915 }
1916
1917 #if RX_BUF_IDX == 3
1918 static __inline__ void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1919 u32 offset, unsigned int size)
1920 {
1921 u32 left = RX_BUF_LEN - offset;
1922
1923 if (size > left) {
1924 memcpy(skb->data, ring + offset, left);
1925 memcpy(skb->data+left, ring, size - left);
1926 } else
1927 memcpy(skb->data, ring + offset, size);
1928 }
1929 #endif
1930
1931 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1932 {
1933 void *ioaddr = tp->mmio_addr;
1934 u16 status;
1935
1936 status = RTL_R16 (IntrStatus) & RxAckBits;
1937
1938 /* Clear out errors and receive interrupts */
1939 if (likely(status != 0)) {
1940 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1941 tp->stats.rx_errors++;
1942 if (status & RxFIFOOver)
1943 tp->stats.rx_fifo_errors++;
1944 }
1945 RTL_W16_F (IntrStatus, RxAckBits);
1946 }
1947 }
1948
1949 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1950 int budget)
1951 {
1952 void *ioaddr = tp->mmio_addr;
1953 int received = 0;
1954 unsigned char *rx_ring = tp->rx_ring;
1955 unsigned int cur_rx = tp->cur_rx;
1956 unsigned int rx_size = 0;
1957
1958 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1959 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1960 RTL_R16 (RxBufAddr),
1961 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1962
1963 while (netif_running(dev) && received < budget
1964 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1965 u32 ring_offset = cur_rx % RX_BUF_LEN;
1966 u32 rx_status;
1967 unsigned int pkt_size;
1968 struct sk_buff *skb;
1969
1970 rmb();
1971
1972 /* read size+status of next frame from DMA ring buffer */
1973 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1974 rx_size = rx_status >> 16;
1975 pkt_size = rx_size - 4;
1976
1977 if (netif_msg_rx_status(tp))
1978 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1979 " cur %4.4x.\n", dev->name, rx_status,
1980 rx_size, cur_rx);
1981 #if RTL8139_DEBUG > 2
1982 {
1983 int i;
1984 DPRINTK ("%s: Frame contents ", dev->name);
1985 for (i = 0; i < 70; i++)
1986 printk (" %2.2x",
1987 rx_ring[ring_offset + i]);
1988 printk (".\n");
1989 }
1990 #endif
1991
1992 /* Packet copy from FIFO still in progress.
1993 * Theoretically, this should never happen
1994 * since EarlyRx is disabled.
1995 */
1996 if (unlikely(rx_size == 0xfff0)) {
1997 if (!tp->fifo_copy_timeout)
1998 tp->fifo_copy_timeout = jiffies + 2;
1999 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
2000 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
2001 rx_size = 0;
2002 goto no_early_rx;
2003 }
2004 if (netif_msg_intr(tp)) {
2005 printk(KERN_DEBUG "%s: fifo copy in progress.",
2006 dev->name);
2007 }
2008 tp->xstats.early_rx++;
2009 break;
2010 }
2011
2012 no_early_rx:
2013 tp->fifo_copy_timeout = 0;
2014
2015 /* If Rx err or invalid rx_size/rx_status received
2016 * (which happens if we get lost in the ring),
2017 * Rx process gets reset, so we abort any further
2018 * Rx processing.
2019 */
2020 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2021 (rx_size < 8) ||
2022 (!(rx_status & RxStatusOK)))) {
2023 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2024 received = -1;
2025 goto out;
2026 }
2027
2028 /* Malloc up new buffer, compatible with net-2e. */
2029 /* Omit the four octet CRC from the length. */
2030
2031 skb = dev_alloc_skb (pkt_size + 2);
2032 if (likely(skb)) {
2033 skb->dev = dev;
2034 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
2035 #if RX_BUF_IDX == 3
2036 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2037 #else
2038 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
2039 #endif
2040 skb_put (skb, pkt_size);
2041
2042 skb->protocol = eth_type_trans (skb, dev);
2043
2044 dev->last_rx = jiffies;
2045 tp->stats.rx_bytes += pkt_size;
2046 tp->stats.rx_packets++;
2047
2048 netif_receive_skb (skb);
2049 } else {
2050 if (net_ratelimit())
2051 printk (KERN_WARNING
2052 "%s: Memory squeeze, dropping packet.\n",
2053 dev->name);
2054 tp->stats.rx_dropped++;
2055 }
2056 received++;
2057
2058 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2059 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2060
2061 rtl8139_isr_ack(tp);
2062 }
2063
2064 if (unlikely(!received || rx_size == 0xfff0))
2065 rtl8139_isr_ack(tp);
2066
2067 #if RTL8139_DEBUG > 1
2068 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2069 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2070 RTL_R16 (RxBufAddr),
2071 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2072 #endif
2073
2074 tp->cur_rx = cur_rx;
2075
2076 /*
2077 * The receive buffer should be mostly empty.
2078 * Tell NAPI to reenable the Rx irq.
2079 */
2080 if (tp->fifo_copy_timeout)
2081 received = budget;
2082
2083 out:
2084 return received;
2085 }
2086
2087
2088 static void rtl8139_weird_interrupt (struct net_device *dev,
2089 struct rtl8139_private *tp,
2090 void *ioaddr,
2091 int status, int link_changed)
2092 {
2093 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2094 dev->name, status);
2095
2096 assert (dev != NULL);
2097 assert (tp != NULL);
2098 assert (ioaddr != NULL);
2099
2100 /* Update the error count. */
2101 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2102 RTL_W32 (RxMissed, 0);
2103
2104 if ((status & RxUnderrun) && link_changed &&
2105 (tp->drv_flags & HAS_LNK_CHNG)) {
2106 rtl_check_media(dev, 0);
2107 status &= ~RxUnderrun;
2108 }
2109
2110 if (status & (RxUnderrun | RxErr))
2111 tp->stats.rx_errors++;
2112
2113 if (status & PCSTimeout)
2114 tp->stats.rx_length_errors++;
2115 if (status & RxUnderrun)
2116 tp->stats.rx_fifo_errors++;
2117 if (status & PCIErr) {
2118 u16 pci_cmd_status;
2119 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2120 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2121
2122 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2123 dev->name, pci_cmd_status);
2124 }
2125 }
2126
2127 static int rtl8139_poll(struct net_device *dev, int *budget)
2128 {
2129 struct rtl8139_private *tp = netdev_priv(dev);
2130 void *ioaddr = tp->mmio_addr;
2131 int orig_budget = min(*budget, dev->quota);
2132 int done = 1;
2133
2134 spin_lock(&tp->rx_lock);
2135 if (likely(RTL_R16(IntrStatus) & RxAckBits)) {
2136 int work_done;
2137
2138 work_done = rtl8139_rx(dev, tp, orig_budget);
2139 if (likely(work_done > 0)) {
2140 *budget -= work_done;
2141 dev->quota -= work_done;
2142 done = (work_done < orig_budget);
2143 }
2144 }
2145
2146 if (done) {
2147 /*
2148 * Order is important since data can get interrupted
2149 * again when we think we are done.
2150 */
2151 local_irq_disable();
2152 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2153 __netif_rx_complete(dev);
2154 local_irq_enable();
2155 }
2156 spin_unlock(&tp->rx_lock);
2157
2158 return !done;
2159 }
2160
2161 /* The interrupt handler does all of the Rx thread work and cleans up
2162 after the Tx thread. */
2163 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
2164 struct pt_regs *regs)
2165 {
2166 struct net_device *dev = (struct net_device *) dev_instance;
2167 struct rtl8139_private *tp = netdev_priv(dev);
2168 void *ioaddr = tp->mmio_addr;
2169 u16 status, ackstat;
2170 int link_changed = 0; /* avoid bogus "uninit" warning */
2171 int handled = 0;
2172
2173 spin_lock (&tp->lock);
2174 status = RTL_R16 (IntrStatus);
2175
2176 /* shared irq? */
2177 if (unlikely((status & rtl8139_intr_mask) == 0))
2178 goto out;
2179
2180 handled = 1;
2181
2182 /* h/w no longer present (hotplug?) or major error, bail */
2183 if (unlikely(status == 0xFFFF))
2184 goto out;
2185
2186 /* close possible race's with dev_close */
2187 if (unlikely(!netif_running(dev))) {
2188 RTL_W16 (IntrMask, 0);
2189 goto out;
2190 }
2191
2192 /* Acknowledge all of the current interrupt sources ASAP, but
2193 an first get an additional status bit from CSCR. */
2194 if (unlikely(status & RxUnderrun))
2195 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2196
2197 ackstat = status & ~(RxAckBits | TxErr);
2198 if (ackstat)
2199 RTL_W16 (IntrStatus, ackstat);
2200
2201 /* Receive packets are processed by poll routine.
2202 If not running start it now. */
2203 if (status & RxAckBits){
2204 if (netif_rx_schedule_prep(dev)) {
2205 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2206 __netif_rx_schedule (dev);
2207 }
2208 }
2209
2210 /* Check uncommon events with one test. */
2211 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2212 rtl8139_weird_interrupt (dev, tp, ioaddr,
2213 status, link_changed);
2214
2215 if (status & (TxOK | TxErr)) {
2216 rtl8139_tx_interrupt (dev, tp, ioaddr);
2217 if (status & TxErr)
2218 RTL_W16 (IntrStatus, TxErr);
2219 }
2220 out:
2221 spin_unlock (&tp->lock);
2222
2223 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2224 dev->name, RTL_R16 (IntrStatus));
2225 return IRQ_RETVAL(handled);
2226 }
2227
2228 #ifdef CONFIG_NET_POLL_CONTROLLER
2229 /*
2230 * Polling receive - used by netconsole and other diagnostic tools
2231 * to allow network i/o with interrupts disabled.
2232 */
2233 static void rtl8139_poll_controller(struct net_device *dev)
2234 {
2235 disable_irq(dev->irq);
2236 rtl8139_interrupt(dev->irq, dev, NULL);
2237 enable_irq(dev->irq);
2238 }
2239 #endif
2240
2241 static int rtl8139_close (struct net_device *dev)
2242 {
2243 struct rtl8139_private *tp = netdev_priv(dev);
2244 void *ioaddr = tp->mmio_addr;
2245 int ret = 0;
2246 unsigned long flags;
2247
2248 netif_stop_queue (dev);
2249
2250 if (tp->thr_pid >= 0) {
2251 tp->time_to_die = 1;
2252 wmb();
2253 ret = kill_proc (tp->thr_pid, SIGTERM, 1);
2254 if (ret) {
2255 printk (KERN_ERR "%s: unable to signal thread\n", dev->name);
2256 return ret;
2257 }
2258 wait_for_completion (&tp->thr_exited);
2259 }
2260
2261 if (netif_msg_ifdown(tp))
2262 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2263 dev->name, RTL_R16 (IntrStatus));
2264
2265 spin_lock_irqsave (&tp->lock, flags);
2266
2267 /* Stop the chip's Tx and Rx DMA processes. */
2268 RTL_W8 (ChipCmd, 0);
2269
2270 /* Disable interrupts by clearing the interrupt mask. */
2271 RTL_W16 (IntrMask, 0);
2272
2273 /* Update the error counts. */
2274 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2275 RTL_W32 (RxMissed, 0);
2276
2277 spin_unlock_irqrestore (&tp->lock, flags);
2278
2279 synchronize_irq (dev->irq); /* racy, but that's ok here */
2280 free_irq (dev->irq, dev);
2281
2282 rtl8139_tx_clear (tp);
2283
2284 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
2285 tp->rx_ring, tp->rx_ring_dma);
2286 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
2287 tp->tx_bufs, tp->tx_bufs_dma);
2288 tp->rx_ring = NULL;
2289 tp->tx_bufs = NULL;
2290
2291 /* Green! Put the chip in low-power mode. */
2292 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2293
2294 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2295 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2296
2297 return 0;
2298 }
2299
2300
2301 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2302 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2303 other threads or interrupts aren't messing with the 8139. */
2304 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2305 {
2306 struct rtl8139_private *np = netdev_priv(dev);
2307 void *ioaddr = np->mmio_addr;
2308
2309 spin_lock_irq(&np->lock);
2310 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2311 u8 cfg3 = RTL_R8 (Config3);
2312 u8 cfg5 = RTL_R8 (Config5);
2313
2314 wol->supported = WAKE_PHY | WAKE_MAGIC
2315 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2316
2317 wol->wolopts = 0;
2318 if (cfg3 & Cfg3_LinkUp)
2319 wol->wolopts |= WAKE_PHY;
2320 if (cfg3 & Cfg3_Magic)
2321 wol->wolopts |= WAKE_MAGIC;
2322 /* (KON)FIXME: See how netdev_set_wol() handles the
2323 following constants. */
2324 if (cfg5 & Cfg5_UWF)
2325 wol->wolopts |= WAKE_UCAST;
2326 if (cfg5 & Cfg5_MWF)
2327 wol->wolopts |= WAKE_MCAST;
2328 if (cfg5 & Cfg5_BWF)
2329 wol->wolopts |= WAKE_BCAST;
2330 }
2331 spin_unlock_irq(&np->lock);
2332 }
2333
2334
2335 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2336 that wol points to kernel memory and other threads or interrupts
2337 aren't messing with the 8139. */
2338 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2339 {
2340 struct rtl8139_private *np = netdev_priv(dev);
2341 void *ioaddr = np->mmio_addr;
2342 u32 support;
2343 u8 cfg3, cfg5;
2344
2345 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2346 ? (WAKE_PHY | WAKE_MAGIC
2347 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2348 : 0);
2349 if (wol->wolopts & ~support)
2350 return -EINVAL;
2351
2352 spin_lock_irq(&np->lock);
2353 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2354 if (wol->wolopts & WAKE_PHY)
2355 cfg3 |= Cfg3_LinkUp;
2356 if (wol->wolopts & WAKE_MAGIC)
2357 cfg3 |= Cfg3_Magic;
2358 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2359 RTL_W8 (Config3, cfg3);
2360 RTL_W8 (Cfg9346, Cfg9346_Lock);
2361
2362 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2363 /* (KON)FIXME: These are untested. We may have to set the
2364 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2365 documentation. */
2366 if (wol->wolopts & WAKE_UCAST)
2367 cfg5 |= Cfg5_UWF;
2368 if (wol->wolopts & WAKE_MCAST)
2369 cfg5 |= Cfg5_MWF;
2370 if (wol->wolopts & WAKE_BCAST)
2371 cfg5 |= Cfg5_BWF;
2372 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2373 spin_unlock_irq(&np->lock);
2374
2375 return 0;
2376 }
2377
2378 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2379 {
2380 struct rtl8139_private *np = netdev_priv(dev);
2381 strcpy(info->driver, DRV_NAME);
2382 strcpy(info->version, DRV_VERSION);
2383 strcpy(info->bus_info, pci_name(np->pci_dev));
2384 info->regdump_len = np->regs_len;
2385 }
2386
2387 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2388 {
2389 struct rtl8139_private *np = netdev_priv(dev);
2390 spin_lock_irq(&np->lock);
2391 mii_ethtool_gset(&np->mii, cmd);
2392 spin_unlock_irq(&np->lock);
2393 return 0;
2394 }
2395
2396 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2397 {
2398 struct rtl8139_private *np = netdev_priv(dev);
2399 int rc;
2400 spin_lock_irq(&np->lock);
2401 rc = mii_ethtool_sset(&np->mii, cmd);
2402 spin_unlock_irq(&np->lock);
2403 return rc;
2404 }
2405
2406 static int rtl8139_nway_reset(struct net_device *dev)
2407 {
2408 struct rtl8139_private *np = netdev_priv(dev);
2409 return mii_nway_restart(&np->mii);
2410 }
2411
2412 static u32 rtl8139_get_link(struct net_device *dev)
2413 {
2414 struct rtl8139_private *np = netdev_priv(dev);
2415 return mii_link_ok(&np->mii);
2416 }
2417
2418 static u32 rtl8139_get_msglevel(struct net_device *dev)
2419 {
2420 struct rtl8139_private *np = netdev_priv(dev);
2421 return np->msg_enable;
2422 }
2423
2424 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2425 {
2426 struct rtl8139_private *np = netdev_priv(dev);
2427 np->msg_enable = datum;
2428 }
2429
2430 /* TODO: we are too slack to do reg dumping for pio, for now */
2431 #ifdef CONFIG_8139TOO_PIO
2432 #define rtl8139_get_regs_len NULL
2433 #define rtl8139_get_regs NULL
2434 #else
2435 static int rtl8139_get_regs_len(struct net_device *dev)
2436 {
2437 struct rtl8139_private *np = netdev_priv(dev);
2438 return np->regs_len;
2439 }
2440
2441 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2442 {
2443 struct rtl8139_private *np = netdev_priv(dev);
2444
2445 regs->version = RTL_REGS_VER;
2446
2447 spin_lock_irq(&np->lock);
2448 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2449 spin_unlock_irq(&np->lock);
2450 }
2451 #endif /* CONFIG_8139TOO_MMIO */
2452
2453 static int rtl8139_get_stats_count(struct net_device *dev)
2454 {
2455 return RTL_NUM_STATS;
2456 }
2457
2458 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2459 {
2460 struct rtl8139_private *np = netdev_priv(dev);
2461
2462 data[0] = np->xstats.early_rx;
2463 data[1] = np->xstats.tx_buf_mapped;
2464 data[2] = np->xstats.tx_timeouts;
2465 data[3] = np->xstats.rx_lost_in_ring;
2466 }
2467
2468 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2469 {
2470 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2471 }
2472
2473 static struct ethtool_ops rtl8139_ethtool_ops = {
2474 .get_drvinfo = rtl8139_get_drvinfo,
2475 .get_settings = rtl8139_get_settings,
2476 .set_settings = rtl8139_set_settings,
2477 .get_regs_len = rtl8139_get_regs_len,
2478 .get_regs = rtl8139_get_regs,
2479 .nway_reset = rtl8139_nway_reset,
2480 .get_link = rtl8139_get_link,
2481 .get_msglevel = rtl8139_get_msglevel,
2482 .set_msglevel = rtl8139_set_msglevel,
2483 .get_wol = rtl8139_get_wol,
2484 .set_wol = rtl8139_set_wol,
2485 .get_strings = rtl8139_get_strings,
2486 .get_stats_count = rtl8139_get_stats_count,
2487 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2488 };
2489
2490 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2491 {
2492 struct rtl8139_private *np = netdev_priv(dev);
2493 int rc;
2494
2495 if (!netif_running(dev))
2496 return -EINVAL;
2497
2498 spin_lock_irq(&np->lock);
2499 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2500 spin_unlock_irq(&np->lock);
2501
2502 return rc;
2503 }
2504
2505
2506 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2507 {
2508 struct rtl8139_private *tp = netdev_priv(dev);
2509 void *ioaddr = tp->mmio_addr;
2510 unsigned long flags;
2511
2512 if (netif_running(dev)) {
2513 spin_lock_irqsave (&tp->lock, flags);
2514 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2515 RTL_W32 (RxMissed, 0);
2516 spin_unlock_irqrestore (&tp->lock, flags);
2517 }
2518
2519 return &tp->stats;
2520 }
2521
2522 /* Set or clear the multicast filter for this adaptor.
2523 This routine is not state sensitive and need not be SMP locked. */
2524
2525 static void __set_rx_mode (struct net_device *dev)
2526 {
2527 struct rtl8139_private *tp = netdev_priv(dev);
2528 void *ioaddr = tp->mmio_addr;
2529 u32 mc_filter[2]; /* Multicast hash filter */
2530 int i, rx_mode;
2531 u32 tmp;
2532
2533 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2534 dev->name, dev->flags, RTL_R32 (RxConfig));
2535
2536 /* Note: do not reorder, GCC is clever about common statements. */
2537 if (dev->flags & IFF_PROMISC) {
2538 /* Unconditionally log net taps. */
2539 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2540 dev->name);
2541 rx_mode =
2542 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2543 AcceptAllPhys;
2544 mc_filter[1] = mc_filter[0] = 0xffffffff;
2545 } else if ((dev->mc_count > multicast_filter_limit)
2546 || (dev->flags & IFF_ALLMULTI)) {
2547 /* Too many to filter perfectly -- accept all multicasts. */
2548 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2549 mc_filter[1] = mc_filter[0] = 0xffffffff;
2550 } else {
2551 struct dev_mc_list *mclist;
2552 rx_mode = AcceptBroadcast | AcceptMyPhys;
2553 mc_filter[1] = mc_filter[0] = 0;
2554 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2555 i++, mclist = mclist->next) {
2556 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2557
2558 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2559 rx_mode |= AcceptMulticast;
2560 }
2561 }
2562
2563 /* We can safely update without stopping the chip. */
2564 tmp = rtl8139_rx_config | rx_mode;
2565 if (tp->rx_config != tmp) {
2566 RTL_W32_F (RxConfig, tmp);
2567 tp->rx_config = tmp;
2568 }
2569 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2570 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2571 }
2572
2573 static void rtl8139_set_rx_mode (struct net_device *dev)
2574 {
2575 unsigned long flags;
2576 struct rtl8139_private *tp = netdev_priv(dev);
2577
2578 spin_lock_irqsave (&tp->lock, flags);
2579 __set_rx_mode(dev);
2580 spin_unlock_irqrestore (&tp->lock, flags);
2581 }
2582
2583 #ifdef CONFIG_PM
2584
2585 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2586 {
2587 struct net_device *dev = pci_get_drvdata (pdev);
2588 struct rtl8139_private *tp = netdev_priv(dev);
2589 void *ioaddr = tp->mmio_addr;
2590 unsigned long flags;
2591
2592 pci_save_state (pdev);
2593
2594 if (!netif_running (dev))
2595 return 0;
2596
2597 netif_device_detach (dev);
2598
2599 spin_lock_irqsave (&tp->lock, flags);
2600
2601 /* Disable interrupts, stop Tx and Rx. */
2602 RTL_W16 (IntrMask, 0);
2603 RTL_W8 (ChipCmd, 0);
2604
2605 /* Update the error counts. */
2606 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2607 RTL_W32 (RxMissed, 0);
2608
2609 spin_unlock_irqrestore (&tp->lock, flags);
2610
2611 pci_set_power_state (pdev, PCI_D3hot);
2612
2613 return 0;
2614 }
2615
2616
2617 static int rtl8139_resume (struct pci_dev *pdev)
2618 {
2619 struct net_device *dev = pci_get_drvdata (pdev);
2620
2621 pci_restore_state (pdev);
2622 if (!netif_running (dev))
2623 return 0;
2624 pci_set_power_state (pdev, PCI_D0);
2625 rtl8139_init_ring (dev);
2626 rtl8139_hw_start (dev);
2627 netif_device_attach (dev);
2628 return 0;
2629 }
2630
2631 #endif /* CONFIG_PM */
2632
2633
2634 static struct pci_driver rtl8139_pci_driver = {
2635 .name = DRV_NAME,
2636 .id_table = rtl8139_pci_tbl,
2637 .probe = rtl8139_init_one,
2638 .remove = __devexit_p(rtl8139_remove_one),
2639 #ifdef CONFIG_PM
2640 .suspend = rtl8139_suspend,
2641 .resume = rtl8139_resume,
2642 #endif /* CONFIG_PM */
2643 };
2644
2645
2646 static int __init rtl8139_init_module (void)
2647 {
2648 /* when we're a module, we always print a version message,
2649 * even if no 8139 board is found.
2650 */
2651 #ifdef MODULE
2652 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2653 #endif
2654
2655 return pci_module_init (&rtl8139_pci_driver);
2656 }
2657
2658
2659 static void __exit rtl8139_cleanup_module (void)
2660 {
2661 pci_unregister_driver (&rtl8139_pci_driver);
2662 }
2663
2664
2665 module_init(rtl8139_init_module);
2666 module_exit(rtl8139_cleanup_module);
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