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[PATCH] aic7xxx_osm build fix
[cris-mirror.git] / drivers / parisc / sba_iommu.c
blob82ea68b55df4f435a35ed1d69f12d7a62f14c132
1 /*
2 ** System Bus Adapter (SBA) I/O MMU manager
3 **
4 ** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>
5 ** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>
6 ** (c) Copyright 2000-2004 Hewlett-Packard Company
7 **
8 ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
9 **
10 ** This program is free software; you can redistribute it and/or modify
11 ** it under the terms of the GNU General Public License as published by
12 ** the Free Software Foundation; either version 2 of the License, or
13 ** (at your option) any later version.
14 **
15 **
16 ** This module initializes the IOC (I/O Controller) found on B1000/C3000/
17 ** J5000/J7000/N-class/L-class machines and their successors.
18 **
19 ** FIXME: add DMA hint support programming in both sba and lba modules.
20 */
21
22 #include <linux/config.h>
23 #include <linux/types.h>
24 #include <linux/kernel.h>
25 #include <linux/spinlock.h>
26 #include <linux/slab.h>
27 #include <linux/init.h>
28
29 #include <linux/mm.h>
30 #include <linux/string.h>
31 #include <linux/pci.h>
32
33 #include <asm/byteorder.h>
34 #include <asm/io.h>
35 #include <asm/dma.h> /* for DMA_CHUNK_SIZE */
36
37 #include <asm/hardware.h> /* for register_parisc_driver() stuff */
38
39 #include <linux/proc_fs.h>
40 #include <asm/runway.h> /* for proc_runway_root */
41 #include <asm/pdc.h> /* for PDC_MODEL_* */
42 #include <asm/pdcpat.h> /* for is_pdc_pat() */
43 #include <asm/parisc-device.h>
44
45
46 /* declared in arch/parisc/kernel/setup.c */
47 extern struct proc_dir_entry * proc_mckinley_root;
48
49 #define MODULE_NAME "SBA"
50
51 #ifdef CONFIG_PROC_FS
52 /* depends on proc fs support. But costs CPU performance */
53 #undef SBA_COLLECT_STATS
54 #endif
55
56 /*
57 ** The number of debug flags is a clue - this code is fragile.
58 ** Don't even think about messing with it unless you have
59 ** plenty of 710's to sacrifice to the computer gods. :^)
60 */
61 #undef DEBUG_SBA_INIT
62 #undef DEBUG_SBA_RUN
63 #undef DEBUG_SBA_RUN_SG
64 #undef DEBUG_SBA_RESOURCE
65 #undef ASSERT_PDIR_SANITY
66 #undef DEBUG_LARGE_SG_ENTRIES
67 #undef DEBUG_DMB_TRAP
68
69 #ifdef DEBUG_SBA_INIT
70 #define DBG_INIT(x...) printk(x)
71 #else
72 #define DBG_INIT(x...)
73 #endif
74
75 #ifdef DEBUG_SBA_RUN
76 #define DBG_RUN(x...) printk(x)
77 #else
78 #define DBG_RUN(x...)
79 #endif
80
81 #ifdef DEBUG_SBA_RUN_SG
82 #define DBG_RUN_SG(x...) printk(x)
83 #else
84 #define DBG_RUN_SG(x...)
85 #endif
86
87
88 #ifdef DEBUG_SBA_RESOURCE
89 #define DBG_RES(x...) printk(x)
90 #else
91 #define DBG_RES(x...)
92 #endif
93
94 #if defined(__LP64__) && !defined(CONFIG_PDC_NARROW)
95 /* "low end" PA8800 machines use ZX1 chipset */
96 #define ZX1_SUPPORT
97 #endif
98
99 #define SBA_INLINE __inline__
100
101
102 /*
103 ** The number of pdir entries to "free" before issueing
104 ** a read to PCOM register to flush out PCOM writes.
105 ** Interacts with allocation granularity (ie 4 or 8 entries
106 ** allocated and free'd/purged at a time might make this
107 ** less interesting).
108 */
109 #define DELAYED_RESOURCE_CNT 16
110
111 #define DEFAULT_DMA_HINT_REG 0
112
113 #define ASTRO_RUNWAY_PORT 0x582
114 #define IKE_MERCED_PORT 0x803
115 #define REO_MERCED_PORT 0x804
116 #define REOG_MERCED_PORT 0x805
117 #define PLUTO_MCKINLEY_PORT 0x880
118
119 #define SBA_FUNC_ID 0x0000 /* function id */
120 #define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */
121
122 #define IS_ASTRO(id) ((id)->hversion == ASTRO_RUNWAY_PORT)
123 #define IS_IKE(id) ((id)->hversion == IKE_MERCED_PORT)
124 #define IS_PLUTO(id) ((id)->hversion == PLUTO_MCKINLEY_PORT)
125
126 #define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */
127
128 #define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE)
129 #define PLUTO_IOC_OFFSET (1 * SBA_FUNC_SIZE)
130 /* Ike's IOC's occupy functions 2 and 3 */
131 #define IKE_IOC_OFFSET(p) ((p+2) * SBA_FUNC_SIZE)
132
133 #define IOC_CTRL 0x8 /* IOC_CTRL offset */
134 #define IOC_CTRL_TC (1 << 0) /* TOC Enable */
135 #define IOC_CTRL_CE (1 << 1) /* Coalesce Enable */
136 #define IOC_CTRL_DE (1 << 2) /* Dillon Enable */
137 #define IOC_CTRL_RM (1 << 8) /* Real Mode */
138 #define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */
139 #define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */
140 #define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */
141
142 #define MAX_IOC 2 /* per Ike. Pluto/Astro only have 1. */
143
144 #define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */
145
146
147 /*
148 ** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
149 ** Firmware programs this stuff. Don't touch it.
150 */
151 #define LMMIO_DIRECT0_BASE 0x300
152 #define LMMIO_DIRECT0_MASK 0x308
153 #define LMMIO_DIRECT0_ROUTE 0x310
154
155 #define LMMIO_DIST_BASE 0x360
156 #define LMMIO_DIST_MASK 0x368
157 #define LMMIO_DIST_ROUTE 0x370
158
159 #define IOS_DIST_BASE 0x390
160 #define IOS_DIST_MASK 0x398
161 #define IOS_DIST_ROUTE 0x3A0
162
163 #define IOS_DIRECT_BASE 0x3C0
164 #define IOS_DIRECT_MASK 0x3C8
165 #define IOS_DIRECT_ROUTE 0x3D0
166
167 /*
168 ** Offsets into I/O TLB (Function 2 and 3 on Ike)
169 */
170 #define ROPE0_CTL 0x200 /* "regbus pci0" */
171 #define ROPE1_CTL 0x208
172 #define ROPE2_CTL 0x210
173 #define ROPE3_CTL 0x218
174 #define ROPE4_CTL 0x220
175 #define ROPE5_CTL 0x228
176 #define ROPE6_CTL 0x230
177 #define ROPE7_CTL 0x238
178
179 #define HF_ENABLE 0x40
180
181
182 #define IOC_IBASE 0x300 /* IO TLB */
183 #define IOC_IMASK 0x308
184 #define IOC_PCOM 0x310
185 #define IOC_TCNFG 0x318
186 #define IOC_PDIR_BASE 0x320
187
188 /* AGP GART driver looks for this */
189 #define SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL
190
191
192 /*
193 ** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
194 ** It's safer (avoid memory corruption) to keep DMA page mappings
195 ** equivalently sized to VM PAGE_SIZE.
196 **
197 ** We really can't avoid generating a new mapping for each
198 ** page since the Virtual Coherence Index has to be generated
199 ** and updated for each page.
200 **
201 ** PAGE_SIZE could be greater than IOVP_SIZE. But not the inverse.
202 */
203 #define IOVP_SIZE PAGE_SIZE
204 #define IOVP_SHIFT PAGE_SHIFT
205 #define IOVP_MASK PAGE_MASK
206
207 #define SBA_PERF_CFG 0x708 /* Performance Counter stuff */
208 #define SBA_PERF_MASK1 0x718
209 #define SBA_PERF_MASK2 0x730
210
211
212 /*
213 ** Offsets into PCI Performance Counters (functions 12 and 13)
214 ** Controlled by PERF registers in function 2 & 3 respectively.
215 */
216 #define SBA_PERF_CNT1 0x200
217 #define SBA_PERF_CNT2 0x208
218 #define SBA_PERF_CNT3 0x210
219
220
221 struct ioc {
222 void __iomem *ioc_hpa; /* I/O MMU base address */
223 char *res_map; /* resource map, bit == pdir entry */
224 u64 *pdir_base; /* physical base address */
225 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
226 unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
227 #ifdef ZX1_SUPPORT
228 unsigned long iovp_mask; /* help convert IOVA to IOVP */
229 #endif
230 unsigned long *res_hint; /* next avail IOVP - circular search */
231 spinlock_t res_lock;
232 unsigned int res_bitshift; /* from the LEFT! */
233 unsigned int res_size; /* size of resource map in bytes */
234 #if SBA_HINT_SUPPORT
235 /* FIXME : DMA HINTs not used */
236 unsigned long hint_mask_pdir; /* bits used for DMA hints */
237 unsigned int hint_shift_pdir;
238 #endif
239 #if DELAYED_RESOURCE_CNT > 0
240 int saved_cnt;
241 struct sba_dma_pair {
242 dma_addr_t iova;
243 size_t size;
244 } saved[DELAYED_RESOURCE_CNT];
245 #endif
246
247 #ifdef SBA_COLLECT_STATS
248 #define SBA_SEARCH_SAMPLE 0x100
249 unsigned long avg_search[SBA_SEARCH_SAMPLE];
250 unsigned long avg_idx; /* current index into avg_search */
251 unsigned long used_pages;
252 unsigned long msingle_calls;
253 unsigned long msingle_pages;
254 unsigned long msg_calls;
255 unsigned long msg_pages;
256 unsigned long usingle_calls;
257 unsigned long usingle_pages;
258 unsigned long usg_calls;
259 unsigned long usg_pages;
260 #endif
261
262 /* STUFF We don't need in performance path */
263 unsigned int pdir_size; /* in bytes, determined by IOV Space size */
264 };
265
266 struct sba_device {
267 struct sba_device *next; /* list of SBA's in system */
268 struct parisc_device *dev; /* dev found in bus walk */
269 struct parisc_device_id *iodc; /* data about dev from firmware */
270 const char *name;
271 void __iomem *sba_hpa; /* base address */
272 spinlock_t sba_lock;
273 unsigned int flags; /* state/functionality enabled */
274 unsigned int hw_rev; /* HW revision of chip */
275
276 struct resource chip_resv; /* MMIO reserved for chip */
277 struct resource iommu_resv; /* MMIO reserved for iommu */
278
279 unsigned int num_ioc; /* number of on-board IOC's */
280 struct ioc ioc[MAX_IOC];
281 };
282
283
284 static struct sba_device *sba_list;
285
286 static unsigned long ioc_needs_fdc = 0;
287
288 /* global count of IOMMUs in the system */
289 static unsigned int global_ioc_cnt = 0;
290
291 /* PA8700 (Piranha 2.2) bug workaround */
292 static unsigned long piranha_bad_128k = 0;
293
294 /* Looks nice and keeps the compiler happy */
295 #define SBA_DEV(d) ((struct sba_device *) (d))
296
297 #if SBA_AGP_SUPPORT
298 static int reserve_sba_gart = 1;
299 #endif
300
301 #define ROUNDUP(x,y) ((x + ((y)-1)) & ~((y)-1))
302
303
304 /************************************
305 ** SBA register read and write support
306 **
307 ** BE WARNED: register writes are posted.
308 ** (ie follow writes which must reach HW with a read)
309 **
310 ** Superdome (in particular, REO) allows only 64-bit CSR accesses.
311 */
312 #define READ_REG32(addr) le32_to_cpu(__raw_readl(addr))
313 #define READ_REG64(addr) le64_to_cpu(__raw_readq(addr))
314 #define WRITE_REG32(val, addr) __raw_writel(cpu_to_le32(val), addr)
315 #define WRITE_REG64(val, addr) __raw_writeq(cpu_to_le64(val), addr)
316
317 #ifdef __LP64__
318 #define READ_REG(addr) READ_REG64(addr)
319 #define WRITE_REG(value, addr) WRITE_REG64(value, addr)
320 #else
321 #define READ_REG(addr) READ_REG32(addr)
322 #define WRITE_REG(value, addr) WRITE_REG32(value, addr)
323 #endif
324
325 #ifdef DEBUG_SBA_INIT
326
327 /* NOTE: When __LP64__ isn't defined, READ_REG64() is two 32-bit reads */
328
329 /**
330 * sba_dump_ranges - debugging only - print ranges assigned to this IOA
331 * @hpa: base address of the sba
332 *
333 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO
334 * IO Adapter (aka Bus Converter).
335 */
336 static void
337 sba_dump_ranges(void __iomem *hpa)
338 {
339 DBG_INIT("SBA at 0x%p\n", hpa);
340 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
341 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
342 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
343 DBG_INIT("\n");
344 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE));
345 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK));
346 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE));
347 }
348
349 /**
350 * sba_dump_tlb - debugging only - print IOMMU operating parameters
351 * @hpa: base address of the IOMMU
352 *
353 * Print the size/location of the IO MMU PDIR.
354 */
355 static void sba_dump_tlb(void __iomem *hpa)
356 {
357 DBG_INIT("IO TLB at 0x%p\n", hpa);
358 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE));
359 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK));
360 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG));
361 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
362 DBG_INIT("\n");
363 }
364 #else
365 #define sba_dump_ranges(x)
366 #define sba_dump_tlb(x)
367 #endif
368
369
370 #ifdef ASSERT_PDIR_SANITY
371
372 /**
373 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
374 * @ioc: IO MMU structure which owns the pdir we are interested in.
375 * @msg: text to print ont the output line.
376 * @pide: pdir index.
377 *
378 * Print one entry of the IO MMU PDIR in human readable form.
379 */
380 static void
381 sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
382 {
383 /* start printing from lowest pde in rval */
384 u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]);
385 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]);
386 uint rcnt;
387
388 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
389 msg,
390 rptr, pide & (BITS_PER_LONG - 1), *rptr);
391
392 rcnt = 0;
393 while (rcnt < BITS_PER_LONG) {
394 printk(KERN_DEBUG "%s %2d %p %016Lx\n",
395 (rcnt == (pide & (BITS_PER_LONG - 1)))
396 ? " -->" : " ",
397 rcnt, ptr, *ptr );
398 rcnt++;
399 ptr++;
400 }
401 printk(KERN_DEBUG "%s", msg);
402 }
403
404
405 /**
406 * sba_check_pdir - debugging only - consistency checker
407 * @ioc: IO MMU structure which owns the pdir we are interested in.
408 * @msg: text to print ont the output line.
409 *
410 * Verify the resource map and pdir state is consistent
411 */
412 static int
413 sba_check_pdir(struct ioc *ioc, char *msg)
414 {
415 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]);
416 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */
417 u64 *pptr = ioc->pdir_base; /* pdir ptr */
418 uint pide = 0;
419
420 while (rptr < rptr_end) {
421 u32 rval = *rptr;
422 int rcnt = 32; /* number of bits we might check */
423
424 while (rcnt) {
425 /* Get last byte and highest bit from that */
426 u32 pde = ((u32) (((char *)pptr)[7])) << 24;
427 if ((rval ^ pde) & 0x80000000)
428 {
429 /*
430 ** BUMMER! -- res_map != pdir --
431 ** Dump rval and matching pdir entries
432 */
433 sba_dump_pdir_entry(ioc, msg, pide);
434 return(1);
435 }
436 rcnt--;
437 rval <<= 1; /* try the next bit */
438 pptr++;
439 pide++;
440 }
441 rptr++; /* look at next word of res_map */
442 }
443 /* It'd be nice if we always got here :^) */
444 return 0;
445 }
446
447
448 /**
449 * sba_dump_sg - debugging only - print Scatter-Gather list
450 * @ioc: IO MMU structure which owns the pdir we are interested in.
451 * @startsg: head of the SG list
452 * @nents: number of entries in SG list
453 *
454 * print the SG list so we can verify it's correct by hand.
455 */
456 static void
457 sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
458 {
459 while (nents-- > 0) {
460 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n",
461 nents,
462 (unsigned long) sg_dma_address(startsg),
463 sg_dma_len(startsg),
464 sg_virt_addr(startsg), startsg->length);
465 startsg++;
466 }
467 }
468
469 #endif /* ASSERT_PDIR_SANITY */
470
471
472
473
474 /**************************************************************
475 *
476 * I/O Pdir Resource Management
477 *
478 * Bits set in the resource map are in use.
479 * Each bit can represent a number of pages.
480 * LSbs represent lower addresses (IOVA's).
481 *
482 ***************************************************************/
483 #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
484
485 /* Convert from IOVP to IOVA and vice versa. */
486
487 #ifdef ZX1_SUPPORT
488 /* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */
489 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset))
490 #define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask)
491 #else
492 /* only support Astro and ancestors. Saves a few cycles in key places */
493 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset))
494 #define SBA_IOVP(ioc,iova) (iova)
495 #endif
496
497 #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
498
499 #define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n)))
500 #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
501
502
503 /**
504 * sba_search_bitmap - find free space in IO PDIR resource bitmap
505 * @ioc: IO MMU structure which owns the pdir we are interested in.
506 * @bits_wanted: number of entries we need.
507 *
508 * Find consecutive free bits in resource bitmap.
509 * Each bit represents one entry in the IO Pdir.
510 * Cool perf optimization: search for log2(size) bits at a time.
511 */
512 static SBA_INLINE unsigned long
513 sba_search_bitmap(struct ioc *ioc, unsigned long bits_wanted)
514 {
515 unsigned long *res_ptr = ioc->res_hint;
516 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
517 unsigned long pide = ~0UL;
518
519 if (bits_wanted > (BITS_PER_LONG/2)) {
520 /* Search word at a time - no mask needed */
521 for(; res_ptr < res_end; ++res_ptr) {
522 if (*res_ptr == 0) {
523 *res_ptr = RESMAP_MASK(bits_wanted);
524 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
525 pide <<= 3; /* convert to bit address */
526 break;
527 }
528 }
529 /* point to the next word on next pass */
530 res_ptr++;
531 ioc->res_bitshift = 0;
532 } else {
533 /*
534 ** Search the resource bit map on well-aligned values.
535 ** "o" is the alignment.
536 ** We need the alignment to invalidate I/O TLB using
537 ** SBA HW features in the unmap path.
538 */
539 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT);
540 uint bitshiftcnt = ROUNDUP(ioc->res_bitshift, o);
541 unsigned long mask;
542
543 if (bitshiftcnt >= BITS_PER_LONG) {
544 bitshiftcnt = 0;
545 res_ptr++;
546 }
547 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt;
548
549 DBG_RES("%s() o %ld %p", __FUNCTION__, o, res_ptr);
550 while(res_ptr < res_end)
551 {
552 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
553 WARN_ON(mask == 0);
554 if(((*res_ptr) & mask) == 0) {
555 *res_ptr |= mask; /* mark resources busy! */
556 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
557 pide <<= 3; /* convert to bit address */
558 pide += bitshiftcnt;
559 break;
560 }
561 mask >>= o;
562 bitshiftcnt += o;
563 if (mask == 0) {
564 mask = RESMAP_MASK(bits_wanted);
565 bitshiftcnt=0;
566 res_ptr++;
567 }
568 }
569 /* look in the same word on the next pass */
570 ioc->res_bitshift = bitshiftcnt + bits_wanted;
571 }
572
573 /* wrapped ? */
574 if (res_end <= res_ptr) {
575 ioc->res_hint = (unsigned long *) ioc->res_map;
576 ioc->res_bitshift = 0;
577 } else {
578 ioc->res_hint = res_ptr;
579 }
580 return (pide);
581 }
582
583
584 /**
585 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
586 * @ioc: IO MMU structure which owns the pdir we are interested in.
587 * @size: number of bytes to create a mapping for
588 *
589 * Given a size, find consecutive unmarked and then mark those bits in the
590 * resource bit map.
591 */
592 static int
593 sba_alloc_range(struct ioc *ioc, size_t size)
594 {
595 unsigned int pages_needed = size >> IOVP_SHIFT;
596 #ifdef SBA_COLLECT_STATS
597 unsigned long cr_start = mfctl(16);
598 #endif
599 unsigned long pide;
600
601 pide = sba_search_bitmap(ioc, pages_needed);
602 if (pide >= (ioc->res_size << 3)) {
603 pide = sba_search_bitmap(ioc, pages_needed);
604 if (pide >= (ioc->res_size << 3))
605 panic("%s: I/O MMU @ %p is out of mapping resources\n",
606 __FILE__, ioc->ioc_hpa);
607 }
608
609 #ifdef ASSERT_PDIR_SANITY
610 /* verify the first enable bit is clear */
611 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) {
612 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
613 }
614 #endif
615
616 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
617 __FUNCTION__, size, pages_needed, pide,
618 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
619 ioc->res_bitshift );
620
621 #ifdef SBA_COLLECT_STATS
622 {
623 unsigned long cr_end = mfctl(16);
624 unsigned long tmp = cr_end - cr_start;
625 /* check for roll over */
626 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
627 }
628 ioc->avg_search[ioc->avg_idx++] = cr_start;
629 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
630
631 ioc->used_pages += pages_needed;
632 #endif
633
634 return (pide);
635 }
636
637
638 /**
639 * sba_free_range - unmark bits in IO PDIR resource bitmap
640 * @ioc: IO MMU structure which owns the pdir we are interested in.
641 * @iova: IO virtual address which was previously allocated.
642 * @size: number of bytes to create a mapping for
643 *
644 * clear bits in the ioc's resource map
645 */
646 static SBA_INLINE void
647 sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
648 {
649 unsigned long iovp = SBA_IOVP(ioc, iova);
650 unsigned int pide = PDIR_INDEX(iovp);
651 unsigned int ridx = pide >> 3; /* convert bit to byte address */
652 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
653
654 int bits_not_wanted = size >> IOVP_SHIFT;
655
656 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
657 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1));
658
659 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n",
660 __FUNCTION__, (uint) iova, size,
661 bits_not_wanted, m, pide, res_ptr, *res_ptr);
662
663 #ifdef SBA_COLLECT_STATS
664 ioc->used_pages -= bits_not_wanted;
665 #endif
666
667 *res_ptr &= ~m;
668 }
669
670
671 /**************************************************************
672 *
673 * "Dynamic DMA Mapping" support (aka "Coherent I/O")
674 *
675 ***************************************************************/
676
677 #if SBA_HINT_SUPPORT
678 #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
679 #endif
680
681 typedef unsigned long space_t;
682 #define KERNEL_SPACE 0
683
684 /**
685 * sba_io_pdir_entry - fill in one IO PDIR entry
686 * @pdir_ptr: pointer to IO PDIR entry
687 * @sid: process Space ID - currently only support KERNEL_SPACE
688 * @vba: Virtual CPU address of buffer to map
689 * @hint: DMA hint set to use for this mapping
690 *
691 * SBA Mapping Routine
692 *
693 * Given a virtual address (vba, arg2) and space id, (sid, arg1)
694 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by
695 * pdir_ptr (arg0).
696 * Using the bass-ackwards HP bit numbering, Each IO Pdir entry
697 * for Astro/Ike looks like:
698 *
699 *
700 * 0 19 51 55 63
701 * +-+---------------------+----------------------------------+----+--------+
702 * |V| U | PPN[43:12] | U | VI |
703 * +-+---------------------+----------------------------------+----+--------+
704 *
705 * Pluto is basically identical, supports fewer physical address bits:
706 *
707 * 0 23 51 55 63
708 * +-+------------------------+-------------------------------+----+--------+
709 * |V| U | PPN[39:12] | U | VI |
710 * +-+------------------------+-------------------------------+----+--------+
711 *
712 * V == Valid Bit (Most Significant Bit is bit 0)
713 * U == Unused
714 * PPN == Physical Page Number
715 * VI == Virtual Index (aka Coherent Index)
716 *
717 * LPA instruction output is put into PPN field.
718 * LCI (Load Coherence Index) instruction provides the "VI" bits.
719 *
720 * We pre-swap the bytes since PCX-W is Big Endian and the
721 * IOMMU uses little endian for the pdir.
722 */
723
724 void SBA_INLINE
725 sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
726 unsigned long hint)
727 {
728 u64 pa; /* physical address */
729 register unsigned ci; /* coherent index */
730
731 pa = virt_to_phys(vba);
732 pa &= IOVP_MASK;
733
734 mtsp(sid,1);
735 asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba));
736 pa |= (ci >> 12) & 0xff; /* move CI (8 bits) into lowest byte */
737
738 pa |= 0x8000000000000000ULL; /* set "valid" bit */
739 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */
740
741 /*
742 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
743 * (bit #61, big endian), we have to flush and sync every time
744 * IO-PDIR is changed in Ike/Astro.
745 */
746 if (ioc_needs_fdc) {
747 asm volatile("fdc 0(%%sr1,%0)\n\tsync" : : "r" (pdir_ptr));
748 }
749 }
750
751
752 /**
753 * sba_mark_invalid - invalidate one or more IO PDIR entries
754 * @ioc: IO MMU structure which owns the pdir we are interested in.
755 * @iova: IO Virtual Address mapped earlier
756 * @byte_cnt: number of bytes this mapping covers.
757 *
758 * Marking the IO PDIR entry(ies) as Invalid and invalidate
759 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register)
760 * is to purge stale entries in the IO TLB when unmapping entries.
761 *
762 * The PCOM register supports purging of multiple pages, with a minium
763 * of 1 page and a maximum of 2GB. Hardware requires the address be
764 * aligned to the size of the range being purged. The size of the range
765 * must be a power of 2. The "Cool perf optimization" in the
766 * allocation routine helps keep that true.
767 */
768 static SBA_INLINE void
769 sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
770 {
771 u32 iovp = (u32) SBA_IOVP(ioc,iova);
772
773 /* Even though this is a big-endian machine, the entries
774 ** in the iopdir are little endian. That's why we clear the byte
775 ** at +7 instead of at +0.
776 */
777 int off = PDIR_INDEX(iovp)*sizeof(u64)+7;
778
779 #ifdef ASSERT_PDIR_SANITY
780 /* Assert first pdir entry is set */
781 if (0x80 != (((u8 *) ioc->pdir_base)[off])) {
782 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
783 }
784 #endif
785
786 if (byte_cnt <= IOVP_SIZE)
787 {
788 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
789
790 /*
791 ** clear I/O PDIR entry "valid" bit
792 ** Do NOT clear the rest - save it for debugging.
793 ** We should only clear bits that have previously
794 ** been enabled.
795 */
796 ((u8 *)(ioc->pdir_base))[off] = 0;
797 } else {
798 u32 t = get_order(byte_cnt) + PAGE_SHIFT;
799
800 iovp |= t;
801 do {
802 /* clear I/O Pdir entry "valid" bit first */
803 ((u8 *)(ioc->pdir_base))[off] = 0;
804 off += sizeof(u64);
805 byte_cnt -= IOVP_SIZE;
806 } while (byte_cnt > 0);
807 }
808
809 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);
810 }
811
812 /**
813 * sba_dma_supported - PCI driver can query DMA support
814 * @dev: instance of PCI owned by the driver that's asking
815 * @mask: number of address bits this PCI device can handle
816 *
817 * See Documentation/DMA-mapping.txt
818 */
819 static int sba_dma_supported( struct device *dev, u64 mask)
820 {
821 struct ioc *ioc;
822 if (dev == NULL) {
823 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
824 BUG();
825 return(0);
826 }
827
828 ioc = GET_IOC(dev);
829
830 /* check if mask is > than the largest IO Virt Address */
831
832 return((int) (mask >= (ioc->ibase +
833 (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
834 }
835
836
837 /**
838 * sba_map_single - map one buffer and return IOVA for DMA
839 * @dev: instance of PCI owned by the driver that's asking.
840 * @addr: driver buffer to map.
841 * @size: number of bytes to map in driver buffer.
842 * @direction: R/W or both.
843 *
844 * See Documentation/DMA-mapping.txt
845 */
846 static dma_addr_t
847 sba_map_single(struct device *dev, void *addr, size_t size,
848 enum dma_data_direction direction)
849 {
850 struct ioc *ioc;
851 unsigned long flags;
852 dma_addr_t iovp;
853 dma_addr_t offset;
854 u64 *pdir_start;
855 int pide;
856
857 ioc = GET_IOC(dev);
858
859 /* save offset bits */
860 offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
861
862 /* round up to nearest IOVP_SIZE */
863 size = (size + offset + ~IOVP_MASK) & IOVP_MASK;
864
865 spin_lock_irqsave(&ioc->res_lock, flags);
866 #ifdef ASSERT_PDIR_SANITY
867 sba_check_pdir(ioc,"Check before sba_map_single()");
868 #endif
869
870 #ifdef SBA_COLLECT_STATS
871 ioc->msingle_calls++;
872 ioc->msingle_pages += size >> IOVP_SHIFT;
873 #endif
874 pide = sba_alloc_range(ioc, size);
875 iovp = (dma_addr_t) pide << IOVP_SHIFT;
876
877 DBG_RUN("%s() 0x%p -> 0x%lx\n",
878 __FUNCTION__, addr, (long) iovp | offset);
879
880 pdir_start = &(ioc->pdir_base[pide]);
881
882 while (size > 0) {
883 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
884
885 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
886 pdir_start,
887 (u8) (((u8 *) pdir_start)[7]),
888 (u8) (((u8 *) pdir_start)[6]),
889 (u8) (((u8 *) pdir_start)[5]),
890 (u8) (((u8 *) pdir_start)[4]),
891 (u8) (((u8 *) pdir_start)[3]),
892 (u8) (((u8 *) pdir_start)[2]),
893 (u8) (((u8 *) pdir_start)[1]),
894 (u8) (((u8 *) pdir_start)[0])
895 );
896
897 addr += IOVP_SIZE;
898 size -= IOVP_SIZE;
899 pdir_start++;
900 }
901 /* form complete address */
902 #ifdef ASSERT_PDIR_SANITY
903 sba_check_pdir(ioc,"Check after sba_map_single()");
904 #endif
905 spin_unlock_irqrestore(&ioc->res_lock, flags);
906 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
907 }
908
909
910 /**
911 * sba_unmap_single - unmap one IOVA and free resources
912 * @dev: instance of PCI owned by the driver that's asking.
913 * @iova: IOVA of driver buffer previously mapped.
914 * @size: number of bytes mapped in driver buffer.
915 * @direction: R/W or both.
916 *
917 * See Documentation/DMA-mapping.txt
918 */
919 static void
920 sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size,
921 enum dma_data_direction direction)
922 {
923 struct ioc *ioc;
924 #if DELAYED_RESOURCE_CNT > 0
925 struct sba_dma_pair *d;
926 #endif
927 unsigned long flags;
928 dma_addr_t offset;
929
930 DBG_RUN("%s() iovp 0x%lx/%x\n", __FUNCTION__, (long) iova, size);
931
932 ioc = GET_IOC(dev);
933 offset = iova & ~IOVP_MASK;
934 iova ^= offset; /* clear offset bits */
935 size += offset;
936 size = ROUNDUP(size, IOVP_SIZE);
937
938 spin_lock_irqsave(&ioc->res_lock, flags);
939
940 #ifdef SBA_COLLECT_STATS
941 ioc->usingle_calls++;
942 ioc->usingle_pages += size >> IOVP_SHIFT;
943 #endif
944
945 sba_mark_invalid(ioc, iova, size);
946
947 #if DELAYED_RESOURCE_CNT > 0
948 /* Delaying when we re-use a IO Pdir entry reduces the number
949 * of MMIO reads needed to flush writes to the PCOM register.
950 */
951 d = &(ioc->saved[ioc->saved_cnt]);
952 d->iova = iova;
953 d->size = size;
954 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
955 int cnt = ioc->saved_cnt;
956 while (cnt--) {
957 sba_free_range(ioc, d->iova, d->size);
958 d--;
959 }
960 ioc->saved_cnt = 0;
961 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
962 }
963 #else /* DELAYED_RESOURCE_CNT == 0 */
964 sba_free_range(ioc, iova, size);
965 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
966 #endif /* DELAYED_RESOURCE_CNT == 0 */
967 spin_unlock_irqrestore(&ioc->res_lock, flags);
968
969 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
970 ** For Astro based systems this isn't a big deal WRT performance.
971 ** As long as 2.4 kernels copyin/copyout data from/to userspace,
972 ** we don't need the syncdma. The issue here is I/O MMU cachelines
973 ** are *not* coherent in all cases. May be hwrev dependent.
974 ** Need to investigate more.
975 asm volatile("syncdma");
976 */
977 }
978
979
980 /**
981 * sba_alloc_consistent - allocate/map shared mem for DMA
982 * @hwdev: instance of PCI owned by the driver that's asking.
983 * @size: number of bytes mapped in driver buffer.
984 * @dma_handle: IOVA of new buffer.
985 *
986 * See Documentation/DMA-mapping.txt
987 */
988 static void *sba_alloc_consistent(struct device *hwdev, size_t size,
989 dma_addr_t *dma_handle, int gfp)
990 {
991 void *ret;
992
993 if (!hwdev) {
994 /* only support PCI */
995 *dma_handle = 0;
996 return 0;
997 }
998
999 ret = (void *) __get_free_pages(gfp, get_order(size));
1000
1001 if (ret) {
1002 memset(ret, 0, size);
1003 *dma_handle = sba_map_single(hwdev, ret, size, 0);
1004 }
1005
1006 return ret;
1007 }
1008
1009
1010 /**
1011 * sba_free_consistent - free/unmap shared mem for DMA
1012 * @hwdev: instance of PCI owned by the driver that's asking.
1013 * @size: number of bytes mapped in driver buffer.
1014 * @vaddr: virtual address IOVA of "consistent" buffer.
1015 * @dma_handler: IO virtual address of "consistent" buffer.
1016 *
1017 * See Documentation/DMA-mapping.txt
1018 */
1019 static void
1020 sba_free_consistent(struct device *hwdev, size_t size, void *vaddr,
1021 dma_addr_t dma_handle)
1022 {
1023 sba_unmap_single(hwdev, dma_handle, size, 0);
1024 free_pages((unsigned long) vaddr, get_order(size));
1025 }
1026
1027
1028 /*
1029 ** Since 0 is a valid pdir_base index value, can't use that
1030 ** to determine if a value is valid or not. Use a flag to indicate
1031 ** the SG list entry contains a valid pdir index.
1032 */
1033 #define PIDE_FLAG 0x80000000UL
1034
1035 #ifdef SBA_COLLECT_STATS
1036 #define IOMMU_MAP_STATS
1037 #endif
1038 #include "iommu-helpers.h"
1039
1040 #ifdef DEBUG_LARGE_SG_ENTRIES
1041 int dump_run_sg = 0;
1042 #endif
1043
1044
1045 /**
1046 * sba_map_sg - map Scatter/Gather list
1047 * @dev: instance of PCI owned by the driver that's asking.
1048 * @sglist: array of buffer/length pairs
1049 * @nents: number of entries in list
1050 * @direction: R/W or both.
1051 *
1052 * See Documentation/DMA-mapping.txt
1053 */
1054 static int
1055 sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
1056 enum dma_data_direction direction)
1057 {
1058 struct ioc *ioc;
1059 int coalesced, filled = 0;
1060 unsigned long flags;
1061
1062 DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents);
1063
1064 ioc = GET_IOC(dev);
1065
1066 /* Fast path single entry scatterlists. */
1067 if (nents == 1) {
1068 sg_dma_address(sglist) = sba_map_single(dev,
1069 (void *)sg_virt_addr(sglist),
1070 sglist->length, direction);
1071 sg_dma_len(sglist) = sglist->length;
1072 return 1;
1073 }
1074
1075 spin_lock_irqsave(&ioc->res_lock, flags);
1076
1077 #ifdef ASSERT_PDIR_SANITY
1078 if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
1079 {
1080 sba_dump_sg(ioc, sglist, nents);
1081 panic("Check before sba_map_sg()");
1082 }
1083 #endif
1084
1085 #ifdef SBA_COLLECT_STATS
1086 ioc->msg_calls++;
1087 #endif
1088
1089 /*
1090 ** First coalesce the chunks and allocate I/O pdir space
1091 **
1092 ** If this is one DMA stream, we can properly map using the
1093 ** correct virtual address associated with each DMA page.
1094 ** w/o this association, we wouldn't have coherent DMA!
1095 ** Access to the virtual address is what forces a two pass algorithm.
1096 */
1097 coalesced = iommu_coalesce_chunks(ioc, sglist, nents, sba_alloc_range);
1098
1099 /*
1100 ** Program the I/O Pdir
1101 **
1102 ** map the virtual addresses to the I/O Pdir
1103 ** o dma_address will contain the pdir index
1104 ** o dma_len will contain the number of bytes to map
1105 ** o address contains the virtual address.
1106 */
1107 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry);
1108
1109 #ifdef ASSERT_PDIR_SANITY
1110 if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
1111 {
1112 sba_dump_sg(ioc, sglist, nents);
1113 panic("Check after sba_map_sg()\n");
1114 }
1115 #endif
1116
1117 spin_unlock_irqrestore(&ioc->res_lock, flags);
1118
1119 DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled);
1120
1121 return filled;
1122 }
1123
1124
1125 /**
1126 * sba_unmap_sg - unmap Scatter/Gather list
1127 * @dev: instance of PCI owned by the driver that's asking.
1128 * @sglist: array of buffer/length pairs
1129 * @nents: number of entries in list
1130 * @direction: R/W or both.
1131 *
1132 * See Documentation/DMA-mapping.txt
1133 */
1134 static void
1135 sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
1136 enum dma_data_direction direction)
1137 {
1138 struct ioc *ioc;
1139 #ifdef ASSERT_PDIR_SANITY
1140 unsigned long flags;
1141 #endif
1142
1143 DBG_RUN_SG("%s() START %d entries, %p,%x\n",
1144 __FUNCTION__, nents, sg_virt_addr(sglist), sglist->length);
1145
1146 ioc = GET_IOC(dev);
1147
1148 #ifdef SBA_COLLECT_STATS
1149 ioc->usg_calls++;
1150 #endif
1151
1152 #ifdef ASSERT_PDIR_SANITY
1153 spin_lock_irqsave(&ioc->res_lock, flags);
1154 sba_check_pdir(ioc,"Check before sba_unmap_sg()");
1155 spin_unlock_irqrestore(&ioc->res_lock, flags);
1156 #endif
1157
1158 while (sg_dma_len(sglist) && nents--) {
1159
1160 sba_unmap_single(dev, sg_dma_address(sglist), sg_dma_len(sglist), direction);
1161 #ifdef SBA_COLLECT_STATS
1162 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT;
1163 ioc->usingle_calls--; /* kluge since call is unmap_sg() */
1164 #endif
1165 ++sglist;
1166 }
1167
1168 DBG_RUN_SG("%s() DONE (nents %d)\n", __FUNCTION__, nents);
1169
1170 #ifdef ASSERT_PDIR_SANITY
1171 spin_lock_irqsave(&ioc->res_lock, flags);
1172 sba_check_pdir(ioc,"Check after sba_unmap_sg()");
1173 spin_unlock_irqrestore(&ioc->res_lock, flags);
1174 #endif
1175
1176 }
1177
1178 static struct hppa_dma_ops sba_ops = {
1179 .dma_supported = sba_dma_supported,
1180 .alloc_consistent = sba_alloc_consistent,
1181 .alloc_noncoherent = sba_alloc_consistent,
1182 .free_consistent = sba_free_consistent,
1183 .map_single = sba_map_single,
1184 .unmap_single = sba_unmap_single,
1185 .map_sg = sba_map_sg,
1186 .unmap_sg = sba_unmap_sg,
1187 .dma_sync_single_for_cpu = NULL,
1188 .dma_sync_single_for_device = NULL,
1189 .dma_sync_sg_for_cpu = NULL,
1190 .dma_sync_sg_for_device = NULL,
1191 };
1192
1193
1194 /**************************************************************************
1195 **
1196 ** SBA PAT PDC support
1197 **
1198 ** o call pdc_pat_cell_module()
1199 ** o store ranges in PCI "resource" structures
1200 **
1201 **************************************************************************/
1202
1203 static void
1204 sba_get_pat_resources(struct sba_device *sba_dev)
1205 {
1206 #if 0
1207 /*
1208 ** TODO/REVISIT/FIXME: support for directed ranges requires calls to
1209 ** PAT PDC to program the SBA/LBA directed range registers...this
1210 ** burden may fall on the LBA code since it directly supports the
1211 ** PCI subsystem. It's not clear yet. - ggg
1212 */
1213 PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp);
1214 FIXME : ???
1215 PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp);
1216 Tells where the dvi bits are located in the address.
1217 PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp);
1218 FIXME : ???
1219 #endif
1220 }
1221
1222
1223 /**************************************************************
1224 *
1225 * Initialization and claim
1226 *
1227 ***************************************************************/
1228 #define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */
1229 #define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */
1230 static void *
1231 sba_alloc_pdir(unsigned int pdir_size)
1232 {
1233 unsigned long pdir_base;
1234 unsigned long pdir_order = get_order(pdir_size);
1235
1236 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
1237 if (NULL == (void *) pdir_base)
1238 panic("sba_ioc_init() could not allocate I/O Page Table\n");
1239
1240 /* If this is not PA8700 (PCX-W2)
1241 ** OR newer than ver 2.2
1242 ** OR in a system that doesn't need VINDEX bits from SBA,
1243 **
1244 ** then we aren't exposed to the HW bug.
1245 */
1246 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13
1247 || (boot_cpu_data.pdc.versions > 0x202)
1248 || (boot_cpu_data.pdc.capabilities & 0x08L) )
1249 return (void *) pdir_base;
1250
1251 /*
1252 * PA8700 (PCX-W2, aka piranha) silent data corruption fix
1253 *
1254 * An interaction between PA8700 CPU (Ver 2.2 or older) and
1255 * Ike/Astro can cause silent data corruption. This is only
1256 * a problem if the I/O PDIR is located in memory such that
1257 * (little-endian) bits 17 and 18 are on and bit 20 is off.
1258 *
1259 * Since the max IO Pdir size is 2MB, by cleverly allocating the
1260 * right physical address, we can either avoid (IOPDIR <= 1MB)
1261 * or minimize (2MB IO Pdir) the problem if we restrict the
1262 * IO Pdir to a maximum size of 2MB-128K (1902K).
1263 *
1264 * Because we always allocate 2^N sized IO pdirs, either of the
1265 * "bad" regions will be the last 128K if at all. That's easy
1266 * to test for.
1267 *
1268 */
1269 if (pdir_order <= (19-12)) {
1270 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) {
1271 /* allocate a new one on 512k alignment */
1272 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12));
1273 /* release original */
1274 free_pages(pdir_base, pdir_order);
1275
1276 pdir_base = new_pdir;
1277
1278 /* release excess */
1279 while (pdir_order < (19-12)) {
1280 new_pdir += pdir_size;
1281 free_pages(new_pdir, pdir_order);
1282 pdir_order +=1;
1283 pdir_size <<=1;
1284 }
1285 }
1286 } else {
1287 /*
1288 ** 1MB or 2MB Pdir
1289 ** Needs to be aligned on an "odd" 1MB boundary.
1290 */
1291 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */
1292
1293 /* release original */
1294 free_pages( pdir_base, pdir_order);
1295
1296 /* release first 1MB */
1297 free_pages(new_pdir, 20-12);
1298
1299 pdir_base = new_pdir + 1024*1024;
1300
1301 if (pdir_order > (20-12)) {
1302 /*
1303 ** 2MB Pdir.
1304 **
1305 ** Flag tells init_bitmap() to mark bad 128k as used
1306 ** and to reduce the size by 128k.
1307 */
1308 piranha_bad_128k = 1;
1309
1310 new_pdir += 3*1024*1024;
1311 /* release last 1MB */
1312 free_pages(new_pdir, 20-12);
1313
1314 /* release unusable 128KB */
1315 free_pages(new_pdir - 128*1024 , 17-12);
1316
1317 pdir_size -= 128*1024;
1318 }
1319 }
1320
1321 memset((void *) pdir_base, 0, pdir_size);
1322 return (void *) pdir_base;
1323 }
1324
1325 /* setup Mercury or Elroy IBASE/IMASK registers. */
1326 static void setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1327 {
1328 /* lba_set_iregs() is in drivers/parisc/lba_pci.c */
1329 extern void lba_set_iregs(struct parisc_device *, u32, u32);
1330 struct device *dev;
1331
1332 list_for_each_entry(dev, &sba->dev.children, node) {
1333 struct parisc_device *lba = to_parisc_device(dev);
1334 int rope_num = (lba->hpa >> 13) & 0xf;
1335 if (rope_num >> 3 == ioc_num)
1336 lba_set_iregs(lba, ioc->ibase, ioc->imask);
1337 }
1338 }
1339
1340 static void
1341 sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1342 {
1343 u32 iova_space_mask;
1344 u32 iova_space_size;
1345 int iov_order, tcnfg;
1346 #if SBA_AGP_SUPPORT
1347 int agp_found = 0;
1348 #endif
1349 /*
1350 ** Firmware programs the base and size of a "safe IOVA space"
1351 ** (one that doesn't overlap memory or LMMIO space) in the
1352 ** IBASE and IMASK registers.
1353 */
1354 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE);
1355 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1;
1356
1357 if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) {
1358 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n");
1359 iova_space_size /= 2;
1360 }
1361
1362 /*
1363 ** iov_order is always based on a 1GB IOVA space since we want to
1364 ** turn on the other half for AGP GART.
1365 */
1366 iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT));
1367 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
1368
1369 DBG_INIT("%s() hpa 0x%lx IOV %dMB (%d bits)\n",
1370 __FUNCTION__, ioc->ioc_hpa, iova_space_size >> 20,
1371 iov_order + PAGE_SHIFT);
1372
1373 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
1374 get_order(ioc->pdir_size));
1375 if (!ioc->pdir_base)
1376 panic("Couldn't allocate I/O Page Table\n");
1377
1378 memset(ioc->pdir_base, 0, ioc->pdir_size);
1379
1380 DBG_INIT("%s() pdir %p size %x\n",
1381 __FUNCTION__, ioc->pdir_base, ioc->pdir_size);
1382
1383 #if SBA_HINT_SUPPORT
1384 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1385 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1386
1387 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1388 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1389 #endif
1390
1391 WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base);
1392 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1393
1394 /* build IMASK for IOC and Elroy */
1395 iova_space_mask = 0xffffffff;
1396 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1397 ioc->imask = iova_space_mask;
1398 #ifdef ZX1_SUPPORT
1399 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1400 #endif
1401 sba_dump_tlb(ioc->ioc_hpa);
1402
1403 setup_ibase_imask(sba, ioc, ioc_num);
1404
1405 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
1406
1407 #ifdef __LP64__
1408 /*
1409 ** Setting the upper bits makes checking for bypass addresses
1410 ** a little faster later on.
1411 */
1412 ioc->imask |= 0xFFFFFFFF00000000UL;
1413 #endif
1414
1415 /* Set I/O PDIR Page size to system page size */
1416 switch (PAGE_SHIFT) {
1417 case 12: tcnfg = 0; break; /* 4K */
1418 case 13: tcnfg = 1; break; /* 8K */
1419 case 14: tcnfg = 2; break; /* 16K */
1420 case 16: tcnfg = 3; break; /* 64K */
1421 default:
1422 panic(__FILE__ "Unsupported system page size %d",
1423 1 << PAGE_SHIFT);
1424 break;
1425 }
1426 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
1427
1428 /*
1429 ** Program the IOC's ibase and enable IOVA translation
1430 ** Bit zero == enable bit.
1431 */
1432 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
1433
1434 /*
1435 ** Clear I/O TLB of any possible entries.
1436 ** (Yes. This is a bit paranoid...but so what)
1437 */
1438 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
1439
1440 #if SBA_AGP_SUPPORT
1441 /*
1442 ** If an AGP device is present, only use half of the IOV space
1443 ** for PCI DMA. Unfortunately we can't know ahead of time
1444 ** whether GART support will actually be used, for now we
1445 ** can just key on any AGP device found in the system.
1446 ** We program the next pdir index after we stop w/ a key for
1447 ** the GART code to handshake on.
1448 */
1449 device=NULL;
1450 for (lba = sba->child; lba; lba = lba->sibling) {
1451 if (IS_QUICKSILVER(lba))
1452 break;
1453 }
1454
1455 if (lba) {
1456 DBG_INIT("%s: Reserving half of IOVA space for AGP GART support\n", __FUNCTION__);
1457 ioc->pdir_size /= 2;
1458 ((u64 *)ioc->pdir_base)[PDIR_INDEX(iova_space_size/2)] = SBA_IOMMU_COOKIE;
1459 } else {
1460 DBG_INIT("%s: No GART needed - no AGP controller found\n", __FUNCTION__);
1461 }
1462 #endif /* 0 */
1463
1464 }
1465
1466 static void
1467 sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1468 {
1469 u32 iova_space_size, iova_space_mask;
1470 unsigned int pdir_size, iov_order;
1471
1472 /*
1473 ** Determine IOVA Space size from memory size.
1474 **
1475 ** Ideally, PCI drivers would register the maximum number
1476 ** of DMA they can have outstanding for each device they
1477 ** own. Next best thing would be to guess how much DMA
1478 ** can be outstanding based on PCI Class/sub-class. Both
1479 ** methods still require some "extra" to support PCI
1480 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
1481 **
1482 ** While we have 32-bits "IOVA" space, top two 2 bits are used
1483 ** for DMA hints - ergo only 30 bits max.
1484 */
1485
1486 iova_space_size = (u32) (num_physpages/global_ioc_cnt);
1487
1488 /* limit IOVA space size to 1MB-1GB */
1489 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
1490 iova_space_size = 1 << (20 - PAGE_SHIFT);
1491 }
1492 #ifdef __LP64__
1493 else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
1494 iova_space_size = 1 << (30 - PAGE_SHIFT);
1495 }
1496 #endif
1497
1498 /*
1499 ** iova space must be log2() in size.
1500 ** thus, pdir/res_map will also be log2().
1501 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
1502 */
1503 iov_order = get_order(iova_space_size << PAGE_SHIFT);
1504
1505 /* iova_space_size is now bytes, not pages */
1506 iova_space_size = 1 << (iov_order + PAGE_SHIFT);
1507
1508 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
1509
1510 DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
1511 __FUNCTION__,
1512 ioc->ioc_hpa,
1513 (unsigned long) num_physpages >> (20 - PAGE_SHIFT),
1514 iova_space_size>>20,
1515 iov_order + PAGE_SHIFT);
1516
1517 ioc->pdir_base = sba_alloc_pdir(pdir_size);
1518
1519 DBG_INIT("%s() pdir %p size %x\n",
1520 __FUNCTION__, ioc->pdir_base, pdir_size);
1521
1522 #if SBA_HINT_SUPPORT
1523 /* FIXME : DMA HINTs not used */
1524 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1525 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1526
1527 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1528 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1529 #endif
1530
1531 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1532
1533 /* build IMASK for IOC and Elroy */
1534 iova_space_mask = 0xffffffff;
1535 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1536
1537 /*
1538 ** On C3000 w/512MB mem, HP-UX 10.20 reports:
1539 ** ibase=0, imask=0xFE000000, size=0x2000000.
1540 */
1541 ioc->ibase = 0;
1542 ioc->imask = iova_space_mask; /* save it */
1543 #ifdef ZX1_SUPPORT
1544 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1545 #endif
1546
1547 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
1548 __FUNCTION__, ioc->ibase, ioc->imask);
1549
1550 /*
1551 ** FIXME: Hint registers are programmed with default hint
1552 ** values during boot, so hints should be sane even if we
1553 ** can't reprogram them the way drivers want.
1554 */
1555
1556 setup_ibase_imask(sba, ioc, ioc_num);
1557
1558 /*
1559 ** Program the IOC's ibase and enable IOVA translation
1560 */
1561 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
1562 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
1563
1564 /* Set I/O PDIR Page size to 4K */
1565 WRITE_REG(0, ioc->ioc_hpa+IOC_TCNFG);
1566
1567 /*
1568 ** Clear I/O TLB of any possible entries.
1569 ** (Yes. This is a bit paranoid...but so what)
1570 */
1571 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
1572
1573 ioc->ibase = 0; /* used by SBA_IOVA and related macros */
1574
1575 DBG_INIT("%s() DONE\n", __FUNCTION__);
1576 }
1577
1578
1579
1580 /**************************************************************************
1581 **
1582 ** SBA initialization code (HW and SW)
1583 **
1584 ** o identify SBA chip itself
1585 ** o initialize SBA chip modes (HardFail)
1586 ** o initialize SBA chip modes (HardFail)
1587 ** o FIXME: initialize DMA hints for reasonable defaults
1588 **
1589 **************************************************************************/
1590
1591 static void __iomem *ioc_remap(struct sba_device *sba_dev, int offset)
1592 {
1593 return ioremap(sba_dev->dev->hpa + offset, SBA_FUNC_SIZE);
1594 }
1595
1596 static void sba_hw_init(struct sba_device *sba_dev)
1597 {
1598 int i;
1599 int num_ioc;
1600 u64 ioc_ctl;
1601
1602 if (!is_pdc_pat()) {
1603 /* Shutdown the USB controller on Astro-based workstations.
1604 ** Once we reprogram the IOMMU, the next DMA performed by
1605 ** USB will HPMC the box. USB is only enabled if a
1606 ** keyboard is present and found.
1607 **
1608 ** With serial console, j6k v5.0 firmware says:
1609 ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7
1610 **
1611 ** FIXME: Using GFX+USB console at power up but direct
1612 ** linux to serial console is still broken.
1613 ** USB could generate DMA so we must reset USB.
1614 ** The proper sequence would be:
1615 ** o block console output
1616 ** o reset USB device
1617 ** o reprogram serial port
1618 ** o unblock console output
1619 */
1620 if (PAGE0->mem_kbd.cl_class == CL_KEYBD) {
1621 pdc_io_reset_devices();
1622 }
1623
1624 }
1625
1626
1627 #if 0
1628 printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa,
1629 PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class);
1630
1631 /*
1632 ** Need to deal with DMA from LAN.
1633 ** Maybe use page zero boot device as a handle to talk
1634 ** to PDC about which device to shutdown.
1635 **
1636 ** Netbooting, j6k v5.0 firmware says:
1637 ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002
1638 ** ARGH! invalid class.
1639 */
1640 if ((PAGE0->mem_boot.cl_class != CL_RANDOM)
1641 && (PAGE0->mem_boot.cl_class != CL_SEQU)) {
1642 pdc_io_reset();
1643 }
1644 #endif
1645
1646 if (!IS_PLUTO(sba_dev->iodc)) {
1647 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
1648 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
1649 __FUNCTION__, sba_dev->sba_hpa, ioc_ctl);
1650 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
1651 ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC;
1652 /* j6700 v1.6 firmware sets 0x294f */
1653 /* A500 firmware sets 0x4d */
1654
1655 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
1656
1657 #ifdef DEBUG_SBA_INIT
1658 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
1659 DBG_INIT(" 0x%Lx\n", ioc_ctl);
1660 #endif
1661 } /* if !PLUTO */
1662
1663 if (IS_ASTRO(sba_dev->iodc)) {
1664 int err;
1665 /* PAT_PDC (L-class) also reports the same goofy base */
1666 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET);
1667 num_ioc = 1;
1668
1669 sba_dev->chip_resv.name = "Astro Intr Ack";
1670 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL;
1671 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ;
1672 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1673 if (err < 0) {
1674 BUG();
1675 }
1676
1677 } else if (IS_PLUTO(sba_dev->iodc)) {
1678 int err;
1679
1680 /* We use a negative value for IOC HPA so it gets
1681 * corrected when we add it with IKE's IOC offset.
1682 * Doesnt look clean, but fewer code.
1683 */
1684 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET);
1685 num_ioc = 1;
1686
1687 sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA";
1688 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL;
1689 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1);
1690 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1691 WARN_ON(err < 0);
1692
1693 sba_dev->iommu_resv.name = "IOVA Space";
1694 sba_dev->iommu_resv.start = 0x40000000UL;
1695 sba_dev->iommu_resv.end = 0x50000000UL - 1;
1696 err = request_resource(&iomem_resource, &(sba_dev->iommu_resv));
1697 WARN_ON(err < 0);
1698 } else {
1699 /* IS_IKE (ie N-class, L3000, L1500) */
1700 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0));
1701 sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1));
1702 num_ioc = 2;
1703
1704 /* TODO - LOOKUP Ike/Stretch chipset mem map */
1705 }
1706 /* XXX: What about Reo? */
1707
1708 sba_dev->num_ioc = num_ioc;
1709 for (i = 0; i < num_ioc; i++) {
1710 /*
1711 ** Make sure the box crashes if we get any errors on a rope.
1712 */
1713 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE0_CTL);
1714 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE1_CTL);
1715 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE2_CTL);
1716 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE3_CTL);
1717 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE4_CTL);
1718 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE5_CTL);
1719 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE6_CTL);
1720 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
1721
1722 /* flush out the writes */
1723 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
1724
1725 DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n",
1726 i,
1727 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40),
1728 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50)
1729 );
1730 DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n",
1731 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108),
1732 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400)
1733 );
1734
1735 if (IS_PLUTO(sba_dev->iodc)) {
1736 sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i);
1737 } else {
1738 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
1739 }
1740 }
1741 }
1742
1743 static void
1744 sba_common_init(struct sba_device *sba_dev)
1745 {
1746 int i;
1747
1748 /* add this one to the head of the list (order doesn't matter)
1749 ** This will be useful for debugging - especially if we get coredumps
1750 */
1751 sba_dev->next = sba_list;
1752 sba_list = sba_dev;
1753
1754 for(i=0; i< sba_dev->num_ioc; i++) {
1755 int res_size;
1756 #ifdef DEBUG_DMB_TRAP
1757 extern void iterate_pages(unsigned long , unsigned long ,
1758 void (*)(pte_t * , unsigned long),
1759 unsigned long );
1760 void set_data_memory_break(pte_t * , unsigned long);
1761 #endif
1762 /* resource map size dictated by pdir_size */
1763 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */
1764
1765 /* Second part of PIRANHA BUG */
1766 if (piranha_bad_128k) {
1767 res_size -= (128*1024)/sizeof(u64);
1768 }
1769
1770 res_size >>= 3; /* convert bit count to byte count */
1771 DBG_INIT("%s() res_size 0x%x\n",
1772 __FUNCTION__, res_size);
1773
1774 sba_dev->ioc[i].res_size = res_size;
1775 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size));
1776
1777 #ifdef DEBUG_DMB_TRAP
1778 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1779 set_data_memory_break, 0);
1780 #endif
1781
1782 if (NULL == sba_dev->ioc[i].res_map)
1783 {
1784 panic("%s:%s() could not allocate resource map\n",
1785 __FILE__, __FUNCTION__ );
1786 }
1787
1788 memset(sba_dev->ioc[i].res_map, 0, res_size);
1789 /* next available IOVP - circular search */
1790 sba_dev->ioc[i].res_hint = (unsigned long *)
1791 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]);
1792
1793 #ifdef ASSERT_PDIR_SANITY
1794 /* Mark first bit busy - ie no IOVA 0 */
1795 sba_dev->ioc[i].res_map[0] = 0x80;
1796 sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL;
1797 #endif
1798
1799 /* Third (and last) part of PIRANHA BUG */
1800 if (piranha_bad_128k) {
1801 /* region from +1408K to +1536 is un-usable. */
1802
1803 int idx_start = (1408*1024/sizeof(u64)) >> 3;
1804 int idx_end = (1536*1024/sizeof(u64)) >> 3;
1805 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]);
1806 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]);
1807
1808 /* mark that part of the io pdir busy */
1809 while (p_start < p_end)
1810 *p_start++ = -1;
1811
1812 }
1813
1814 #ifdef DEBUG_DMB_TRAP
1815 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1816 set_data_memory_break, 0);
1817 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size,
1818 set_data_memory_break, 0);
1819 #endif
1820
1821 DBG_INIT("%s() %d res_map %x %p\n",
1822 __FUNCTION__, i, res_size, sba_dev->ioc[i].res_map);
1823 }
1824
1825 spin_lock_init(&sba_dev->sba_lock);
1826 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC;
1827
1828 #ifdef DEBUG_SBA_INIT
1829 /*
1830 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
1831 * (bit #61, big endian), we have to flush and sync every time
1832 * IO-PDIR is changed in Ike/Astro.
1833 */
1834 if (boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC) {
1835 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n");
1836 } else {
1837 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n");
1838 }
1839 #endif
1840 }
1841
1842 #ifdef CONFIG_PROC_FS
1843 static int sba_proc_info(char *buf, char **start, off_t offset, int len)
1844 {
1845 struct sba_device *sba_dev = sba_list;
1846 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
1847 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */
1848 unsigned long i;
1849 #ifdef SBA_COLLECT_STATS
1850 unsigned long avg = 0, min, max;
1851 #endif
1852
1853 sprintf(buf, "%s rev %d.%d\n",
1854 sba_dev->name,
1855 (sba_dev->hw_rev & 0x7) + 1,
1856 (sba_dev->hw_rev & 0x18) >> 3
1857 );
1858 sprintf(buf, "%sIO PDIR size : %d bytes (%d entries)\n",
1859 buf,
1860 (int) ((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */
1861 total_pages);
1862
1863 sprintf(buf, "%sResource bitmap : %d bytes (%d pages)\n",
1864 buf, ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */
1865
1866 sprintf(buf, "%sLMMIO_BASE/MASK/ROUTE %08x %08x %08x\n",
1867 buf,
1868 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE),
1869 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK),
1870 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE)
1871 );
1872
1873 for (i=0; i<4; i++)
1874 sprintf(buf, "%sDIR%ld_BASE/MASK/ROUTE %08x %08x %08x\n",
1875 buf, i,
1876 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18),
1877 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18),
1878 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18)
1879 );
1880
1881 #ifdef SBA_COLLECT_STATS
1882 sprintf(buf, "%sIO PDIR entries : %ld free %ld used (%d%%)\n", buf,
1883 total_pages - ioc->used_pages, ioc->used_pages,
1884 (int) (ioc->used_pages * 100 / total_pages));
1885
1886 min = max = ioc->avg_search[0];
1887 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
1888 avg += ioc->avg_search[i];
1889 if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
1890 if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
1891 }
1892 avg /= SBA_SEARCH_SAMPLE;
1893 sprintf(buf, "%s Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
1894 buf, min, avg, max);
1895
1896 sprintf(buf, "%spci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
1897 buf, ioc->msingle_calls, ioc->msingle_pages,
1898 (int) ((ioc->msingle_pages * 1000)/ioc->msingle_calls));
1899
1900 /* KLUGE - unmap_sg calls unmap_single for each mapped page */
1901 min = ioc->usingle_calls;
1902 max = ioc->usingle_pages - ioc->usg_pages;
1903 sprintf(buf, "%spci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
1904 buf, min, max,
1905 (int) ((max * 1000)/min));
1906
1907 sprintf(buf, "%spci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1908 buf, ioc->msg_calls, ioc->msg_pages,
1909 (int) ((ioc->msg_pages * 1000)/ioc->msg_calls));
1910
1911 sprintf(buf, "%spci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1912 buf, ioc->usg_calls, ioc->usg_pages,
1913 (int) ((ioc->usg_pages * 1000)/ioc->usg_calls));
1914 #endif
1915
1916 return strlen(buf);
1917 }
1918
1919 #if 0
1920 /* XXX too much output - exceeds 4k limit and needs to be re-written */
1921 static int
1922 sba_resource_map(char *buf, char **start, off_t offset, int len)
1923 {
1924 struct sba_device *sba_dev = sba_list;
1925 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Mutli-IOC suppoer! */
1926 unsigned int *res_ptr = (unsigned int *)ioc->res_map;
1927 int i;
1928
1929 buf[0] = '\0';
1930 for(i = 0; i < (ioc->res_size / sizeof(unsigned int)); ++i, ++res_ptr) {
1931 if ((i & 7) == 0)
1932 strcat(buf,"\n ");
1933 sprintf(buf, "%s %08x", buf, *res_ptr);
1934 }
1935 strcat(buf, "\n");
1936
1937 return strlen(buf);
1938 }
1939 #endif /* 0 */
1940 #endif /* CONFIG_PROC_FS */
1941
1942 static struct parisc_device_id sba_tbl[] = {
1943 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb },
1944 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc },
1945 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
1946 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
1947 { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc },
1948 { 0, }
1949 };
1950
1951 int sba_driver_callback(struct parisc_device *);
1952
1953 static struct parisc_driver sba_driver = {
1954 .name = MODULE_NAME,
1955 .id_table = sba_tbl,
1956 .probe = sba_driver_callback,
1957 };
1958
1959 /*
1960 ** Determine if sba should claim this chip (return 0) or not (return 1).
1961 ** If so, initialize the chip and tell other partners in crime they
1962 ** have work to do.
1963 */
1964 int
1965 sba_driver_callback(struct parisc_device *dev)
1966 {
1967 struct sba_device *sba_dev;
1968 u32 func_class;
1969 int i;
1970 char *version;
1971 void __iomem *sba_addr = ioremap(dev->hpa, SBA_FUNC_SIZE);
1972
1973 sba_dump_ranges(sba_addr);
1974
1975 /* Read HW Rev First */
1976 func_class = READ_REG(sba_addr + SBA_FCLASS);
1977
1978 if (IS_ASTRO(&dev->id)) {
1979 unsigned long fclass;
1980 static char astro_rev[]="Astro ?.?";
1981
1982 /* Astro is broken...Read HW Rev First */
1983 fclass = READ_REG(sba_addr);
1984
1985 astro_rev[6] = '1' + (char) (fclass & 0x7);
1986 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
1987 version = astro_rev;
1988
1989 } else if (IS_IKE(&dev->id)) {
1990 static char ike_rev[] = "Ike rev ?";
1991 ike_rev[8] = '0' + (char) (func_class & 0xff);
1992 version = ike_rev;
1993 } else if (IS_PLUTO(&dev->id)) {
1994 static char pluto_rev[]="Pluto ?.?";
1995 pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4);
1996 pluto_rev[8] = '0' + (char) (func_class & 0x0f);
1997 version = pluto_rev;
1998 } else {
1999 static char reo_rev[] = "REO rev ?";
2000 reo_rev[8] = '0' + (char) (func_class & 0xff);
2001 version = reo_rev;
2002 }
2003
2004 if (!global_ioc_cnt) {
2005 global_ioc_cnt = count_parisc_driver(&sba_driver);
2006
2007 /* Astro and Pluto have one IOC per SBA */
2008 if ((!IS_ASTRO(&dev->id)) || (!IS_PLUTO(&dev->id)))
2009 global_ioc_cnt *= 2;
2010 }
2011
2012 printk(KERN_INFO "%s found %s at 0x%lx\n",
2013 MODULE_NAME, version, dev->hpa);
2014
2015 sba_dev = kmalloc(sizeof(struct sba_device), GFP_KERNEL);
2016 if (!sba_dev) {
2017 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
2018 return -ENOMEM;
2019 }
2020
2021 parisc_set_drvdata(dev, sba_dev);
2022 memset(sba_dev, 0, sizeof(struct sba_device));
2023
2024 for(i=0; i<MAX_IOC; i++)
2025 spin_lock_init(&(sba_dev->ioc[i].res_lock));
2026
2027 sba_dev->dev = dev;
2028 sba_dev->hw_rev = func_class;
2029 sba_dev->iodc = &dev->id;
2030 sba_dev->name = dev->name;
2031 sba_dev->sba_hpa = sba_addr;
2032
2033 sba_get_pat_resources(sba_dev);
2034 sba_hw_init(sba_dev);
2035 sba_common_init(sba_dev);
2036
2037 hppa_dma_ops = &sba_ops;
2038
2039 #ifdef CONFIG_PROC_FS
2040 if (IS_ASTRO(&dev->id)) {
2041 create_proc_info_entry("Astro", 0, proc_runway_root, sba_proc_info);
2042 } else if (IS_IKE(&dev->id)) {
2043 create_proc_info_entry("Ike", 0, proc_runway_root, sba_proc_info);
2044 } else if (IS_PLUTO(&dev->id)) {
2045 create_proc_info_entry("Pluto", 0, proc_mckinley_root, sba_proc_info);
2046 } else {
2047 create_proc_info_entry("Reo", 0, proc_runway_root, sba_proc_info);
2048 }
2049 #if 0
2050 create_proc_info_entry("bitmap", 0, proc_runway_root, sba_resource_map);
2051 #endif
2052 #endif
2053 parisc_vmerge_boundary = IOVP_SIZE;
2054 parisc_vmerge_max_size = IOVP_SIZE * BITS_PER_LONG;
2055 parisc_has_iommu();
2056 return 0;
2057 }
2058
2059 /*
2060 ** One time initialization to let the world know the SBA was found.
2061 ** This is the only routine which is NOT static.
2062 ** Must be called exactly once before pci_init().
2063 */
2064 void __init sba_init(void)
2065 {
2066 register_parisc_driver(&sba_driver);
2067 }
2068
2069
2070 /**
2071 * sba_get_iommu - Assign the iommu pointer for the pci bus controller.
2072 * @dev: The parisc device.
2073 *
2074 * Returns the appropriate IOMMU data for the given parisc PCI controller.
2075 * This is cached and used later for PCI DMA Mapping.
2076 */
2077 void * sba_get_iommu(struct parisc_device *pci_hba)
2078 {
2079 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2080 struct sba_device *sba = sba_dev->dev.driver_data;
2081 char t = sba_dev->id.hw_type;
2082 int iocnum = (pci_hba->hw_path >> 3); /* rope # */
2083
2084 WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
2085
2086 return &(sba->ioc[iocnum]);
2087 }
2088
2089
2090 /**
2091 * sba_directed_lmmio - return first directed LMMIO range routed to rope
2092 * @pa_dev: The parisc device.
2093 * @r: resource PCI host controller wants start/end fields assigned.
2094 *
2095 * For the given parisc PCI controller, determine if any direct ranges
2096 * are routed down the corresponding rope.
2097 */
2098 void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r)
2099 {
2100 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2101 struct sba_device *sba = sba_dev->dev.driver_data;
2102 char t = sba_dev->id.hw_type;
2103 int i;
2104 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2105
2106 if ((t!=HPHW_IOA) && (t!=HPHW_BCPORT))
2107 BUG();
2108
2109 r->start = r->end = 0;
2110
2111 /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */
2112 for (i=0; i<4; i++) {
2113 int base, size;
2114 void __iomem *reg = sba->sba_hpa + i*0x18;
2115
2116 base = READ_REG32(reg + LMMIO_DIRECT0_BASE);
2117 if ((base & 1) == 0)
2118 continue; /* not enabled */
2119
2120 size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE);
2121
2122 if ((size & (ROPES_PER_IOC-1)) != rope)
2123 continue; /* directed down different rope */
2124
2125 r->start = (base & ~1UL) | PCI_F_EXTEND;
2126 size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK);
2127 r->end = r->start + size;
2128 }
2129 }
2130
2131
2132 /**
2133 * sba_distributed_lmmio - return portion of distributed LMMIO range
2134 * @pa_dev: The parisc device.
2135 * @r: resource PCI host controller wants start/end fields assigned.
2136 *
2137 * For the given parisc PCI controller, return portion of distributed LMMIO
2138 * range. The distributed LMMIO is always present and it's just a question
2139 * of the base address and size of the range.
2140 */
2141 void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r )
2142 {
2143 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2144 struct sba_device *sba = sba_dev->dev.driver_data;
2145 char t = sba_dev->id.hw_type;
2146 int base, size;
2147 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2148
2149 if ((t!=HPHW_IOA) && (t!=HPHW_BCPORT))
2150 BUG();
2151
2152 r->start = r->end = 0;
2153
2154 base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE);
2155 if ((base & 1) == 0) {
2156 BUG(); /* Gah! Distr Range wasn't enabled! */
2157 return;
2158 }
2159
2160 r->start = (base & ~1UL) | PCI_F_EXTEND;
2161
2162 size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC;
2163 r->start += rope * (size + 1); /* adjust base for this rope */
2164 r->end = r->start + size;
2165 }
CRIS linux kernel tree