[PATCH] aic7xxx_osm build fix
[cris-mirror.git] / drivers / s390 / cio / ioasm.h
blobc874607d9a806ec9fccbe908a5569198c0351ae3
1 #ifndef S390_CIO_IOASM_H
2 #define S390_CIO_IOASM_H
4 /*
5 * TPI info structure
6 */
7 struct tpi_info {
8 __u32 reserved1 : 16; /* reserved 0x00000001 */
9 __u32 irq : 16; /* aka. subchannel number */
10 __u32 intparm; /* interruption parameter */
11 __u32 adapter_IO : 1;
12 __u32 reserved2 : 1;
13 __u32 isc : 3;
14 __u32 reserved3 : 12;
15 __u32 int_type : 3;
16 __u32 reserved4 : 12;
17 } __attribute__ ((packed));
21 * Some S390 specific IO instructions as inline
24 extern __inline__ int stsch(int irq, volatile struct schib *addr)
26 int ccode;
28 __asm__ __volatile__(
29 " lr 1,%1\n"
30 " stsch 0(%2)\n"
31 " ipm %0\n"
32 " srl %0,28"
33 : "=d" (ccode)
34 : "d" (irq | 0x10000), "a" (addr)
35 : "cc", "1" );
36 return ccode;
39 extern __inline__ int msch(int irq, volatile struct schib *addr)
41 int ccode;
43 __asm__ __volatile__(
44 " lr 1,%1\n"
45 " msch 0(%2)\n"
46 " ipm %0\n"
47 " srl %0,28"
48 : "=d" (ccode)
49 : "d" (irq | 0x10000L), "a" (addr)
50 : "cc", "1" );
51 return ccode;
54 extern __inline__ int msch_err(int irq, volatile struct schib *addr)
56 int ccode;
58 __asm__ __volatile__(
59 " lhi %0,%3\n"
60 " lr 1,%1\n"
61 " msch 0(%2)\n"
62 "0: ipm %0\n"
63 " srl %0,28\n"
64 "1:\n"
65 #ifdef CONFIG_ARCH_S390X
66 ".section __ex_table,\"a\"\n"
67 " .align 8\n"
68 " .quad 0b,1b\n"
69 ".previous"
70 #else
71 ".section __ex_table,\"a\"\n"
72 " .align 4\n"
73 " .long 0b,1b\n"
74 ".previous"
75 #endif
76 : "=&d" (ccode)
77 : "d" (irq | 0x10000L), "a" (addr), "K" (-EIO)
78 : "cc", "1" );
79 return ccode;
82 extern __inline__ int tsch(int irq, volatile struct irb *addr)
84 int ccode;
86 __asm__ __volatile__(
87 " lr 1,%1\n"
88 " tsch 0(%2)\n"
89 " ipm %0\n"
90 " srl %0,28"
91 : "=d" (ccode)
92 : "d" (irq | 0x10000L), "a" (addr)
93 : "cc", "1" );
94 return ccode;
97 extern __inline__ int tpi( volatile struct tpi_info *addr)
99 int ccode;
101 __asm__ __volatile__(
102 " tpi 0(%1)\n"
103 " ipm %0\n"
104 " srl %0,28"
105 : "=d" (ccode)
106 : "a" (addr)
107 : "cc", "1" );
108 return ccode;
111 extern __inline__ int ssch(int irq, volatile struct orb *addr)
113 int ccode;
115 __asm__ __volatile__(
116 " lr 1,%1\n"
117 " ssch 0(%2)\n"
118 " ipm %0\n"
119 " srl %0,28"
120 : "=d" (ccode)
121 : "d" (irq | 0x10000L), "a" (addr)
122 : "cc", "1" );
123 return ccode;
126 extern __inline__ int rsch(int irq)
128 int ccode;
130 __asm__ __volatile__(
131 " lr 1,%1\n"
132 " rsch\n"
133 " ipm %0\n"
134 " srl %0,28"
135 : "=d" (ccode)
136 : "d" (irq | 0x10000L)
137 : "cc", "1" );
138 return ccode;
141 extern __inline__ int csch(int irq)
143 int ccode;
145 __asm__ __volatile__(
146 " lr 1,%1\n"
147 " csch\n"
148 " ipm %0\n"
149 " srl %0,28"
150 : "=d" (ccode)
151 : "d" (irq | 0x10000L)
152 : "cc", "1" );
153 return ccode;
156 extern __inline__ int hsch(int irq)
158 int ccode;
160 __asm__ __volatile__(
161 " lr 1,%1\n"
162 " hsch\n"
163 " ipm %0\n"
164 " srl %0,28"
165 : "=d" (ccode)
166 : "d" (irq | 0x10000L)
167 : "cc", "1" );
168 return ccode;
171 extern __inline__ int xsch(int irq)
173 int ccode;
175 __asm__ __volatile__(
176 " lr 1,%1\n"
177 " .insn rre,0xb2760000,%1,0\n"
178 " ipm %0\n"
179 " srl %0,28"
180 : "=d" (ccode)
181 : "d" (irq | 0x10000L)
182 : "cc", "1" );
183 return ccode;
186 extern __inline__ int chsc(void *chsc_area)
188 int cc;
190 __asm__ __volatile__ (
191 ".insn rre,0xb25f0000,%1,0 \n\t"
192 "ipm %0 \n\t"
193 "srl %0,28 \n\t"
194 : "=d" (cc)
195 : "d" (chsc_area)
196 : "cc" );
198 return cc;
201 extern __inline__ int iac( void)
203 int ccode;
205 __asm__ __volatile__(
206 " iac 1\n"
207 " ipm %0\n"
208 " srl %0,28"
209 : "=d" (ccode) : : "cc", "1" );
210 return ccode;
213 extern __inline__ int rchp(int chpid)
215 int ccode;
217 __asm__ __volatile__(
218 " lr 1,%1\n"
219 " rchp\n"
220 " ipm %0\n"
221 " srl %0,28"
222 : "=d" (ccode)
223 : "d" (chpid)
224 : "cc", "1" );
225 return ccode;
228 #endif