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[PATCH] aic7xxx_osm build fix
[cris-mirror.git] / drivers / serial / sunsab.c
blob10e2990a40d42a2453780c5e045642c28866411e
1 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
2 *
3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
4 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
5 *
6 * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
7 * Maxim Krasnyanskiy <maxk@qualcomm.com>
8 *
9 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
10 * rates to be programmed into the UART. Also eliminated a lot of
11 * duplicated code in the console setup.
12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
13 *
14 * Ported to new 2.5.x UART layer.
15 * David S. Miller <davem@redhat.com>
16 */
17
18 #include <linux/config.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/sched.h>
22 #include <linux/errno.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/major.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/ioport.h>
29 #include <linux/circ_buf.h>
30 #include <linux/serial.h>
31 #include <linux/sysrq.h>
32 #include <linux/console.h>
33 #include <linux/spinlock.h>
34 #include <linux/slab.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
37
38 #include <asm/io.h>
39 #include <asm/irq.h>
40 #include <asm/oplib.h>
41 #include <asm/ebus.h>
42
43 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
44 #define SUPPORT_SYSRQ
45 #endif
46
47 #include <linux/serial_core.h>
48
49 #include "suncore.h"
50 #include "sunsab.h"
51
52 struct uart_sunsab_port {
53 struct uart_port port; /* Generic UART port */
54 union sab82532_async_regs __iomem *regs; /* Chip registers */
55 unsigned long irqflags; /* IRQ state flags */
56 int dsr; /* Current DSR state */
57 unsigned int cec_timeout; /* Chip poll timeout... */
58 unsigned int tec_timeout; /* likewise */
59 unsigned char interrupt_mask0;/* ISR0 masking */
60 unsigned char interrupt_mask1;/* ISR1 masking */
61 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */
62 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */
63 int type; /* SAB82532 version */
64
65 /* Setting configuration bits while the transmitter is active
66 * can cause garbage characters to get emitted by the chip.
67 * Therefore, we cache such writes here and do the real register
68 * write the next time the transmitter becomes idle.
69 */
70 unsigned int cached_ebrg;
71 unsigned char cached_mode;
72 unsigned char cached_pvr;
73 unsigned char cached_dafo;
74 };
75
76 /*
77 * This assumes you have a 29.4912 MHz clock for your UART.
78 */
79 #define SAB_BASE_BAUD ( 29491200 / 16 )
80
81 static char *sab82532_version[16] = {
82 "V1.0", "V2.0", "V3.2", "V(0x03)",
83 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
84 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
85 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
86 };
87
88 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
89 #define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */
90
91 #define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */
92 #define SAB82532_XMIT_FIFO_SIZE 32
93
94 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
95 {
96 int timeout = up->tec_timeout;
97
98 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
99 udelay(1);
100 }
101
102 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
103 {
104 int timeout = up->cec_timeout;
105
106 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
107 udelay(1);
108 }
109
110 static struct tty_struct *
111 receive_chars(struct uart_sunsab_port *up,
112 union sab82532_irq_status *stat,
113 struct pt_regs *regs)
114 {
115 struct tty_struct *tty = NULL;
116 unsigned char buf[32];
117 int saw_console_brk = 0;
118 int free_fifo = 0;
119 int count = 0;
120 int i;
121
122 if (up->port.info != NULL) /* Unopened serial console */
123 tty = up->port.info->tty;
124
125 /* Read number of BYTES (Character + Status) available. */
126 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
127 count = SAB82532_RECV_FIFO_SIZE;
128 free_fifo++;
129 }
130
131 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
132 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
133 free_fifo++;
134 }
135
136 /* Issue a FIFO read command in case we where idle. */
137 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
138 sunsab_cec_wait(up);
139 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
140 return tty;
141 }
142
143 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
144 free_fifo++;
145
146 /* Read the FIFO. */
147 for (i = 0; i < count; i++)
148 buf[i] = readb(&up->regs->r.rfifo[i]);
149
150 /* Issue Receive Message Complete command. */
151 if (free_fifo) {
152 sunsab_cec_wait(up);
153 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
154 }
155
156 /* Count may be zero for BRK, so we check for it here */
157 if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
158 (up->port.line == up->port.cons->index))
159 saw_console_brk = 1;
160
161 for (i = 0; i < count; i++) {
162 unsigned char ch = buf[i];
163
164 if (tty == NULL) {
165 uart_handle_sysrq_char(&up->port, ch, regs);
166 continue;
167 }
168
169 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
170 tty->flip.work.func((void *)tty);
171 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
172 return tty; // if TTY_DONT_FLIP is set
173 }
174
175 *tty->flip.char_buf_ptr = ch;
176 *tty->flip.flag_buf_ptr = TTY_NORMAL;
177 up->port.icount.rx++;
178
179 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
180 SAB82532_ISR0_FERR |
181 SAB82532_ISR0_RFO)) ||
182 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
183 /*
184 * For statistics only
185 */
186 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
187 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
188 SAB82532_ISR0_FERR);
189 up->port.icount.brk++;
190 /*
191 * We do the SysRQ and SAK checking
192 * here because otherwise the break
193 * may get masked by ignore_status_mask
194 * or read_status_mask.
195 */
196 if (uart_handle_break(&up->port))
197 continue;
198 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
199 up->port.icount.parity++;
200 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
201 up->port.icount.frame++;
202 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
203 up->port.icount.overrun++;
204
205 /*
206 * Mask off conditions which should be ingored.
207 */
208 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
209 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
210
211 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
212 *tty->flip.flag_buf_ptr = TTY_BREAK;
213 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
214 *tty->flip.flag_buf_ptr = TTY_PARITY;
215 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
216 *tty->flip.flag_buf_ptr = TTY_FRAME;
217 }
218
219 if (uart_handle_sysrq_char(&up->port, ch, regs))
220 continue;
221
222 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
223 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0){
224 tty->flip.flag_buf_ptr++;
225 tty->flip.char_buf_ptr++;
226 tty->flip.count++;
227 }
228 if ((stat->sreg.isr0 & SAB82532_ISR0_RFO) &&
229 tty->flip.count < TTY_FLIPBUF_SIZE) {
230 /*
231 * Overrun is special, since it's reported
232 * immediately, and doesn't affect the current
233 * character.
234 */
235 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
236 tty->flip.flag_buf_ptr++;
237 tty->flip.char_buf_ptr++;
238 tty->flip.count++;
239 }
240 }
241
242 if (saw_console_brk)
243 sun_do_break();
244
245 return tty;
246 }
247
248 static void sunsab_stop_tx(struct uart_port *, unsigned int);
249 static void sunsab_tx_idle(struct uart_sunsab_port *);
250
251 static void transmit_chars(struct uart_sunsab_port *up,
252 union sab82532_irq_status *stat)
253 {
254 struct circ_buf *xmit = &up->port.info->xmit;
255 int i;
256
257 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
258 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
259 writeb(up->interrupt_mask1, &up->regs->w.imr1);
260 set_bit(SAB82532_ALLS, &up->irqflags);
261 }
262
263 #if 0 /* bde@nwlink.com says this check causes problems */
264 if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
265 return;
266 #endif
267
268 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
269 return;
270
271 set_bit(SAB82532_XPR, &up->irqflags);
272 sunsab_tx_idle(up);
273
274 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
275 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
276 writeb(up->interrupt_mask1, &up->regs->w.imr1);
277 uart_write_wakeup(&up->port);
278 return;
279 }
280
281 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
282 writeb(up->interrupt_mask1, &up->regs->w.imr1);
283 clear_bit(SAB82532_ALLS, &up->irqflags);
284
285 /* Stuff 32 bytes into Transmit FIFO. */
286 clear_bit(SAB82532_XPR, &up->irqflags);
287 for (i = 0; i < up->port.fifosize; i++) {
288 writeb(xmit->buf[xmit->tail],
289 &up->regs->w.xfifo[i]);
290 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
291 up->port.icount.tx++;
292 if (uart_circ_empty(xmit))
293 break;
294 }
295
296 /* Issue a Transmit Frame command. */
297 sunsab_cec_wait(up);
298 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
299
300 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
301 uart_write_wakeup(&up->port);
302
303 if (uart_circ_empty(xmit))
304 sunsab_stop_tx(&up->port, 0);
305 }
306
307 static void check_status(struct uart_sunsab_port *up,
308 union sab82532_irq_status *stat)
309 {
310 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
311 uart_handle_dcd_change(&up->port,
312 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
313
314 if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
315 uart_handle_cts_change(&up->port,
316 (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
317
318 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
319 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
320 up->port.icount.dsr++;
321 }
322
323 wake_up_interruptible(&up->port.info->delta_msr_wait);
324 }
325
326 static irqreturn_t sunsab_interrupt(int irq, void *dev_id, struct pt_regs *regs)
327 {
328 struct uart_sunsab_port *up = dev_id;
329 struct tty_struct *tty;
330 union sab82532_irq_status status;
331 unsigned long flags;
332
333 spin_lock_irqsave(&up->port.lock, flags);
334
335 status.stat = 0;
336 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA0)
337 status.sreg.isr0 = readb(&up->regs->r.isr0);
338 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA1)
339 status.sreg.isr1 = readb(&up->regs->r.isr1);
340
341 tty = NULL;
342 if (status.stat) {
343 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
344 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
345 (status.sreg.isr1 & SAB82532_ISR1_BRK))
346 tty = receive_chars(up, &status, regs);
347 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
348 (status.sreg.isr1 & SAB82532_ISR1_CSC))
349 check_status(up, &status);
350 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
351 transmit_chars(up, &status);
352 }
353
354 spin_unlock(&up->port.lock);
355
356 if (tty)
357 tty_flip_buffer_push(tty);
358
359 up++;
360
361 spin_lock(&up->port.lock);
362
363 status.stat = 0;
364 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB0)
365 status.sreg.isr0 = readb(&up->regs->r.isr0);
366 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB1)
367 status.sreg.isr1 = readb(&up->regs->r.isr1);
368
369 tty = NULL;
370 if (status.stat) {
371 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
372 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
373 (status.sreg.isr1 & SAB82532_ISR1_BRK))
374
375 tty = receive_chars(up, &status, regs);
376 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
377 (status.sreg.isr1 & (SAB82532_ISR1_BRK | SAB82532_ISR1_CSC)))
378 check_status(up, &status);
379 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
380 transmit_chars(up, &status);
381 }
382
383 spin_unlock_irqrestore(&up->port.lock, flags);
384
385 if (tty)
386 tty_flip_buffer_push(tty);
387
388 return IRQ_HANDLED;
389 }
390
391 /* port->lock is not held. */
392 static unsigned int sunsab_tx_empty(struct uart_port *port)
393 {
394 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
395 int ret;
396
397 /* Do not need a lock for a state test like this. */
398 if (test_bit(SAB82532_ALLS, &up->irqflags))
399 ret = TIOCSER_TEMT;
400 else
401 ret = 0;
402
403 return ret;
404 }
405
406 /* port->lock held by caller. */
407 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
408 {
409 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
410
411 if (mctrl & TIOCM_RTS) {
412 up->cached_mode &= ~SAB82532_MODE_FRTS;
413 up->cached_mode |= SAB82532_MODE_RTS;
414 } else {
415 up->cached_mode |= (SAB82532_MODE_FRTS |
416 SAB82532_MODE_RTS);
417 }
418 if (mctrl & TIOCM_DTR) {
419 up->cached_pvr &= ~(up->pvr_dtr_bit);
420 } else {
421 up->cached_pvr |= up->pvr_dtr_bit;
422 }
423
424 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
425 if (test_bit(SAB82532_XPR, &up->irqflags))
426 sunsab_tx_idle(up);
427 }
428
429 /* port->lock is not held. */
430 static unsigned int sunsab_get_mctrl(struct uart_port *port)
431 {
432 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
433 unsigned long flags;
434 unsigned char val;
435 unsigned int result;
436
437 result = 0;
438
439 spin_lock_irqsave(&up->port.lock, flags);
440
441 val = readb(&up->regs->r.pvr);
442 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
443
444 val = readb(&up->regs->r.vstr);
445 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
446
447 val = readb(&up->regs->r.star);
448 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
449
450 spin_unlock_irqrestore(&up->port.lock, flags);
451
452 return result;
453 }
454
455 /* port->lock held by caller. */
456 static void sunsab_stop_tx(struct uart_port *port, unsigned int tty_stop)
457 {
458 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
459
460 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
461 writeb(up->interrupt_mask1, &up->regs->w.imr1);
462 }
463
464 /* port->lock held by caller. */
465 static void sunsab_tx_idle(struct uart_sunsab_port *up)
466 {
467 if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
468 u8 tmp;
469
470 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
471 writeb(up->cached_mode, &up->regs->rw.mode);
472 writeb(up->cached_pvr, &up->regs->rw.pvr);
473 writeb(up->cached_dafo, &up->regs->w.dafo);
474
475 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
476 tmp = readb(&up->regs->rw.ccr2);
477 tmp &= ~0xc0;
478 tmp |= (up->cached_ebrg >> 2) & 0xc0;
479 writeb(tmp, &up->regs->rw.ccr2);
480 }
481 }
482
483 /* port->lock held by caller. */
484 static void sunsab_start_tx(struct uart_port *port, unsigned int tty_start)
485 {
486 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
487 struct circ_buf *xmit = &up->port.info->xmit;
488 int i;
489
490 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
491 writeb(up->interrupt_mask1, &up->regs->w.imr1);
492
493 if (!test_bit(SAB82532_XPR, &up->irqflags))
494 return;
495
496 clear_bit(SAB82532_ALLS, &up->irqflags);
497 clear_bit(SAB82532_XPR, &up->irqflags);
498
499 for (i = 0; i < up->port.fifosize; i++) {
500 writeb(xmit->buf[xmit->tail],
501 &up->regs->w.xfifo[i]);
502 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
503 up->port.icount.tx++;
504 if (uart_circ_empty(xmit))
505 break;
506 }
507
508 /* Issue a Transmit Frame command. */
509 sunsab_cec_wait(up);
510 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
511 }
512
513 /* port->lock is not held. */
514 static void sunsab_send_xchar(struct uart_port *port, char ch)
515 {
516 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
517 unsigned long flags;
518
519 spin_lock_irqsave(&up->port.lock, flags);
520
521 sunsab_tec_wait(up);
522 writeb(ch, &up->regs->w.tic);
523
524 spin_unlock_irqrestore(&up->port.lock, flags);
525 }
526
527 /* port->lock held by caller. */
528 static void sunsab_stop_rx(struct uart_port *port)
529 {
530 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
531
532 up->interrupt_mask0 |= SAB82532_ISR0_TCD;
533 writeb(up->interrupt_mask1, &up->regs->w.imr0);
534 }
535
536 /* port->lock held by caller. */
537 static void sunsab_enable_ms(struct uart_port *port)
538 {
539 /* For now we always receive these interrupts. */
540 }
541
542 /* port->lock is not held. */
543 static void sunsab_break_ctl(struct uart_port *port, int break_state)
544 {
545 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
546 unsigned long flags;
547 unsigned char val;
548
549 spin_lock_irqsave(&up->port.lock, flags);
550
551 val = up->cached_dafo;
552 if (break_state)
553 val |= SAB82532_DAFO_XBRK;
554 else
555 val &= ~SAB82532_DAFO_XBRK;
556 up->cached_dafo = val;
557
558 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
559 if (test_bit(SAB82532_XPR, &up->irqflags))
560 sunsab_tx_idle(up);
561
562 spin_unlock_irqrestore(&up->port.lock, flags);
563 }
564
565 /* port->lock is not held. */
566 static int sunsab_startup(struct uart_port *port)
567 {
568 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
569 unsigned long flags;
570 unsigned char tmp;
571
572 spin_lock_irqsave(&up->port.lock, flags);
573
574 /*
575 * Wait for any commands or immediate characters
576 */
577 sunsab_cec_wait(up);
578 sunsab_tec_wait(up);
579
580 /*
581 * Clear the FIFO buffers.
582 */
583 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
584 sunsab_cec_wait(up);
585 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
586
587 /*
588 * Clear the interrupt registers.
589 */
590 (void) readb(&up->regs->r.isr0);
591 (void) readb(&up->regs->r.isr1);
592
593 /*
594 * Now, initialize the UART
595 */
596 writeb(0, &up->regs->w.ccr0); /* power-down */
597 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
598 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
599 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
600 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
601 SAB82532_CCR2_TOE, &up->regs->w.ccr2);
602 writeb(0, &up->regs->w.ccr3);
603 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
604 up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
605 SAB82532_MODE_RAC);
606 writeb(up->cached_mode, &up->regs->w.mode);
607 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
608
609 tmp = readb(&up->regs->rw.ccr0);
610 tmp |= SAB82532_CCR0_PU; /* power-up */
611 writeb(tmp, &up->regs->rw.ccr0);
612
613 /*
614 * Finally, enable interrupts
615 */
616 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
617 SAB82532_IMR0_PLLA);
618 writeb(up->interrupt_mask0, &up->regs->w.imr0);
619 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
620 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
621 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
622 SAB82532_IMR1_XPR);
623 writeb(up->interrupt_mask1, &up->regs->w.imr1);
624 set_bit(SAB82532_ALLS, &up->irqflags);
625 set_bit(SAB82532_XPR, &up->irqflags);
626
627 spin_unlock_irqrestore(&up->port.lock, flags);
628
629 return 0;
630 }
631
632 /* port->lock is not held. */
633 static void sunsab_shutdown(struct uart_port *port)
634 {
635 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
636 unsigned long flags;
637
638 spin_lock_irqsave(&up->port.lock, flags);
639
640 /* Disable Interrupts */
641 up->interrupt_mask0 = 0xff;
642 writeb(up->interrupt_mask0, &up->regs->w.imr0);
643 up->interrupt_mask1 = 0xff;
644 writeb(up->interrupt_mask1, &up->regs->w.imr1);
645
646 /* Disable break condition */
647 up->cached_dafo = readb(&up->regs->rw.dafo);
648 up->cached_dafo &= ~SAB82532_DAFO_XBRK;
649 writeb(up->cached_dafo, &up->regs->rw.dafo);
650
651 /* Disable Receiver */
652 up->cached_mode &= ~SAB82532_MODE_RAC;
653 writeb(up->cached_mode, &up->regs->rw.mode);
654
655 /*
656 * XXX FIXME
657 *
658 * If the chip is powered down here the system hangs/crashes during
659 * reboot or shutdown. This needs to be investigated further,
660 * similar behaviour occurs in 2.4 when the driver is configured
661 * as a module only. One hint may be that data is sometimes
662 * transmitted at 9600 baud during shutdown (regardless of the
663 * speed the chip was configured for when the port was open).
664 */
665 #if 0
666 /* Power Down */
667 tmp = readb(&up->regs->rw.ccr0);
668 tmp &= ~SAB82532_CCR0_PU;
669 writeb(tmp, &up->regs->rw.ccr0);
670 #endif
671
672 spin_unlock_irqrestore(&up->port.lock, flags);
673 }
674
675 /*
676 * This is used to figure out the divisor speeds.
677 *
678 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
679 *
680 * with 0 <= N < 64 and 0 <= M < 16
681 */
682
683 static void calc_ebrg(int baud, int *n_ret, int *m_ret)
684 {
685 int n, m;
686
687 if (baud == 0) {
688 *n_ret = 0;
689 *m_ret = 0;
690 return;
691 }
692
693 /*
694 * We scale numbers by 10 so that we get better accuracy
695 * without having to use floating point. Here we increment m
696 * until n is within the valid range.
697 */
698 n = (SAB_BASE_BAUD * 10) / baud;
699 m = 0;
700 while (n >= 640) {
701 n = n / 2;
702 m++;
703 }
704 n = (n+5) / 10;
705 /*
706 * We try very hard to avoid speeds with M == 0 since they may
707 * not work correctly for XTAL frequences above 10 MHz.
708 */
709 if ((m == 0) && ((n & 1) == 0)) {
710 n = n / 2;
711 m++;
712 }
713 *n_ret = n - 1;
714 *m_ret = m;
715 }
716
717 /* Internal routine, port->lock is held and local interrupts are disabled. */
718 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
719 unsigned int iflag, unsigned int baud,
720 unsigned int quot)
721 {
722 unsigned char dafo;
723 int bits, n, m;
724
725 /* Byte size and parity */
726 switch (cflag & CSIZE) {
727 case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
728 case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
729 case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
730 case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
731 /* Never happens, but GCC is too dumb to figure it out */
732 default: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
733 }
734
735 if (cflag & CSTOPB) {
736 dafo |= SAB82532_DAFO_STOP;
737 bits++;
738 }
739
740 if (cflag & PARENB) {
741 dafo |= SAB82532_DAFO_PARE;
742 bits++;
743 }
744
745 if (cflag & PARODD) {
746 dafo |= SAB82532_DAFO_PAR_ODD;
747 } else {
748 dafo |= SAB82532_DAFO_PAR_EVEN;
749 }
750 up->cached_dafo = dafo;
751
752 calc_ebrg(baud, &n, &m);
753
754 up->cached_ebrg = n | (m << 6);
755
756 up->tec_timeout = (10 * 1000000) / baud;
757 up->cec_timeout = up->tec_timeout >> 2;
758
759 /* CTS flow control flags */
760 /* We encode read_status_mask and ignore_status_mask like so:
761 *
762 * ---------------------
763 * | ... | ISR1 | ISR0 |
764 * ---------------------
765 * .. 15 8 7 0
766 */
767
768 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
769 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
770 SAB82532_ISR0_CDSC);
771 up->port.read_status_mask |= (SAB82532_ISR1_CSC |
772 SAB82532_ISR1_ALLS |
773 SAB82532_ISR1_XPR) << 8;
774 if (iflag & INPCK)
775 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
776 SAB82532_ISR0_FERR);
777 if (iflag & (BRKINT | PARMRK))
778 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
779
780 /*
781 * Characteres to ignore
782 */
783 up->port.ignore_status_mask = 0;
784 if (iflag & IGNPAR)
785 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
786 SAB82532_ISR0_FERR);
787 if (iflag & IGNBRK) {
788 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
789 /*
790 * If we're ignoring parity and break indicators,
791 * ignore overruns too (for real raw support).
792 */
793 if (iflag & IGNPAR)
794 up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
795 }
796
797 /*
798 * ignore all characters if CREAD is not set
799 */
800 if ((cflag & CREAD) == 0)
801 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
802 SAB82532_ISR0_TCD);
803
804 uart_update_timeout(&up->port, cflag,
805 (up->port.uartclk / (16 * quot)));
806
807 /* Now schedule a register update when the chip's
808 * transmitter is idle.
809 */
810 up->cached_mode |= SAB82532_MODE_RAC;
811 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
812 if (test_bit(SAB82532_XPR, &up->irqflags))
813 sunsab_tx_idle(up);
814 }
815
816 /* port->lock is not held. */
817 static void sunsab_set_termios(struct uart_port *port, struct termios *termios,
818 struct termios *old)
819 {
820 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
821 unsigned long flags;
822 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
823 unsigned int quot = uart_get_divisor(port, baud);
824
825 spin_lock_irqsave(&up->port.lock, flags);
826 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
827 spin_unlock_irqrestore(&up->port.lock, flags);
828 }
829
830 static const char *sunsab_type(struct uart_port *port)
831 {
832 struct uart_sunsab_port *up = (void *)port;
833 static char buf[36];
834
835 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
836 return buf;
837 }
838
839 static void sunsab_release_port(struct uart_port *port)
840 {
841 }
842
843 static int sunsab_request_port(struct uart_port *port)
844 {
845 return 0;
846 }
847
848 static void sunsab_config_port(struct uart_port *port, int flags)
849 {
850 }
851
852 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
853 {
854 return -EINVAL;
855 }
856
857 static struct uart_ops sunsab_pops = {
858 .tx_empty = sunsab_tx_empty,
859 .set_mctrl = sunsab_set_mctrl,
860 .get_mctrl = sunsab_get_mctrl,
861 .stop_tx = sunsab_stop_tx,
862 .start_tx = sunsab_start_tx,
863 .send_xchar = sunsab_send_xchar,
864 .stop_rx = sunsab_stop_rx,
865 .enable_ms = sunsab_enable_ms,
866 .break_ctl = sunsab_break_ctl,
867 .startup = sunsab_startup,
868 .shutdown = sunsab_shutdown,
869 .set_termios = sunsab_set_termios,
870 .type = sunsab_type,
871 .release_port = sunsab_release_port,
872 .request_port = sunsab_request_port,
873 .config_port = sunsab_config_port,
874 .verify_port = sunsab_verify_port,
875 };
876
877 static struct uart_driver sunsab_reg = {
878 .owner = THIS_MODULE,
879 .driver_name = "serial",
880 .devfs_name = "tts/",
881 .dev_name = "ttyS",
882 .major = TTY_MAJOR,
883 };
884
885 static struct uart_sunsab_port *sunsab_ports;
886 static int num_channels;
887
888 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
889
890 static __inline__ void sunsab_console_putchar(struct uart_sunsab_port *up, char c)
891 {
892 unsigned long flags;
893
894 spin_lock_irqsave(&up->port.lock, flags);
895
896 sunsab_tec_wait(up);
897 writeb(c, &up->regs->w.tic);
898
899 spin_unlock_irqrestore(&up->port.lock, flags);
900 }
901
902 static void sunsab_console_write(struct console *con, const char *s, unsigned n)
903 {
904 struct uart_sunsab_port *up = &sunsab_ports[con->index];
905 int i;
906
907 for (i = 0; i < n; i++) {
908 if (*s == '\n')
909 sunsab_console_putchar(up, '\r');
910 sunsab_console_putchar(up, *s++);
911 }
912 sunsab_tec_wait(up);
913 }
914
915 static int sunsab_console_setup(struct console *con, char *options)
916 {
917 struct uart_sunsab_port *up = &sunsab_ports[con->index];
918 unsigned long flags;
919 unsigned int baud, quot;
920
921 printk("Console: ttyS%d (SAB82532)\n",
922 (sunsab_reg.minor - 64) + con->index);
923
924 sunserial_console_termios(con);
925
926 /* Firmware console speed is limited to 150-->38400 baud so
927 * this hackish cflag thing is OK.
928 */
929 switch (con->cflag & CBAUD) {
930 case B150: baud = 150; break;
931 case B300: baud = 300; break;
932 case B600: baud = 600; break;
933 case B1200: baud = 1200; break;
934 case B2400: baud = 2400; break;
935 case B4800: baud = 4800; break;
936 default: case B9600: baud = 9600; break;
937 case B19200: baud = 19200; break;
938 case B38400: baud = 38400; break;
939 };
940
941 /*
942 * Temporary fix.
943 */
944 spin_lock_init(&up->port.lock);
945
946 /*
947 * Initialize the hardware
948 */
949 sunsab_startup(&up->port);
950
951 spin_lock_irqsave(&up->port.lock, flags);
952
953 /*
954 * Finally, enable interrupts
955 */
956 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
957 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
958 writeb(up->interrupt_mask0, &up->regs->w.imr0);
959 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
960 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
961 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
962 SAB82532_IMR1_XPR;
963 writeb(up->interrupt_mask1, &up->regs->w.imr1);
964
965 quot = uart_get_divisor(&up->port, baud);
966 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
967 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
968
969 spin_unlock_irqrestore(&up->port.lock, flags);
970
971 return 0;
972 }
973
974 static struct console sunsab_console = {
975 .name = "ttyS",
976 .write = sunsab_console_write,
977 .device = uart_console_device,
978 .setup = sunsab_console_setup,
979 .flags = CON_PRINTBUFFER,
980 .index = -1,
981 .data = &sunsab_reg,
982 };
983 #define SUNSAB_CONSOLE (&sunsab_console)
984
985 static void __init sunsab_console_init(void)
986 {
987 int i;
988
989 if (con_is_present())
990 return;
991
992 for (i = 0; i < num_channels; i++) {
993 int this_minor = sunsab_reg.minor + i;
994
995 if ((this_minor - 64) == (serial_console - 1))
996 break;
997 }
998 if (i == num_channels)
999 return;
1000
1001 sunsab_console.index = i;
1002 register_console(&sunsab_console);
1003 }
1004 #else
1005 #define SUNSAB_CONSOLE (NULL)
1006 #define sunsab_console_init() do { } while (0)
1007 #endif
1008
1009 static void __init for_each_sab_edev(void (*callback)(struct linux_ebus_device *, void *), void *arg)
1010 {
1011 struct linux_ebus *ebus;
1012 struct linux_ebus_device *edev = NULL;
1013
1014 for_each_ebus(ebus) {
1015 for_each_ebusdev(edev, ebus) {
1016 if (!strcmp(edev->prom_name, "se")) {
1017 callback(edev, arg);
1018 continue;
1019 } else if (!strcmp(edev->prom_name, "serial")) {
1020 char compat[32];
1021 int clen;
1022
1023 /* On RIO this can be an SE, check it. We could
1024 * just check ebus->is_rio, but this is more portable.
1025 */
1026 clen = prom_getproperty(edev->prom_node, "compatible",
1027 compat, sizeof(compat));
1028 if (clen > 0) {
1029 if (strncmp(compat, "sab82532", 8) == 0) {
1030 callback(edev, arg);
1031 continue;
1032 }
1033 }
1034 }
1035 }
1036 }
1037 }
1038
1039 static void __init sab_count_callback(struct linux_ebus_device *edev, void *arg)
1040 {
1041 int *count_p = arg;
1042
1043 (*count_p)++;
1044 }
1045
1046 static void __init sab_attach_callback(struct linux_ebus_device *edev, void *arg)
1047 {
1048 int *instance_p = arg;
1049 struct uart_sunsab_port *up;
1050 unsigned long regs, offset;
1051 int i;
1052
1053 /* Note: ports are located in reverse order */
1054 regs = edev->resource[0].start;
1055 offset = sizeof(union sab82532_async_regs);
1056 for (i = 0; i < 2; i++) {
1057 up = &sunsab_ports[(*instance_p * 2) + 1 - i];
1058
1059 memset(up, 0, sizeof(*up));
1060 up->regs = ioremap(regs + offset, sizeof(union sab82532_async_regs));
1061 up->port.irq = edev->irqs[0];
1062 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
1063 up->port.mapbase = (unsigned long)up->regs;
1064 up->port.iotype = SERIAL_IO_MEM;
1065
1066 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
1067
1068 offset -= sizeof(union sab82532_async_regs);
1069 }
1070
1071 (*instance_p)++;
1072 }
1073
1074 static int __init probe_for_sabs(void)
1075 {
1076 int this_sab = 0;
1077
1078 /* Find device instances. */
1079 for_each_sab_edev(&sab_count_callback, &this_sab);
1080 if (!this_sab)
1081 return -ENODEV;
1082
1083 /* Allocate tables. */
1084 sunsab_ports = kmalloc(sizeof(struct uart_sunsab_port) * this_sab * 2,
1085 GFP_KERNEL);
1086 if (!sunsab_ports)
1087 return -ENOMEM;
1088
1089 num_channels = this_sab * 2;
1090
1091 this_sab = 0;
1092 for_each_sab_edev(&sab_attach_callback, &this_sab);
1093 return 0;
1094 }
1095
1096 static void __init sunsab_init_hw(void)
1097 {
1098 int i;
1099
1100 for (i = 0; i < num_channels; i++) {
1101 struct uart_sunsab_port *up = &sunsab_ports[i];
1102
1103 up->port.line = i;
1104 up->port.ops = &sunsab_pops;
1105 up->port.type = PORT_SUNSAB;
1106 up->port.uartclk = SAB_BASE_BAUD;
1107
1108 up->type = readb(&up->regs->r.vstr) & 0x0f;
1109 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
1110 writeb(0xff, &up->regs->w.pim);
1111 if (up->port.line == 0) {
1112 up->pvr_dsr_bit = (1 << 0);
1113 up->pvr_dtr_bit = (1 << 1);
1114 } else {
1115 up->pvr_dsr_bit = (1 << 3);
1116 up->pvr_dtr_bit = (1 << 2);
1117 }
1118 up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
1119 writeb(up->cached_pvr, &up->regs->w.pvr);
1120 up->cached_mode = readb(&up->regs->rw.mode);
1121 up->cached_mode |= SAB82532_MODE_FRTS;
1122 writeb(up->cached_mode, &up->regs->rw.mode);
1123 up->cached_mode |= SAB82532_MODE_RTS;
1124 writeb(up->cached_mode, &up->regs->rw.mode);
1125
1126 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1127 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1128
1129 if (!(up->port.line & 0x01)) {
1130 if (request_irq(up->port.irq, sunsab_interrupt,
1131 SA_SHIRQ, "serial(sab82532)", up)) {
1132 printk("sunsab%d: can't get IRQ %x\n",
1133 i, up->port.irq);
1134 continue;
1135 }
1136 }
1137 }
1138 }
1139
1140 static int __init sunsab_init(void)
1141 {
1142 int ret = probe_for_sabs();
1143 int i;
1144
1145 if (ret < 0)
1146 return ret;
1147
1148 sunsab_init_hw();
1149
1150 sunsab_reg.minor = sunserial_current_minor;
1151 sunsab_reg.nr = num_channels;
1152 sunsab_reg.cons = SUNSAB_CONSOLE;
1153
1154 ret = uart_register_driver(&sunsab_reg);
1155 if (ret < 0) {
1156 int i;
1157
1158 for (i = 0; i < num_channels; i++) {
1159 struct uart_sunsab_port *up = &sunsab_ports[i];
1160
1161 if (!(up->port.line & 0x01))
1162 free_irq(up->port.irq, up);
1163 iounmap(up->regs);
1164 }
1165 kfree(sunsab_ports);
1166 sunsab_ports = NULL;
1167
1168 return ret;
1169 }
1170
1171 sunserial_current_minor += num_channels;
1172
1173 sunsab_console_init();
1174
1175 for (i = 0; i < num_channels; i++) {
1176 struct uart_sunsab_port *up = &sunsab_ports[i];
1177
1178 uart_add_one_port(&sunsab_reg, &up->port);
1179 }
1180
1181 return 0;
1182 }
1183
1184 static void __exit sunsab_exit(void)
1185 {
1186 int i;
1187
1188 for (i = 0; i < num_channels; i++) {
1189 struct uart_sunsab_port *up = &sunsab_ports[i];
1190
1191 uart_remove_one_port(&sunsab_reg, &up->port);
1192
1193 if (!(up->port.line & 0x01))
1194 free_irq(up->port.irq, up);
1195 iounmap(up->regs);
1196 }
1197
1198 sunserial_current_minor -= num_channels;
1199 uart_unregister_driver(&sunsab_reg);
1200
1201 kfree(sunsab_ports);
1202 sunsab_ports = NULL;
1203 }
1204
1205 module_init(sunsab_init);
1206 module_exit(sunsab_exit);
1207
1208 MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1209 MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1210 MODULE_LICENSE("GPL");
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