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[PATCH] aic7xxx_osm build fix
[cris-mirror.git] / drivers / usb / gadget / pxa2xx_udc.c
blob6390c5726d81ce50eecfd9c2791064ed564fecae
1 /*
2 * linux/drivers/usb/gadget/pxa2xx_udc.c
3 * Intel PXA2xx and IXP4xx on-chip full speed USB device controllers
4 *
5 * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
6 * Copyright (C) 2003 Robert Schwebel, Pengutronix
7 * Copyright (C) 2003 Benedikt Spranger, Pengutronix
8 * Copyright (C) 2003 David Brownell
9 * Copyright (C) 2003 Joshua Wise
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 */
26
27 #undef DEBUG
28 // #define VERBOSE DBG_VERBOSE
29
30 #include <linux/config.h>
31 #include <linux/module.h>
32 #include <linux/kernel.h>
33 #include <linux/ioport.h>
34 #include <linux/types.h>
35 #include <linux/version.h>
36 #include <linux/errno.h>
37 #include <linux/delay.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/init.h>
41 #include <linux/timer.h>
42 #include <linux/list.h>
43 #include <linux/interrupt.h>
44 #include <linux/proc_fs.h>
45 #include <linux/mm.h>
46 #include <linux/device.h>
47 #include <linux/dma-mapping.h>
48
49 #include <asm/byteorder.h>
50 #include <asm/dma.h>
51 #include <asm/io.h>
52 #include <asm/irq.h>
53 #include <asm/system.h>
54 #include <asm/mach-types.h>
55 #include <asm/unaligned.h>
56 #include <asm/hardware.h>
57 #include <asm/arch/pxa-regs.h>
58
59 #include <linux/usb_ch9.h>
60 #include <linux/usb_gadget.h>
61
62 #include <asm/arch/udc.h>
63
64
65 /*
66 * This driver handles the USB Device Controller (UDC) in Intel's PXA 2xx
67 * series processors. The UDC for the IXP 4xx series is very similar.
68 * There are fifteen endpoints, in addition to ep0.
69 *
70 * Such controller drivers work with a gadget driver. The gadget driver
71 * returns descriptors, implements configuration and data protocols used
72 * by the host to interact with this device, and allocates endpoints to
73 * the different protocol interfaces. The controller driver virtualizes
74 * usb hardware so that the gadget drivers will be more portable.
75 *
76 * This UDC hardware wants to implement a bit too much USB protocol, so
77 * it constrains the sorts of USB configuration change events that work.
78 * The errata for these chips are misleading; some "fixed" bugs from
79 * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
80 */
81
82 #define DRIVER_VERSION "14-Dec-2003"
83 #define DRIVER_DESC "PXA 2xx USB Device Controller driver"
84
85
86 static const char driver_name [] = "pxa2xx_udc";
87
88 static const char ep0name [] = "ep0";
89
90
91 // #define USE_DMA
92 // #define USE_OUT_DMA
93 // #define DISABLE_TEST_MODE
94
95 #ifdef CONFIG_ARCH_IXP4XX
96 #undef USE_DMA
97
98 /* cpu-specific register addresses are compiled in to this code */
99 #ifdef CONFIG_ARCH_PXA
100 #error "Can't configure both IXP and PXA"
101 #endif
102
103 #endif
104
105 #include "pxa2xx_udc.h"
106
107
108 #ifdef USE_DMA
109 static int use_dma = 1;
110 module_param(use_dma, bool, 0);
111 MODULE_PARM_DESC (use_dma, "true to use dma");
112
113 static void dma_nodesc_handler (int dmach, void *_ep, struct pt_regs *r);
114 static void kick_dma(struct pxa2xx_ep *ep, struct pxa2xx_request *req);
115
116 #ifdef USE_OUT_DMA
117 #define DMASTR " (dma support)"
118 #else
119 #define DMASTR " (dma in)"
120 #endif
121
122 #else /* !USE_DMA */
123 #define DMASTR " (pio only)"
124 #undef USE_OUT_DMA
125 #endif
126
127 #ifdef CONFIG_USB_PXA2XX_SMALL
128 #define SIZE_STR " (small)"
129 #else
130 #define SIZE_STR ""
131 #endif
132
133 #ifdef DISABLE_TEST_MODE
134 /* (mode == 0) == no undocumented chip tweaks
135 * (mode & 1) == double buffer bulk IN
136 * (mode & 2) == double buffer bulk OUT
137 * ... so mode = 3 (or 7, 15, etc) does it for both
138 */
139 static ushort fifo_mode = 0;
140 module_param(fifo_mode, ushort, 0);
141 MODULE_PARM_DESC (fifo_mode, "pxa2xx udc fifo mode");
142 #endif
143
144 /* ---------------------------------------------------------------------------
145 * endpoint related parts of the api to the usb controller hardware,
146 * used by gadget driver; and the inner talker-to-hardware core.
147 * ---------------------------------------------------------------------------
148 */
149
150 static void pxa2xx_ep_fifo_flush (struct usb_ep *ep);
151 static void nuke (struct pxa2xx_ep *, int status);
152
153 static void pio_irq_enable(int bEndpointAddress)
154 {
155 bEndpointAddress &= 0xf;
156 if (bEndpointAddress < 8)
157 UICR0 &= ~(1 << bEndpointAddress);
158 else {
159 bEndpointAddress -= 8;
160 UICR1 &= ~(1 << bEndpointAddress);
161 }
162 }
163
164 static void pio_irq_disable(int bEndpointAddress)
165 {
166 bEndpointAddress &= 0xf;
167 if (bEndpointAddress < 8)
168 UICR0 |= 1 << bEndpointAddress;
169 else {
170 bEndpointAddress -= 8;
171 UICR1 |= 1 << bEndpointAddress;
172 }
173 }
174
175 /* The UDCCR reg contains mask and interrupt status bits,
176 * so using '|=' isn't safe as it may ack an interrupt.
177 */
178 #define UDCCR_MASK_BITS (UDCCR_REM | UDCCR_SRM | UDCCR_UDE)
179
180 static inline void udc_set_mask_UDCCR(int mask)
181 {
182 UDCCR = (UDCCR & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS);
183 }
184
185 static inline void udc_clear_mask_UDCCR(int mask)
186 {
187 UDCCR = (UDCCR & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS);
188 }
189
190 static inline void udc_ack_int_UDCCR(int mask)
191 {
192 /* udccr contains the bits we dont want to change */
193 __u32 udccr = UDCCR & UDCCR_MASK_BITS;
194
195 UDCCR = udccr | (mask & ~UDCCR_MASK_BITS);
196 }
197
198 /*
199 * endpoint enable/disable
200 *
201 * we need to verify the descriptors used to enable endpoints. since pxa2xx
202 * endpoint configurations are fixed, and are pretty much always enabled,
203 * there's not a lot to manage here.
204 *
205 * because pxa2xx can't selectively initialize bulk (or interrupt) endpoints,
206 * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
207 * for a single interface (with only the default altsetting) and for gadget
208 * drivers that don't halt endpoints (not reset by set_interface). that also
209 * means that if you use ISO, you must violate the USB spec rule that all
210 * iso endpoints must be in non-default altsettings.
211 */
212 static int pxa2xx_ep_enable (struct usb_ep *_ep,
213 const struct usb_endpoint_descriptor *desc)
214 {
215 struct pxa2xx_ep *ep;
216 struct pxa2xx_udc *dev;
217
218 ep = container_of (_ep, struct pxa2xx_ep, ep);
219 if (!_ep || !desc || ep->desc || _ep->name == ep0name
220 || desc->bDescriptorType != USB_DT_ENDPOINT
221 || ep->bEndpointAddress != desc->bEndpointAddress
222 || ep->fifo_size < le16_to_cpu
223 (desc->wMaxPacketSize)) {
224 DMSG("%s, bad ep or descriptor\n", __FUNCTION__);
225 return -EINVAL;
226 }
227
228 /* xfer types must match, except that interrupt ~= bulk */
229 if (ep->bmAttributes != desc->bmAttributes
230 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
231 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
232 DMSG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
233 return -EINVAL;
234 }
235
236 /* hardware _could_ do smaller, but driver doesn't */
237 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
238 && le16_to_cpu (desc->wMaxPacketSize)
239 != BULK_FIFO_SIZE)
240 || !desc->wMaxPacketSize) {
241 DMSG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
242 return -ERANGE;
243 }
244
245 dev = ep->dev;
246 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
247 DMSG("%s, bogus device state\n", __FUNCTION__);
248 return -ESHUTDOWN;
249 }
250
251 ep->desc = desc;
252 ep->dma = -1;
253 ep->stopped = 0;
254 ep->pio_irqs = ep->dma_irqs = 0;
255 ep->ep.maxpacket = le16_to_cpu (desc->wMaxPacketSize);
256
257 /* flush fifo (mostly for OUT buffers) */
258 pxa2xx_ep_fifo_flush (_ep);
259
260 /* ... reset halt state too, if we could ... */
261
262 #ifdef USE_DMA
263 /* for (some) bulk and ISO endpoints, try to get a DMA channel and
264 * bind it to the endpoint. otherwise use PIO.
265 */
266 switch (ep->bmAttributes) {
267 case USB_ENDPOINT_XFER_ISOC:
268 if (le16_to_cpu(desc->wMaxPacketSize) % 32)
269 break;
270 // fall through
271 case USB_ENDPOINT_XFER_BULK:
272 if (!use_dma || !ep->reg_drcmr)
273 break;
274 ep->dma = pxa_request_dma ((char *)_ep->name,
275 (le16_to_cpu (desc->wMaxPacketSize) > 64)
276 ? DMA_PRIO_MEDIUM /* some iso */
277 : DMA_PRIO_LOW,
278 dma_nodesc_handler, ep);
279 if (ep->dma >= 0) {
280 *ep->reg_drcmr = DRCMR_MAPVLD | ep->dma;
281 DMSG("%s using dma%d\n", _ep->name, ep->dma);
282 }
283 }
284 #endif
285
286 DBG(DBG_VERBOSE, "enabled %s\n", _ep->name);
287 return 0;
288 }
289
290 static int pxa2xx_ep_disable (struct usb_ep *_ep)
291 {
292 struct pxa2xx_ep *ep;
293
294 ep = container_of (_ep, struct pxa2xx_ep, ep);
295 if (!_ep || !ep->desc) {
296 DMSG("%s, %s not enabled\n", __FUNCTION__,
297 _ep ? ep->ep.name : NULL);
298 return -EINVAL;
299 }
300 nuke (ep, -ESHUTDOWN);
301
302 #ifdef USE_DMA
303 if (ep->dma >= 0) {
304 *ep->reg_drcmr = 0;
305 pxa_free_dma (ep->dma);
306 ep->dma = -1;
307 }
308 #endif
309
310 /* flush fifo (mostly for IN buffers) */
311 pxa2xx_ep_fifo_flush (_ep);
312
313 ep->desc = NULL;
314 ep->stopped = 1;
315
316 DBG(DBG_VERBOSE, "%s disabled\n", _ep->name);
317 return 0;
318 }
319
320 /*-------------------------------------------------------------------------*/
321
322 /* for the pxa2xx, these can just wrap kmalloc/kfree. gadget drivers
323 * must still pass correctly initialized endpoints, since other controller
324 * drivers may care about how it's currently set up (dma issues etc).
325 */
326
327 /*
328 * pxa2xx_ep_alloc_request - allocate a request data structure
329 */
330 static struct usb_request *
331 pxa2xx_ep_alloc_request (struct usb_ep *_ep, int gfp_flags)
332 {
333 struct pxa2xx_request *req;
334
335 req = kmalloc (sizeof *req, gfp_flags);
336 if (!req)
337 return NULL;
338
339 memset (req, 0, sizeof *req);
340 INIT_LIST_HEAD (&req->queue);
341 return &req->req;
342 }
343
344
345 /*
346 * pxa2xx_ep_free_request - deallocate a request data structure
347 */
348 static void
349 pxa2xx_ep_free_request (struct usb_ep *_ep, struct usb_request *_req)
350 {
351 struct pxa2xx_request *req;
352
353 req = container_of (_req, struct pxa2xx_request, req);
354 WARN_ON (!list_empty (&req->queue));
355 kfree(req);
356 }
357
358
359 /* PXA cache needs flushing with DMA I/O (it's dma-incoherent), but there's
360 * no device-affinity and the heap works perfectly well for i/o buffers.
361 * It wastes much less memory than dma_alloc_coherent() would, and even
362 * prevents cacheline (32 bytes wide) sharing problems.
363 */
364 static void *
365 pxa2xx_ep_alloc_buffer(struct usb_ep *_ep, unsigned bytes,
366 dma_addr_t *dma, int gfp_flags)
367 {
368 char *retval;
369
370 retval = kmalloc (bytes, gfp_flags & ~(__GFP_DMA|__GFP_HIGHMEM));
371 if (retval)
372 #ifdef USE_DMA
373 *dma = virt_to_bus (retval);
374 #else
375 *dma = (dma_addr_t)~0;
376 #endif
377 return retval;
378 }
379
380 static void
381 pxa2xx_ep_free_buffer(struct usb_ep *_ep, void *buf, dma_addr_t dma,
382 unsigned bytes)
383 {
384 kfree (buf);
385 }
386
387 /*-------------------------------------------------------------------------*/
388
389 /*
390 * done - retire a request; caller blocked irqs
391 */
392 static void done(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int status)
393 {
394 unsigned stopped = ep->stopped;
395
396 list_del_init(&req->queue);
397
398 if (likely (req->req.status == -EINPROGRESS))
399 req->req.status = status;
400 else
401 status = req->req.status;
402
403 if (status && status != -ESHUTDOWN)
404 DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n",
405 ep->ep.name, &req->req, status,
406 req->req.actual, req->req.length);
407
408 /* don't modify queue heads during completion callback */
409 ep->stopped = 1;
410 req->req.complete(&ep->ep, &req->req);
411 ep->stopped = stopped;
412 }
413
414
415 static inline void ep0_idle (struct pxa2xx_udc *dev)
416 {
417 dev->ep0state = EP0_IDLE;
418 }
419
420 static int
421 write_packet(volatile u32 *uddr, struct pxa2xx_request *req, unsigned max)
422 {
423 u8 *buf;
424 unsigned length, count;
425
426 buf = req->req.buf + req->req.actual;
427 prefetch(buf);
428
429 /* how big will this packet be? */
430 length = min(req->req.length - req->req.actual, max);
431 req->req.actual += length;
432
433 count = length;
434 while (likely(count--))
435 *uddr = *buf++;
436
437 return length;
438 }
439
440 /*
441 * write to an IN endpoint fifo, as many packets as possible.
442 * irqs will use this to write the rest later.
443 * caller guarantees at least one packet buffer is ready (or a zlp).
444 */
445 static int
446 write_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
447 {
448 unsigned max;
449
450 max = le16_to_cpu(ep->desc->wMaxPacketSize);
451 do {
452 unsigned count;
453 int is_last, is_short;
454
455 count = write_packet(ep->reg_uddr, req, max);
456
457 /* last packet is usually short (or a zlp) */
458 if (unlikely (count != max))
459 is_last = is_short = 1;
460 else {
461 if (likely(req->req.length != req->req.actual)
462 || req->req.zero)
463 is_last = 0;
464 else
465 is_last = 1;
466 /* interrupt/iso maxpacket may not fill the fifo */
467 is_short = unlikely (max < ep->fifo_size);
468 }
469
470 DBG(DBG_VERY_NOISY, "wrote %s %d bytes%s%s %d left %p\n",
471 ep->ep.name, count,
472 is_last ? "/L" : "", is_short ? "/S" : "",
473 req->req.length - req->req.actual, req);
474
475 /* let loose that packet. maybe try writing another one,
476 * double buffering might work. TSP, TPC, and TFS
477 * bit values are the same for all normal IN endpoints.
478 */
479 *ep->reg_udccs = UDCCS_BI_TPC;
480 if (is_short)
481 *ep->reg_udccs = UDCCS_BI_TSP;
482
483 /* requests complete when all IN data is in the FIFO */
484 if (is_last) {
485 done (ep, req, 0);
486 if (list_empty(&ep->queue) || unlikely(ep->dma >= 0)) {
487 pio_irq_disable (ep->bEndpointAddress);
488 #ifdef USE_DMA
489 /* unaligned data and zlps couldn't use dma */
490 if (unlikely(!list_empty(&ep->queue))) {
491 req = list_entry(ep->queue.next,
492 struct pxa2xx_request, queue);
493 kick_dma(ep,req);
494 return 0;
495 }
496 #endif
497 }
498 return 1;
499 }
500
501 // TODO experiment: how robust can fifo mode tweaking be?
502 // double buffering is off in the default fifo mode, which
503 // prevents TFS from being set here.
504
505 } while (*ep->reg_udccs & UDCCS_BI_TFS);
506 return 0;
507 }
508
509 /* caller asserts req->pending (ep0 irq status nyet cleared); starts
510 * ep0 data stage. these chips want very simple state transitions.
511 */
512 static inline
513 void ep0start(struct pxa2xx_udc *dev, u32 flags, const char *tag)
514 {
515 UDCCS0 = flags|UDCCS0_SA|UDCCS0_OPR;
516 USIR0 = USIR0_IR0;
517 dev->req_pending = 0;
518 DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n",
519 __FUNCTION__, tag, UDCCS0, flags);
520 }
521
522 static int
523 write_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
524 {
525 unsigned count;
526 int is_short;
527
528 count = write_packet(&UDDR0, req, EP0_FIFO_SIZE);
529 ep->dev->stats.write.bytes += count;
530
531 /* last packet "must be" short (or a zlp) */
532 is_short = (count != EP0_FIFO_SIZE);
533
534 DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n", count,
535 req->req.length - req->req.actual, req);
536
537 if (unlikely (is_short)) {
538 if (ep->dev->req_pending)
539 ep0start(ep->dev, UDCCS0_IPR, "short IN");
540 else
541 UDCCS0 = UDCCS0_IPR;
542
543 count = req->req.length;
544 done (ep, req, 0);
545 ep0_idle(ep->dev);
546 #if 1
547 /* This seems to get rid of lost status irqs in some cases:
548 * host responds quickly, or next request involves config
549 * change automagic, or should have been hidden, or ...
550 *
551 * FIXME get rid of all udelays possible...
552 */
553 if (count >= EP0_FIFO_SIZE) {
554 count = 100;
555 do {
556 if ((UDCCS0 & UDCCS0_OPR) != 0) {
557 /* clear OPR, generate ack */
558 UDCCS0 = UDCCS0_OPR;
559 break;
560 }
561 count--;
562 udelay(1);
563 } while (count);
564 }
565 #endif
566 } else if (ep->dev->req_pending)
567 ep0start(ep->dev, 0, "IN");
568 return is_short;
569 }
570
571
572 /*
573 * read_fifo - unload packet(s) from the fifo we use for usb OUT
574 * transfers and put them into the request. caller should have made
575 * sure there's at least one packet ready.
576 *
577 * returns true if the request completed because of short packet or the
578 * request buffer having filled (and maybe overran till end-of-packet).
579 */
580 static int
581 read_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
582 {
583 for (;;) {
584 u32 udccs;
585 u8 *buf;
586 unsigned bufferspace, count, is_short;
587
588 /* make sure there's a packet in the FIFO.
589 * UDCCS_{BO,IO}_RPC are all the same bit value.
590 * UDCCS_{BO,IO}_RNE are all the same bit value.
591 */
592 udccs = *ep->reg_udccs;
593 if (unlikely ((udccs & UDCCS_BO_RPC) == 0))
594 break;
595 buf = req->req.buf + req->req.actual;
596 prefetchw(buf);
597 bufferspace = req->req.length - req->req.actual;
598
599 /* read all bytes from this packet */
600 if (likely (udccs & UDCCS_BO_RNE)) {
601 count = 1 + (0x0ff & *ep->reg_ubcr);
602 req->req.actual += min (count, bufferspace);
603 } else /* zlp */
604 count = 0;
605 is_short = (count < ep->ep.maxpacket);
606 DBG(DBG_VERY_NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
607 ep->ep.name, udccs, count,
608 is_short ? "/S" : "",
609 req, req->req.actual, req->req.length);
610 while (likely (count-- != 0)) {
611 u8 byte = (u8) *ep->reg_uddr;
612
613 if (unlikely (bufferspace == 0)) {
614 /* this happens when the driver's buffer
615 * is smaller than what the host sent.
616 * discard the extra data.
617 */
618 if (req->req.status != -EOVERFLOW)
619 DMSG("%s overflow %d\n",
620 ep->ep.name, count);
621 req->req.status = -EOVERFLOW;
622 } else {
623 *buf++ = byte;
624 bufferspace--;
625 }
626 }
627 *ep->reg_udccs = UDCCS_BO_RPC;
628 /* RPC/RSP/RNE could now reflect the other packet buffer */
629
630 /* iso is one request per packet */
631 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
632 if (udccs & UDCCS_IO_ROF)
633 req->req.status = -EHOSTUNREACH;
634 /* more like "is_done" */
635 is_short = 1;
636 }
637
638 /* completion */
639 if (is_short || req->req.actual == req->req.length) {
640 done (ep, req, 0);
641 if (list_empty(&ep->queue))
642 pio_irq_disable (ep->bEndpointAddress);
643 return 1;
644 }
645
646 /* finished that packet. the next one may be waiting... */
647 }
648 return 0;
649 }
650
651 /*
652 * special ep0 version of the above. no UBCR0 or double buffering; status
653 * handshaking is magic. most device protocols don't need control-OUT.
654 * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
655 * protocols do use them.
656 */
657 static int
658 read_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
659 {
660 u8 *buf, byte;
661 unsigned bufferspace;
662
663 buf = req->req.buf + req->req.actual;
664 bufferspace = req->req.length - req->req.actual;
665
666 while (UDCCS0 & UDCCS0_RNE) {
667 byte = (u8) UDDR0;
668
669 if (unlikely (bufferspace == 0)) {
670 /* this happens when the driver's buffer
671 * is smaller than what the host sent.
672 * discard the extra data.
673 */
674 if (req->req.status != -EOVERFLOW)
675 DMSG("%s overflow\n", ep->ep.name);
676 req->req.status = -EOVERFLOW;
677 } else {
678 *buf++ = byte;
679 req->req.actual++;
680 bufferspace--;
681 }
682 }
683
684 UDCCS0 = UDCCS0_OPR | UDCCS0_IPR;
685
686 /* completion */
687 if (req->req.actual >= req->req.length)
688 return 1;
689
690 /* finished that packet. the next one may be waiting... */
691 return 0;
692 }
693
694 #ifdef USE_DMA
695
696 #define MAX_IN_DMA ((DCMD_LENGTH + 1) - BULK_FIFO_SIZE)
697
698 static void
699 start_dma_nodesc(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int is_in)
700 {
701 u32 dcmd = req->req.length;
702 u32 buf = req->req.dma;
703 u32 fifo = io_v2p ((u32)ep->reg_uddr);
704
705 /* caller guarantees there's a packet or more remaining
706 * - IN may end with a short packet (TSP set separately),
707 * - OUT is always full length
708 */
709 buf += req->req.actual;
710 dcmd -= req->req.actual;
711 ep->dma_fixup = 0;
712
713 /* no-descriptor mode can be simple for bulk-in, iso-in, iso-out */
714 DCSR(ep->dma) = DCSR_NODESC;
715 if (is_in) {
716 DSADR(ep->dma) = buf;
717 DTADR(ep->dma) = fifo;
718 if (dcmd > MAX_IN_DMA)
719 dcmd = MAX_IN_DMA;
720 else
721 ep->dma_fixup = (dcmd % ep->ep.maxpacket) != 0;
722 dcmd |= DCMD_BURST32 | DCMD_WIDTH1
723 | DCMD_FLOWTRG | DCMD_INCSRCADDR;
724 } else {
725 #ifdef USE_OUT_DMA
726 DSADR(ep->dma) = fifo;
727 DTADR(ep->dma) = buf;
728 if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
729 dcmd = ep->ep.maxpacket;
730 dcmd |= DCMD_BURST32 | DCMD_WIDTH1
731 | DCMD_FLOWSRC | DCMD_INCTRGADDR;
732 #endif
733 }
734 DCMD(ep->dma) = dcmd;
735 DCSR(ep->dma) = DCSR_RUN | DCSR_NODESC
736 | (unlikely(is_in)
737 ? DCSR_STOPIRQEN /* use dma_nodesc_handler() */
738 : 0); /* use handle_ep() */
739 }
740
741 static void kick_dma(struct pxa2xx_ep *ep, struct pxa2xx_request *req)
742 {
743 int is_in = ep->bEndpointAddress & USB_DIR_IN;
744
745 if (is_in) {
746 /* unaligned tx buffers and zlps only work with PIO */
747 if ((req->req.dma & 0x0f) != 0
748 || unlikely((req->req.length - req->req.actual)
749 == 0)) {
750 pio_irq_enable(ep->bEndpointAddress);
751 if ((*ep->reg_udccs & UDCCS_BI_TFS) != 0)
752 (void) write_fifo(ep, req);
753 } else {
754 start_dma_nodesc(ep, req, USB_DIR_IN);
755 }
756 } else {
757 if ((req->req.length - req->req.actual) < ep->ep.maxpacket) {
758 DMSG("%s short dma read...\n", ep->ep.name);
759 /* we're always set up for pio out */
760 read_fifo (ep, req);
761 } else {
762 *ep->reg_udccs = UDCCS_BO_DME
763 | (*ep->reg_udccs & UDCCS_BO_FST);
764 start_dma_nodesc(ep, req, USB_DIR_OUT);
765 }
766 }
767 }
768
769 static void cancel_dma(struct pxa2xx_ep *ep)
770 {
771 struct pxa2xx_request *req;
772 u32 tmp;
773
774 if (DCSR(ep->dma) == 0 || list_empty(&ep->queue))
775 return;
776
777 DCSR(ep->dma) = 0;
778 while ((DCSR(ep->dma) & DCSR_STOPSTATE) == 0)
779 cpu_relax();
780
781 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
782 tmp = DCMD(ep->dma) & DCMD_LENGTH;
783 req->req.actual = req->req.length - (tmp & DCMD_LENGTH);
784
785 /* the last tx packet may be incomplete, so flush the fifo.
786 * FIXME correct req.actual if we can
787 */
788 if (ep->bEndpointAddress & USB_DIR_IN)
789 *ep->reg_udccs = UDCCS_BI_FTF;
790 }
791
792 /* dma channel stopped ... normal tx end (IN), or on error (IN/OUT) */
793 static void dma_nodesc_handler(int dmach, void *_ep, struct pt_regs *r)
794 {
795 struct pxa2xx_ep *ep = _ep;
796 struct pxa2xx_request *req;
797 u32 tmp, completed;
798
799 local_irq_disable();
800
801 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
802
803 ep->dma_irqs++;
804 ep->dev->stats.irqs++;
805 HEX_DISPLAY(ep->dev->stats.irqs);
806
807 /* ack/clear */
808 tmp = DCSR(ep->dma);
809 DCSR(ep->dma) = tmp;
810 if ((tmp & DCSR_STOPSTATE) == 0
811 || (DDADR(ep->dma) & DDADR_STOP) != 0) {
812 DBG(DBG_VERBOSE, "%s, dcsr %08x ddadr %08x\n",
813 ep->ep.name, DCSR(ep->dma), DDADR(ep->dma));
814 goto done;
815 }
816 DCSR(ep->dma) = 0; /* clear DCSR_STOPSTATE */
817
818 /* update transfer status */
819 completed = tmp & DCSR_BUSERR;
820 if (ep->bEndpointAddress & USB_DIR_IN)
821 tmp = DSADR(ep->dma);
822 else
823 tmp = DTADR(ep->dma);
824 req->req.actual = tmp - req->req.dma;
825
826 /* FIXME seems we sometimes see partial transfers... */
827
828 if (unlikely(completed != 0))
829 req->req.status = -EIO;
830 else if (req->req.actual) {
831 /* these registers have zeroes in low bits; they miscount
832 * some (end-of-transfer) short packets: tx 14 as tx 12
833 */
834 if (ep->dma_fixup)
835 req->req.actual = min(req->req.actual + 3,
836 req->req.length);
837
838 tmp = (req->req.length - req->req.actual);
839 completed = (tmp == 0);
840 if (completed && (ep->bEndpointAddress & USB_DIR_IN)) {
841
842 /* maybe validate final short packet ... */
843 if ((req->req.actual % ep->ep.maxpacket) != 0)
844 *ep->reg_udccs = UDCCS_BI_TSP/*|UDCCS_BI_TPC*/;
845
846 /* ... or zlp, using pio fallback */
847 else if (ep->bmAttributes == USB_ENDPOINT_XFER_BULK
848 && req->req.zero) {
849 DMSG("%s zlp terminate ...\n", ep->ep.name);
850 completed = 0;
851 }
852 }
853 }
854
855 if (likely(completed)) {
856 done(ep, req, 0);
857
858 /* maybe re-activate after completion */
859 if (ep->stopped || list_empty(&ep->queue))
860 goto done;
861 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
862 }
863 kick_dma(ep, req);
864 done:
865 local_irq_enable();
866 }
867
868 #endif
869
870 /*-------------------------------------------------------------------------*/
871
872 static int
873 pxa2xx_ep_queue(struct usb_ep *_ep, struct usb_request *_req, int gfp_flags)
874 {
875 struct pxa2xx_request *req;
876 struct pxa2xx_ep *ep;
877 struct pxa2xx_udc *dev;
878 unsigned long flags;
879
880 req = container_of(_req, struct pxa2xx_request, req);
881 if (unlikely (!_req || !_req->complete || !_req->buf
882 || !list_empty(&req->queue))) {
883 DMSG("%s, bad params\n", __FUNCTION__);
884 return -EINVAL;
885 }
886
887 ep = container_of(_ep, struct pxa2xx_ep, ep);
888 if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
889 DMSG("%s, bad ep\n", __FUNCTION__);
890 return -EINVAL;
891 }
892
893 dev = ep->dev;
894 if (unlikely (!dev->driver
895 || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
896 DMSG("%s, bogus device state\n", __FUNCTION__);
897 return -ESHUTDOWN;
898 }
899
900 /* iso is always one packet per request, that's the only way
901 * we can report per-packet status. that also helps with dma.
902 */
903 if (unlikely (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
904 && req->req.length > le16_to_cpu
905 (ep->desc->wMaxPacketSize)))
906 return -EMSGSIZE;
907
908 #ifdef USE_DMA
909 // FIXME caller may already have done the dma mapping
910 if (ep->dma >= 0) {
911 _req->dma = dma_map_single(dev->dev,
912 _req->buf, _req->length,
913 ((ep->bEndpointAddress & USB_DIR_IN) != 0)
914 ? DMA_TO_DEVICE
915 : DMA_FROM_DEVICE);
916 }
917 #endif
918
919 DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n",
920 _ep->name, _req, _req->length, _req->buf);
921
922 local_irq_save(flags);
923
924 _req->status = -EINPROGRESS;
925 _req->actual = 0;
926
927 /* kickstart this i/o queue? */
928 if (list_empty(&ep->queue) && !ep->stopped) {
929 if (ep->desc == 0 /* ep0 */) {
930 unsigned length = _req->length;
931
932 switch (dev->ep0state) {
933 case EP0_IN_DATA_PHASE:
934 dev->stats.write.ops++;
935 if (write_ep0_fifo(ep, req))
936 req = NULL;
937 break;
938
939 case EP0_OUT_DATA_PHASE:
940 dev->stats.read.ops++;
941 /* messy ... */
942 if (dev->req_config) {
943 DBG(DBG_VERBOSE, "ep0 config ack%s\n",
944 dev->has_cfr ? "" : " raced");
945 if (dev->has_cfr)
946 UDCCFR = UDCCFR_AREN|UDCCFR_ACM
947 |UDCCFR_MB1;
948 done(ep, req, 0);
949 dev->ep0state = EP0_END_XFER;
950 local_irq_restore (flags);
951 return 0;
952 }
953 if (dev->req_pending)
954 ep0start(dev, UDCCS0_IPR, "OUT");
955 if (length == 0 || ((UDCCS0 & UDCCS0_RNE) != 0
956 && read_ep0_fifo(ep, req))) {
957 ep0_idle(dev);
958 done(ep, req, 0);
959 req = NULL;
960 }
961 break;
962
963 default:
964 DMSG("ep0 i/o, odd state %d\n", dev->ep0state);
965 local_irq_restore (flags);
966 return -EL2HLT;
967 }
968 #ifdef USE_DMA
969 /* either start dma or prime pio pump */
970 } else if (ep->dma >= 0) {
971 kick_dma(ep, req);
972 #endif
973 /* can the FIFO can satisfy the request immediately? */
974 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0
975 && (*ep->reg_udccs & UDCCS_BI_TFS) != 0
976 && write_fifo(ep, req)) {
977 req = NULL;
978 } else if ((*ep->reg_udccs & UDCCS_BO_RFS) != 0
979 && read_fifo(ep, req)) {
980 req = NULL;
981 }
982
983 if (likely (req && ep->desc) && ep->dma < 0)
984 pio_irq_enable(ep->bEndpointAddress);
985 }
986
987 /* pio or dma irq handler advances the queue. */
988 if (likely (req != 0))
989 list_add_tail(&req->queue, &ep->queue);
990 local_irq_restore(flags);
991
992 return 0;
993 }
994
995
996 /*
997 * nuke - dequeue ALL requests
998 */
999 static void nuke(struct pxa2xx_ep *ep, int status)
1000 {
1001 struct pxa2xx_request *req;
1002
1003 /* called with irqs blocked */
1004 #ifdef USE_DMA
1005 if (ep->dma >= 0 && !ep->stopped)
1006 cancel_dma(ep);
1007 #endif
1008 while (!list_empty(&ep->queue)) {
1009 req = list_entry(ep->queue.next,
1010 struct pxa2xx_request,
1011 queue);
1012 done(ep, req, status);
1013 }
1014 if (ep->desc)
1015 pio_irq_disable (ep->bEndpointAddress);
1016 }
1017
1018
1019 /* dequeue JUST ONE request */
1020 static int pxa2xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1021 {
1022 struct pxa2xx_ep *ep;
1023 struct pxa2xx_request *req;
1024 unsigned long flags;
1025
1026 ep = container_of(_ep, struct pxa2xx_ep, ep);
1027 if (!_ep || ep->ep.name == ep0name)
1028 return -EINVAL;
1029
1030 local_irq_save(flags);
1031
1032 /* make sure it's actually queued on this endpoint */
1033 list_for_each_entry (req, &ep->queue, queue) {
1034 if (&req->req == _req)
1035 break;
1036 }
1037 if (&req->req != _req) {
1038 local_irq_restore(flags);
1039 return -EINVAL;
1040 }
1041
1042 #ifdef USE_DMA
1043 if (ep->dma >= 0 && ep->queue.next == &req->queue && !ep->stopped) {
1044 cancel_dma(ep);
1045 done(ep, req, -ECONNRESET);
1046 /* restart i/o */
1047 if (!list_empty(&ep->queue)) {
1048 req = list_entry(ep->queue.next,
1049 struct pxa2xx_request, queue);
1050 kick_dma(ep, req);
1051 }
1052 } else
1053 #endif
1054 done(ep, req, -ECONNRESET);
1055
1056 local_irq_restore(flags);
1057 return 0;
1058 }
1059
1060 /*-------------------------------------------------------------------------*/
1061
1062 static int pxa2xx_ep_set_halt(struct usb_ep *_ep, int value)
1063 {
1064 struct pxa2xx_ep *ep;
1065 unsigned long flags;
1066
1067 ep = container_of(_ep, struct pxa2xx_ep, ep);
1068 if (unlikely (!_ep
1069 || (!ep->desc && ep->ep.name != ep0name))
1070 || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1071 DMSG("%s, bad ep\n", __FUNCTION__);
1072 return -EINVAL;
1073 }
1074 if (value == 0) {
1075 /* this path (reset toggle+halt) is needed to implement
1076 * SET_INTERFACE on normal hardware. but it can't be
1077 * done from software on the PXA UDC, and the hardware
1078 * forgets to do it as part of SET_INTERFACE automagic.
1079 */
1080 DMSG("only host can clear %s halt\n", _ep->name);
1081 return -EROFS;
1082 }
1083
1084 local_irq_save(flags);
1085
1086 if ((ep->bEndpointAddress & USB_DIR_IN) != 0
1087 && ((*ep->reg_udccs & UDCCS_BI_TFS) == 0
1088 || !list_empty(&ep->queue))) {
1089 local_irq_restore(flags);
1090 return -EAGAIN;
1091 }
1092
1093 /* FST bit is the same for control, bulk in, bulk out, interrupt in */
1094 *ep->reg_udccs = UDCCS_BI_FST|UDCCS_BI_FTF;
1095
1096 /* ep0 needs special care */
1097 if (!ep->desc) {
1098 start_watchdog(ep->dev);
1099 ep->dev->req_pending = 0;
1100 ep->dev->ep0state = EP0_STALL;
1101
1102 /* and bulk/intr endpoints like dropping stalls too */
1103 } else {
1104 unsigned i;
1105 for (i = 0; i < 1000; i += 20) {
1106 if (*ep->reg_udccs & UDCCS_BI_SST)
1107 break;
1108 udelay(20);
1109 }
1110 }
1111 local_irq_restore(flags);
1112
1113 DBG(DBG_VERBOSE, "%s halt\n", _ep->name);
1114 return 0;
1115 }
1116
1117 static int pxa2xx_ep_fifo_status(struct usb_ep *_ep)
1118 {
1119 struct pxa2xx_ep *ep;
1120
1121 ep = container_of(_ep, struct pxa2xx_ep, ep);
1122 if (!_ep) {
1123 DMSG("%s, bad ep\n", __FUNCTION__);
1124 return -ENODEV;
1125 }
1126 /* pxa can't report unclaimed bytes from IN fifos */
1127 if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
1128 return -EOPNOTSUPP;
1129 if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
1130 || (*ep->reg_udccs & UDCCS_BO_RFS) == 0)
1131 return 0;
1132 else
1133 return (*ep->reg_ubcr & 0xfff) + 1;
1134 }
1135
1136 static void pxa2xx_ep_fifo_flush(struct usb_ep *_ep)
1137 {
1138 struct pxa2xx_ep *ep;
1139
1140 ep = container_of(_ep, struct pxa2xx_ep, ep);
1141 if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
1142 DMSG("%s, bad ep\n", __FUNCTION__);
1143 return;
1144 }
1145
1146 /* toggle and halt bits stay unchanged */
1147
1148 /* for OUT, just read and discard the FIFO contents. */
1149 if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
1150 while (((*ep->reg_udccs) & UDCCS_BO_RNE) != 0)
1151 (void) *ep->reg_uddr;
1152 return;
1153 }
1154
1155 /* most IN status is the same, but ISO can't stall */
1156 *ep->reg_udccs = UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
1157 | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1158 ? 0 : UDCCS_BI_SST;
1159 }
1160
1161
1162 static struct usb_ep_ops pxa2xx_ep_ops = {
1163 .enable = pxa2xx_ep_enable,
1164 .disable = pxa2xx_ep_disable,
1165
1166 .alloc_request = pxa2xx_ep_alloc_request,
1167 .free_request = pxa2xx_ep_free_request,
1168
1169 .alloc_buffer = pxa2xx_ep_alloc_buffer,
1170 .free_buffer = pxa2xx_ep_free_buffer,
1171
1172 .queue = pxa2xx_ep_queue,
1173 .dequeue = pxa2xx_ep_dequeue,
1174
1175 .set_halt = pxa2xx_ep_set_halt,
1176 .fifo_status = pxa2xx_ep_fifo_status,
1177 .fifo_flush = pxa2xx_ep_fifo_flush,
1178 };
1179
1180
1181 /* ---------------------------------------------------------------------------
1182 * device-scoped parts of the api to the usb controller hardware
1183 * ---------------------------------------------------------------------------
1184 */
1185
1186 static int pxa2xx_udc_get_frame(struct usb_gadget *_gadget)
1187 {
1188 return ((UFNRH & 0x07) << 8) | (UFNRL & 0xff);
1189 }
1190
1191 static int pxa2xx_udc_wakeup(struct usb_gadget *_gadget)
1192 {
1193 /* host may not have enabled remote wakeup */
1194 if ((UDCCS0 & UDCCS0_DRWF) == 0)
1195 return -EHOSTUNREACH;
1196 udc_set_mask_UDCCR(UDCCR_RSM);
1197 return 0;
1198 }
1199
1200 static void stop_activity(struct pxa2xx_udc *, struct usb_gadget_driver *);
1201 static void udc_enable (struct pxa2xx_udc *);
1202 static void udc_disable(struct pxa2xx_udc *);
1203
1204 /* We disable the UDC -- and its 48 MHz clock -- whenever it's not
1205 * in active use.
1206 */
1207 static int pullup(struct pxa2xx_udc *udc, int is_active)
1208 {
1209 is_active = is_active && udc->vbus && udc->pullup;
1210 DMSG("%s\n", is_active ? "active" : "inactive");
1211 if (is_active)
1212 udc_enable(udc);
1213 else {
1214 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1215 DMSG("disconnect %s\n", udc->driver
1216 ? udc->driver->driver.name
1217 : "(no driver)");
1218 stop_activity(udc, udc->driver);
1219 }
1220 udc_disable(udc);
1221 }
1222 return 0;
1223 }
1224
1225 /* VBUS reporting logically comes from a transceiver */
1226 static int pxa2xx_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
1227 {
1228 struct pxa2xx_udc *udc;
1229
1230 udc = container_of(_gadget, struct pxa2xx_udc, gadget);
1231 udc->vbus = is_active = (is_active != 0);
1232 DMSG("vbus %s\n", is_active ? "supplied" : "inactive");
1233 pullup(udc, is_active);
1234 return 0;
1235 }
1236
1237 /* drivers may have software control over D+ pullup */
1238 static int pxa2xx_udc_pullup(struct usb_gadget *_gadget, int is_active)
1239 {
1240 struct pxa2xx_udc *udc;
1241
1242 udc = container_of(_gadget, struct pxa2xx_udc, gadget);
1243
1244 /* not all boards support pullup control */
1245 if (!udc->mach->udc_command)
1246 return -EOPNOTSUPP;
1247
1248 is_active = (is_active != 0);
1249 udc->pullup = is_active;
1250 pullup(udc, is_active);
1251 return 0;
1252 }
1253
1254 static const struct usb_gadget_ops pxa2xx_udc_ops = {
1255 .get_frame = pxa2xx_udc_get_frame,
1256 .wakeup = pxa2xx_udc_wakeup,
1257 .vbus_session = pxa2xx_udc_vbus_session,
1258 .pullup = pxa2xx_udc_pullup,
1259
1260 // .vbus_draw ... boards may consume current from VBUS, up to
1261 // 100-500mA based on config. the 500uA suspend ceiling means
1262 // that exclusively vbus-powered PXA designs violate USB specs.
1263 };
1264
1265 /*-------------------------------------------------------------------------*/
1266
1267 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
1268
1269 static const char proc_node_name [] = "driver/udc";
1270
1271 static int
1272 udc_proc_read(char *page, char **start, off_t off, int count,
1273 int *eof, void *_dev)
1274 {
1275 char *buf = page;
1276 struct pxa2xx_udc *dev = _dev;
1277 char *next = buf;
1278 unsigned size = count;
1279 unsigned long flags;
1280 int i, t;
1281 u32 tmp;
1282
1283 if (off != 0)
1284 return 0;
1285
1286 local_irq_save(flags);
1287
1288 /* basic device status */
1289 t = scnprintf(next, size, DRIVER_DESC "\n"
1290 "%s version: %s\nGadget driver: %s\nHost %s\n\n",
1291 driver_name, DRIVER_VERSION SIZE_STR DMASTR,
1292 dev->driver ? dev->driver->driver.name : "(none)",
1293 is_usb_connected() ? "full speed" : "disconnected");
1294 size -= t;
1295 next += t;
1296
1297 /* registers for device and ep0 */
1298 t = scnprintf(next, size,
1299 "uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
1300 UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL);
1301 size -= t;
1302 next += t;
1303
1304 tmp = UDCCR;
1305 t = scnprintf(next, size,
1306 "udccr %02X =%s%s%s%s%s%s%s%s\n", tmp,
1307 (tmp & UDCCR_REM) ? " rem" : "",
1308 (tmp & UDCCR_RSTIR) ? " rstir" : "",
1309 (tmp & UDCCR_SRM) ? " srm" : "",
1310 (tmp & UDCCR_SUSIR) ? " susir" : "",
1311 (tmp & UDCCR_RESIR) ? " resir" : "",
1312 (tmp & UDCCR_RSM) ? " rsm" : "",
1313 (tmp & UDCCR_UDA) ? " uda" : "",
1314 (tmp & UDCCR_UDE) ? " ude" : "");
1315 size -= t;
1316 next += t;
1317
1318 tmp = UDCCS0;
1319 t = scnprintf(next, size,
1320 "udccs0 %02X =%s%s%s%s%s%s%s%s\n", tmp,
1321 (tmp & UDCCS0_SA) ? " sa" : "",
1322 (tmp & UDCCS0_RNE) ? " rne" : "",
1323 (tmp & UDCCS0_FST) ? " fst" : "",
1324 (tmp & UDCCS0_SST) ? " sst" : "",
1325 (tmp & UDCCS0_DRWF) ? " dwrf" : "",
1326 (tmp & UDCCS0_FTF) ? " ftf" : "",
1327 (tmp & UDCCS0_IPR) ? " ipr" : "",
1328 (tmp & UDCCS0_OPR) ? " opr" : "");
1329 size -= t;
1330 next += t;
1331
1332 if (dev->has_cfr) {
1333 tmp = UDCCFR;
1334 t = scnprintf(next, size,
1335 "udccfr %02X =%s%s\n", tmp,
1336 (tmp & UDCCFR_AREN) ? " aren" : "",
1337 (tmp & UDCCFR_ACM) ? " acm" : "");
1338 size -= t;
1339 next += t;
1340 }
1341
1342 if (!is_usb_connected() || !dev->driver)
1343 goto done;
1344
1345 t = scnprintf(next, size, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n",
1346 dev->stats.write.bytes, dev->stats.write.ops,
1347 dev->stats.read.bytes, dev->stats.read.ops,
1348 dev->stats.irqs);
1349 size -= t;
1350 next += t;
1351
1352 /* dump endpoint queues */
1353 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1354 struct pxa2xx_ep *ep = &dev->ep [i];
1355 struct pxa2xx_request *req;
1356 int t;
1357
1358 if (i != 0) {
1359 const struct usb_endpoint_descriptor *d;
1360
1361 d = ep->desc;
1362 if (!d)
1363 continue;
1364 tmp = *dev->ep [i].reg_udccs;
1365 t = scnprintf(next, size,
1366 "%s max %d %s udccs %02x irqs %lu/%lu\n",
1367 ep->ep.name, le16_to_cpu (d->wMaxPacketSize),
1368 (ep->dma >= 0) ? "dma" : "pio", tmp,
1369 ep->pio_irqs, ep->dma_irqs);
1370 /* TODO translate all five groups of udccs bits! */
1371
1372 } else /* ep0 should only have one transfer queued */
1373 t = scnprintf(next, size, "ep0 max 16 pio irqs %lu\n",
1374 ep->pio_irqs);
1375 if (t <= 0 || t > size)
1376 goto done;
1377 size -= t;
1378 next += t;
1379
1380 if (list_empty(&ep->queue)) {
1381 t = scnprintf(next, size, "\t(nothing queued)\n");
1382 if (t <= 0 || t > size)
1383 goto done;
1384 size -= t;
1385 next += t;
1386 continue;
1387 }
1388 list_for_each_entry(req, &ep->queue, queue) {
1389 #ifdef USE_DMA
1390 if (ep->dma >= 0 && req->queue.prev == &ep->queue)
1391 t = scnprintf(next, size,
1392 "\treq %p len %d/%d "
1393 "buf %p (dma%d dcmd %08x)\n",
1394 &req->req, req->req.actual,
1395 req->req.length, req->req.buf,
1396 ep->dma, DCMD(ep->dma)
1397 // low 13 bits == bytes-to-go
1398 );
1399 else
1400 #endif
1401 t = scnprintf(next, size,
1402 "\treq %p len %d/%d buf %p\n",
1403 &req->req, req->req.actual,
1404 req->req.length, req->req.buf);
1405 if (t <= 0 || t > size)
1406 goto done;
1407 size -= t;
1408 next += t;
1409 }
1410 }
1411
1412 done:
1413 local_irq_restore(flags);
1414 *eof = 1;
1415 return count - size;
1416 }
1417
1418 #define create_proc_files() \
1419 create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev)
1420 #define remove_proc_files() \
1421 remove_proc_entry(proc_node_name, NULL)
1422
1423 #else /* !CONFIG_USB_GADGET_DEBUG_FILES */
1424
1425 #define create_proc_files() do {} while (0)
1426 #define remove_proc_files() do {} while (0)
1427
1428 #endif /* CONFIG_USB_GADGET_DEBUG_FILES */
1429
1430 /* "function" sysfs attribute */
1431 static ssize_t
1432 show_function (struct device *_dev, char *buf)
1433 {
1434 struct pxa2xx_udc *dev = dev_get_drvdata (_dev);
1435
1436 if (!dev->driver
1437 || !dev->driver->function
1438 || strlen (dev->driver->function) > PAGE_SIZE)
1439 return 0;
1440 return scnprintf (buf, PAGE_SIZE, "%s\n", dev->driver->function);
1441 }
1442 static DEVICE_ATTR (function, S_IRUGO, show_function, NULL);
1443
1444 /*-------------------------------------------------------------------------*/
1445
1446 /*
1447 * udc_disable - disable USB device controller
1448 */
1449 static void udc_disable(struct pxa2xx_udc *dev)
1450 {
1451 /* block all irqs */
1452 udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM);
1453 UICR0 = UICR1 = 0xff;
1454 UFNRH = UFNRH_SIM;
1455
1456 /* if hardware supports it, disconnect from usb */
1457 make_usb_disappear();
1458
1459 udc_clear_mask_UDCCR(UDCCR_UDE);
1460
1461 #ifdef CONFIG_ARCH_PXA
1462 /* Disable clock for USB device */
1463 pxa_set_cken(CKEN11_USB, 0);
1464 #endif
1465
1466 ep0_idle (dev);
1467 dev->gadget.speed = USB_SPEED_UNKNOWN;
1468 LED_CONNECTED_OFF;
1469 }
1470
1471
1472 /*
1473 * udc_reinit - initialize software state
1474 */
1475 static void udc_reinit(struct pxa2xx_udc *dev)
1476 {
1477 u32 i;
1478
1479 /* device/ep0 records init */
1480 INIT_LIST_HEAD (&dev->gadget.ep_list);
1481 INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
1482 dev->ep0state = EP0_IDLE;
1483
1484 /* basic endpoint records init */
1485 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1486 struct pxa2xx_ep *ep = &dev->ep[i];
1487
1488 if (i != 0)
1489 list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
1490
1491 ep->desc = NULL;
1492 ep->stopped = 0;
1493 INIT_LIST_HEAD (&ep->queue);
1494 ep->pio_irqs = ep->dma_irqs = 0;
1495 }
1496
1497 /* the rest was statically initialized, and is read-only */
1498 }
1499
1500 /* until it's enabled, this UDC should be completely invisible
1501 * to any USB host.
1502 */
1503 static void udc_enable (struct pxa2xx_udc *dev)
1504 {
1505 udc_clear_mask_UDCCR(UDCCR_UDE);
1506
1507 #ifdef CONFIG_ARCH_PXA
1508 /* Enable clock for USB device */
1509 pxa_set_cken(CKEN11_USB, 1);
1510 udelay(5);
1511 #endif
1512
1513 /* try to clear these bits before we enable the udc */
1514 udc_ack_int_UDCCR(UDCCR_SUSIR|/*UDCCR_RSTIR|*/UDCCR_RESIR);
1515
1516 ep0_idle(dev);
1517 dev->gadget.speed = USB_SPEED_UNKNOWN;
1518 dev->stats.irqs = 0;
1519
1520 /*
1521 * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1522 * - enable UDC
1523 * - if RESET is already in progress, ack interrupt
1524 * - unmask reset interrupt
1525 */
1526 udc_set_mask_UDCCR(UDCCR_UDE);
1527 if (!(UDCCR & UDCCR_UDA))
1528 udc_ack_int_UDCCR(UDCCR_RSTIR);
1529
1530 if (dev->has_cfr /* UDC_RES2 is defined */) {
1531 /* pxa255 (a0+) can avoid a set_config race that could
1532 * prevent gadget drivers from configuring correctly
1533 */
1534 UDCCFR = UDCCFR_ACM | UDCCFR_MB1;
1535 } else {
1536 /* "USB test mode" for pxa250 errata 40-42 (stepping a0, a1)
1537 * which could result in missing packets and interrupts.
1538 * supposedly one bit per endpoint, controlling whether it
1539 * double buffers or not; ACM/AREN bits fit into the holes.
1540 * zero bits (like USIR0_IRx) disable double buffering.
1541 */
1542 UDC_RES1 = 0x00;
1543 UDC_RES2 = 0x00;
1544 }
1545
1546 #ifdef DISABLE_TEST_MODE
1547 /* "test mode" seems to have become the default in later chip
1548 * revs, preventing double buffering (and invalidating docs).
1549 * this EXPERIMENT enables it for bulk endpoints by tweaking
1550 * undefined/reserved register bits (that other drivers clear).
1551 * Belcarra code comments noted this usage.
1552 */
1553 if (fifo_mode & 1) { /* IN endpoints */
1554 UDC_RES1 |= USIR0_IR1|USIR0_IR6;
1555 UDC_RES2 |= USIR1_IR11;
1556 }
1557 if (fifo_mode & 2) { /* OUT endpoints */
1558 UDC_RES1 |= USIR0_IR2|USIR0_IR7;
1559 UDC_RES2 |= USIR1_IR12;
1560 }
1561 #endif
1562
1563 /* enable suspend/resume and reset irqs */
1564 udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);
1565
1566 /* enable ep0 irqs */
1567 UICR0 &= ~UICR0_IM0;
1568
1569 /* if hardware supports it, pullup D+ and wait for reset */
1570 let_usb_appear();
1571 }
1572
1573
1574 /* when a driver is successfully registered, it will receive
1575 * control requests including set_configuration(), which enables
1576 * non-control requests. then usb traffic follows until a
1577 * disconnect is reported. then a host may connect again, or
1578 * the driver might get unbound.
1579 */
1580 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1581 {
1582 struct pxa2xx_udc *dev = the_controller;
1583 int retval;
1584
1585 if (!driver
1586 || driver->speed != USB_SPEED_FULL
1587 || !driver->bind
1588 || !driver->unbind
1589 || !driver->disconnect
1590 || !driver->setup)
1591 return -EINVAL;
1592 if (!dev)
1593 return -ENODEV;
1594 if (dev->driver)
1595 return -EBUSY;
1596
1597 /* first hook up the driver ... */
1598 dev->driver = driver;
1599 dev->gadget.dev.driver = &driver->driver;
1600 dev->pullup = 1;
1601
1602 device_add (&dev->gadget.dev);
1603 retval = driver->bind(&dev->gadget);
1604 if (retval) {
1605 DMSG("bind to driver %s --> error %d\n",
1606 driver->driver.name, retval);
1607 device_del (&dev->gadget.dev);
1608
1609 dev->driver = NULL;
1610 dev->gadget.dev.driver = NULL;
1611 return retval;
1612 }
1613 device_create_file(dev->dev, &dev_attr_function);
1614
1615 /* ... then enable host detection and ep0; and we're ready
1616 * for set_configuration as well as eventual disconnect.
1617 */
1618 DMSG("registered gadget driver '%s'\n", driver->driver.name);
1619 pullup(dev, 1);
1620 dump_state(dev);
1621 return 0;
1622 }
1623 EXPORT_SYMBOL(usb_gadget_register_driver);
1624
1625 static void
1626 stop_activity(struct pxa2xx_udc *dev, struct usb_gadget_driver *driver)
1627 {
1628 int i;
1629
1630 /* don't disconnect drivers more than once */
1631 if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1632 driver = NULL;
1633 dev->gadget.speed = USB_SPEED_UNKNOWN;
1634
1635 /* prevent new request submissions, kill any outstanding requests */
1636 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1637 struct pxa2xx_ep *ep = &dev->ep[i];
1638
1639 ep->stopped = 1;
1640 nuke(ep, -ESHUTDOWN);
1641 }
1642 del_timer_sync(&dev->timer);
1643
1644 /* report disconnect; the driver is already quiesced */
1645 LED_CONNECTED_OFF;
1646 if (driver)
1647 driver->disconnect(&dev->gadget);
1648
1649 /* re-init driver-visible data structures */
1650 udc_reinit(dev);
1651 }
1652
1653 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1654 {
1655 struct pxa2xx_udc *dev = the_controller;
1656
1657 if (!dev)
1658 return -ENODEV;
1659 if (!driver || driver != dev->driver)
1660 return -EINVAL;
1661
1662 local_irq_disable();
1663 pullup(dev, 0);
1664 stop_activity(dev, driver);
1665 local_irq_enable();
1666
1667 driver->unbind(&dev->gadget);
1668 dev->driver = NULL;
1669
1670 device_del (&dev->gadget.dev);
1671 device_remove_file(dev->dev, &dev_attr_function);
1672
1673 DMSG("unregistered gadget driver '%s'\n", driver->driver.name);
1674 dump_state(dev);
1675 return 0;
1676 }
1677 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1678
1679
1680 /*-------------------------------------------------------------------------*/
1681
1682 #ifdef CONFIG_ARCH_LUBBOCK
1683
1684 /* Lubbock has separate connect and disconnect irqs. More typical designs
1685 * use one GPIO as the VBUS IRQ, and another to control the D+ pullup.
1686 */
1687
1688 static irqreturn_t
1689 lubbock_vbus_irq(int irq, void *_dev, struct pt_regs *r)
1690 {
1691 struct pxa2xx_udc *dev = _dev;
1692 int vbus;
1693
1694 dev->stats.irqs++;
1695 HEX_DISPLAY(dev->stats.irqs);
1696 switch (irq) {
1697 case LUBBOCK_USB_IRQ:
1698 LED_CONNECTED_ON;
1699 vbus = 1;
1700 disable_irq(LUBBOCK_USB_IRQ);
1701 enable_irq(LUBBOCK_USB_DISC_IRQ);
1702 break;
1703 case LUBBOCK_USB_DISC_IRQ:
1704 LED_CONNECTED_OFF;
1705 vbus = 0;
1706 disable_irq(LUBBOCK_USB_DISC_IRQ);
1707 enable_irq(LUBBOCK_USB_IRQ);
1708 break;
1709 default:
1710 return IRQ_NONE;
1711 }
1712
1713 pxa2xx_udc_vbus_session(&dev->gadget, vbus);
1714 return IRQ_HANDLED;
1715 }
1716
1717 #endif
1718
1719
1720 /*-------------------------------------------------------------------------*/
1721
1722 static inline void clear_ep_state (struct pxa2xx_udc *dev)
1723 {
1724 unsigned i;
1725
1726 /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1727 * fifos, and pending transactions mustn't be continued in any case.
1728 */
1729 for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
1730 nuke(&dev->ep[i], -ECONNABORTED);
1731 }
1732
1733 static void udc_watchdog(unsigned long _dev)
1734 {
1735 struct pxa2xx_udc *dev = (void *)_dev;
1736
1737 local_irq_disable();
1738 if (dev->ep0state == EP0_STALL
1739 && (UDCCS0 & UDCCS0_FST) == 0
1740 && (UDCCS0 & UDCCS0_SST) == 0) {
1741 UDCCS0 = UDCCS0_FST|UDCCS0_FTF;
1742 DBG(DBG_VERBOSE, "ep0 re-stall\n");
1743 start_watchdog(dev);
1744 }
1745 local_irq_enable();
1746 }
1747
1748 static void handle_ep0 (struct pxa2xx_udc *dev)
1749 {
1750 u32 udccs0 = UDCCS0;
1751 struct pxa2xx_ep *ep = &dev->ep [0];
1752 struct pxa2xx_request *req;
1753 union {
1754 struct usb_ctrlrequest r;
1755 u8 raw [8];
1756 u32 word [2];
1757 } u;
1758
1759 if (list_empty(&ep->queue))
1760 req = NULL;
1761 else
1762 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
1763
1764 /* clear stall status */
1765 if (udccs0 & UDCCS0_SST) {
1766 nuke(ep, -EPIPE);
1767 UDCCS0 = UDCCS0_SST;
1768 del_timer(&dev->timer);
1769 ep0_idle(dev);
1770 }
1771
1772 /* previous request unfinished? non-error iff back-to-back ... */
1773 if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1774 nuke(ep, 0);
1775 del_timer(&dev->timer);
1776 ep0_idle(dev);
1777 }
1778
1779 switch (dev->ep0state) {
1780 case EP0_IDLE:
1781 /* late-breaking status? */
1782 udccs0 = UDCCS0;
1783
1784 /* start control request? */
1785 if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
1786 == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
1787 int i;
1788
1789 nuke (ep, -EPROTO);
1790
1791 /* read SETUP packet */
1792 for (i = 0; i < 8; i++) {
1793 if (unlikely(!(UDCCS0 & UDCCS0_RNE))) {
1794 bad_setup:
1795 DMSG("SETUP %d!\n", i);
1796 goto stall;
1797 }
1798 u.raw [i] = (u8) UDDR0;
1799 }
1800 if (unlikely((UDCCS0 & UDCCS0_RNE) != 0))
1801 goto bad_setup;
1802
1803 got_setup:
1804 DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1805 u.r.bRequestType, u.r.bRequest,
1806 le16_to_cpu(u.r.wValue),
1807 le16_to_cpu(u.r.wIndex),
1808 le16_to_cpu(u.r.wLength));
1809
1810 /* cope with automagic for some standard requests. */
1811 dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
1812 == USB_TYPE_STANDARD;
1813 dev->req_config = 0;
1814 dev->req_pending = 1;
1815 switch (u.r.bRequest) {
1816 /* hardware restricts gadget drivers here! */
1817 case USB_REQ_SET_CONFIGURATION:
1818 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1819 /* reflect hardware's automagic
1820 * up to the gadget driver.
1821 */
1822 config_change:
1823 dev->req_config = 1;
1824 clear_ep_state(dev);
1825 /* if !has_cfr, there's no synch
1826 * else use AREN (later) not SA|OPR
1827 * USIR0_IR0 acts edge sensitive
1828 */
1829 }
1830 break;
1831 /* ... and here, even more ... */
1832 case USB_REQ_SET_INTERFACE:
1833 if (u.r.bRequestType == USB_RECIP_INTERFACE) {
1834 /* udc hardware is broken by design:
1835 * - altsetting may only be zero;
1836 * - hw resets all interfaces' eps;
1837 * - ep reset doesn't include halt(?).
1838 */
1839 DMSG("broken set_interface (%d/%d)\n",
1840 le16_to_cpu(u.r.wIndex),
1841 le16_to_cpu(u.r.wValue));
1842 goto config_change;
1843 }
1844 break;
1845 /* hardware was supposed to hide this */
1846 case USB_REQ_SET_ADDRESS:
1847 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1848 ep0start(dev, 0, "address");
1849 return;
1850 }
1851 break;
1852 }
1853
1854 if (u.r.bRequestType & USB_DIR_IN)
1855 dev->ep0state = EP0_IN_DATA_PHASE;
1856 else
1857 dev->ep0state = EP0_OUT_DATA_PHASE;
1858
1859 i = dev->driver->setup(&dev->gadget, &u.r);
1860 if (i < 0) {
1861 /* hardware automagic preventing STALL... */
1862 if (dev->req_config) {
1863 /* hardware sometimes neglects to tell
1864 * tell us about config change events,
1865 * so later ones may fail...
1866 */
1867 WARN("config change %02x fail %d?\n",
1868 u.r.bRequest, i);
1869 return;
1870 /* TODO experiment: if has_cfr,
1871 * hardware didn't ACK; maybe we
1872 * could actually STALL!
1873 */
1874 }
1875 DBG(DBG_VERBOSE, "protocol STALL, "
1876 "%02x err %d\n", UDCCS0, i);
1877 stall:
1878 /* the watchdog timer helps deal with cases
1879 * where udc seems to clear FST wrongly, and
1880 * then NAKs instead of STALLing.
1881 */
1882 ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
1883 start_watchdog(dev);
1884 dev->ep0state = EP0_STALL;
1885
1886 /* deferred i/o == no response yet */
1887 } else if (dev->req_pending) {
1888 if (likely(dev->ep0state == EP0_IN_DATA_PHASE
1889 || dev->req_std || u.r.wLength))
1890 ep0start(dev, 0, "defer");
1891 else
1892 ep0start(dev, UDCCS0_IPR, "defer/IPR");
1893 }
1894
1895 /* expect at least one data or status stage irq */
1896 return;
1897
1898 } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
1899 == (UDCCS0_OPR|UDCCS0_SA))) {
1900 unsigned i;
1901
1902 /* pxa210/250 erratum 131 for B0/B1 says RNE lies.
1903 * still observed on a pxa255 a0.
1904 */
1905 DBG(DBG_VERBOSE, "e131\n");
1906 nuke(ep, -EPROTO);
1907
1908 /* read SETUP data, but don't trust it too much */
1909 for (i = 0; i < 8; i++)
1910 u.raw [i] = (u8) UDDR0;
1911 if ((u.r.bRequestType & USB_RECIP_MASK)
1912 > USB_RECIP_OTHER)
1913 goto stall;
1914 if (u.word [0] == 0 && u.word [1] == 0)
1915 goto stall;
1916 goto got_setup;
1917 } else {
1918 /* some random early IRQ:
1919 * - we acked FST
1920 * - IPR cleared
1921 * - OPR got set, without SA (likely status stage)
1922 */
1923 UDCCS0 = udccs0 & (UDCCS0_SA|UDCCS0_OPR);
1924 }
1925 break;
1926 case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
1927 if (udccs0 & UDCCS0_OPR) {
1928 UDCCS0 = UDCCS0_OPR|UDCCS0_FTF;
1929 DBG(DBG_VERBOSE, "ep0in premature status\n");
1930 if (req)
1931 done(ep, req, 0);
1932 ep0_idle(dev);
1933 } else /* irq was IPR clearing */ {
1934 if (req) {
1935 /* this IN packet might finish the request */
1936 (void) write_ep0_fifo(ep, req);
1937 } /* else IN token before response was written */
1938 }
1939 break;
1940 case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
1941 if (udccs0 & UDCCS0_OPR) {
1942 if (req) {
1943 /* this OUT packet might finish the request */
1944 if (read_ep0_fifo(ep, req))
1945 done(ep, req, 0);
1946 /* else more OUT packets expected */
1947 } /* else OUT token before read was issued */
1948 } else /* irq was IPR clearing */ {
1949 DBG(DBG_VERBOSE, "ep0out premature status\n");
1950 if (req)
1951 done(ep, req, 0);
1952 ep0_idle(dev);
1953 }
1954 break;
1955 case EP0_END_XFER:
1956 if (req)
1957 done(ep, req, 0);
1958 /* ack control-IN status (maybe in-zlp was skipped)
1959 * also appears after some config change events.
1960 */
1961 if (udccs0 & UDCCS0_OPR)
1962 UDCCS0 = UDCCS0_OPR;
1963 ep0_idle(dev);
1964 break;
1965 case EP0_STALL:
1966 UDCCS0 = UDCCS0_FST;
1967 break;
1968 }
1969 USIR0 = USIR0_IR0;
1970 }
1971
1972 static void handle_ep(struct pxa2xx_ep *ep)
1973 {
1974 struct pxa2xx_request *req;
1975 int is_in = ep->bEndpointAddress & USB_DIR_IN;
1976 int completed;
1977 u32 udccs, tmp;
1978
1979 do {
1980 completed = 0;
1981 if (likely (!list_empty(&ep->queue)))
1982 req = list_entry(ep->queue.next,
1983 struct pxa2xx_request, queue);
1984 else
1985 req = NULL;
1986
1987 // TODO check FST handling
1988
1989 udccs = *ep->reg_udccs;
1990 if (unlikely(is_in)) { /* irq from TPC, SST, or (ISO) TUR */
1991 tmp = UDCCS_BI_TUR;
1992 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1993 tmp |= UDCCS_BI_SST;
1994 tmp &= udccs;
1995 if (likely (tmp))
1996 *ep->reg_udccs = tmp;
1997 if (req && likely ((udccs & UDCCS_BI_TFS) != 0))
1998 completed = write_fifo(ep, req);
1999
2000 } else { /* irq from RPC (or for ISO, ROF) */
2001 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
2002 tmp = UDCCS_BO_SST | UDCCS_BO_DME;
2003 else
2004 tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
2005 tmp &= udccs;
2006 if (likely(tmp))
2007 *ep->reg_udccs = tmp;
2008
2009 /* fifos can hold packets, ready for reading... */
2010 if (likely(req)) {
2011 #ifdef USE_OUT_DMA
2012 // TODO didn't yet debug out-dma. this approach assumes
2013 // the worst about short packets and RPC; it might be better.
2014
2015 if (likely(ep->dma >= 0)) {
2016 if (!(udccs & UDCCS_BO_RSP)) {
2017 *ep->reg_udccs = UDCCS_BO_RPC;
2018 ep->dma_irqs++;
2019 return;
2020 }
2021 }
2022 #endif
2023 completed = read_fifo(ep, req);
2024 } else
2025 pio_irq_disable (ep->bEndpointAddress);
2026 }
2027 ep->pio_irqs++;
2028 } while (completed);
2029 }
2030
2031 /*
2032 * pxa2xx_udc_irq - interrupt handler
2033 *
2034 * avoid delays in ep0 processing. the control handshaking isn't always
2035 * under software control (pxa250c0 and the pxa255 are better), and delays
2036 * could cause usb protocol errors.
2037 */
2038 static irqreturn_t
2039 pxa2xx_udc_irq(int irq, void *_dev, struct pt_regs *r)
2040 {
2041 struct pxa2xx_udc *dev = _dev;
2042 int handled;
2043
2044 dev->stats.irqs++;
2045 HEX_DISPLAY(dev->stats.irqs);
2046 do {
2047 u32 udccr = UDCCR;
2048
2049 handled = 0;
2050
2051 /* SUSpend Interrupt Request */
2052 if (unlikely(udccr & UDCCR_SUSIR)) {
2053 udc_ack_int_UDCCR(UDCCR_SUSIR);
2054 handled = 1;
2055 DBG(DBG_VERBOSE, "USB suspend%s\n", is_usb_connected()
2056 ? "" : "+disconnect");
2057
2058 if (!is_usb_connected())
2059 stop_activity(dev, dev->driver);
2060 else if (dev->gadget.speed != USB_SPEED_UNKNOWN
2061 && dev->driver
2062 && dev->driver->suspend)
2063 dev->driver->suspend(&dev->gadget);
2064 ep0_idle (dev);
2065 }
2066
2067 /* RESume Interrupt Request */
2068 if (unlikely(udccr & UDCCR_RESIR)) {
2069 udc_ack_int_UDCCR(UDCCR_RESIR);
2070 handled = 1;
2071 DBG(DBG_VERBOSE, "USB resume\n");
2072
2073 if (dev->gadget.speed != USB_SPEED_UNKNOWN
2074 && dev->driver
2075 && dev->driver->resume
2076 && is_usb_connected())
2077 dev->driver->resume(&dev->gadget);
2078 }
2079
2080 /* ReSeT Interrupt Request - USB reset */
2081 if (unlikely(udccr & UDCCR_RSTIR)) {
2082 udc_ack_int_UDCCR(UDCCR_RSTIR);
2083 handled = 1;
2084
2085 if ((UDCCR & UDCCR_UDA) == 0) {
2086 DBG(DBG_VERBOSE, "USB reset start\n");
2087
2088 /* reset driver and endpoints,
2089 * in case that's not yet done
2090 */
2091 stop_activity (dev, dev->driver);
2092
2093 } else {
2094 DBG(DBG_VERBOSE, "USB reset end\n");
2095 dev->gadget.speed = USB_SPEED_FULL;
2096 LED_CONNECTED_ON;
2097 memset(&dev->stats, 0, sizeof dev->stats);
2098 /* driver and endpoints are still reset */
2099 }
2100
2101 } else {
2102 u32 usir0 = USIR0 & ~UICR0;
2103 u32 usir1 = USIR1 & ~UICR1;
2104 int i;
2105
2106 if (unlikely (!usir0 && !usir1))
2107 continue;
2108
2109 DBG(DBG_VERY_NOISY, "irq %02x.%02x\n", usir1, usir0);
2110
2111 /* control traffic */
2112 if (usir0 & USIR0_IR0) {
2113 dev->ep[0].pio_irqs++;
2114 handle_ep0(dev);
2115 handled = 1;
2116 }
2117
2118 /* endpoint data transfers */
2119 for (i = 0; i < 8; i++) {
2120 u32 tmp = 1 << i;
2121
2122 if (i && (usir0 & tmp)) {
2123 handle_ep(&dev->ep[i]);
2124 USIR0 |= tmp;
2125 handled = 1;
2126 }
2127 if (usir1 & tmp) {
2128 handle_ep(&dev->ep[i+8]);
2129 USIR1 |= tmp;
2130 handled = 1;
2131 }
2132 }
2133 }
2134
2135 /* we could also ask for 1 msec SOF (SIR) interrupts */
2136
2137 } while (handled);
2138 return IRQ_HANDLED;
2139 }
2140
2141 /*-------------------------------------------------------------------------*/
2142
2143 static void nop_release (struct device *dev)
2144 {
2145 DMSG("%s %s\n", __FUNCTION__, dev->bus_id);
2146 }
2147
2148 /* this uses load-time allocation and initialization (instead of
2149 * doing it at run-time) to save code, eliminate fault paths, and
2150 * be more obviously correct.
2151 */
2152 static struct pxa2xx_udc memory = {
2153 .gadget = {
2154 .ops = &pxa2xx_udc_ops,
2155 .ep0 = &memory.ep[0].ep,
2156 .name = driver_name,
2157 .dev = {
2158 .bus_id = "gadget",
2159 .release = nop_release,
2160 },
2161 },
2162
2163 /* control endpoint */
2164 .ep[0] = {
2165 .ep = {
2166 .name = ep0name,
2167 .ops = &pxa2xx_ep_ops,
2168 .maxpacket = EP0_FIFO_SIZE,
2169 },
2170 .dev = &memory,
2171 .reg_udccs = &UDCCS0,
2172 .reg_uddr = &UDDR0,
2173 },
2174
2175 /* first group of endpoints */
2176 .ep[1] = {
2177 .ep = {
2178 .name = "ep1in-bulk",
2179 .ops = &pxa2xx_ep_ops,
2180 .maxpacket = BULK_FIFO_SIZE,
2181 },
2182 .dev = &memory,
2183 .fifo_size = BULK_FIFO_SIZE,
2184 .bEndpointAddress = USB_DIR_IN | 1,
2185 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2186 .reg_udccs = &UDCCS1,
2187 .reg_uddr = &UDDR1,
2188 drcmr (25)
2189 },
2190 .ep[2] = {
2191 .ep = {
2192 .name = "ep2out-bulk",
2193 .ops = &pxa2xx_ep_ops,
2194 .maxpacket = BULK_FIFO_SIZE,
2195 },
2196 .dev = &memory,
2197 .fifo_size = BULK_FIFO_SIZE,
2198 .bEndpointAddress = 2,
2199 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2200 .reg_udccs = &UDCCS2,
2201 .reg_ubcr = &UBCR2,
2202 .reg_uddr = &UDDR2,
2203 drcmr (26)
2204 },
2205 #ifndef CONFIG_USB_PXA2XX_SMALL
2206 .ep[3] = {
2207 .ep = {
2208 .name = "ep3in-iso",
2209 .ops = &pxa2xx_ep_ops,
2210 .maxpacket = ISO_FIFO_SIZE,
2211 },
2212 .dev = &memory,
2213 .fifo_size = ISO_FIFO_SIZE,
2214 .bEndpointAddress = USB_DIR_IN | 3,
2215 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2216 .reg_udccs = &UDCCS3,
2217 .reg_uddr = &UDDR3,
2218 drcmr (27)
2219 },
2220 .ep[4] = {
2221 .ep = {
2222 .name = "ep4out-iso",
2223 .ops = &pxa2xx_ep_ops,
2224 .maxpacket = ISO_FIFO_SIZE,
2225 },
2226 .dev = &memory,
2227 .fifo_size = ISO_FIFO_SIZE,
2228 .bEndpointAddress = 4,
2229 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2230 .reg_udccs = &UDCCS4,
2231 .reg_ubcr = &UBCR4,
2232 .reg_uddr = &UDDR4,
2233 drcmr (28)
2234 },
2235 .ep[5] = {
2236 .ep = {
2237 .name = "ep5in-int",
2238 .ops = &pxa2xx_ep_ops,
2239 .maxpacket = INT_FIFO_SIZE,
2240 },
2241 .dev = &memory,
2242 .fifo_size = INT_FIFO_SIZE,
2243 .bEndpointAddress = USB_DIR_IN | 5,
2244 .bmAttributes = USB_ENDPOINT_XFER_INT,
2245 .reg_udccs = &UDCCS5,
2246 .reg_uddr = &UDDR5,
2247 },
2248
2249 /* second group of endpoints */
2250 .ep[6] = {
2251 .ep = {
2252 .name = "ep6in-bulk",
2253 .ops = &pxa2xx_ep_ops,
2254 .maxpacket = BULK_FIFO_SIZE,
2255 },
2256 .dev = &memory,
2257 .fifo_size = BULK_FIFO_SIZE,
2258 .bEndpointAddress = USB_DIR_IN | 6,
2259 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2260 .reg_udccs = &UDCCS6,
2261 .reg_uddr = &UDDR6,
2262 drcmr (30)
2263 },
2264 .ep[7] = {
2265 .ep = {
2266 .name = "ep7out-bulk",
2267 .ops = &pxa2xx_ep_ops,
2268 .maxpacket = BULK_FIFO_SIZE,
2269 },
2270 .dev = &memory,
2271 .fifo_size = BULK_FIFO_SIZE,
2272 .bEndpointAddress = 7,
2273 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2274 .reg_udccs = &UDCCS7,
2275 .reg_ubcr = &UBCR7,
2276 .reg_uddr = &UDDR7,
2277 drcmr (31)
2278 },
2279 .ep[8] = {
2280 .ep = {
2281 .name = "ep8in-iso",
2282 .ops = &pxa2xx_ep_ops,
2283 .maxpacket = ISO_FIFO_SIZE,
2284 },
2285 .dev = &memory,
2286 .fifo_size = ISO_FIFO_SIZE,
2287 .bEndpointAddress = USB_DIR_IN | 8,
2288 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2289 .reg_udccs = &UDCCS8,
2290 .reg_uddr = &UDDR8,
2291 drcmr (32)
2292 },
2293 .ep[9] = {
2294 .ep = {
2295 .name = "ep9out-iso",
2296 .ops = &pxa2xx_ep_ops,
2297 .maxpacket = ISO_FIFO_SIZE,
2298 },
2299 .dev = &memory,
2300 .fifo_size = ISO_FIFO_SIZE,
2301 .bEndpointAddress = 9,
2302 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2303 .reg_udccs = &UDCCS9,
2304 .reg_ubcr = &UBCR9,
2305 .reg_uddr = &UDDR9,
2306 drcmr (33)
2307 },
2308 .ep[10] = {
2309 .ep = {
2310 .name = "ep10in-int",
2311 .ops = &pxa2xx_ep_ops,
2312 .maxpacket = INT_FIFO_SIZE,
2313 },
2314 .dev = &memory,
2315 .fifo_size = INT_FIFO_SIZE,
2316 .bEndpointAddress = USB_DIR_IN | 10,
2317 .bmAttributes = USB_ENDPOINT_XFER_INT,
2318 .reg_udccs = &UDCCS10,
2319 .reg_uddr = &UDDR10,
2320 },
2321
2322 /* third group of endpoints */
2323 .ep[11] = {
2324 .ep = {
2325 .name = "ep11in-bulk",
2326 .ops = &pxa2xx_ep_ops,
2327 .maxpacket = BULK_FIFO_SIZE,
2328 },
2329 .dev = &memory,
2330 .fifo_size = BULK_FIFO_SIZE,
2331 .bEndpointAddress = USB_DIR_IN | 11,
2332 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2333 .reg_udccs = &UDCCS11,
2334 .reg_uddr = &UDDR11,
2335 drcmr (35)
2336 },
2337 .ep[12] = {
2338 .ep = {
2339 .name = "ep12out-bulk",
2340 .ops = &pxa2xx_ep_ops,
2341 .maxpacket = BULK_FIFO_SIZE,
2342 },
2343 .dev = &memory,
2344 .fifo_size = BULK_FIFO_SIZE,
2345 .bEndpointAddress = 12,
2346 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2347 .reg_udccs = &UDCCS12,
2348 .reg_ubcr = &UBCR12,
2349 .reg_uddr = &UDDR12,
2350 drcmr (36)
2351 },
2352 .ep[13] = {
2353 .ep = {
2354 .name = "ep13in-iso",
2355 .ops = &pxa2xx_ep_ops,
2356 .maxpacket = ISO_FIFO_SIZE,
2357 },
2358 .dev = &memory,
2359 .fifo_size = ISO_FIFO_SIZE,
2360 .bEndpointAddress = USB_DIR_IN | 13,
2361 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2362 .reg_udccs = &UDCCS13,
2363 .reg_uddr = &UDDR13,
2364 drcmr (37)
2365 },
2366 .ep[14] = {
2367 .ep = {
2368 .name = "ep14out-iso",
2369 .ops = &pxa2xx_ep_ops,
2370 .maxpacket = ISO_FIFO_SIZE,
2371 },
2372 .dev = &memory,
2373 .fifo_size = ISO_FIFO_SIZE,
2374 .bEndpointAddress = 14,
2375 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2376 .reg_udccs = &UDCCS14,
2377 .reg_ubcr = &UBCR14,
2378 .reg_uddr = &UDDR14,
2379 drcmr (38)
2380 },
2381 .ep[15] = {
2382 .ep = {
2383 .name = "ep15in-int",
2384 .ops = &pxa2xx_ep_ops,
2385 .maxpacket = INT_FIFO_SIZE,
2386 },
2387 .dev = &memory,
2388 .fifo_size = INT_FIFO_SIZE,
2389 .bEndpointAddress = USB_DIR_IN | 15,
2390 .bmAttributes = USB_ENDPOINT_XFER_INT,
2391 .reg_udccs = &UDCCS15,
2392 .reg_uddr = &UDDR15,
2393 },
2394 #endif /* !CONFIG_USB_PXA2XX_SMALL */
2395 };
2396
2397 #define CP15R0_VENDOR_MASK 0xffffe000
2398
2399 #if defined(CONFIG_ARCH_PXA)
2400 #define CP15R0_XSCALE_VALUE 0x69052000 /* intel/arm/xscale */
2401
2402 #elif defined(CONFIG_ARCH_IXP4XX)
2403 #define CP15R0_XSCALE_VALUE 0x69054000 /* intel/arm/ixp4xx */
2404
2405 #endif
2406
2407 #define CP15R0_PROD_MASK 0x000003f0
2408 #define PXA25x 0x00000100 /* and PXA26x */
2409 #define PXA210 0x00000120
2410
2411 #define CP15R0_REV_MASK 0x0000000f
2412
2413 #define CP15R0_PRODREV_MASK (CP15R0_PROD_MASK | CP15R0_REV_MASK)
2414
2415 #define PXA255_A0 0x00000106 /* or PXA260_B1 */
2416 #define PXA250_C0 0x00000105 /* or PXA26x_B0 */
2417 #define PXA250_B2 0x00000104
2418 #define PXA250_B1 0x00000103 /* or PXA260_A0 */
2419 #define PXA250_B0 0x00000102
2420 #define PXA250_A1 0x00000101
2421 #define PXA250_A0 0x00000100
2422
2423 #define PXA210_C0 0x00000125
2424 #define PXA210_B2 0x00000124
2425 #define PXA210_B1 0x00000123
2426 #define PXA210_B0 0x00000122
2427 #define IXP425_A0 0x000001c1
2428
2429 /*
2430 * probe - binds to the platform device
2431 */
2432 static int __init pxa2xx_udc_probe(struct device *_dev)
2433 {
2434 struct pxa2xx_udc *dev = &memory;
2435 int retval, out_dma = 1;
2436 u32 chiprev;
2437
2438 /* insist on Intel/ARM/XScale */
2439 asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev));
2440 if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) {
2441 printk(KERN_ERR "%s: not XScale!\n", driver_name);
2442 return -ENODEV;
2443 }
2444
2445 /* trigger chiprev-specific logic */
2446 switch (chiprev & CP15R0_PRODREV_MASK) {
2447 #if defined(CONFIG_ARCH_PXA)
2448 case PXA255_A0:
2449 dev->has_cfr = 1;
2450 break;
2451 case PXA250_A0:
2452 case PXA250_A1:
2453 /* A0/A1 "not released"; ep 13, 15 unusable */
2454 /* fall through */
2455 case PXA250_B2: case PXA210_B2:
2456 case PXA250_B1: case PXA210_B1:
2457 case PXA250_B0: case PXA210_B0:
2458 out_dma = 0;
2459 /* fall through */
2460 case PXA250_C0: case PXA210_C0:
2461 break;
2462 #elif defined(CONFIG_ARCH_IXP4XX)
2463 case IXP425_A0:
2464 out_dma = 0;
2465 break;
2466 #endif
2467 default:
2468 out_dma = 0;
2469 printk(KERN_ERR "%s: unrecognized processor: %08x\n",
2470 driver_name, chiprev);
2471 /* iop3xx, ixp4xx, ... */
2472 return -ENODEV;
2473 }
2474
2475 pr_debug("%s: IRQ %d%s%s%s\n", driver_name, IRQ_USB,
2476 dev->has_cfr ? "" : " (!cfr)",
2477 out_dma ? "" : " (broken dma-out)",
2478 SIZE_STR DMASTR
2479 );
2480
2481 #ifdef USE_DMA
2482 #ifndef USE_OUT_DMA
2483 out_dma = 0;
2484 #endif
2485 /* pxa 250 erratum 130 prevents using OUT dma (fixed C0) */
2486 if (!out_dma) {
2487 DMSG("disabled OUT dma\n");
2488 dev->ep[ 2].reg_drcmr = dev->ep[ 4].reg_drcmr = 0;
2489 dev->ep[ 7].reg_drcmr = dev->ep[ 9].reg_drcmr = 0;
2490 dev->ep[12].reg_drcmr = dev->ep[14].reg_drcmr = 0;
2491 }
2492 #endif
2493
2494 /* other non-static parts of init */
2495 dev->dev = _dev;
2496 dev->mach = _dev->platform_data;
2497
2498 init_timer(&dev->timer);
2499 dev->timer.function = udc_watchdog;
2500 dev->timer.data = (unsigned long) dev;
2501
2502 device_initialize(&dev->gadget.dev);
2503 dev->gadget.dev.parent = _dev;
2504 dev->gadget.dev.dma_mask = _dev->dma_mask;
2505
2506 the_controller = dev;
2507 dev_set_drvdata(_dev, dev);
2508
2509 udc_disable(dev);
2510 udc_reinit(dev);
2511
2512 dev->vbus = is_usb_connected();
2513
2514 /* irq setup after old hardware state is cleaned up */
2515 retval = request_irq(IRQ_USB, pxa2xx_udc_irq,
2516 SA_INTERRUPT, driver_name, dev);
2517 if (retval != 0) {
2518 printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2519 driver_name, IRQ_USB, retval);
2520 return -EBUSY;
2521 }
2522 dev->got_irq = 1;
2523
2524 #ifdef CONFIG_ARCH_LUBBOCK
2525 if (machine_is_lubbock()) {
2526 retval = request_irq(LUBBOCK_USB_DISC_IRQ,
2527 lubbock_vbus_irq,
2528 SA_INTERRUPT | SA_SAMPLE_RANDOM,
2529 driver_name, dev);
2530 if (retval != 0) {
2531 printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2532 driver_name, LUBBOCK_USB_DISC_IRQ, retval);
2533 lubbock_fail0:
2534 free_irq(IRQ_USB, dev);
2535 return -EBUSY;
2536 }
2537 retval = request_irq(LUBBOCK_USB_IRQ,
2538 lubbock_vbus_irq,
2539 SA_INTERRUPT | SA_SAMPLE_RANDOM,
2540 driver_name, dev);
2541 if (retval != 0) {
2542 printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2543 driver_name, LUBBOCK_USB_IRQ, retval);
2544 free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2545 goto lubbock_fail0;
2546 }
2547 #ifdef DEBUG
2548 /* with U-Boot (but not BLOB), hex is off by default */
2549 HEX_DISPLAY(dev->stats.irqs);
2550 LUB_DISC_BLNK_LED &= 0xff;
2551 #endif
2552 }
2553 #endif
2554 create_proc_files();
2555
2556 return 0;
2557 }
2558 static int __exit pxa2xx_udc_remove(struct device *_dev)
2559 {
2560 struct pxa2xx_udc *dev = dev_get_drvdata(_dev);
2561
2562 udc_disable(dev);
2563 remove_proc_files();
2564 usb_gadget_unregister_driver(dev->driver);
2565
2566 if (dev->got_irq) {
2567 free_irq(IRQ_USB, dev);
2568 dev->got_irq = 0;
2569 }
2570 if (machine_is_lubbock()) {
2571 free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2572 free_irq(LUBBOCK_USB_IRQ, dev);
2573 }
2574 dev_set_drvdata(_dev, NULL);
2575 the_controller = NULL;
2576 return 0;
2577 }
2578
2579 /*-------------------------------------------------------------------------*/
2580
2581 #ifdef CONFIG_PM
2582
2583 /* USB suspend (controlled by the host) and system suspend (controlled
2584 * by the PXA) don't necessarily work well together. If USB is active,
2585 * the 48 MHz clock is required; so the system can't enter 33 MHz idle
2586 * mode, or any deeper PM saving state.
2587 *
2588 * For now, we punt and forcibly disconnect from the USB host when PXA
2589 * enters any suspend state. While we're disconnected, we always disable
2590 * the 48MHz USB clock ... allowing PXA sleep and/or 33 MHz idle states.
2591 * Boards without software pullup control shouldn't use those states.
2592 * VBUS IRQs should probably be ignored so that the PXA device just acts
2593 * "dead" to USB hosts until system resume.
2594 */
2595 static int pxa2xx_udc_suspend(struct device *dev, u32 state, u32 level)
2596 {
2597 struct pxa2xx_udc *udc = dev_get_drvdata(dev);
2598
2599 if (level == SUSPEND_POWER_DOWN) {
2600 if (!udc->mach->udc_command)
2601 WARN("USB host won't detect disconnect!\n");
2602 pullup(udc, 0);
2603 }
2604 return 0;
2605 }
2606
2607 static int pxa2xx_udc_resume(struct device *dev, u32 level)
2608 {
2609 struct pxa2xx_udc *udc = dev_get_drvdata(dev);
2610
2611 if (level == RESUME_POWER_ON)
2612 pullup(udc, 1);
2613 return 0;
2614 }
2615
2616 #else
2617 #define pxa2xx_udc_suspend NULL
2618 #define pxa2xx_udc_resume NULL
2619 #endif
2620
2621 /*-------------------------------------------------------------------------*/
2622
2623 static struct device_driver udc_driver = {
2624 .name = "pxa2xx-udc",
2625 .bus = &platform_bus_type,
2626 .probe = pxa2xx_udc_probe,
2627 .remove = __exit_p(pxa2xx_udc_remove),
2628 .suspend = pxa2xx_udc_suspend,
2629 .resume = pxa2xx_udc_resume,
2630 };
2631
2632 static int __init udc_init(void)
2633 {
2634 printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION);
2635 return driver_register(&udc_driver);
2636 }
2637 module_init(udc_init);
2638
2639 static void __exit udc_exit(void)
2640 {
2641 driver_unregister(&udc_driver);
2642 }
2643 module_exit(udc_exit);
2644
2645 MODULE_DESCRIPTION(DRIVER_DESC);
2646 MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
2647 MODULE_LICENSE("GPL");
2648
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