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Merge tag 'xtensa-20180225' of git://github.com/jcmvbkbc/linux-xtensa
[cris-mirror.git] / arch / arm64 / kernel / traps.c
blobeb2d15147e8d3bb2be8731400990f18979022fce
1 /*
2 * Based on arch/arm/kernel/traps.c
3 *
4 * Copyright (C) 1995-2009 Russell King
5 * Copyright (C) 2012 ARM Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <linux/bug.h>
21 #include <linux/signal.h>
22 #include <linux/personality.h>
23 #include <linux/kallsyms.h>
24 #include <linux/spinlock.h>
25 #include <linux/uaccess.h>
26 #include <linux/hardirq.h>
27 #include <linux/kdebug.h>
28 #include <linux/module.h>
29 #include <linux/kexec.h>
30 #include <linux/delay.h>
31 #include <linux/init.h>
32 #include <linux/sched/signal.h>
33 #include <linux/sched/debug.h>
34 #include <linux/sched/task_stack.h>
35 #include <linux/sizes.h>
36 #include <linux/syscalls.h>
37 #include <linux/mm_types.h>
38
39 #include <asm/atomic.h>
40 #include <asm/bug.h>
41 #include <asm/daifflags.h>
42 #include <asm/debug-monitors.h>
43 #include <asm/esr.h>
44 #include <asm/insn.h>
45 #include <asm/traps.h>
46 #include <asm/smp.h>
47 #include <asm/stack_pointer.h>
48 #include <asm/stacktrace.h>
49 #include <asm/exception.h>
50 #include <asm/system_misc.h>
51 #include <asm/sysreg.h>
52
53 static const char *handler[]= {
54 "Synchronous Abort",
55 "IRQ",
56 "FIQ",
57 "Error"
58 };
59
60 int show_unhandled_signals = 0;
61
62 static void dump_backtrace_entry(unsigned long where)
63 {
64 printk(" %pS\n", (void *)where);
65 }
66
67 static void __dump_instr(const char *lvl, struct pt_regs *regs)
68 {
69 unsigned long addr = instruction_pointer(regs);
70 char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
71 int i;
72
73 for (i = -4; i < 1; i++) {
74 unsigned int val, bad;
75
76 bad = get_user(val, &((u32 *)addr)[i]);
77
78 if (!bad)
79 p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val);
80 else {
81 p += sprintf(p, "bad PC value");
82 break;
83 }
84 }
85 printk("%sCode: %s\n", lvl, str);
86 }
87
88 static void dump_instr(const char *lvl, struct pt_regs *regs)
89 {
90 if (!user_mode(regs)) {
91 mm_segment_t fs = get_fs();
92 set_fs(KERNEL_DS);
93 __dump_instr(lvl, regs);
94 set_fs(fs);
95 } else {
96 __dump_instr(lvl, regs);
97 }
98 }
99
100 void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
101 {
102 struct stackframe frame;
103 int skip;
104
105 pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk);
106
107 if (!tsk)
108 tsk = current;
109
110 if (!try_get_task_stack(tsk))
111 return;
112
113 if (tsk == current) {
114 frame.fp = (unsigned long)__builtin_frame_address(0);
115 frame.pc = (unsigned long)dump_backtrace;
116 } else {
117 /*
118 * task blocked in __switch_to
119 */
120 frame.fp = thread_saved_fp(tsk);
121 frame.pc = thread_saved_pc(tsk);
122 }
123 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
124 frame.graph = tsk->curr_ret_stack;
125 #endif
126
127 skip = !!regs;
128 printk("Call trace:\n");
129 do {
130 /* skip until specified stack frame */
131 if (!skip) {
132 dump_backtrace_entry(frame.pc);
133 } else if (frame.fp == regs->regs[29]) {
134 skip = 0;
135 /*
136 * Mostly, this is the case where this function is
137 * called in panic/abort. As exception handler's
138 * stack frame does not contain the corresponding pc
139 * at which an exception has taken place, use regs->pc
140 * instead.
141 */
142 dump_backtrace_entry(regs->pc);
143 }
144 } while (!unwind_frame(tsk, &frame));
145
146 put_task_stack(tsk);
147 }
148
149 void show_stack(struct task_struct *tsk, unsigned long *sp)
150 {
151 dump_backtrace(NULL, tsk);
152 barrier();
153 }
154
155 #ifdef CONFIG_PREEMPT
156 #define S_PREEMPT " PREEMPT"
157 #else
158 #define S_PREEMPT ""
159 #endif
160 #define S_SMP " SMP"
161
162 static int __die(const char *str, int err, struct pt_regs *regs)
163 {
164 struct task_struct *tsk = current;
165 static int die_counter;
166 int ret;
167
168 pr_emerg("Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n",
169 str, err, ++die_counter);
170
171 /* trap and error numbers are mostly meaningless on ARM */
172 ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV);
173 if (ret == NOTIFY_STOP)
174 return ret;
175
176 print_modules();
177 __show_regs(regs);
178 pr_emerg("Process %.*s (pid: %d, stack limit = 0x%p)\n",
179 TASK_COMM_LEN, tsk->comm, task_pid_nr(tsk),
180 end_of_stack(tsk));
181
182 if (!user_mode(regs)) {
183 dump_backtrace(regs, tsk);
184 dump_instr(KERN_EMERG, regs);
185 }
186
187 return ret;
188 }
189
190 static DEFINE_RAW_SPINLOCK(die_lock);
191
192 /*
193 * This function is protected against re-entrancy.
194 */
195 void die(const char *str, struct pt_regs *regs, int err)
196 {
197 int ret;
198 unsigned long flags;
199
200 raw_spin_lock_irqsave(&die_lock, flags);
201
202 oops_enter();
203
204 console_verbose();
205 bust_spinlocks(1);
206 ret = __die(str, err, regs);
207
208 if (regs && kexec_should_crash(current))
209 crash_kexec(regs);
210
211 bust_spinlocks(0);
212 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
213 oops_exit();
214
215 if (in_interrupt())
216 panic("Fatal exception in interrupt");
217 if (panic_on_oops)
218 panic("Fatal exception");
219
220 raw_spin_unlock_irqrestore(&die_lock, flags);
221
222 if (ret != NOTIFY_STOP)
223 do_exit(SIGSEGV);
224 }
225
226 void arm64_notify_die(const char *str, struct pt_regs *regs,
227 struct siginfo *info, int err)
228 {
229 if (user_mode(regs)) {
230 current->thread.fault_address = 0;
231 current->thread.fault_code = err;
232 force_sig_info(info->si_signo, info, current);
233 } else {
234 die(str, regs, err);
235 }
236 }
237
238 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size)
239 {
240 regs->pc += size;
241
242 /*
243 * If we were single stepping, we want to get the step exception after
244 * we return from the trap.
245 */
246 user_fastforward_single_step(current);
247 }
248
249 static LIST_HEAD(undef_hook);
250 static DEFINE_RAW_SPINLOCK(undef_lock);
251
252 void register_undef_hook(struct undef_hook *hook)
253 {
254 unsigned long flags;
255
256 raw_spin_lock_irqsave(&undef_lock, flags);
257 list_add(&hook->node, &undef_hook);
258 raw_spin_unlock_irqrestore(&undef_lock, flags);
259 }
260
261 void unregister_undef_hook(struct undef_hook *hook)
262 {
263 unsigned long flags;
264
265 raw_spin_lock_irqsave(&undef_lock, flags);
266 list_del(&hook->node);
267 raw_spin_unlock_irqrestore(&undef_lock, flags);
268 }
269
270 static int call_undef_hook(struct pt_regs *regs)
271 {
272 struct undef_hook *hook;
273 unsigned long flags;
274 u32 instr;
275 int (*fn)(struct pt_regs *regs, u32 instr) = NULL;
276 void __user *pc = (void __user *)instruction_pointer(regs);
277
278 if (!user_mode(regs))
279 return 1;
280
281 if (compat_thumb_mode(regs)) {
282 /* 16-bit Thumb instruction */
283 __le16 instr_le;
284 if (get_user(instr_le, (__le16 __user *)pc))
285 goto exit;
286 instr = le16_to_cpu(instr_le);
287 if (aarch32_insn_is_wide(instr)) {
288 u32 instr2;
289
290 if (get_user(instr_le, (__le16 __user *)(pc + 2)))
291 goto exit;
292 instr2 = le16_to_cpu(instr_le);
293 instr = (instr << 16) | instr2;
294 }
295 } else {
296 /* 32-bit ARM instruction */
297 __le32 instr_le;
298 if (get_user(instr_le, (__le32 __user *)pc))
299 goto exit;
300 instr = le32_to_cpu(instr_le);
301 }
302
303 raw_spin_lock_irqsave(&undef_lock, flags);
304 list_for_each_entry(hook, &undef_hook, node)
305 if ((instr & hook->instr_mask) == hook->instr_val &&
306 (regs->pstate & hook->pstate_mask) == hook->pstate_val)
307 fn = hook->fn;
308
309 raw_spin_unlock_irqrestore(&undef_lock, flags);
310 exit:
311 return fn ? fn(regs, instr) : 1;
312 }
313
314 void force_signal_inject(int signal, int code, struct pt_regs *regs,
315 unsigned long address)
316 {
317 siginfo_t info;
318 void __user *pc = (void __user *)instruction_pointer(regs);
319 const char *desc;
320
321 switch (signal) {
322 case SIGILL:
323 desc = "undefined instruction";
324 break;
325 case SIGSEGV:
326 desc = "illegal memory access";
327 break;
328 default:
329 desc = "unknown or unrecoverable error";
330 break;
331 }
332
333 if (unhandled_signal(current, signal) &&
334 show_unhandled_signals_ratelimited()) {
335 pr_info("%s[%d]: %s: pc=%p\n",
336 current->comm, task_pid_nr(current), desc, pc);
337 dump_instr(KERN_INFO, regs);
338 }
339
340 info.si_signo = signal;
341 info.si_errno = 0;
342 info.si_code = code;
343 info.si_addr = pc;
344
345 arm64_notify_die(desc, regs, &info, 0);
346 }
347
348 /*
349 * Set up process info to signal segmentation fault - called on access error.
350 */
351 void arm64_notify_segfault(struct pt_regs *regs, unsigned long addr)
352 {
353 int code;
354
355 down_read(&current->mm->mmap_sem);
356 if (find_vma(current->mm, addr) == NULL)
357 code = SEGV_MAPERR;
358 else
359 code = SEGV_ACCERR;
360 up_read(&current->mm->mmap_sem);
361
362 force_signal_inject(SIGSEGV, code, regs, addr);
363 }
364
365 asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
366 {
367 /* check for AArch32 breakpoint instructions */
368 if (!aarch32_break_handler(regs))
369 return;
370
371 if (call_undef_hook(regs) == 0)
372 return;
373
374 force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0);
375 }
376
377 int cpu_enable_cache_maint_trap(void *__unused)
378 {
379 config_sctlr_el1(SCTLR_EL1_UCI, 0);
380 return 0;
381 }
382
383 #define __user_cache_maint(insn, address, res) \
384 if (address >= user_addr_max()) { \
385 res = -EFAULT; \
386 } else { \
387 uaccess_ttbr0_enable(); \
388 asm volatile ( \
389 "1: " insn ", %1\n" \
390 " mov %w0, #0\n" \
391 "2:\n" \
392 " .pushsection .fixup,\"ax\"\n" \
393 " .align 2\n" \
394 "3: mov %w0, %w2\n" \
395 " b 2b\n" \
396 " .popsection\n" \
397 _ASM_EXTABLE(1b, 3b) \
398 : "=r" (res) \
399 : "r" (address), "i" (-EFAULT)); \
400 uaccess_ttbr0_disable(); \
401 }
402
403 static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)
404 {
405 unsigned long address;
406 int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
407 int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;
408 int ret = 0;
409
410 address = untagged_addr(pt_regs_read_reg(regs, rt));
411
412 switch (crm) {
413 case ESR_ELx_SYS64_ISS_CRM_DC_CVAU: /* DC CVAU, gets promoted */
414 __user_cache_maint("dc civac", address, ret);
415 break;
416 case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */
417 __user_cache_maint("dc civac", address, ret);
418 break;
419 case ESR_ELx_SYS64_ISS_CRM_DC_CVAP: /* DC CVAP */
420 __user_cache_maint("sys 3, c7, c12, 1", address, ret);
421 break;
422 case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC: /* DC CIVAC */
423 __user_cache_maint("dc civac", address, ret);
424 break;
425 case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */
426 __user_cache_maint("ic ivau", address, ret);
427 break;
428 default:
429 force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0);
430 return;
431 }
432
433 if (ret)
434 arm64_notify_segfault(regs, address);
435 else
436 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
437 }
438
439 static void ctr_read_handler(unsigned int esr, struct pt_regs *regs)
440 {
441 int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
442 unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);
443
444 pt_regs_write_reg(regs, rt, val);
445
446 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
447 }
448
449 static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
450 {
451 int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
452
453 pt_regs_write_reg(regs, rt, arch_counter_get_cntvct());
454 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
455 }
456
457 static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)
458 {
459 int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
460
461 pt_regs_write_reg(regs, rt, arch_timer_get_rate());
462 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
463 }
464
465 struct sys64_hook {
466 unsigned int esr_mask;
467 unsigned int esr_val;
468 void (*handler)(unsigned int esr, struct pt_regs *regs);
469 };
470
471 static struct sys64_hook sys64_hooks[] = {
472 {
473 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK,
474 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL,
475 .handler = user_cache_maint_handler,
476 },
477 {
478 /* Trap read access to CTR_EL0 */
479 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
480 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ,
481 .handler = ctr_read_handler,
482 },
483 {
484 /* Trap read access to CNTVCT_EL0 */
485 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
486 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT,
487 .handler = cntvct_read_handler,
488 },
489 {
490 /* Trap read access to CNTFRQ_EL0 */
491 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
492 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ,
493 .handler = cntfrq_read_handler,
494 },
495 {},
496 };
497
498 asmlinkage void __exception do_sysinstr(unsigned int esr, struct pt_regs *regs)
499 {
500 struct sys64_hook *hook;
501
502 for (hook = sys64_hooks; hook->handler; hook++)
503 if ((hook->esr_mask & esr) == hook->esr_val) {
504 hook->handler(esr, regs);
505 return;
506 }
507
508 /*
509 * New SYS instructions may previously have been undefined at EL0. Fall
510 * back to our usual undefined instruction handler so that we handle
511 * these consistently.
512 */
513 do_undefinstr(regs);
514 }
515
516 long compat_arm_syscall(struct pt_regs *regs);
517
518 asmlinkage long do_ni_syscall(struct pt_regs *regs)
519 {
520 #ifdef CONFIG_COMPAT
521 long ret;
522 if (is_compat_task()) {
523 ret = compat_arm_syscall(regs);
524 if (ret != -ENOSYS)
525 return ret;
526 }
527 #endif
528
529 return sys_ni_syscall();
530 }
531
532 static const char *esr_class_str[] = {
533 [0 ... ESR_ELx_EC_MAX] = "UNRECOGNIZED EC",
534 [ESR_ELx_EC_UNKNOWN] = "Unknown/Uncategorized",
535 [ESR_ELx_EC_WFx] = "WFI/WFE",
536 [ESR_ELx_EC_CP15_32] = "CP15 MCR/MRC",
537 [ESR_ELx_EC_CP15_64] = "CP15 MCRR/MRRC",
538 [ESR_ELx_EC_CP14_MR] = "CP14 MCR/MRC",
539 [ESR_ELx_EC_CP14_LS] = "CP14 LDC/STC",
540 [ESR_ELx_EC_FP_ASIMD] = "ASIMD",
541 [ESR_ELx_EC_CP10_ID] = "CP10 MRC/VMRS",
542 [ESR_ELx_EC_CP14_64] = "CP14 MCRR/MRRC",
543 [ESR_ELx_EC_ILL] = "PSTATE.IL",
544 [ESR_ELx_EC_SVC32] = "SVC (AArch32)",
545 [ESR_ELx_EC_HVC32] = "HVC (AArch32)",
546 [ESR_ELx_EC_SMC32] = "SMC (AArch32)",
547 [ESR_ELx_EC_SVC64] = "SVC (AArch64)",
548 [ESR_ELx_EC_HVC64] = "HVC (AArch64)",
549 [ESR_ELx_EC_SMC64] = "SMC (AArch64)",
550 [ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)",
551 [ESR_ELx_EC_SVE] = "SVE",
552 [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF",
553 [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)",
554 [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)",
555 [ESR_ELx_EC_PC_ALIGN] = "PC Alignment",
556 [ESR_ELx_EC_DABT_LOW] = "DABT (lower EL)",
557 [ESR_ELx_EC_DABT_CUR] = "DABT (current EL)",
558 [ESR_ELx_EC_SP_ALIGN] = "SP Alignment",
559 [ESR_ELx_EC_FP_EXC32] = "FP (AArch32)",
560 [ESR_ELx_EC_FP_EXC64] = "FP (AArch64)",
561 [ESR_ELx_EC_SERROR] = "SError",
562 [ESR_ELx_EC_BREAKPT_LOW] = "Breakpoint (lower EL)",
563 [ESR_ELx_EC_BREAKPT_CUR] = "Breakpoint (current EL)",
564 [ESR_ELx_EC_SOFTSTP_LOW] = "Software Step (lower EL)",
565 [ESR_ELx_EC_SOFTSTP_CUR] = "Software Step (current EL)",
566 [ESR_ELx_EC_WATCHPT_LOW] = "Watchpoint (lower EL)",
567 [ESR_ELx_EC_WATCHPT_CUR] = "Watchpoint (current EL)",
568 [ESR_ELx_EC_BKPT32] = "BKPT (AArch32)",
569 [ESR_ELx_EC_VECTOR32] = "Vector catch (AArch32)",
570 [ESR_ELx_EC_BRK64] = "BRK (AArch64)",
571 };
572
573 const char *esr_get_class_string(u32 esr)
574 {
575 return esr_class_str[ESR_ELx_EC(esr)];
576 }
577
578 /*
579 * bad_mode handles the impossible case in the exception vector. This is always
580 * fatal.
581 */
582 asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr)
583 {
584 console_verbose();
585
586 pr_crit("Bad mode in %s handler detected on CPU%d, code 0x%08x -- %s\n",
587 handler[reason], smp_processor_id(), esr,
588 esr_get_class_string(esr));
589
590 die("Oops - bad mode", regs, 0);
591 local_daif_mask();
592 panic("bad mode");
593 }
594
595 /*
596 * bad_el0_sync handles unexpected, but potentially recoverable synchronous
597 * exceptions taken from EL0. Unlike bad_mode, this returns.
598 */
599 asmlinkage void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr)
600 {
601 siginfo_t info;
602 void __user *pc = (void __user *)instruction_pointer(regs);
603 console_verbose();
604
605 pr_crit("Bad EL0 synchronous exception detected on CPU%d, code 0x%08x -- %s\n",
606 smp_processor_id(), esr, esr_get_class_string(esr));
607 __show_regs(regs);
608
609 info.si_signo = SIGILL;
610 info.si_errno = 0;
611 info.si_code = ILL_ILLOPC;
612 info.si_addr = pc;
613
614 current->thread.fault_address = 0;
615 current->thread.fault_code = 0;
616
617 force_sig_info(info.si_signo, &info, current);
618 }
619
620 #ifdef CONFIG_VMAP_STACK
621
622 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack)
623 __aligned(16);
624
625 asmlinkage void handle_bad_stack(struct pt_regs *regs)
626 {
627 unsigned long tsk_stk = (unsigned long)current->stack;
628 unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr);
629 unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack);
630 unsigned int esr = read_sysreg(esr_el1);
631 unsigned long far = read_sysreg(far_el1);
632
633 console_verbose();
634 pr_emerg("Insufficient stack space to handle exception!");
635
636 pr_emerg("ESR: 0x%08x -- %s\n", esr, esr_get_class_string(esr));
637 pr_emerg("FAR: 0x%016lx\n", far);
638
639 pr_emerg("Task stack: [0x%016lx..0x%016lx]\n",
640 tsk_stk, tsk_stk + THREAD_SIZE);
641 pr_emerg("IRQ stack: [0x%016lx..0x%016lx]\n",
642 irq_stk, irq_stk + THREAD_SIZE);
643 pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n",
644 ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE);
645
646 __show_regs(regs);
647
648 /*
649 * We use nmi_panic to limit the potential for recusive overflows, and
650 * to get a better stack trace.
651 */
652 nmi_panic(NULL, "kernel stack overflow");
653 cpu_park_loop();
654 }
655 #endif
656
657 void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr)
658 {
659 console_verbose();
660
661 pr_crit("SError Interrupt on CPU%d, code 0x%08x -- %s\n",
662 smp_processor_id(), esr, esr_get_class_string(esr));
663 if (regs)
664 __show_regs(regs);
665
666 nmi_panic(regs, "Asynchronous SError Interrupt");
667
668 cpu_park_loop();
669 unreachable();
670 }
671
672 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr)
673 {
674 u32 aet = arm64_ras_serror_get_severity(esr);
675
676 switch (aet) {
677 case ESR_ELx_AET_CE: /* corrected error */
678 case ESR_ELx_AET_UEO: /* restartable, not yet consumed */
679 /*
680 * The CPU can make progress. We may take UEO again as
681 * a more severe error.
682 */
683 return false;
684
685 case ESR_ELx_AET_UEU: /* Uncorrected Unrecoverable */
686 case ESR_ELx_AET_UER: /* Uncorrected Recoverable */
687 /*
688 * The CPU can't make progress. The exception may have
689 * been imprecise.
690 */
691 return true;
692
693 case ESR_ELx_AET_UC: /* Uncontainable or Uncategorized error */
694 default:
695 /* Error has been silently propagated */
696 arm64_serror_panic(regs, esr);
697 }
698 }
699
700 asmlinkage void do_serror(struct pt_regs *regs, unsigned int esr)
701 {
702 nmi_enter();
703
704 /* non-RAS errors are not containable */
705 if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr))
706 arm64_serror_panic(regs, esr);
707
708 nmi_exit();
709 }
710
711 void __pte_error(const char *file, int line, unsigned long val)
712 {
713 pr_err("%s:%d: bad pte %016lx.\n", file, line, val);
714 }
715
716 void __pmd_error(const char *file, int line, unsigned long val)
717 {
718 pr_err("%s:%d: bad pmd %016lx.\n", file, line, val);
719 }
720
721 void __pud_error(const char *file, int line, unsigned long val)
722 {
723 pr_err("%s:%d: bad pud %016lx.\n", file, line, val);
724 }
725
726 void __pgd_error(const char *file, int line, unsigned long val)
727 {
728 pr_err("%s:%d: bad pgd %016lx.\n", file, line, val);
729 }
730
731 /* GENERIC_BUG traps */
732
733 int is_valid_bugaddr(unsigned long addr)
734 {
735 /*
736 * bug_handler() only called for BRK #BUG_BRK_IMM.
737 * So the answer is trivial -- any spurious instances with no
738 * bug table entry will be rejected by report_bug() and passed
739 * back to the debug-monitors code and handled as a fatal
740 * unexpected debug exception.
741 */
742 return 1;
743 }
744
745 static int bug_handler(struct pt_regs *regs, unsigned int esr)
746 {
747 if (user_mode(regs))
748 return DBG_HOOK_ERROR;
749
750 switch (report_bug(regs->pc, regs)) {
751 case BUG_TRAP_TYPE_BUG:
752 die("Oops - BUG", regs, 0);
753 break;
754
755 case BUG_TRAP_TYPE_WARN:
756 break;
757
758 default:
759 /* unknown/unrecognised bug trap type */
760 return DBG_HOOK_ERROR;
761 }
762
763 /* If thread survives, skip over the BUG instruction and continue: */
764 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
765 return DBG_HOOK_HANDLED;
766 }
767
768 static struct break_hook bug_break_hook = {
769 .esr_val = 0xf2000000 | BUG_BRK_IMM,
770 .esr_mask = 0xffffffff,
771 .fn = bug_handler,
772 };
773
774 /*
775 * Initial handler for AArch64 BRK exceptions
776 * This handler only used until debug_traps_init().
777 */
778 int __init early_brk64(unsigned long addr, unsigned int esr,
779 struct pt_regs *regs)
780 {
781 return bug_handler(regs, esr) != DBG_HOOK_HANDLED;
782 }
783
784 /* This registration must happen early, before debug_traps_init(). */
785 void __init trap_init(void)
786 {
787 register_break_hook(&bug_break_hook);
788 }
CRIS linux kernel tree