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Merge tag 'xtensa-20180225' of git://github.com/jcmvbkbc/linux-xtensa
[cris-mirror.git] / include / linux / qed / qed_if.h
blob15e398c7230ef5bcecdf1acecf19475022731d28
1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef _QED_IF_H
34 #define _QED_IF_H
35
36 #include <linux/types.h>
37 #include <linux/interrupt.h>
38 #include <linux/netdevice.h>
39 #include <linux/pci.h>
40 #include <linux/skbuff.h>
41 #include <linux/types.h>
42 #include <asm/byteorder.h>
43 #include <linux/io.h>
44 #include <linux/compiler.h>
45 #include <linux/kernel.h>
46 #include <linux/list.h>
47 #include <linux/slab.h>
48 #include <linux/qed/common_hsi.h>
49 #include <linux/qed/qed_chain.h>
50
51 enum dcbx_protocol_type {
52 DCBX_PROTOCOL_ISCSI,
53 DCBX_PROTOCOL_FCOE,
54 DCBX_PROTOCOL_ROCE,
55 DCBX_PROTOCOL_ROCE_V2,
56 DCBX_PROTOCOL_ETH,
57 DCBX_MAX_PROTOCOL_TYPE
58 };
59
60 #define QED_ROCE_PROTOCOL_INDEX (3)
61
62 #define QED_LLDP_CHASSIS_ID_STAT_LEN 4
63 #define QED_LLDP_PORT_ID_STAT_LEN 4
64 #define QED_DCBX_MAX_APP_PROTOCOL 32
65 #define QED_MAX_PFC_PRIORITIES 8
66 #define QED_DCBX_DSCP_SIZE 64
67
68 struct qed_dcbx_lldp_remote {
69 u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
70 u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN];
71 bool enable_rx;
72 bool enable_tx;
73 u32 tx_interval;
74 u32 max_credit;
75 };
76
77 struct qed_dcbx_lldp_local {
78 u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
79 u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN];
80 };
81
82 struct qed_dcbx_app_prio {
83 u8 roce;
84 u8 roce_v2;
85 u8 fcoe;
86 u8 iscsi;
87 u8 eth;
88 };
89
90 struct qed_dbcx_pfc_params {
91 bool willing;
92 bool enabled;
93 u8 prio[QED_MAX_PFC_PRIORITIES];
94 u8 max_tc;
95 };
96
97 enum qed_dcbx_sf_ieee_type {
98 QED_DCBX_SF_IEEE_ETHTYPE,
99 QED_DCBX_SF_IEEE_TCP_PORT,
100 QED_DCBX_SF_IEEE_UDP_PORT,
101 QED_DCBX_SF_IEEE_TCP_UDP_PORT
102 };
103
104 struct qed_app_entry {
105 bool ethtype;
106 enum qed_dcbx_sf_ieee_type sf_ieee;
107 bool enabled;
108 u8 prio;
109 u16 proto_id;
110 enum dcbx_protocol_type proto_type;
111 };
112
113 struct qed_dcbx_params {
114 struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL];
115 u16 num_app_entries;
116 bool app_willing;
117 bool app_valid;
118 bool app_error;
119 bool ets_willing;
120 bool ets_enabled;
121 bool ets_cbs;
122 bool valid;
123 u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES];
124 u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES];
125 u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES];
126 struct qed_dbcx_pfc_params pfc;
127 u8 max_ets_tc;
128 };
129
130 struct qed_dcbx_admin_params {
131 struct qed_dcbx_params params;
132 bool valid;
133 };
134
135 struct qed_dcbx_remote_params {
136 struct qed_dcbx_params params;
137 bool valid;
138 };
139
140 struct qed_dcbx_operational_params {
141 struct qed_dcbx_app_prio app_prio;
142 struct qed_dcbx_params params;
143 bool valid;
144 bool enabled;
145 bool ieee;
146 bool cee;
147 bool local;
148 u32 err;
149 };
150
151 struct qed_dcbx_get {
152 struct qed_dcbx_operational_params operational;
153 struct qed_dcbx_lldp_remote lldp_remote;
154 struct qed_dcbx_lldp_local lldp_local;
155 struct qed_dcbx_remote_params remote;
156 struct qed_dcbx_admin_params local;
157 };
158
159 enum qed_nvm_images {
160 QED_NVM_IMAGE_ISCSI_CFG,
161 QED_NVM_IMAGE_FCOE_CFG,
162 };
163
164 struct qed_link_eee_params {
165 u32 tx_lpi_timer;
166 #define QED_EEE_1G_ADV BIT(0)
167 #define QED_EEE_10G_ADV BIT(1)
168
169 /* Capabilities are represented using QED_EEE_*_ADV values */
170 u8 adv_caps;
171 u8 lp_adv_caps;
172 bool enable;
173 bool tx_lpi_enable;
174 };
175
176 enum qed_led_mode {
177 QED_LED_MODE_OFF,
178 QED_LED_MODE_ON,
179 QED_LED_MODE_RESTORE
180 };
181
182 #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
183 (void __iomem *)(reg_addr))
184
185 #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
186
187 #define QED_COALESCE_MAX 0x1FF
188 #define QED_DEFAULT_RX_USECS 12
189 #define QED_DEFAULT_TX_USECS 48
190
191 /* forward */
192 struct qed_dev;
193
194 struct qed_eth_pf_params {
195 /* The following parameters are used during HW-init
196 * and these parameters need to be passed as arguments
197 * to update_pf_params routine invoked before slowpath start
198 */
199 u16 num_cons;
200
201 /* per-VF number of CIDs */
202 u8 num_vf_cons;
203 #define ETH_PF_PARAMS_VF_CONS_DEFAULT (32)
204
205 /* To enable arfs, previous to HW-init a positive number needs to be
206 * set [as filters require allocated searcher ILT memory].
207 * This will set the maximal number of configured steering-filters.
208 */
209 u32 num_arfs_filters;
210 };
211
212 struct qed_fcoe_pf_params {
213 /* The following parameters are used during protocol-init */
214 u64 glbl_q_params_addr;
215 u64 bdq_pbl_base_addr[2];
216
217 /* The following parameters are used during HW-init
218 * and these parameters need to be passed as arguments
219 * to update_pf_params routine invoked before slowpath start
220 */
221 u16 num_cons;
222 u16 num_tasks;
223
224 /* The following parameters are used during protocol-init */
225 u16 sq_num_pbl_pages;
226
227 u16 cq_num_entries;
228 u16 cmdq_num_entries;
229 u16 rq_buffer_log_size;
230 u16 mtu;
231 u16 dummy_icid;
232 u16 bdq_xoff_threshold[2];
233 u16 bdq_xon_threshold[2];
234 u16 rq_buffer_size;
235 u8 num_cqs; /* num of global CQs */
236 u8 log_page_size;
237 u8 gl_rq_pi;
238 u8 gl_cmd_pi;
239 u8 debug_mode;
240 u8 is_target;
241 u8 bdq_pbl_num_entries[2];
242 };
243
244 /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */
245 struct qed_iscsi_pf_params {
246 u64 glbl_q_params_addr;
247 u64 bdq_pbl_base_addr[3];
248 u16 cq_num_entries;
249 u16 cmdq_num_entries;
250 u32 two_msl_timer;
251 u16 tx_sws_timer;
252
253 /* The following parameters are used during HW-init
254 * and these parameters need to be passed as arguments
255 * to update_pf_params routine invoked before slowpath start
256 */
257 u16 num_cons;
258 u16 num_tasks;
259
260 /* The following parameters are used during protocol-init */
261 u16 half_way_close_timeout;
262 u16 bdq_xoff_threshold[3];
263 u16 bdq_xon_threshold[3];
264 u16 cmdq_xoff_threshold;
265 u16 cmdq_xon_threshold;
266 u16 rq_buffer_size;
267
268 u8 num_sq_pages_in_ring;
269 u8 num_r2tq_pages_in_ring;
270 u8 num_uhq_pages_in_ring;
271 u8 num_queues;
272 u8 log_page_size;
273 u8 rqe_log_size;
274 u8 max_fin_rt;
275 u8 gl_rq_pi;
276 u8 gl_cmd_pi;
277 u8 debug_mode;
278 u8 ll2_ooo_queue_id;
279
280 u8 is_target;
281 u8 is_soc_en;
282 u8 soc_num_of_blocks_log;
283 u8 bdq_pbl_num_entries[3];
284 };
285
286 struct qed_rdma_pf_params {
287 /* Supplied to QED during resource allocation (may affect the ILT and
288 * the doorbell BAR).
289 */
290 u32 min_dpis; /* number of requested DPIs */
291 u32 num_qps; /* number of requested Queue Pairs */
292 u32 num_srqs; /* number of requested SRQ */
293 u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */
294 u8 gl_pi; /* protocol index */
295
296 /* Will allocate rate limiters to be used with QPs */
297 u8 enable_dcqcn;
298 };
299
300 struct qed_pf_params {
301 struct qed_eth_pf_params eth_pf_params;
302 struct qed_fcoe_pf_params fcoe_pf_params;
303 struct qed_iscsi_pf_params iscsi_pf_params;
304 struct qed_rdma_pf_params rdma_pf_params;
305 };
306
307 enum qed_int_mode {
308 QED_INT_MODE_INTA,
309 QED_INT_MODE_MSIX,
310 QED_INT_MODE_MSI,
311 QED_INT_MODE_POLL,
312 };
313
314 struct qed_sb_info {
315 struct status_block_e4 *sb_virt;
316 dma_addr_t sb_phys;
317 u32 sb_ack; /* Last given ack */
318 u16 igu_sb_id;
319 void __iomem *igu_addr;
320 u8 flags;
321 #define QED_SB_INFO_INIT 0x1
322 #define QED_SB_INFO_SETUP 0x2
323
324 struct qed_dev *cdev;
325 };
326
327 enum qed_dev_type {
328 QED_DEV_TYPE_BB,
329 QED_DEV_TYPE_AH,
330 };
331
332 struct qed_dev_info {
333 unsigned long pci_mem_start;
334 unsigned long pci_mem_end;
335 unsigned int pci_irq;
336 u8 num_hwfns;
337
338 u8 hw_mac[ETH_ALEN];
339 bool is_mf_default;
340
341 /* FW version */
342 u16 fw_major;
343 u16 fw_minor;
344 u16 fw_rev;
345 u16 fw_eng;
346
347 /* MFW version */
348 u32 mfw_rev;
349 #define QED_MFW_VERSION_0_MASK 0x000000FF
350 #define QED_MFW_VERSION_0_OFFSET 0
351 #define QED_MFW_VERSION_1_MASK 0x0000FF00
352 #define QED_MFW_VERSION_1_OFFSET 8
353 #define QED_MFW_VERSION_2_MASK 0x00FF0000
354 #define QED_MFW_VERSION_2_OFFSET 16
355 #define QED_MFW_VERSION_3_MASK 0xFF000000
356 #define QED_MFW_VERSION_3_OFFSET 24
357
358 u32 flash_size;
359 u8 mf_mode;
360 bool tx_switching;
361 bool rdma_supported;
362 u16 mtu;
363
364 bool wol_support;
365
366 /* MBI version */
367 u32 mbi_version;
368 #define QED_MBI_VERSION_0_MASK 0x000000FF
369 #define QED_MBI_VERSION_0_OFFSET 0
370 #define QED_MBI_VERSION_1_MASK 0x0000FF00
371 #define QED_MBI_VERSION_1_OFFSET 8
372 #define QED_MBI_VERSION_2_MASK 0x00FF0000
373 #define QED_MBI_VERSION_2_OFFSET 16
374
375 enum qed_dev_type dev_type;
376
377 /* Output parameters for qede */
378 bool vxlan_enable;
379 bool gre_enable;
380 bool geneve_enable;
381
382 u8 abs_pf_id;
383 };
384
385 enum qed_sb_type {
386 QED_SB_TYPE_L2_QUEUE,
387 QED_SB_TYPE_CNQ,
388 QED_SB_TYPE_STORAGE,
389 };
390
391 enum qed_protocol {
392 QED_PROTOCOL_ETH,
393 QED_PROTOCOL_ISCSI,
394 QED_PROTOCOL_FCOE,
395 };
396
397 enum qed_link_mode_bits {
398 QED_LM_FIBRE_BIT = BIT(0),
399 QED_LM_Autoneg_BIT = BIT(1),
400 QED_LM_Asym_Pause_BIT = BIT(2),
401 QED_LM_Pause_BIT = BIT(3),
402 QED_LM_1000baseT_Half_BIT = BIT(4),
403 QED_LM_1000baseT_Full_BIT = BIT(5),
404 QED_LM_10000baseKR_Full_BIT = BIT(6),
405 QED_LM_25000baseKR_Full_BIT = BIT(7),
406 QED_LM_40000baseLR4_Full_BIT = BIT(8),
407 QED_LM_50000baseKR2_Full_BIT = BIT(9),
408 QED_LM_100000baseKR4_Full_BIT = BIT(10),
409 QED_LM_COUNT = 11
410 };
411
412 struct qed_link_params {
413 bool link_up;
414
415 #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0)
416 #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1)
417 #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2)
418 #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3)
419 #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4)
420 #define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5)
421 u32 override_flags;
422 bool autoneg;
423 u32 adv_speeds;
424 u32 forced_speed;
425 #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0)
426 #define QED_LINK_PAUSE_RX_ENABLE BIT(1)
427 #define QED_LINK_PAUSE_TX_ENABLE BIT(2)
428 u32 pause_config;
429 #define QED_LINK_LOOPBACK_NONE BIT(0)
430 #define QED_LINK_LOOPBACK_INT_PHY BIT(1)
431 #define QED_LINK_LOOPBACK_EXT_PHY BIT(2)
432 #define QED_LINK_LOOPBACK_EXT BIT(3)
433 #define QED_LINK_LOOPBACK_MAC BIT(4)
434 u32 loopback_mode;
435 struct qed_link_eee_params eee;
436 };
437
438 struct qed_link_output {
439 bool link_up;
440
441 /* In QED_LM_* defs */
442 u32 supported_caps;
443 u32 advertised_caps;
444 u32 lp_caps;
445
446 u32 speed; /* In Mb/s */
447 u8 duplex; /* In DUPLEX defs */
448 u8 port; /* In PORT defs */
449 bool autoneg;
450 u32 pause_config;
451
452 /* EEE - capability & param */
453 bool eee_supported;
454 bool eee_active;
455 u8 sup_caps;
456 struct qed_link_eee_params eee;
457 };
458
459 struct qed_probe_params {
460 enum qed_protocol protocol;
461 u32 dp_module;
462 u8 dp_level;
463 bool is_vf;
464 };
465
466 #define QED_DRV_VER_STR_SIZE 12
467 struct qed_slowpath_params {
468 u32 int_mode;
469 u8 drv_major;
470 u8 drv_minor;
471 u8 drv_rev;
472 u8 drv_eng;
473 u8 name[QED_DRV_VER_STR_SIZE];
474 };
475
476 #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
477
478 struct qed_int_info {
479 struct msix_entry *msix;
480 u8 msix_cnt;
481
482 /* This should be updated by the protocol driver */
483 u8 used_cnt;
484 };
485
486 struct qed_common_cb_ops {
487 void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc);
488 void (*link_update)(void *dev,
489 struct qed_link_output *link);
490 void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type);
491 };
492
493 struct qed_selftest_ops {
494 /**
495 * @brief selftest_interrupt - Perform interrupt test
496 *
497 * @param cdev
498 *
499 * @return 0 on success, error otherwise.
500 */
501 int (*selftest_interrupt)(struct qed_dev *cdev);
502
503 /**
504 * @brief selftest_memory - Perform memory test
505 *
506 * @param cdev
507 *
508 * @return 0 on success, error otherwise.
509 */
510 int (*selftest_memory)(struct qed_dev *cdev);
511
512 /**
513 * @brief selftest_register - Perform register test
514 *
515 * @param cdev
516 *
517 * @return 0 on success, error otherwise.
518 */
519 int (*selftest_register)(struct qed_dev *cdev);
520
521 /**
522 * @brief selftest_clock - Perform clock test
523 *
524 * @param cdev
525 *
526 * @return 0 on success, error otherwise.
527 */
528 int (*selftest_clock)(struct qed_dev *cdev);
529
530 /**
531 * @brief selftest_nvram - Perform nvram test
532 *
533 * @param cdev
534 *
535 * @return 0 on success, error otherwise.
536 */
537 int (*selftest_nvram) (struct qed_dev *cdev);
538 };
539
540 struct qed_common_ops {
541 struct qed_selftest_ops *selftest;
542
543 struct qed_dev* (*probe)(struct pci_dev *dev,
544 struct qed_probe_params *params);
545
546 void (*remove)(struct qed_dev *cdev);
547
548 int (*set_power_state)(struct qed_dev *cdev,
549 pci_power_t state);
550
551 void (*set_name) (struct qed_dev *cdev, char name[]);
552
553 /* Client drivers need to make this call before slowpath_start.
554 * PF params required for the call before slowpath_start is
555 * documented within the qed_pf_params structure definition.
556 */
557 void (*update_pf_params)(struct qed_dev *cdev,
558 struct qed_pf_params *params);
559 int (*slowpath_start)(struct qed_dev *cdev,
560 struct qed_slowpath_params *params);
561
562 int (*slowpath_stop)(struct qed_dev *cdev);
563
564 /* Requests to use `cnt' interrupts for fastpath.
565 * upon success, returns number of interrupts allocated for fastpath.
566 */
567 int (*set_fp_int)(struct qed_dev *cdev,
568 u16 cnt);
569
570 /* Fills `info' with pointers required for utilizing interrupts */
571 int (*get_fp_int)(struct qed_dev *cdev,
572 struct qed_int_info *info);
573
574 u32 (*sb_init)(struct qed_dev *cdev,
575 struct qed_sb_info *sb_info,
576 void *sb_virt_addr,
577 dma_addr_t sb_phy_addr,
578 u16 sb_id,
579 enum qed_sb_type type);
580
581 u32 (*sb_release)(struct qed_dev *cdev,
582 struct qed_sb_info *sb_info,
583 u16 sb_id);
584
585 void (*simd_handler_config)(struct qed_dev *cdev,
586 void *token,
587 int index,
588 void (*handler)(void *));
589
590 void (*simd_handler_clean)(struct qed_dev *cdev,
591 int index);
592 int (*dbg_grc)(struct qed_dev *cdev,
593 void *buffer, u32 *num_dumped_bytes);
594
595 int (*dbg_grc_size)(struct qed_dev *cdev);
596
597 int (*dbg_all_data) (struct qed_dev *cdev, void *buffer);
598
599 int (*dbg_all_data_size) (struct qed_dev *cdev);
600
601 /**
602 * @brief can_link_change - can the instance change the link or not
603 *
604 * @param cdev
605 *
606 * @return true if link-change is allowed, false otherwise.
607 */
608 bool (*can_link_change)(struct qed_dev *cdev);
609
610 /**
611 * @brief set_link - set links according to params
612 *
613 * @param cdev
614 * @param params - values used to override the default link configuration
615 *
616 * @return 0 on success, error otherwise.
617 */
618 int (*set_link)(struct qed_dev *cdev,
619 struct qed_link_params *params);
620
621 /**
622 * @brief get_link - returns the current link state.
623 *
624 * @param cdev
625 * @param if_link - structure to be filled with current link configuration.
626 */
627 void (*get_link)(struct qed_dev *cdev,
628 struct qed_link_output *if_link);
629
630 /**
631 * @brief - drains chip in case Tx completions fail to arrive due to pause.
632 *
633 * @param cdev
634 */
635 int (*drain)(struct qed_dev *cdev);
636
637 /**
638 * @brief update_msglvl - update module debug level
639 *
640 * @param cdev
641 * @param dp_module
642 * @param dp_level
643 */
644 void (*update_msglvl)(struct qed_dev *cdev,
645 u32 dp_module,
646 u8 dp_level);
647
648 int (*chain_alloc)(struct qed_dev *cdev,
649 enum qed_chain_use_mode intended_use,
650 enum qed_chain_mode mode,
651 enum qed_chain_cnt_type cnt_type,
652 u32 num_elems,
653 size_t elem_size,
654 struct qed_chain *p_chain,
655 struct qed_chain_ext_pbl *ext_pbl);
656
657 void (*chain_free)(struct qed_dev *cdev,
658 struct qed_chain *p_chain);
659
660 /**
661 * @brief nvm_get_image - reads an entire image from nvram
662 *
663 * @param cdev
664 * @param type - type of the request nvram image
665 * @param buf - preallocated buffer to fill with the image
666 * @param len - length of the allocated buffer
667 *
668 * @return 0 on success, error otherwise
669 */
670 int (*nvm_get_image)(struct qed_dev *cdev,
671 enum qed_nvm_images type, u8 *buf, u16 len);
672
673 /**
674 * @brief set_coalesce - Configure Rx coalesce value in usec
675 *
676 * @param cdev
677 * @param rx_coal - Rx coalesce value in usec
678 * @param tx_coal - Tx coalesce value in usec
679 * @param qid - Queue index
680 * @param sb_id - Status Block Id
681 *
682 * @return 0 on success, error otherwise.
683 */
684 int (*set_coalesce)(struct qed_dev *cdev,
685 u16 rx_coal, u16 tx_coal, void *handle);
686
687 /**
688 * @brief set_led - Configure LED mode
689 *
690 * @param cdev
691 * @param mode - LED mode
692 *
693 * @return 0 on success, error otherwise.
694 */
695 int (*set_led)(struct qed_dev *cdev,
696 enum qed_led_mode mode);
697
698 /**
699 * @brief update_drv_state - API to inform the change in the driver state.
700 *
701 * @param cdev
702 * @param active
703 *
704 */
705 int (*update_drv_state)(struct qed_dev *cdev, bool active);
706
707 /**
708 * @brief update_mac - API to inform the change in the mac address
709 *
710 * @param cdev
711 * @param mac
712 *
713 */
714 int (*update_mac)(struct qed_dev *cdev, u8 *mac);
715
716 /**
717 * @brief update_mtu - API to inform the change in the mtu
718 *
719 * @param cdev
720 * @param mtu
721 *
722 */
723 int (*update_mtu)(struct qed_dev *cdev, u16 mtu);
724
725 /**
726 * @brief update_wol - update of changes in the WoL configuration
727 *
728 * @param cdev
729 * @param enabled - true iff WoL should be enabled.
730 */
731 int (*update_wol) (struct qed_dev *cdev, bool enabled);
732 };
733
734 #define MASK_FIELD(_name, _value) \
735 ((_value) &= (_name ## _MASK))
736
737 #define FIELD_VALUE(_name, _value) \
738 ((_value & _name ## _MASK) << _name ## _SHIFT)
739
740 #define SET_FIELD(value, name, flag) \
741 do { \
742 (value) &= ~(name ## _MASK << name ## _SHIFT); \
743 (value) |= (((u64)flag) << (name ## _SHIFT)); \
744 } while (0)
745
746 #define GET_FIELD(value, name) \
747 (((value) >> (name ## _SHIFT)) & name ## _MASK)
748
749 /* Debug print definitions */
750 #define DP_ERR(cdev, fmt, ...) \
751 do { \
752 pr_err("[%s:%d(%s)]" fmt, \
753 __func__, __LINE__, \
754 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
755 ## __VA_ARGS__); \
756 } while (0)
757
758 #define DP_NOTICE(cdev, fmt, ...) \
759 do { \
760 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
761 pr_notice("[%s:%d(%s)]" fmt, \
762 __func__, __LINE__, \
763 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
764 ## __VA_ARGS__); \
765 \
766 } \
767 } while (0)
768
769 #define DP_INFO(cdev, fmt, ...) \
770 do { \
771 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \
772 pr_notice("[%s:%d(%s)]" fmt, \
773 __func__, __LINE__, \
774 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
775 ## __VA_ARGS__); \
776 } \
777 } while (0)
778
779 #define DP_VERBOSE(cdev, module, fmt, ...) \
780 do { \
781 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \
782 ((cdev)->dp_module & module))) { \
783 pr_notice("[%s:%d(%s)]" fmt, \
784 __func__, __LINE__, \
785 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
786 ## __VA_ARGS__); \
787 } \
788 } while (0)
789
790 enum DP_LEVEL {
791 QED_LEVEL_VERBOSE = 0x0,
792 QED_LEVEL_INFO = 0x1,
793 QED_LEVEL_NOTICE = 0x2,
794 QED_LEVEL_ERR = 0x3,
795 };
796
797 #define QED_LOG_LEVEL_SHIFT (30)
798 #define QED_LOG_VERBOSE_MASK (0x3fffffff)
799 #define QED_LOG_INFO_MASK (0x40000000)
800 #define QED_LOG_NOTICE_MASK (0x80000000)
801
802 enum DP_MODULE {
803 QED_MSG_SPQ = 0x10000,
804 QED_MSG_STATS = 0x20000,
805 QED_MSG_DCB = 0x40000,
806 QED_MSG_IOV = 0x80000,
807 QED_MSG_SP = 0x100000,
808 QED_MSG_STORAGE = 0x200000,
809 QED_MSG_CXT = 0x800000,
810 QED_MSG_LL2 = 0x1000000,
811 QED_MSG_ILT = 0x2000000,
812 QED_MSG_RDMA = 0x4000000,
813 QED_MSG_DEBUG = 0x8000000,
814 /* to be added...up to 0x8000000 */
815 };
816
817 enum qed_mf_mode {
818 QED_MF_DEFAULT,
819 QED_MF_OVLAN,
820 QED_MF_NPAR,
821 };
822
823 struct qed_eth_stats_common {
824 u64 no_buff_discards;
825 u64 packet_too_big_discard;
826 u64 ttl0_discard;
827 u64 rx_ucast_bytes;
828 u64 rx_mcast_bytes;
829 u64 rx_bcast_bytes;
830 u64 rx_ucast_pkts;
831 u64 rx_mcast_pkts;
832 u64 rx_bcast_pkts;
833 u64 mftag_filter_discards;
834 u64 mac_filter_discards;
835 u64 tx_ucast_bytes;
836 u64 tx_mcast_bytes;
837 u64 tx_bcast_bytes;
838 u64 tx_ucast_pkts;
839 u64 tx_mcast_pkts;
840 u64 tx_bcast_pkts;
841 u64 tx_err_drop_pkts;
842 u64 tpa_coalesced_pkts;
843 u64 tpa_coalesced_events;
844 u64 tpa_aborts_num;
845 u64 tpa_not_coalesced_pkts;
846 u64 tpa_coalesced_bytes;
847
848 /* port */
849 u64 rx_64_byte_packets;
850 u64 rx_65_to_127_byte_packets;
851 u64 rx_128_to_255_byte_packets;
852 u64 rx_256_to_511_byte_packets;
853 u64 rx_512_to_1023_byte_packets;
854 u64 rx_1024_to_1518_byte_packets;
855 u64 rx_crc_errors;
856 u64 rx_mac_crtl_frames;
857 u64 rx_pause_frames;
858 u64 rx_pfc_frames;
859 u64 rx_align_errors;
860 u64 rx_carrier_errors;
861 u64 rx_oversize_packets;
862 u64 rx_jabbers;
863 u64 rx_undersize_packets;
864 u64 rx_fragments;
865 u64 tx_64_byte_packets;
866 u64 tx_65_to_127_byte_packets;
867 u64 tx_128_to_255_byte_packets;
868 u64 tx_256_to_511_byte_packets;
869 u64 tx_512_to_1023_byte_packets;
870 u64 tx_1024_to_1518_byte_packets;
871 u64 tx_pause_frames;
872 u64 tx_pfc_frames;
873 u64 brb_truncates;
874 u64 brb_discards;
875 u64 rx_mac_bytes;
876 u64 rx_mac_uc_packets;
877 u64 rx_mac_mc_packets;
878 u64 rx_mac_bc_packets;
879 u64 rx_mac_frames_ok;
880 u64 tx_mac_bytes;
881 u64 tx_mac_uc_packets;
882 u64 tx_mac_mc_packets;
883 u64 tx_mac_bc_packets;
884 u64 tx_mac_ctrl_frames;
885 };
886
887 struct qed_eth_stats_bb {
888 u64 rx_1519_to_1522_byte_packets;
889 u64 rx_1519_to_2047_byte_packets;
890 u64 rx_2048_to_4095_byte_packets;
891 u64 rx_4096_to_9216_byte_packets;
892 u64 rx_9217_to_16383_byte_packets;
893 u64 tx_1519_to_2047_byte_packets;
894 u64 tx_2048_to_4095_byte_packets;
895 u64 tx_4096_to_9216_byte_packets;
896 u64 tx_9217_to_16383_byte_packets;
897 u64 tx_lpi_entry_count;
898 u64 tx_total_collisions;
899 };
900
901 struct qed_eth_stats_ah {
902 u64 rx_1519_to_max_byte_packets;
903 u64 tx_1519_to_max_byte_packets;
904 };
905
906 struct qed_eth_stats {
907 struct qed_eth_stats_common common;
908
909 union {
910 struct qed_eth_stats_bb bb;
911 struct qed_eth_stats_ah ah;
912 };
913 };
914
915 #define QED_SB_IDX 0x0002
916
917 #define RX_PI 0
918 #define TX_PI(tc) (RX_PI + 1 + tc)
919
920 struct qed_sb_cnt_info {
921 /* Original, current, and free SBs for PF */
922 int orig;
923 int cnt;
924 int free_cnt;
925
926 /* Original, current and free SBS for child VFs */
927 int iov_orig;
928 int iov_cnt;
929 int free_cnt_iov;
930 };
931
932 static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
933 {
934 u32 prod = 0;
935 u16 rc = 0;
936
937 prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
938 STATUS_BLOCK_E4_PROD_INDEX_MASK;
939 if (sb_info->sb_ack != prod) {
940 sb_info->sb_ack = prod;
941 rc |= QED_SB_IDX;
942 }
943
944 /* Let SB update */
945 mmiowb();
946 return rc;
947 }
948
949 /**
950 *
951 * @brief This function creates an update command for interrupts that is
952 * written to the IGU.
953 *
954 * @param sb_info - This is the structure allocated and
955 * initialized per status block. Assumption is
956 * that it was initialized using qed_sb_init
957 * @param int_cmd - Enable/Disable/Nop
958 * @param upd_flg - whether igu consumer should be
959 * updated.
960 *
961 * @return inline void
962 */
963 static inline void qed_sb_ack(struct qed_sb_info *sb_info,
964 enum igu_int_cmd int_cmd,
965 u8 upd_flg)
966 {
967 struct igu_prod_cons_update igu_ack = { 0 };
968
969 igu_ack.sb_id_and_flags =
970 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
971 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
972 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
973 (IGU_SEG_ACCESS_REG <<
974 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
975
976 DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags);
977
978 /* Both segments (interrupts & acks) are written to same place address;
979 * Need to guarantee all commands will be received (in-order) by HW.
980 */
981 mmiowb();
982 barrier();
983 }
984
985 static inline void __internal_ram_wr(void *p_hwfn,
986 void __iomem *addr,
987 int size,
988 u32 *data)
989
990 {
991 unsigned int i;
992
993 for (i = 0; i < size / sizeof(*data); i++)
994 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
995 }
996
997 static inline void internal_ram_wr(void __iomem *addr,
998 int size,
999 u32 *data)
1000 {
1001 __internal_ram_wr(NULL, addr, size, data);
1002 }
1003
1004 enum qed_rss_caps {
1005 QED_RSS_IPV4 = 0x1,
1006 QED_RSS_IPV6 = 0x2,
1007 QED_RSS_IPV4_TCP = 0x4,
1008 QED_RSS_IPV6_TCP = 0x8,
1009 QED_RSS_IPV4_UDP = 0x10,
1010 QED_RSS_IPV6_UDP = 0x20,
1011 };
1012
1013 #define QED_RSS_IND_TABLE_SIZE 128
1014 #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */
1015 #endif
CRIS linux kernel tree