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Merge tag 'xtensa-20180225' of git://github.com/jcmvbkbc/linux-xtensa
[cris-mirror.git] / include / uapi / linux / perf_event.h
blobe0739a1aa4b25569c679fd81d60b4aa9ce1aa5a5
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /*
3 * Performance events:
4 *
5 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de>
6 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar
7 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra
8 *
9 * Data type definitions, declarations, prototypes.
10 *
11 * Started by: Thomas Gleixner and Ingo Molnar
12 *
13 * For licencing details see kernel-base/COPYING
14 */
15 #ifndef _UAPI_LINUX_PERF_EVENT_H
16 #define _UAPI_LINUX_PERF_EVENT_H
17
18 #include <linux/types.h>
19 #include <linux/ioctl.h>
20 #include <asm/byteorder.h>
21
22 /*
23 * User-space ABI bits:
24 */
25
26 /*
27 * attr.type
28 */
29 enum perf_type_id {
30 PERF_TYPE_HARDWARE = 0,
31 PERF_TYPE_SOFTWARE = 1,
32 PERF_TYPE_TRACEPOINT = 2,
33 PERF_TYPE_HW_CACHE = 3,
34 PERF_TYPE_RAW = 4,
35 PERF_TYPE_BREAKPOINT = 5,
36
37 PERF_TYPE_MAX, /* non-ABI */
38 };
39
40 /*
41 * Generalized performance event event_id types, used by the
42 * attr.event_id parameter of the sys_perf_event_open()
43 * syscall:
44 */
45 enum perf_hw_id {
46 /*
47 * Common hardware events, generalized by the kernel:
48 */
49 PERF_COUNT_HW_CPU_CYCLES = 0,
50 PERF_COUNT_HW_INSTRUCTIONS = 1,
51 PERF_COUNT_HW_CACHE_REFERENCES = 2,
52 PERF_COUNT_HW_CACHE_MISSES = 3,
53 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,
54 PERF_COUNT_HW_BRANCH_MISSES = 5,
55 PERF_COUNT_HW_BUS_CYCLES = 6,
56 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7,
57 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8,
58 PERF_COUNT_HW_REF_CPU_CYCLES = 9,
59
60 PERF_COUNT_HW_MAX, /* non-ABI */
61 };
62
63 /*
64 * Generalized hardware cache events:
65 *
66 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
67 * { read, write, prefetch } x
68 * { accesses, misses }
69 */
70 enum perf_hw_cache_id {
71 PERF_COUNT_HW_CACHE_L1D = 0,
72 PERF_COUNT_HW_CACHE_L1I = 1,
73 PERF_COUNT_HW_CACHE_LL = 2,
74 PERF_COUNT_HW_CACHE_DTLB = 3,
75 PERF_COUNT_HW_CACHE_ITLB = 4,
76 PERF_COUNT_HW_CACHE_BPU = 5,
77 PERF_COUNT_HW_CACHE_NODE = 6,
78
79 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */
80 };
81
82 enum perf_hw_cache_op_id {
83 PERF_COUNT_HW_CACHE_OP_READ = 0,
84 PERF_COUNT_HW_CACHE_OP_WRITE = 1,
85 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2,
86
87 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */
88 };
89
90 enum perf_hw_cache_op_result_id {
91 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,
92 PERF_COUNT_HW_CACHE_RESULT_MISS = 1,
93
94 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */
95 };
96
97 /*
98 * Special "software" events provided by the kernel, even if the hardware
99 * does not support performance events. These events measure various
100 * physical and sw events of the kernel (and allow the profiling of them as
101 * well):
102 */
103 enum perf_sw_ids {
104 PERF_COUNT_SW_CPU_CLOCK = 0,
105 PERF_COUNT_SW_TASK_CLOCK = 1,
106 PERF_COUNT_SW_PAGE_FAULTS = 2,
107 PERF_COUNT_SW_CONTEXT_SWITCHES = 3,
108 PERF_COUNT_SW_CPU_MIGRATIONS = 4,
109 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5,
110 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,
111 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7,
112 PERF_COUNT_SW_EMULATION_FAULTS = 8,
113 PERF_COUNT_SW_DUMMY = 9,
114 PERF_COUNT_SW_BPF_OUTPUT = 10,
115
116 PERF_COUNT_SW_MAX, /* non-ABI */
117 };
118
119 /*
120 * Bits that can be set in attr.sample_type to request information
121 * in the overflow packets.
122 */
123 enum perf_event_sample_format {
124 PERF_SAMPLE_IP = 1U << 0,
125 PERF_SAMPLE_TID = 1U << 1,
126 PERF_SAMPLE_TIME = 1U << 2,
127 PERF_SAMPLE_ADDR = 1U << 3,
128 PERF_SAMPLE_READ = 1U << 4,
129 PERF_SAMPLE_CALLCHAIN = 1U << 5,
130 PERF_SAMPLE_ID = 1U << 6,
131 PERF_SAMPLE_CPU = 1U << 7,
132 PERF_SAMPLE_PERIOD = 1U << 8,
133 PERF_SAMPLE_STREAM_ID = 1U << 9,
134 PERF_SAMPLE_RAW = 1U << 10,
135 PERF_SAMPLE_BRANCH_STACK = 1U << 11,
136 PERF_SAMPLE_REGS_USER = 1U << 12,
137 PERF_SAMPLE_STACK_USER = 1U << 13,
138 PERF_SAMPLE_WEIGHT = 1U << 14,
139 PERF_SAMPLE_DATA_SRC = 1U << 15,
140 PERF_SAMPLE_IDENTIFIER = 1U << 16,
141 PERF_SAMPLE_TRANSACTION = 1U << 17,
142 PERF_SAMPLE_REGS_INTR = 1U << 18,
143 PERF_SAMPLE_PHYS_ADDR = 1U << 19,
144
145 PERF_SAMPLE_MAX = 1U << 20, /* non-ABI */
146 };
147
148 /*
149 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set
150 *
151 * If the user does not pass priv level information via branch_sample_type,
152 * the kernel uses the event's priv level. Branch and event priv levels do
153 * not have to match. Branch priv level is checked for permissions.
154 *
155 * The branch types can be combined, however BRANCH_ANY covers all types
156 * of branches and therefore it supersedes all the other types.
157 */
158 enum perf_branch_sample_type_shift {
159 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */
160 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */
161 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */
162
163 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */
164 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */
165 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */
166 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */
167 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */
168 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */
169 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */
170 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */
171
172 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */
173 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */
174 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */
175
176 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */
177 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */
178
179 PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */
180
181 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */
182 };
183
184 enum perf_branch_sample_type {
185 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT,
186 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT,
187 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT,
188
189 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT,
190 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT,
191 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT,
192 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT,
193 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT,
194 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT,
195 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT,
196 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT,
197
198 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT,
199 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT,
200 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT,
201
202 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT,
203 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT,
204
205 PERF_SAMPLE_BRANCH_TYPE_SAVE =
206 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT,
207
208 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT,
209 };
210
211 /*
212 * Common flow change classification
213 */
214 enum {
215 PERF_BR_UNKNOWN = 0, /* unknown */
216 PERF_BR_COND = 1, /* conditional */
217 PERF_BR_UNCOND = 2, /* unconditional */
218 PERF_BR_IND = 3, /* indirect */
219 PERF_BR_CALL = 4, /* function call */
220 PERF_BR_IND_CALL = 5, /* indirect function call */
221 PERF_BR_RET = 6, /* function return */
222 PERF_BR_SYSCALL = 7, /* syscall */
223 PERF_BR_SYSRET = 8, /* syscall return */
224 PERF_BR_COND_CALL = 9, /* conditional function call */
225 PERF_BR_COND_RET = 10, /* conditional function return */
226 PERF_BR_MAX,
227 };
228
229 #define PERF_SAMPLE_BRANCH_PLM_ALL \
230 (PERF_SAMPLE_BRANCH_USER|\
231 PERF_SAMPLE_BRANCH_KERNEL|\
232 PERF_SAMPLE_BRANCH_HV)
233
234 /*
235 * Values to determine ABI of the registers dump.
236 */
237 enum perf_sample_regs_abi {
238 PERF_SAMPLE_REGS_ABI_NONE = 0,
239 PERF_SAMPLE_REGS_ABI_32 = 1,
240 PERF_SAMPLE_REGS_ABI_64 = 2,
241 };
242
243 /*
244 * Values for the memory transaction event qualifier, mostly for
245 * abort events. Multiple bits can be set.
246 */
247 enum {
248 PERF_TXN_ELISION = (1 << 0), /* From elision */
249 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */
250 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */
251 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */
252 PERF_TXN_RETRY = (1 << 4), /* Retry possible */
253 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */
254 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */
255 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */
256
257 PERF_TXN_MAX = (1 << 8), /* non-ABI */
258
259 /* bits 32..63 are reserved for the abort code */
260
261 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32),
262 PERF_TXN_ABORT_SHIFT = 32,
263 };
264
265 /*
266 * The format of the data returned by read() on a perf event fd,
267 * as specified by attr.read_format:
268 *
269 * struct read_format {
270 * { u64 value;
271 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
272 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
273 * { u64 id; } && PERF_FORMAT_ID
274 * } && !PERF_FORMAT_GROUP
275 *
276 * { u64 nr;
277 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
278 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
279 * { u64 value;
280 * { u64 id; } && PERF_FORMAT_ID
281 * } cntr[nr];
282 * } && PERF_FORMAT_GROUP
283 * };
284 */
285 enum perf_event_read_format {
286 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0,
287 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1,
288 PERF_FORMAT_ID = 1U << 2,
289 PERF_FORMAT_GROUP = 1U << 3,
290
291 PERF_FORMAT_MAX = 1U << 4, /* non-ABI */
292 };
293
294 #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */
295 #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */
296 #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */
297 #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */
298 /* add: sample_stack_user */
299 #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */
300 #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */
301
302 /*
303 * Hardware event_id to monitor via a performance monitoring event:
304 *
305 * @sample_max_stack: Max number of frame pointers in a callchain,
306 * should be < /proc/sys/kernel/perf_event_max_stack
307 */
308 struct perf_event_attr {
309
310 /*
311 * Major type: hardware/software/tracepoint/etc.
312 */
313 __u32 type;
314
315 /*
316 * Size of the attr structure, for fwd/bwd compat.
317 */
318 __u32 size;
319
320 /*
321 * Type specific configuration information.
322 */
323 __u64 config;
324
325 union {
326 __u64 sample_period;
327 __u64 sample_freq;
328 };
329
330 __u64 sample_type;
331 __u64 read_format;
332
333 __u64 disabled : 1, /* off by default */
334 inherit : 1, /* children inherit it */
335 pinned : 1, /* must always be on PMU */
336 exclusive : 1, /* only group on PMU */
337 exclude_user : 1, /* don't count user */
338 exclude_kernel : 1, /* ditto kernel */
339 exclude_hv : 1, /* ditto hypervisor */
340 exclude_idle : 1, /* don't count when idle */
341 mmap : 1, /* include mmap data */
342 comm : 1, /* include comm data */
343 freq : 1, /* use freq, not period */
344 inherit_stat : 1, /* per task counts */
345 enable_on_exec : 1, /* next exec enables */
346 task : 1, /* trace fork/exit */
347 watermark : 1, /* wakeup_watermark */
348 /*
349 * precise_ip:
350 *
351 * 0 - SAMPLE_IP can have arbitrary skid
352 * 1 - SAMPLE_IP must have constant skid
353 * 2 - SAMPLE_IP requested to have 0 skid
354 * 3 - SAMPLE_IP must have 0 skid
355 *
356 * See also PERF_RECORD_MISC_EXACT_IP
357 */
358 precise_ip : 2, /* skid constraint */
359 mmap_data : 1, /* non-exec mmap data */
360 sample_id_all : 1, /* sample_type all events */
361
362 exclude_host : 1, /* don't count in host */
363 exclude_guest : 1, /* don't count in guest */
364
365 exclude_callchain_kernel : 1, /* exclude kernel callchains */
366 exclude_callchain_user : 1, /* exclude user callchains */
367 mmap2 : 1, /* include mmap with inode data */
368 comm_exec : 1, /* flag comm events that are due to an exec */
369 use_clockid : 1, /* use @clockid for time fields */
370 context_switch : 1, /* context switch data */
371 write_backward : 1, /* Write ring buffer from end to beginning */
372 namespaces : 1, /* include namespaces data */
373 __reserved_1 : 35;
374
375 union {
376 __u32 wakeup_events; /* wakeup every n events */
377 __u32 wakeup_watermark; /* bytes before wakeup */
378 };
379
380 __u32 bp_type;
381 union {
382 __u64 bp_addr;
383 __u64 config1; /* extension of config */
384 };
385 union {
386 __u64 bp_len;
387 __u64 config2; /* extension of config1 */
388 };
389 __u64 branch_sample_type; /* enum perf_branch_sample_type */
390
391 /*
392 * Defines set of user regs to dump on samples.
393 * See asm/perf_regs.h for details.
394 */
395 __u64 sample_regs_user;
396
397 /*
398 * Defines size of the user stack to dump on samples.
399 */
400 __u32 sample_stack_user;
401
402 __s32 clockid;
403 /*
404 * Defines set of regs to dump for each sample
405 * state captured on:
406 * - precise = 0: PMU interrupt
407 * - precise > 0: sampled instruction
408 *
409 * See asm/perf_regs.h for details.
410 */
411 __u64 sample_regs_intr;
412
413 /*
414 * Wakeup watermark for AUX area
415 */
416 __u32 aux_watermark;
417 __u16 sample_max_stack;
418 __u16 __reserved_2; /* align to __u64 */
419 };
420
421 /*
422 * Structure used by below PERF_EVENT_IOC_QUERY_BPF command
423 * to query bpf programs attached to the same perf tracepoint
424 * as the given perf event.
425 */
426 struct perf_event_query_bpf {
427 /*
428 * The below ids array length
429 */
430 __u32 ids_len;
431 /*
432 * Set by the kernel to indicate the number of
433 * available programs
434 */
435 __u32 prog_cnt;
436 /*
437 * User provided buffer to store program ids
438 */
439 __u32 ids[0];
440 };
441
442 #define perf_flags(attr) (*(&(attr)->read_format + 1))
443
444 /*
445 * Ioctls that can be done on a perf event fd:
446 */
447 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0)
448 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1)
449 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2)
450 #define PERF_EVENT_IOC_RESET _IO ('$', 3)
451 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64)
452 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5)
453 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *)
454 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *)
455 #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32)
456 #define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32)
457 #define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *)
458
459 enum perf_event_ioc_flags {
460 PERF_IOC_FLAG_GROUP = 1U << 0,
461 };
462
463 /*
464 * Structure of the page that can be mapped via mmap
465 */
466 struct perf_event_mmap_page {
467 __u32 version; /* version number of this structure */
468 __u32 compat_version; /* lowest version this is compat with */
469
470 /*
471 * Bits needed to read the hw events in user-space.
472 *
473 * u32 seq, time_mult, time_shift, index, width;
474 * u64 count, enabled, running;
475 * u64 cyc, time_offset;
476 * s64 pmc = 0;
477 *
478 * do {
479 * seq = pc->lock;
480 * barrier()
481 *
482 * enabled = pc->time_enabled;
483 * running = pc->time_running;
484 *
485 * if (pc->cap_usr_time && enabled != running) {
486 * cyc = rdtsc();
487 * time_offset = pc->time_offset;
488 * time_mult = pc->time_mult;
489 * time_shift = pc->time_shift;
490 * }
491 *
492 * index = pc->index;
493 * count = pc->offset;
494 * if (pc->cap_user_rdpmc && index) {
495 * width = pc->pmc_width;
496 * pmc = rdpmc(index - 1);
497 * }
498 *
499 * barrier();
500 * } while (pc->lock != seq);
501 *
502 * NOTE: for obvious reason this only works on self-monitoring
503 * processes.
504 */
505 __u32 lock; /* seqlock for synchronization */
506 __u32 index; /* hardware event identifier */
507 __s64 offset; /* add to hardware event value */
508 __u64 time_enabled; /* time event active */
509 __u64 time_running; /* time event on cpu */
510 union {
511 __u64 capabilities;
512 struct {
513 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */
514 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */
515
516 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */
517 cap_user_time : 1, /* The time_* fields are used */
518 cap_user_time_zero : 1, /* The time_zero field is used */
519 cap_____res : 59;
520 };
521 };
522
523 /*
524 * If cap_user_rdpmc this field provides the bit-width of the value
525 * read using the rdpmc() or equivalent instruction. This can be used
526 * to sign extend the result like:
527 *
528 * pmc <<= 64 - width;
529 * pmc >>= 64 - width; // signed shift right
530 * count += pmc;
531 */
532 __u16 pmc_width;
533
534 /*
535 * If cap_usr_time the below fields can be used to compute the time
536 * delta since time_enabled (in ns) using rdtsc or similar.
537 *
538 * u64 quot, rem;
539 * u64 delta;
540 *
541 * quot = (cyc >> time_shift);
542 * rem = cyc & (((u64)1 << time_shift) - 1);
543 * delta = time_offset + quot * time_mult +
544 * ((rem * time_mult) >> time_shift);
545 *
546 * Where time_offset,time_mult,time_shift and cyc are read in the
547 * seqcount loop described above. This delta can then be added to
548 * enabled and possible running (if index), improving the scaling:
549 *
550 * enabled += delta;
551 * if (index)
552 * running += delta;
553 *
554 * quot = count / running;
555 * rem = count % running;
556 * count = quot * enabled + (rem * enabled) / running;
557 */
558 __u16 time_shift;
559 __u32 time_mult;
560 __u64 time_offset;
561 /*
562 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated
563 * from sample timestamps.
564 *
565 * time = timestamp - time_zero;
566 * quot = time / time_mult;
567 * rem = time % time_mult;
568 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult;
569 *
570 * And vice versa:
571 *
572 * quot = cyc >> time_shift;
573 * rem = cyc & (((u64)1 << time_shift) - 1);
574 * timestamp = time_zero + quot * time_mult +
575 * ((rem * time_mult) >> time_shift);
576 */
577 __u64 time_zero;
578 __u32 size; /* Header size up to __reserved[] fields. */
579
580 /*
581 * Hole for extension of the self monitor capabilities
582 */
583
584 __u8 __reserved[118*8+4]; /* align to 1k. */
585
586 /*
587 * Control data for the mmap() data buffer.
588 *
589 * User-space reading the @data_head value should issue an smp_rmb(),
590 * after reading this value.
591 *
592 * When the mapping is PROT_WRITE the @data_tail value should be
593 * written by userspace to reflect the last read data, after issueing
594 * an smp_mb() to separate the data read from the ->data_tail store.
595 * In this case the kernel will not over-write unread data.
596 *
597 * See perf_output_put_handle() for the data ordering.
598 *
599 * data_{offset,size} indicate the location and size of the perf record
600 * buffer within the mmapped area.
601 */
602 __u64 data_head; /* head in the data section */
603 __u64 data_tail; /* user-space written tail */
604 __u64 data_offset; /* where the buffer starts */
605 __u64 data_size; /* data buffer size */
606
607 /*
608 * AUX area is defined by aux_{offset,size} fields that should be set
609 * by the userspace, so that
610 *
611 * aux_offset >= data_offset + data_size
612 *
613 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size.
614 *
615 * Ring buffer pointers aux_{head,tail} have the same semantics as
616 * data_{head,tail} and same ordering rules apply.
617 */
618 __u64 aux_head;
619 __u64 aux_tail;
620 __u64 aux_offset;
621 __u64 aux_size;
622 };
623
624 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0)
625 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0)
626 #define PERF_RECORD_MISC_KERNEL (1 << 0)
627 #define PERF_RECORD_MISC_USER (2 << 0)
628 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0)
629 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0)
630 #define PERF_RECORD_MISC_GUEST_USER (5 << 0)
631
632 /*
633 * Indicates that /proc/PID/maps parsing are truncated by time out.
634 */
635 #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12)
636 /*
637 * Following PERF_RECORD_MISC_* are used on different
638 * events, so can reuse the same bit position:
639 *
640 * PERF_RECORD_MISC_MMAP_DATA - PERF_RECORD_MMAP* events
641 * PERF_RECORD_MISC_COMM_EXEC - PERF_RECORD_COMM event
642 * PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events
643 */
644 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13)
645 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13)
646 #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13)
647 /*
648 * Indicates that the content of PERF_SAMPLE_IP points to
649 * the actual instruction that triggered the event. See also
650 * perf_event_attr::precise_ip.
651 */
652 #define PERF_RECORD_MISC_EXACT_IP (1 << 14)
653 /*
654 * Reserve the last bit to indicate some extended misc field
655 */
656 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15)
657
658 struct perf_event_header {
659 __u32 type;
660 __u16 misc;
661 __u16 size;
662 };
663
664 struct perf_ns_link_info {
665 __u64 dev;
666 __u64 ino;
667 };
668
669 enum {
670 NET_NS_INDEX = 0,
671 UTS_NS_INDEX = 1,
672 IPC_NS_INDEX = 2,
673 PID_NS_INDEX = 3,
674 USER_NS_INDEX = 4,
675 MNT_NS_INDEX = 5,
676 CGROUP_NS_INDEX = 6,
677
678 NR_NAMESPACES, /* number of available namespaces */
679 };
680
681 enum perf_event_type {
682
683 /*
684 * If perf_event_attr.sample_id_all is set then all event types will
685 * have the sample_type selected fields related to where/when
686 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU,
687 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed
688 * just after the perf_event_header and the fields already present for
689 * the existing fields, i.e. at the end of the payload. That way a newer
690 * perf.data file will be supported by older perf tools, with these new
691 * optional fields being ignored.
692 *
693 * struct sample_id {
694 * { u32 pid, tid; } && PERF_SAMPLE_TID
695 * { u64 time; } && PERF_SAMPLE_TIME
696 * { u64 id; } && PERF_SAMPLE_ID
697 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
698 * { u32 cpu, res; } && PERF_SAMPLE_CPU
699 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
700 * } && perf_event_attr::sample_id_all
701 *
702 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The
703 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed
704 * relative to header.size.
705 */
706
707 /*
708 * The MMAP events record the PROT_EXEC mappings so that we can
709 * correlate userspace IPs to code. They have the following structure:
710 *
711 * struct {
712 * struct perf_event_header header;
713 *
714 * u32 pid, tid;
715 * u64 addr;
716 * u64 len;
717 * u64 pgoff;
718 * char filename[];
719 * struct sample_id sample_id;
720 * };
721 */
722 PERF_RECORD_MMAP = 1,
723
724 /*
725 * struct {
726 * struct perf_event_header header;
727 * u64 id;
728 * u64 lost;
729 * struct sample_id sample_id;
730 * };
731 */
732 PERF_RECORD_LOST = 2,
733
734 /*
735 * struct {
736 * struct perf_event_header header;
737 *
738 * u32 pid, tid;
739 * char comm[];
740 * struct sample_id sample_id;
741 * };
742 */
743 PERF_RECORD_COMM = 3,
744
745 /*
746 * struct {
747 * struct perf_event_header header;
748 * u32 pid, ppid;
749 * u32 tid, ptid;
750 * u64 time;
751 * struct sample_id sample_id;
752 * };
753 */
754 PERF_RECORD_EXIT = 4,
755
756 /*
757 * struct {
758 * struct perf_event_header header;
759 * u64 time;
760 * u64 id;
761 * u64 stream_id;
762 * struct sample_id sample_id;
763 * };
764 */
765 PERF_RECORD_THROTTLE = 5,
766 PERF_RECORD_UNTHROTTLE = 6,
767
768 /*
769 * struct {
770 * struct perf_event_header header;
771 * u32 pid, ppid;
772 * u32 tid, ptid;
773 * u64 time;
774 * struct sample_id sample_id;
775 * };
776 */
777 PERF_RECORD_FORK = 7,
778
779 /*
780 * struct {
781 * struct perf_event_header header;
782 * u32 pid, tid;
783 *
784 * struct read_format values;
785 * struct sample_id sample_id;
786 * };
787 */
788 PERF_RECORD_READ = 8,
789
790 /*
791 * struct {
792 * struct perf_event_header header;
793 *
794 * #
795 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID.
796 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position
797 * # is fixed relative to header.
798 * #
799 *
800 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
801 * { u64 ip; } && PERF_SAMPLE_IP
802 * { u32 pid, tid; } && PERF_SAMPLE_TID
803 * { u64 time; } && PERF_SAMPLE_TIME
804 * { u64 addr; } && PERF_SAMPLE_ADDR
805 * { u64 id; } && PERF_SAMPLE_ID
806 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
807 * { u32 cpu, res; } && PERF_SAMPLE_CPU
808 * { u64 period; } && PERF_SAMPLE_PERIOD
809 *
810 * { struct read_format values; } && PERF_SAMPLE_READ
811 *
812 * { u64 nr,
813 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN
814 *
815 * #
816 * # The RAW record below is opaque data wrt the ABI
817 * #
818 * # That is, the ABI doesn't make any promises wrt to
819 * # the stability of its content, it may vary depending
820 * # on event, hardware, kernel version and phase of
821 * # the moon.
822 * #
823 * # In other words, PERF_SAMPLE_RAW contents are not an ABI.
824 * #
825 *
826 * { u32 size;
827 * char data[size];}&& PERF_SAMPLE_RAW
828 *
829 * { u64 nr;
830 * { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK
831 *
832 * { u64 abi; # enum perf_sample_regs_abi
833 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER
834 *
835 * { u64 size;
836 * char data[size];
837 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER
838 *
839 * { u64 weight; } && PERF_SAMPLE_WEIGHT
840 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC
841 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION
842 * { u64 abi; # enum perf_sample_regs_abi
843 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR
844 * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR
845 * };
846 */
847 PERF_RECORD_SAMPLE = 9,
848
849 /*
850 * The MMAP2 records are an augmented version of MMAP, they add
851 * maj, min, ino numbers to be used to uniquely identify each mapping
852 *
853 * struct {
854 * struct perf_event_header header;
855 *
856 * u32 pid, tid;
857 * u64 addr;
858 * u64 len;
859 * u64 pgoff;
860 * u32 maj;
861 * u32 min;
862 * u64 ino;
863 * u64 ino_generation;
864 * u32 prot, flags;
865 * char filename[];
866 * struct sample_id sample_id;
867 * };
868 */
869 PERF_RECORD_MMAP2 = 10,
870
871 /*
872 * Records that new data landed in the AUX buffer part.
873 *
874 * struct {
875 * struct perf_event_header header;
876 *
877 * u64 aux_offset;
878 * u64 aux_size;
879 * u64 flags;
880 * struct sample_id sample_id;
881 * };
882 */
883 PERF_RECORD_AUX = 11,
884
885 /*
886 * Indicates that instruction trace has started
887 *
888 * struct {
889 * struct perf_event_header header;
890 * u32 pid;
891 * u32 tid;
892 * struct sample_id sample_id;
893 * };
894 */
895 PERF_RECORD_ITRACE_START = 12,
896
897 /*
898 * Records the dropped/lost sample number.
899 *
900 * struct {
901 * struct perf_event_header header;
902 *
903 * u64 lost;
904 * struct sample_id sample_id;
905 * };
906 */
907 PERF_RECORD_LOST_SAMPLES = 13,
908
909 /*
910 * Records a context switch in or out (flagged by
911 * PERF_RECORD_MISC_SWITCH_OUT). See also
912 * PERF_RECORD_SWITCH_CPU_WIDE.
913 *
914 * struct {
915 * struct perf_event_header header;
916 * struct sample_id sample_id;
917 * };
918 */
919 PERF_RECORD_SWITCH = 14,
920
921 /*
922 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and
923 * next_prev_tid that are the next (switching out) or previous
924 * (switching in) pid/tid.
925 *
926 * struct {
927 * struct perf_event_header header;
928 * u32 next_prev_pid;
929 * u32 next_prev_tid;
930 * struct sample_id sample_id;
931 * };
932 */
933 PERF_RECORD_SWITCH_CPU_WIDE = 15,
934
935 /*
936 * struct {
937 * struct perf_event_header header;
938 * u32 pid;
939 * u32 tid;
940 * u64 nr_namespaces;
941 * { u64 dev, inode; } [nr_namespaces];
942 * struct sample_id sample_id;
943 * };
944 */
945 PERF_RECORD_NAMESPACES = 16,
946
947 PERF_RECORD_MAX, /* non-ABI */
948 };
949
950 #define PERF_MAX_STACK_DEPTH 127
951 #define PERF_MAX_CONTEXTS_PER_STACK 8
952
953 enum perf_callchain_context {
954 PERF_CONTEXT_HV = (__u64)-32,
955 PERF_CONTEXT_KERNEL = (__u64)-128,
956 PERF_CONTEXT_USER = (__u64)-512,
957
958 PERF_CONTEXT_GUEST = (__u64)-2048,
959 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176,
960 PERF_CONTEXT_GUEST_USER = (__u64)-2560,
961
962 PERF_CONTEXT_MAX = (__u64)-4095,
963 };
964
965 /**
966 * PERF_RECORD_AUX::flags bits
967 */
968 #define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */
969 #define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */
970 #define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */
971 #define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */
972
973 #define PERF_FLAG_FD_NO_GROUP (1UL << 0)
974 #define PERF_FLAG_FD_OUTPUT (1UL << 1)
975 #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */
976 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */
977
978 #if defined(__LITTLE_ENDIAN_BITFIELD)
979 union perf_mem_data_src {
980 __u64 val;
981 struct {
982 __u64 mem_op:5, /* type of opcode */
983 mem_lvl:14, /* memory hierarchy level */
984 mem_snoop:5, /* snoop mode */
985 mem_lock:2, /* lock instr */
986 mem_dtlb:7, /* tlb access */
987 mem_lvl_num:4, /* memory hierarchy level number */
988 mem_remote:1, /* remote */
989 mem_snoopx:2, /* snoop mode, ext */
990 mem_rsvd:24;
991 };
992 };
993 #elif defined(__BIG_ENDIAN_BITFIELD)
994 union perf_mem_data_src {
995 __u64 val;
996 struct {
997 __u64 mem_rsvd:24,
998 mem_snoopx:2, /* snoop mode, ext */
999 mem_remote:1, /* remote */
1000 mem_lvl_num:4, /* memory hierarchy level number */
1001 mem_dtlb:7, /* tlb access */
1002 mem_lock:2, /* lock instr */
1003 mem_snoop:5, /* snoop mode */
1004 mem_lvl:14, /* memory hierarchy level */
1005 mem_op:5; /* type of opcode */
1006 };
1007 };
1008 #else
1009 #error "Unknown endianness"
1010 #endif
1011
1012 /* type of opcode (load/store/prefetch,code) */
1013 #define PERF_MEM_OP_NA 0x01 /* not available */
1014 #define PERF_MEM_OP_LOAD 0x02 /* load instruction */
1015 #define PERF_MEM_OP_STORE 0x04 /* store instruction */
1016 #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */
1017 #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */
1018 #define PERF_MEM_OP_SHIFT 0
1019
1020 /* memory hierarchy (memory level, hit or miss) */
1021 #define PERF_MEM_LVL_NA 0x01 /* not available */
1022 #define PERF_MEM_LVL_HIT 0x02 /* hit level */
1023 #define PERF_MEM_LVL_MISS 0x04 /* miss level */
1024 #define PERF_MEM_LVL_L1 0x08 /* L1 */
1025 #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */
1026 #define PERF_MEM_LVL_L2 0x20 /* L2 */
1027 #define PERF_MEM_LVL_L3 0x40 /* L3 */
1028 #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */
1029 #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */
1030 #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */
1031 #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */
1032 #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */
1033 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */
1034 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */
1035 #define PERF_MEM_LVL_SHIFT 5
1036
1037 #define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */
1038 #define PERF_MEM_REMOTE_SHIFT 37
1039
1040 #define PERF_MEM_LVLNUM_L1 0x01 /* L1 */
1041 #define PERF_MEM_LVLNUM_L2 0x02 /* L2 */
1042 #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */
1043 #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */
1044 /* 5-0xa available */
1045 #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */
1046 #define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */
1047 #define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */
1048 #define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */
1049 #define PERF_MEM_LVLNUM_NA 0x0f /* N/A */
1050
1051 #define PERF_MEM_LVLNUM_SHIFT 33
1052
1053 /* snoop mode */
1054 #define PERF_MEM_SNOOP_NA 0x01 /* not available */
1055 #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */
1056 #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */
1057 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */
1058 #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */
1059 #define PERF_MEM_SNOOP_SHIFT 19
1060
1061 #define PERF_MEM_SNOOPX_FWD 0x01 /* forward */
1062 /* 1 free */
1063 #define PERF_MEM_SNOOPX_SHIFT 37
1064
1065 /* locked instruction */
1066 #define PERF_MEM_LOCK_NA 0x01 /* not available */
1067 #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */
1068 #define PERF_MEM_LOCK_SHIFT 24
1069
1070 /* TLB access */
1071 #define PERF_MEM_TLB_NA 0x01 /* not available */
1072 #define PERF_MEM_TLB_HIT 0x02 /* hit level */
1073 #define PERF_MEM_TLB_MISS 0x04 /* miss level */
1074 #define PERF_MEM_TLB_L1 0x08 /* L1 */
1075 #define PERF_MEM_TLB_L2 0x10 /* L2 */
1076 #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/
1077 #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */
1078 #define PERF_MEM_TLB_SHIFT 26
1079
1080 #define PERF_MEM_S(a, s) \
1081 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
1082
1083 /*
1084 * single taken branch record layout:
1085 *
1086 * from: source instruction (may not always be a branch insn)
1087 * to: branch target
1088 * mispred: branch target was mispredicted
1089 * predicted: branch target was predicted
1090 *
1091 * support for mispred, predicted is optional. In case it
1092 * is not supported mispred = predicted = 0.
1093 *
1094 * in_tx: running in a hardware transaction
1095 * abort: aborting a hardware transaction
1096 * cycles: cycles from last branch (or 0 if not supported)
1097 * type: branch type
1098 */
1099 struct perf_branch_entry {
1100 __u64 from;
1101 __u64 to;
1102 __u64 mispred:1, /* target mispredicted */
1103 predicted:1,/* target predicted */
1104 in_tx:1, /* in transaction */
1105 abort:1, /* transaction abort */
1106 cycles:16, /* cycle count to last branch */
1107 type:4, /* branch type */
1108 reserved:40;
1109 };
1110
1111 #endif /* _UAPI_LINUX_PERF_EVENT_H */
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