Merge tag 'xtensa-20180225' of git://github.com/jcmvbkbc/linux-xtensa
[cris-mirror.git] / include / uapi / linux / serial_core.h
blob1c8413f93e3daafc9f138e8a619093ec3fc96cd1
1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
2 /*
3 * linux/drivers/char/serial_core.h
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #ifndef _UAPILINUX_SERIAL_CORE_H
22 #define _UAPILINUX_SERIAL_CORE_H
24 #include <linux/serial.h>
27 * The type definitions. These are from Ted Ts'o's serial.h
29 #define PORT_UNKNOWN 0
30 #define PORT_8250 1
31 #define PORT_16450 2
32 #define PORT_16550 3
33 #define PORT_16550A 4
34 #define PORT_CIRRUS 5
35 #define PORT_16650 6
36 #define PORT_16650V2 7
37 #define PORT_16750 8
38 #define PORT_STARTECH 9
39 #define PORT_16C950 10
40 #define PORT_16654 11
41 #define PORT_16850 12
42 #define PORT_RSA 13
43 #define PORT_NS16550A 14
44 #define PORT_XSCALE 15
45 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
46 #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
47 #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
48 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
49 #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
50 #define PORT_XR17D15X 21 /* Exar XR17D15x UART */
51 #define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */
52 #define PORT_8250_CIR 23 /* CIR infrared port, has its own driver */
53 #define PORT_XR17V35X 24 /* Exar XR17V35x UARTs */
54 #define PORT_BRCM_TRUMANAGE 25
55 #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */
56 #define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */
57 #define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
58 #define PORT_RT2880 29 /* Ralink RT2880 internal UART */
59 #define PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64 FIFOs */
62 * ARM specific type numbers. These are not currently guaranteed
63 * to be implemented, and will change in the future. These are
64 * separate so any additions to the old serial.c that occur before
65 * we are merged can be easily merged here.
67 #define PORT_PXA 31
68 #define PORT_AMBA 32
69 #define PORT_CLPS711X 33
70 #define PORT_SA1100 34
71 #define PORT_UART00 35
72 #define PORT_OWL 36
73 #define PORT_21285 37
75 /* Sparc type numbers. */
76 #define PORT_SUNZILOG 38
77 #define PORT_SUNSAB 39
79 /* Intel EG20 */
80 #define PORT_PCH_8LINE 44
81 #define PORT_PCH_2LINE 45
83 /* DEC */
84 #define PORT_DZ 46
85 #define PORT_ZS 47
87 /* Parisc type numbers. */
88 #define PORT_MUX 48
90 /* Atmel AT91 SoC */
91 #define PORT_ATMEL 49
93 /* Macintosh Zilog type numbers */
94 #define PORT_MAC_ZILOG 50 /* m68k : not yet implemented */
95 #define PORT_PMAC_ZILOG 51
97 /* SH-SCI */
98 #define PORT_SCI 52
99 #define PORT_SCIF 53
100 #define PORT_IRDA 54
102 /* Samsung S3C2410 SoC and derivatives thereof */
103 #define PORT_S3C2410 55
105 /* SGI IP22 aka Indy / Challenge S / Indigo 2 */
106 #define PORT_IP22ZILOG 56
108 /* Sharp LH7a40x -- an ARM9 SoC series */
109 #define PORT_LH7A40X 57
111 /* PPC CPM type number */
112 #define PORT_CPM 58
114 /* MPC52xx (and MPC512x) type numbers */
115 #define PORT_MPC52xx 59
117 /* IBM icom */
118 #define PORT_ICOM 60
120 /* Samsung S3C2440 SoC */
121 #define PORT_S3C2440 61
123 /* Motorola i.MX SoC */
124 #define PORT_IMX 62
126 /* Marvell MPSC */
127 #define PORT_MPSC 63
129 /* TXX9 type number */
130 #define PORT_TXX9 64
132 /* NEC VR4100 series SIU/DSIU */
133 #define PORT_VR41XX_SIU 65
134 #define PORT_VR41XX_DSIU 66
136 /* Samsung S3C2400 SoC */
137 #define PORT_S3C2400 67
139 /* M32R SIO */
140 #define PORT_M32R_SIO 68
142 /*Digi jsm */
143 #define PORT_JSM 69
145 #define PORT_PNX8XXX 70
147 /* Hilscher netx */
148 #define PORT_NETX 71
150 /* SUN4V Hypervisor Console */
151 #define PORT_SUNHV 72
153 #define PORT_S3C2412 73
155 /* Xilinx uartlite */
156 #define PORT_UARTLITE 74
158 /* Blackfin bf5xx */
159 #define PORT_BFIN 75
161 /* Micrel KS8695 */
162 #define PORT_KS8695 76
164 /* Broadcom SB1250, etc. SOC */
165 #define PORT_SB1250_DUART 77
167 /* Freescale ColdFire */
168 #define PORT_MCF 78
170 /* Blackfin SPORT */
171 #define PORT_BFIN_SPORT 79
173 /* MN10300 on-chip UART numbers */
174 #define PORT_MN10300 80
175 #define PORT_MN10300_CTS 81
177 #define PORT_SC26XX 82
179 /* SH-SCI */
180 #define PORT_SCIFA 83
182 #define PORT_S3C6400 84
184 /* NWPSERIAL, now removed */
185 #define PORT_NWPSERIAL 85
187 /* MAX3100 */
188 #define PORT_MAX3100 86
190 /* Timberdale UART */
191 #define PORT_TIMBUART 87
193 /* Qualcomm MSM SoCs */
194 #define PORT_MSM 88
196 /* BCM63xx family SoCs */
197 #define PORT_BCM63XX 89
199 /* Aeroflex Gaisler GRLIB APBUART */
200 #define PORT_APBUART 90
202 /* Altera UARTs */
203 #define PORT_ALTERA_JTAGUART 91
204 #define PORT_ALTERA_UART 92
206 /* SH-SCI */
207 #define PORT_SCIFB 93
209 /* MAX310X */
210 #define PORT_MAX310X 94
212 /* TI DA8xx/66AK2x */
213 #define PORT_DA830 95
215 /* TI OMAP-UART */
216 #define PORT_OMAP 96
218 /* VIA VT8500 SoC */
219 #define PORT_VT8500 97
221 /* Cadence (Xilinx Zynq) UART */
222 #define PORT_XUARTPS 98
224 /* Atheros AR933X SoC */
225 #define PORT_AR933X 99
227 /* Energy Micro efm32 SoC */
228 #define PORT_EFMUART 100
230 /* ARC (Synopsys) on-chip UART */
231 #define PORT_ARC 101
233 /* Rocketport EXPRESS/INFINITY */
234 #define PORT_RP2 102
236 /* Freescale lpuart */
237 #define PORT_LPUART 103
239 /* SH-SCI */
240 #define PORT_HSCIF 104
242 /* ST ASC type numbers */
243 #define PORT_ASC 105
245 /* Tilera TILE-Gx UART */
246 #define PORT_TILEGX 106
248 /* MEN 16z135 UART */
249 #define PORT_MEN_Z135 107
251 /* SC16IS74xx */
252 #define PORT_SC16IS7XX 108
254 /* MESON */
255 #define PORT_MESON 109
257 /* Conexant Digicolor */
258 #define PORT_DIGICOLOR 110
260 /* SPRD SERIAL */
261 #define PORT_SPRD 111
263 /* Cris v10 / v32 SoC */
264 #define PORT_CRIS 112
266 /* STM32 USART */
267 #define PORT_STM32 113
269 /* MVEBU UART */
270 #define PORT_MVEBU 114
272 /* Microchip PIC32 UART */
273 #define PORT_PIC32 115
275 /* MPS2 UART */
276 #define PORT_MPS2UART 116
278 /* MediaTek BTIF */
279 #define PORT_MTK_BTIF 117
281 #endif /* _UAPILINUX_SERIAL_CORE_H */