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Merge tag 'xtensa-20180225' of git://github.com/jcmvbkbc/linux-xtensa
[cris-mirror.git] / sound / soc / bcm / bcm2835-i2s.c
blobd5f73a8ab8932768c4df1470e94e78bff98d7787
1 /*
2 * ALSA SoC I2S Audio Layer for Broadcom BCM2835 SoC
3 *
4 * Author: Florian Meier <florian.meier@koalo.de>
5 * Copyright 2013
6 *
7 * Based on
8 * Raspberry Pi PCM I2S ALSA Driver
9 * Copyright (c) by Phil Poole 2013
10 *
11 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
12 * Vladimir Barinov, <vbarinov@embeddedalley.com>
13 * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
14 *
15 * OMAP ALSA SoC DAI driver using McBSP port
16 * Copyright (C) 2008 Nokia Corporation
17 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
18 * Peter Ujfalusi <peter.ujfalusi@ti.com>
19 *
20 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
21 * Author: Timur Tabi <timur@freescale.com>
22 * Copyright 2007-2010 Freescale Semiconductor, Inc.
23 *
24 * This program is free software; you can redistribute it and/or
25 * modify it under the terms of the GNU General Public License
26 * version 2 as published by the Free Software Foundation.
27 *
28 * This program is distributed in the hope that it will be useful, but
29 * WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
31 * General Public License for more details.
32 */
33
34 #include <linux/bitops.h>
35 #include <linux/clk.h>
36 #include <linux/delay.h>
37 #include <linux/device.h>
38 #include <linux/init.h>
39 #include <linux/io.h>
40 #include <linux/module.h>
41 #include <linux/of_address.h>
42 #include <linux/slab.h>
43
44 #include <sound/core.h>
45 #include <sound/dmaengine_pcm.h>
46 #include <sound/initval.h>
47 #include <sound/pcm.h>
48 #include <sound/pcm_params.h>
49 #include <sound/soc.h>
50
51 /* I2S registers */
52 #define BCM2835_I2S_CS_A_REG 0x00
53 #define BCM2835_I2S_FIFO_A_REG 0x04
54 #define BCM2835_I2S_MODE_A_REG 0x08
55 #define BCM2835_I2S_RXC_A_REG 0x0c
56 #define BCM2835_I2S_TXC_A_REG 0x10
57 #define BCM2835_I2S_DREQ_A_REG 0x14
58 #define BCM2835_I2S_INTEN_A_REG 0x18
59 #define BCM2835_I2S_INTSTC_A_REG 0x1c
60 #define BCM2835_I2S_GRAY_REG 0x20
61
62 /* I2S register settings */
63 #define BCM2835_I2S_STBY BIT(25)
64 #define BCM2835_I2S_SYNC BIT(24)
65 #define BCM2835_I2S_RXSEX BIT(23)
66 #define BCM2835_I2S_RXF BIT(22)
67 #define BCM2835_I2S_TXE BIT(21)
68 #define BCM2835_I2S_RXD BIT(20)
69 #define BCM2835_I2S_TXD BIT(19)
70 #define BCM2835_I2S_RXR BIT(18)
71 #define BCM2835_I2S_TXW BIT(17)
72 #define BCM2835_I2S_CS_RXERR BIT(16)
73 #define BCM2835_I2S_CS_TXERR BIT(15)
74 #define BCM2835_I2S_RXSYNC BIT(14)
75 #define BCM2835_I2S_TXSYNC BIT(13)
76 #define BCM2835_I2S_DMAEN BIT(9)
77 #define BCM2835_I2S_RXTHR(v) ((v) << 7)
78 #define BCM2835_I2S_TXTHR(v) ((v) << 5)
79 #define BCM2835_I2S_RXCLR BIT(4)
80 #define BCM2835_I2S_TXCLR BIT(3)
81 #define BCM2835_I2S_TXON BIT(2)
82 #define BCM2835_I2S_RXON BIT(1)
83 #define BCM2835_I2S_EN (1)
84
85 #define BCM2835_I2S_CLKDIS BIT(28)
86 #define BCM2835_I2S_PDMN BIT(27)
87 #define BCM2835_I2S_PDME BIT(26)
88 #define BCM2835_I2S_FRXP BIT(25)
89 #define BCM2835_I2S_FTXP BIT(24)
90 #define BCM2835_I2S_CLKM BIT(23)
91 #define BCM2835_I2S_CLKI BIT(22)
92 #define BCM2835_I2S_FSM BIT(21)
93 #define BCM2835_I2S_FSI BIT(20)
94 #define BCM2835_I2S_FLEN(v) ((v) << 10)
95 #define BCM2835_I2S_FSLEN(v) (v)
96
97 #define BCM2835_I2S_CHWEX BIT(15)
98 #define BCM2835_I2S_CHEN BIT(14)
99 #define BCM2835_I2S_CHPOS(v) ((v) << 4)
100 #define BCM2835_I2S_CHWID(v) (v)
101 #define BCM2835_I2S_CH1(v) ((v) << 16)
102 #define BCM2835_I2S_CH2(v) (v)
103 #define BCM2835_I2S_CH1_POS(v) BCM2835_I2S_CH1(BCM2835_I2S_CHPOS(v))
104 #define BCM2835_I2S_CH2_POS(v) BCM2835_I2S_CH2(BCM2835_I2S_CHPOS(v))
105
106 #define BCM2835_I2S_TX_PANIC(v) ((v) << 24)
107 #define BCM2835_I2S_RX_PANIC(v) ((v) << 16)
108 #define BCM2835_I2S_TX(v) ((v) << 8)
109 #define BCM2835_I2S_RX(v) (v)
110
111 #define BCM2835_I2S_INT_RXERR BIT(3)
112 #define BCM2835_I2S_INT_TXERR BIT(2)
113 #define BCM2835_I2S_INT_RXR BIT(1)
114 #define BCM2835_I2S_INT_TXW BIT(0)
115
116 /* Frame length register is 10 bit, maximum length 1024 */
117 #define BCM2835_I2S_MAX_FRAME_LENGTH 1024
118
119 /* General device struct */
120 struct bcm2835_i2s_dev {
121 struct device *dev;
122 struct snd_dmaengine_dai_dma_data dma_data[2];
123 unsigned int fmt;
124 unsigned int tdm_slots;
125 unsigned int rx_mask;
126 unsigned int tx_mask;
127 unsigned int slot_width;
128 unsigned int frame_length;
129
130 struct regmap *i2s_regmap;
131 struct clk *clk;
132 bool clk_prepared;
133 int clk_rate;
134 };
135
136 static void bcm2835_i2s_start_clock(struct bcm2835_i2s_dev *dev)
137 {
138 unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
139
140 if (dev->clk_prepared)
141 return;
142
143 switch (master) {
144 case SND_SOC_DAIFMT_CBS_CFS:
145 case SND_SOC_DAIFMT_CBS_CFM:
146 clk_prepare_enable(dev->clk);
147 dev->clk_prepared = true;
148 break;
149 default:
150 break;
151 }
152 }
153
154 static void bcm2835_i2s_stop_clock(struct bcm2835_i2s_dev *dev)
155 {
156 if (dev->clk_prepared)
157 clk_disable_unprepare(dev->clk);
158 dev->clk_prepared = false;
159 }
160
161 static void bcm2835_i2s_clear_fifos(struct bcm2835_i2s_dev *dev,
162 bool tx, bool rx)
163 {
164 int timeout = 1000;
165 uint32_t syncval;
166 uint32_t csreg;
167 uint32_t i2s_active_state;
168 bool clk_was_prepared;
169 uint32_t off;
170 uint32_t clr;
171
172 off = tx ? BCM2835_I2S_TXON : 0;
173 off |= rx ? BCM2835_I2S_RXON : 0;
174
175 clr = tx ? BCM2835_I2S_TXCLR : 0;
176 clr |= rx ? BCM2835_I2S_RXCLR : 0;
177
178 /* Backup the current state */
179 regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
180 i2s_active_state = csreg & (BCM2835_I2S_RXON | BCM2835_I2S_TXON);
181
182 /* Start clock if not running */
183 clk_was_prepared = dev->clk_prepared;
184 if (!clk_was_prepared)
185 bcm2835_i2s_start_clock(dev);
186
187 /* Stop I2S module */
188 regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, off, 0);
189
190 /*
191 * Clear the FIFOs
192 * Requires at least 2 PCM clock cycles to take effect
193 */
194 regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, clr, clr);
195
196 /* Wait for 2 PCM clock cycles */
197
198 /*
199 * Toggle the SYNC flag. After 2 PCM clock cycles it can be read back
200 * FIXME: This does not seem to work for slave mode!
201 */
202 regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &syncval);
203 syncval &= BCM2835_I2S_SYNC;
204
205 regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
206 BCM2835_I2S_SYNC, ~syncval);
207
208 /* Wait for the SYNC flag changing it's state */
209 while (--timeout) {
210 regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
211 if ((csreg & BCM2835_I2S_SYNC) != syncval)
212 break;
213 }
214
215 if (!timeout)
216 dev_err(dev->dev, "I2S SYNC error!\n");
217
218 /* Stop clock if it was not running before */
219 if (!clk_was_prepared)
220 bcm2835_i2s_stop_clock(dev);
221
222 /* Restore I2S state */
223 regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
224 BCM2835_I2S_RXON | BCM2835_I2S_TXON, i2s_active_state);
225 }
226
227 static int bcm2835_i2s_set_dai_fmt(struct snd_soc_dai *dai,
228 unsigned int fmt)
229 {
230 struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
231 dev->fmt = fmt;
232 return 0;
233 }
234
235 static int bcm2835_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai,
236 unsigned int ratio)
237 {
238 struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
239
240 if (!ratio) {
241 dev->tdm_slots = 0;
242 return 0;
243 }
244
245 if (ratio > BCM2835_I2S_MAX_FRAME_LENGTH)
246 return -EINVAL;
247
248 dev->tdm_slots = 2;
249 dev->rx_mask = 0x03;
250 dev->tx_mask = 0x03;
251 dev->slot_width = ratio / 2;
252 dev->frame_length = ratio;
253
254 return 0;
255 }
256
257 static int bcm2835_i2s_set_dai_tdm_slot(struct snd_soc_dai *dai,
258 unsigned int tx_mask, unsigned int rx_mask,
259 int slots, int width)
260 {
261 struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
262
263 if (slots) {
264 if (slots < 0 || width < 0)
265 return -EINVAL;
266
267 /* Limit masks to available slots */
268 rx_mask &= GENMASK(slots - 1, 0);
269 tx_mask &= GENMASK(slots - 1, 0);
270
271 /*
272 * The driver is limited to 2-channel setups.
273 * Check that exactly 2 bits are set in the masks.
274 */
275 if (hweight_long((unsigned long) rx_mask) != 2
276 || hweight_long((unsigned long) tx_mask) != 2)
277 return -EINVAL;
278
279 if (slots * width > BCM2835_I2S_MAX_FRAME_LENGTH)
280 return -EINVAL;
281 }
282
283 dev->tdm_slots = slots;
284
285 dev->rx_mask = rx_mask;
286 dev->tx_mask = tx_mask;
287 dev->slot_width = width;
288 dev->frame_length = slots * width;
289
290 return 0;
291 }
292
293 /*
294 * Convert logical slot number into physical slot number.
295 *
296 * If odd_offset is 0 sequential number is identical to logical number.
297 * This is used for DSP modes with slot numbering 0 1 2 3 ...
298 *
299 * Otherwise odd_offset defines the physical offset for odd numbered
300 * slots. This is used for I2S and left/right justified modes to
301 * translate from logical slot numbers 0 1 2 3 ... into physical slot
302 * numbers 0 2 ... 3 4 ...
303 */
304 static int bcm2835_i2s_convert_slot(unsigned int slot, unsigned int odd_offset)
305 {
306 if (!odd_offset)
307 return slot;
308
309 if (slot & 1)
310 return (slot >> 1) + odd_offset;
311
312 return slot >> 1;
313 }
314
315 /*
316 * Calculate channel position from mask and slot width.
317 *
318 * Mask must contain exactly 2 set bits.
319 * Lowest set bit is channel 1 position, highest set bit channel 2.
320 * The constant offset is added to both channel positions.
321 *
322 * If odd_offset is > 0 slot positions are translated to
323 * I2S-style TDM slot numbering ( 0 2 ... 3 4 ...) with odd
324 * logical slot numbers starting at physical slot odd_offset.
325 */
326 static void bcm2835_i2s_calc_channel_pos(
327 unsigned int *ch1_pos, unsigned int *ch2_pos,
328 unsigned int mask, unsigned int width,
329 unsigned int bit_offset, unsigned int odd_offset)
330 {
331 *ch1_pos = bcm2835_i2s_convert_slot((ffs(mask) - 1), odd_offset)
332 * width + bit_offset;
333 *ch2_pos = bcm2835_i2s_convert_slot((fls(mask) - 1), odd_offset)
334 * width + bit_offset;
335 }
336
337 static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,
338 struct snd_pcm_hw_params *params,
339 struct snd_soc_dai *dai)
340 {
341 struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
342 unsigned int data_length, data_delay, framesync_length;
343 unsigned int slots, slot_width, odd_slot_offset;
344 int frame_length, bclk_rate;
345 unsigned int rx_mask, tx_mask;
346 unsigned int rx_ch1_pos, rx_ch2_pos, tx_ch1_pos, tx_ch2_pos;
347 unsigned int mode, format;
348 bool bit_clock_master = false;
349 bool frame_sync_master = false;
350 bool frame_start_falling_edge = false;
351 uint32_t csreg;
352 int ret = 0;
353
354 /*
355 * If a stream is already enabled,
356 * the registers are already set properly.
357 */
358 regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
359
360 if (csreg & (BCM2835_I2S_TXON | BCM2835_I2S_RXON))
361 return 0;
362
363 data_length = params_width(params);
364 data_delay = 0;
365 odd_slot_offset = 0;
366 mode = 0;
367
368 if (dev->tdm_slots) {
369 slots = dev->tdm_slots;
370 slot_width = dev->slot_width;
371 frame_length = dev->frame_length;
372 rx_mask = dev->rx_mask;
373 tx_mask = dev->tx_mask;
374 bclk_rate = dev->frame_length * params_rate(params);
375 } else {
376 slots = 2;
377 slot_width = params_width(params);
378 rx_mask = 0x03;
379 tx_mask = 0x03;
380
381 frame_length = snd_soc_params_to_frame_size(params);
382 if (frame_length < 0)
383 return frame_length;
384
385 bclk_rate = snd_soc_params_to_bclk(params);
386 if (bclk_rate < 0)
387 return bclk_rate;
388 }
389
390 /* Check if data fits into slots */
391 if (data_length > slot_width)
392 return -EINVAL;
393
394 /* Check if CPU is bit clock master */
395 switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
396 case SND_SOC_DAIFMT_CBS_CFS:
397 case SND_SOC_DAIFMT_CBS_CFM:
398 bit_clock_master = true;
399 break;
400 case SND_SOC_DAIFMT_CBM_CFS:
401 case SND_SOC_DAIFMT_CBM_CFM:
402 bit_clock_master = false;
403 break;
404 default:
405 return -EINVAL;
406 }
407
408 /* Check if CPU is frame sync master */
409 switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
410 case SND_SOC_DAIFMT_CBS_CFS:
411 case SND_SOC_DAIFMT_CBM_CFS:
412 frame_sync_master = true;
413 break;
414 case SND_SOC_DAIFMT_CBS_CFM:
415 case SND_SOC_DAIFMT_CBM_CFM:
416 frame_sync_master = false;
417 break;
418 default:
419 return -EINVAL;
420 }
421
422 /* Clock should only be set up here if CPU is clock master */
423 if (bit_clock_master &&
424 (!dev->clk_prepared || dev->clk_rate != bclk_rate)) {
425 if (dev->clk_prepared)
426 bcm2835_i2s_stop_clock(dev);
427
428 if (dev->clk_rate != bclk_rate) {
429 ret = clk_set_rate(dev->clk, bclk_rate);
430 if (ret)
431 return ret;
432 dev->clk_rate = bclk_rate;
433 }
434
435 bcm2835_i2s_start_clock(dev);
436 }
437
438 /* Setup the frame format */
439 format = BCM2835_I2S_CHEN;
440
441 if (data_length >= 24)
442 format |= BCM2835_I2S_CHWEX;
443
444 format |= BCM2835_I2S_CHWID((data_length-8)&0xf);
445
446 /* CH2 format is the same as for CH1 */
447 format = BCM2835_I2S_CH1(format) | BCM2835_I2S_CH2(format);
448
449 switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
450 case SND_SOC_DAIFMT_I2S:
451 /* I2S mode needs an even number of slots */
452 if (slots & 1)
453 return -EINVAL;
454
455 /*
456 * Use I2S-style logical slot numbering: even slots
457 * are in first half of frame, odd slots in second half.
458 */
459 odd_slot_offset = slots >> 1;
460
461 /* MSB starts one cycle after frame start */
462 data_delay = 1;
463
464 /* Setup frame sync signal for 50% duty cycle */
465 framesync_length = frame_length / 2;
466 frame_start_falling_edge = true;
467 break;
468 case SND_SOC_DAIFMT_LEFT_J:
469 if (slots & 1)
470 return -EINVAL;
471
472 odd_slot_offset = slots >> 1;
473 data_delay = 0;
474 framesync_length = frame_length / 2;
475 frame_start_falling_edge = false;
476 break;
477 case SND_SOC_DAIFMT_RIGHT_J:
478 if (slots & 1)
479 return -EINVAL;
480
481 /* Odd frame lengths aren't supported */
482 if (frame_length & 1)
483 return -EINVAL;
484
485 odd_slot_offset = slots >> 1;
486 data_delay = slot_width - data_length;
487 framesync_length = frame_length / 2;
488 frame_start_falling_edge = false;
489 break;
490 case SND_SOC_DAIFMT_DSP_A:
491 data_delay = 1;
492 framesync_length = 1;
493 frame_start_falling_edge = false;
494 break;
495 case SND_SOC_DAIFMT_DSP_B:
496 data_delay = 0;
497 framesync_length = 1;
498 frame_start_falling_edge = false;
499 break;
500 default:
501 return -EINVAL;
502 }
503
504 bcm2835_i2s_calc_channel_pos(&rx_ch1_pos, &rx_ch2_pos,
505 rx_mask, slot_width, data_delay, odd_slot_offset);
506 bcm2835_i2s_calc_channel_pos(&tx_ch1_pos, &tx_ch2_pos,
507 tx_mask, slot_width, data_delay, odd_slot_offset);
508
509 /*
510 * Transmitting data immediately after frame start, eg
511 * in left-justified or DSP mode A, only works stable
512 * if bcm2835 is the frame clock master.
513 */
514 if ((!rx_ch1_pos || !tx_ch1_pos) && !frame_sync_master)
515 dev_warn(dev->dev,
516 "Unstable slave config detected, L/R may be swapped");
517
518 /*
519 * Set format for both streams.
520 * We cannot set another frame length
521 * (and therefore word length) anyway,
522 * so the format will be the same.
523 */
524 regmap_write(dev->i2s_regmap, BCM2835_I2S_RXC_A_REG,
525 format
526 | BCM2835_I2S_CH1_POS(rx_ch1_pos)
527 | BCM2835_I2S_CH2_POS(rx_ch2_pos));
528 regmap_write(dev->i2s_regmap, BCM2835_I2S_TXC_A_REG,
529 format
530 | BCM2835_I2S_CH1_POS(tx_ch1_pos)
531 | BCM2835_I2S_CH2_POS(tx_ch2_pos));
532
533 /* Setup the I2S mode */
534
535 if (data_length <= 16) {
536 /*
537 * Use frame packed mode (2 channels per 32 bit word)
538 * We cannot set another frame length in the second stream
539 * (and therefore word length) anyway,
540 * so the format will be the same.
541 */
542 mode |= BCM2835_I2S_FTXP | BCM2835_I2S_FRXP;
543 }
544
545 mode |= BCM2835_I2S_FLEN(frame_length - 1);
546 mode |= BCM2835_I2S_FSLEN(framesync_length);
547
548 /* CLKM selects bcm2835 clock slave mode */
549 if (!bit_clock_master)
550 mode |= BCM2835_I2S_CLKM;
551
552 /* FSM selects bcm2835 frame sync slave mode */
553 if (!frame_sync_master)
554 mode |= BCM2835_I2S_FSM;
555
556 /* CLKI selects normal clocking mode, sampling on rising edge */
557 switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
558 case SND_SOC_DAIFMT_NB_NF:
559 case SND_SOC_DAIFMT_NB_IF:
560 mode |= BCM2835_I2S_CLKI;
561 break;
562 case SND_SOC_DAIFMT_IB_NF:
563 case SND_SOC_DAIFMT_IB_IF:
564 break;
565 default:
566 return -EINVAL;
567 }
568
569 /* FSI selects frame start on falling edge */
570 switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
571 case SND_SOC_DAIFMT_NB_NF:
572 case SND_SOC_DAIFMT_IB_NF:
573 if (frame_start_falling_edge)
574 mode |= BCM2835_I2S_FSI;
575 break;
576 case SND_SOC_DAIFMT_NB_IF:
577 case SND_SOC_DAIFMT_IB_IF:
578 if (!frame_start_falling_edge)
579 mode |= BCM2835_I2S_FSI;
580 break;
581 default:
582 return -EINVAL;
583 }
584
585 regmap_write(dev->i2s_regmap, BCM2835_I2S_MODE_A_REG, mode);
586
587 /* Setup the DMA parameters */
588 regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
589 BCM2835_I2S_RXTHR(1)
590 | BCM2835_I2S_TXTHR(1)
591 | BCM2835_I2S_DMAEN, 0xffffffff);
592
593 regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_DREQ_A_REG,
594 BCM2835_I2S_TX_PANIC(0x10)
595 | BCM2835_I2S_RX_PANIC(0x30)
596 | BCM2835_I2S_TX(0x30)
597 | BCM2835_I2S_RX(0x20), 0xffffffff);
598
599 /* Clear FIFOs */
600 bcm2835_i2s_clear_fifos(dev, true, true);
601
602 dev_dbg(dev->dev,
603 "slots: %d width: %d rx mask: 0x%02x tx_mask: 0x%02x\n",
604 slots, slot_width, rx_mask, tx_mask);
605
606 dev_dbg(dev->dev, "frame len: %d sync len: %d data len: %d\n",
607 frame_length, framesync_length, data_length);
608
609 dev_dbg(dev->dev, "rx pos: %d,%d tx pos: %d,%d\n",
610 rx_ch1_pos, rx_ch2_pos, tx_ch1_pos, tx_ch2_pos);
611
612 dev_dbg(dev->dev, "sampling rate: %d bclk rate: %d\n",
613 params_rate(params), bclk_rate);
614
615 dev_dbg(dev->dev, "CLKM: %d CLKI: %d FSM: %d FSI: %d frame start: %s edge\n",
616 !!(mode & BCM2835_I2S_CLKM),
617 !!(mode & BCM2835_I2S_CLKI),
618 !!(mode & BCM2835_I2S_FSM),
619 !!(mode & BCM2835_I2S_FSI),
620 (mode & BCM2835_I2S_FSI) ? "falling" : "rising");
621
622 return ret;
623 }
624
625 static int bcm2835_i2s_prepare(struct snd_pcm_substream *substream,
626 struct snd_soc_dai *dai)
627 {
628 struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
629 uint32_t cs_reg;
630
631 /*
632 * Clear both FIFOs if the one that should be started
633 * is not empty at the moment. This should only happen
634 * after overrun. Otherwise, hw_params would have cleared
635 * the FIFO.
636 */
637 regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &cs_reg);
638
639 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK
640 && !(cs_reg & BCM2835_I2S_TXE))
641 bcm2835_i2s_clear_fifos(dev, true, false);
642 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE
643 && (cs_reg & BCM2835_I2S_RXD))
644 bcm2835_i2s_clear_fifos(dev, false, true);
645
646 return 0;
647 }
648
649 static void bcm2835_i2s_stop(struct bcm2835_i2s_dev *dev,
650 struct snd_pcm_substream *substream,
651 struct snd_soc_dai *dai)
652 {
653 uint32_t mask;
654
655 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
656 mask = BCM2835_I2S_RXON;
657 else
658 mask = BCM2835_I2S_TXON;
659
660 regmap_update_bits(dev->i2s_regmap,
661 BCM2835_I2S_CS_A_REG, mask, 0);
662
663 /* Stop also the clock when not SND_SOC_DAIFMT_CONT */
664 if (!dai->active && !(dev->fmt & SND_SOC_DAIFMT_CONT))
665 bcm2835_i2s_stop_clock(dev);
666 }
667
668 static int bcm2835_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
669 struct snd_soc_dai *dai)
670 {
671 struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
672 uint32_t mask;
673
674 switch (cmd) {
675 case SNDRV_PCM_TRIGGER_START:
676 case SNDRV_PCM_TRIGGER_RESUME:
677 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
678 bcm2835_i2s_start_clock(dev);
679
680 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
681 mask = BCM2835_I2S_RXON;
682 else
683 mask = BCM2835_I2S_TXON;
684
685 regmap_update_bits(dev->i2s_regmap,
686 BCM2835_I2S_CS_A_REG, mask, mask);
687 break;
688
689 case SNDRV_PCM_TRIGGER_STOP:
690 case SNDRV_PCM_TRIGGER_SUSPEND:
691 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
692 bcm2835_i2s_stop(dev, substream, dai);
693 break;
694 default:
695 return -EINVAL;
696 }
697
698 return 0;
699 }
700
701 static int bcm2835_i2s_startup(struct snd_pcm_substream *substream,
702 struct snd_soc_dai *dai)
703 {
704 struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
705
706 if (dai->active)
707 return 0;
708
709 /* Should this still be running stop it */
710 bcm2835_i2s_stop_clock(dev);
711
712 /* Enable PCM block */
713 regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
714 BCM2835_I2S_EN, BCM2835_I2S_EN);
715
716 /*
717 * Disable STBY.
718 * Requires at least 4 PCM clock cycles to take effect.
719 */
720 regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
721 BCM2835_I2S_STBY, BCM2835_I2S_STBY);
722
723 return 0;
724 }
725
726 static void bcm2835_i2s_shutdown(struct snd_pcm_substream *substream,
727 struct snd_soc_dai *dai)
728 {
729 struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
730
731 bcm2835_i2s_stop(dev, substream, dai);
732
733 /* If both streams are stopped, disable module and clock */
734 if (dai->active)
735 return;
736
737 /* Disable the module */
738 regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
739 BCM2835_I2S_EN, 0);
740
741 /*
742 * Stopping clock is necessary, because stop does
743 * not stop the clock when SND_SOC_DAIFMT_CONT
744 */
745 bcm2835_i2s_stop_clock(dev);
746 }
747
748 static const struct snd_soc_dai_ops bcm2835_i2s_dai_ops = {
749 .startup = bcm2835_i2s_startup,
750 .shutdown = bcm2835_i2s_shutdown,
751 .prepare = bcm2835_i2s_prepare,
752 .trigger = bcm2835_i2s_trigger,
753 .hw_params = bcm2835_i2s_hw_params,
754 .set_fmt = bcm2835_i2s_set_dai_fmt,
755 .set_bclk_ratio = bcm2835_i2s_set_dai_bclk_ratio,
756 .set_tdm_slot = bcm2835_i2s_set_dai_tdm_slot,
757 };
758
759 static int bcm2835_i2s_dai_probe(struct snd_soc_dai *dai)
760 {
761 struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
762
763 snd_soc_dai_init_dma_data(dai,
764 &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
765 &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
766
767 return 0;
768 }
769
770 static struct snd_soc_dai_driver bcm2835_i2s_dai = {
771 .name = "bcm2835-i2s",
772 .probe = bcm2835_i2s_dai_probe,
773 .playback = {
774 .channels_min = 2,
775 .channels_max = 2,
776 .rates = SNDRV_PCM_RATE_CONTINUOUS,
777 .rate_min = 8000,
778 .rate_max = 384000,
779 .formats = SNDRV_PCM_FMTBIT_S16_LE
780 | SNDRV_PCM_FMTBIT_S24_LE
781 | SNDRV_PCM_FMTBIT_S32_LE
782 },
783 .capture = {
784 .channels_min = 2,
785 .channels_max = 2,
786 .rates = SNDRV_PCM_RATE_CONTINUOUS,
787 .rate_min = 8000,
788 .rate_max = 384000,
789 .formats = SNDRV_PCM_FMTBIT_S16_LE
790 | SNDRV_PCM_FMTBIT_S24_LE
791 | SNDRV_PCM_FMTBIT_S32_LE
792 },
793 .ops = &bcm2835_i2s_dai_ops,
794 .symmetric_rates = 1,
795 .symmetric_samplebits = 1,
796 };
797
798 static bool bcm2835_i2s_volatile_reg(struct device *dev, unsigned int reg)
799 {
800 switch (reg) {
801 case BCM2835_I2S_CS_A_REG:
802 case BCM2835_I2S_FIFO_A_REG:
803 case BCM2835_I2S_INTSTC_A_REG:
804 case BCM2835_I2S_GRAY_REG:
805 return true;
806 default:
807 return false;
808 };
809 }
810
811 static bool bcm2835_i2s_precious_reg(struct device *dev, unsigned int reg)
812 {
813 switch (reg) {
814 case BCM2835_I2S_FIFO_A_REG:
815 return true;
816 default:
817 return false;
818 };
819 }
820
821 static const struct regmap_config bcm2835_regmap_config = {
822 .reg_bits = 32,
823 .reg_stride = 4,
824 .val_bits = 32,
825 .max_register = BCM2835_I2S_GRAY_REG,
826 .precious_reg = bcm2835_i2s_precious_reg,
827 .volatile_reg = bcm2835_i2s_volatile_reg,
828 .cache_type = REGCACHE_RBTREE,
829 };
830
831 static const struct snd_soc_component_driver bcm2835_i2s_component = {
832 .name = "bcm2835-i2s-comp",
833 };
834
835 static int bcm2835_i2s_probe(struct platform_device *pdev)
836 {
837 struct bcm2835_i2s_dev *dev;
838 int ret;
839 struct resource *mem;
840 void __iomem *base;
841 const __be32 *addr;
842 dma_addr_t dma_base;
843
844 dev = devm_kzalloc(&pdev->dev, sizeof(*dev),
845 GFP_KERNEL);
846 if (!dev)
847 return -ENOMEM;
848
849 /* get the clock */
850 dev->clk_prepared = false;
851 dev->clk = devm_clk_get(&pdev->dev, NULL);
852 if (IS_ERR(dev->clk)) {
853 dev_err(&pdev->dev, "could not get clk: %ld\n",
854 PTR_ERR(dev->clk));
855 return PTR_ERR(dev->clk);
856 }
857
858 /* Request ioarea */
859 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
860 base = devm_ioremap_resource(&pdev->dev, mem);
861 if (IS_ERR(base))
862 return PTR_ERR(base);
863
864 dev->i2s_regmap = devm_regmap_init_mmio(&pdev->dev, base,
865 &bcm2835_regmap_config);
866 if (IS_ERR(dev->i2s_regmap))
867 return PTR_ERR(dev->i2s_regmap);
868
869 /* Set the DMA address - we have to parse DT ourselves */
870 addr = of_get_address(pdev->dev.of_node, 0, NULL, NULL);
871 if (!addr) {
872 dev_err(&pdev->dev, "could not get DMA-register address\n");
873 return -EINVAL;
874 }
875 dma_base = be32_to_cpup(addr);
876
877 dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
878 dma_base + BCM2835_I2S_FIFO_A_REG;
879
880 dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
881 dma_base + BCM2835_I2S_FIFO_A_REG;
882
883 /* Set the bus width */
884 dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width =
885 DMA_SLAVE_BUSWIDTH_4_BYTES;
886 dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr_width =
887 DMA_SLAVE_BUSWIDTH_4_BYTES;
888
889 /* Set burst */
890 dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 2;
891 dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 2;
892
893 /*
894 * Set the PACK flag to enable S16_LE support (2 S16_LE values
895 * packed into 32-bit transfers).
896 */
897 dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].flags =
898 SND_DMAENGINE_PCM_DAI_FLAG_PACK;
899 dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].flags =
900 SND_DMAENGINE_PCM_DAI_FLAG_PACK;
901
902 /* Store the pdev */
903 dev->dev = &pdev->dev;
904 dev_set_drvdata(&pdev->dev, dev);
905
906 ret = devm_snd_soc_register_component(&pdev->dev,
907 &bcm2835_i2s_component, &bcm2835_i2s_dai, 1);
908 if (ret) {
909 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
910 return ret;
911 }
912
913 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
914 if (ret) {
915 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
916 return ret;
917 }
918
919 return 0;
920 }
921
922 static const struct of_device_id bcm2835_i2s_of_match[] = {
923 { .compatible = "brcm,bcm2835-i2s", },
924 {},
925 };
926
927 MODULE_DEVICE_TABLE(of, bcm2835_i2s_of_match);
928
929 static struct platform_driver bcm2835_i2s_driver = {
930 .probe = bcm2835_i2s_probe,
931 .driver = {
932 .name = "bcm2835-i2s",
933 .of_match_table = bcm2835_i2s_of_match,
934 },
935 };
936
937 module_platform_driver(bcm2835_i2s_driver);
938
939 MODULE_ALIAS("platform:bcm2835-i2s");
940 MODULE_DESCRIPTION("BCM2835 I2S interface");
941 MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
942 MODULE_LICENSE("GPL v2");
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