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Merge tag 'xtensa-20180225' of git://github.com/jcmvbkbc/linux-xtensa
[cris-mirror.git] / sound / soc / pxa / pxa-ssp.c
blob0291c7cb64eb1edd631a153a82fe979691aafa8e
1 /*
2 * pxa-ssp.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * TODO:
14 * o Test network mode for > 16bit sample size
15 */
16
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/pxa2xx_ssp.h>
24 #include <linux/of.h>
25 #include <linux/dmaengine.h>
26
27 #include <asm/irq.h>
28
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/initval.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/pxa2xx-lib.h>
35 #include <sound/dmaengine_pcm.h>
36
37 #include "../../arm/pxa2xx-pcm.h"
38 #include "pxa-ssp.h"
39
40 /*
41 * SSP audio private data
42 */
43 struct ssp_priv {
44 struct ssp_device *ssp;
45 unsigned int sysclk;
46 int dai_fmt;
47 #ifdef CONFIG_PM
48 uint32_t cr0;
49 uint32_t cr1;
50 uint32_t to;
51 uint32_t psp;
52 #endif
53 };
54
55 static void dump_registers(struct ssp_device *ssp)
56 {
57 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
58 pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1),
59 pxa_ssp_read_reg(ssp, SSTO));
60
61 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
62 pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR),
63 pxa_ssp_read_reg(ssp, SSACD));
64 }
65
66 static void pxa_ssp_enable(struct ssp_device *ssp)
67 {
68 uint32_t sscr0;
69
70 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE;
71 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
72 }
73
74 static void pxa_ssp_disable(struct ssp_device *ssp)
75 {
76 uint32_t sscr0;
77
78 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE;
79 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
80 }
81
82 static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4,
83 int out, struct snd_dmaengine_dai_dma_data *dma)
84 {
85 dma->addr_width = width4 ? DMA_SLAVE_BUSWIDTH_4_BYTES :
86 DMA_SLAVE_BUSWIDTH_2_BYTES;
87 dma->maxburst = 16;
88 dma->addr = ssp->phys_base + SSDR;
89 }
90
91 static int pxa_ssp_startup(struct snd_pcm_substream *substream,
92 struct snd_soc_dai *cpu_dai)
93 {
94 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
95 struct ssp_device *ssp = priv->ssp;
96 struct snd_dmaengine_dai_dma_data *dma;
97 int ret = 0;
98
99 if (!cpu_dai->active) {
100 clk_prepare_enable(ssp->clk);
101 pxa_ssp_disable(ssp);
102 }
103
104 dma = kzalloc(sizeof(struct snd_dmaengine_dai_dma_data), GFP_KERNEL);
105 if (!dma)
106 return -ENOMEM;
107
108 dma->filter_data = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
109 &ssp->drcmr_tx : &ssp->drcmr_rx;
110
111 snd_soc_dai_set_dma_data(cpu_dai, substream, dma);
112
113 return ret;
114 }
115
116 static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
117 struct snd_soc_dai *cpu_dai)
118 {
119 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
120 struct ssp_device *ssp = priv->ssp;
121
122 if (!cpu_dai->active) {
123 pxa_ssp_disable(ssp);
124 clk_disable_unprepare(ssp->clk);
125 }
126
127 kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
128 snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
129 }
130
131 #ifdef CONFIG_PM
132
133 static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
134 {
135 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
136 struct ssp_device *ssp = priv->ssp;
137
138 if (!cpu_dai->active)
139 clk_prepare_enable(ssp->clk);
140
141 priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
142 priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
143 priv->to = __raw_readl(ssp->mmio_base + SSTO);
144 priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
145
146 pxa_ssp_disable(ssp);
147 clk_disable_unprepare(ssp->clk);
148 return 0;
149 }
150
151 static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
152 {
153 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
154 struct ssp_device *ssp = priv->ssp;
155 uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
156
157 clk_prepare_enable(ssp->clk);
158
159 __raw_writel(sssr, ssp->mmio_base + SSSR);
160 __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
161 __raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
162 __raw_writel(priv->to, ssp->mmio_base + SSTO);
163 __raw_writel(priv->psp, ssp->mmio_base + SSPSP);
164
165 if (cpu_dai->active)
166 pxa_ssp_enable(ssp);
167 else
168 clk_disable_unprepare(ssp->clk);
169
170 return 0;
171 }
172
173 #else
174 #define pxa_ssp_suspend NULL
175 #define pxa_ssp_resume NULL
176 #endif
177
178 /**
179 * ssp_set_clkdiv - set SSP clock divider
180 * @div: serial clock rate divider
181 */
182 static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div)
183 {
184 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
185
186 if (ssp->type == PXA25x_SSP) {
187 sscr0 &= ~0x0000ff00;
188 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
189 } else {
190 sscr0 &= ~0x000fff00;
191 sscr0 |= (div - 1) << 8; /* 1..4096 */
192 }
193 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
194 }
195
196 /**
197 * pxa_ssp_get_clkdiv - get SSP clock divider
198 */
199 static u32 pxa_ssp_get_scr(struct ssp_device *ssp)
200 {
201 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
202 u32 div;
203
204 if (ssp->type == PXA25x_SSP)
205 div = ((sscr0 >> 8) & 0xff) * 2 + 2;
206 else
207 div = ((sscr0 >> 8) & 0xfff) + 1;
208 return div;
209 }
210
211 /*
212 * Set the SSP ports SYSCLK.
213 */
214 static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
215 int clk_id, unsigned int freq, int dir)
216 {
217 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
218 struct ssp_device *ssp = priv->ssp;
219 int val;
220
221 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
222 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
223
224 dev_dbg(&ssp->pdev->dev,
225 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
226 cpu_dai->id, clk_id, freq);
227
228 switch (clk_id) {
229 case PXA_SSP_CLK_NET_PLL:
230 sscr0 |= SSCR0_MOD;
231 break;
232 case PXA_SSP_CLK_PLL:
233 /* Internal PLL is fixed */
234 if (ssp->type == PXA25x_SSP)
235 priv->sysclk = 1843200;
236 else
237 priv->sysclk = 13000000;
238 break;
239 case PXA_SSP_CLK_EXT:
240 priv->sysclk = freq;
241 sscr0 |= SSCR0_ECS;
242 break;
243 case PXA_SSP_CLK_NET:
244 priv->sysclk = freq;
245 sscr0 |= SSCR0_NCS | SSCR0_MOD;
246 break;
247 case PXA_SSP_CLK_AUDIO:
248 priv->sysclk = 0;
249 pxa_ssp_set_scr(ssp, 1);
250 sscr0 |= SSCR0_ACS;
251 break;
252 default:
253 return -ENODEV;
254 }
255
256 /* The SSP clock must be disabled when changing SSP clock mode
257 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
258 if (ssp->type != PXA3xx_SSP)
259 clk_disable_unprepare(ssp->clk);
260 val = pxa_ssp_read_reg(ssp, SSCR0) | sscr0;
261 pxa_ssp_write_reg(ssp, SSCR0, val);
262 if (ssp->type != PXA3xx_SSP)
263 clk_prepare_enable(ssp->clk);
264
265 return 0;
266 }
267
268 /*
269 * Set the SSP clock dividers.
270 */
271 static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
272 int div_id, int div)
273 {
274 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
275 struct ssp_device *ssp = priv->ssp;
276 int val;
277
278 switch (div_id) {
279 case PXA_SSP_AUDIO_DIV_ACDS:
280 val = (pxa_ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
281 pxa_ssp_write_reg(ssp, SSACD, val);
282 break;
283 case PXA_SSP_AUDIO_DIV_SCDB:
284 val = pxa_ssp_read_reg(ssp, SSACD);
285 val &= ~SSACD_SCDB;
286 if (ssp->type == PXA3xx_SSP)
287 val &= ~SSACD_SCDX8;
288 switch (div) {
289 case PXA_SSP_CLK_SCDB_1:
290 val |= SSACD_SCDB;
291 break;
292 case PXA_SSP_CLK_SCDB_4:
293 break;
294 case PXA_SSP_CLK_SCDB_8:
295 if (ssp->type == PXA3xx_SSP)
296 val |= SSACD_SCDX8;
297 else
298 return -EINVAL;
299 break;
300 default:
301 return -EINVAL;
302 }
303 pxa_ssp_write_reg(ssp, SSACD, val);
304 break;
305 case PXA_SSP_DIV_SCR:
306 pxa_ssp_set_scr(ssp, div);
307 break;
308 default:
309 return -ENODEV;
310 }
311
312 return 0;
313 }
314
315 /*
316 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
317 */
318 static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
319 int source, unsigned int freq_in, unsigned int freq_out)
320 {
321 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
322 struct ssp_device *ssp = priv->ssp;
323 u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;
324
325 if (ssp->type == PXA3xx_SSP)
326 pxa_ssp_write_reg(ssp, SSACDD, 0);
327
328 switch (freq_out) {
329 case 5622000:
330 break;
331 case 11345000:
332 ssacd |= (0x1 << 4);
333 break;
334 case 12235000:
335 ssacd |= (0x2 << 4);
336 break;
337 case 14857000:
338 ssacd |= (0x3 << 4);
339 break;
340 case 32842000:
341 ssacd |= (0x4 << 4);
342 break;
343 case 48000000:
344 ssacd |= (0x5 << 4);
345 break;
346 case 0:
347 /* Disable */
348 break;
349
350 default:
351 /* PXA3xx has a clock ditherer which can be used to generate
352 * a wider range of frequencies - calculate a value for it.
353 */
354 if (ssp->type == PXA3xx_SSP) {
355 u32 val;
356 u64 tmp = 19968;
357
358 tmp *= 1000000;
359 do_div(tmp, freq_out);
360 val = tmp;
361
362 val = (val << 16) | 64;
363 pxa_ssp_write_reg(ssp, SSACDD, val);
364
365 ssacd |= (0x6 << 4);
366
367 dev_dbg(&ssp->pdev->dev,
368 "Using SSACDD %x to supply %uHz\n",
369 val, freq_out);
370 break;
371 }
372
373 return -EINVAL;
374 }
375
376 pxa_ssp_write_reg(ssp, SSACD, ssacd);
377
378 return 0;
379 }
380
381 /*
382 * Set the active slots in TDM/Network mode
383 */
384 static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
385 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
386 {
387 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
388 struct ssp_device *ssp = priv->ssp;
389 u32 sscr0;
390
391 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
392 sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
393
394 /* set slot width */
395 if (slot_width > 16)
396 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
397 else
398 sscr0 |= SSCR0_DataSize(slot_width);
399
400 if (slots > 1) {
401 /* enable network mode */
402 sscr0 |= SSCR0_MOD;
403
404 /* set number of active slots */
405 sscr0 |= SSCR0_SlotsPerFrm(slots);
406
407 /* set active slot mask */
408 pxa_ssp_write_reg(ssp, SSTSA, tx_mask);
409 pxa_ssp_write_reg(ssp, SSRSA, rx_mask);
410 }
411 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
412
413 return 0;
414 }
415
416 /*
417 * Tristate the SSP DAI lines
418 */
419 static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
420 int tristate)
421 {
422 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
423 struct ssp_device *ssp = priv->ssp;
424 u32 sscr1;
425
426 sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
427 if (tristate)
428 sscr1 &= ~SSCR1_TTE;
429 else
430 sscr1 |= SSCR1_TTE;
431 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
432
433 return 0;
434 }
435
436 /*
437 * Set up the SSP DAI format.
438 * The SSP Port must be inactive before calling this function as the
439 * physical interface format is changed.
440 */
441 static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
442 unsigned int fmt)
443 {
444 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
445 struct ssp_device *ssp = priv->ssp;
446 u32 sscr0, sscr1, sspsp, scfr;
447
448 /* check if we need to change anything at all */
449 if (priv->dai_fmt == fmt)
450 return 0;
451
452 /* we can only change the settings if the port is not in use */
453 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) {
454 dev_err(&ssp->pdev->dev,
455 "can't change hardware dai format: stream is in use");
456 return -EINVAL;
457 }
458
459 /* reset port settings */
460 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
461 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
462 sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
463 sspsp = 0;
464
465 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
466 case SND_SOC_DAIFMT_CBM_CFM:
467 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR;
468 break;
469 case SND_SOC_DAIFMT_CBM_CFS:
470 sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR;
471 break;
472 case SND_SOC_DAIFMT_CBS_CFS:
473 break;
474 default:
475 return -EINVAL;
476 }
477
478 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
479 case SND_SOC_DAIFMT_NB_NF:
480 sspsp |= SSPSP_SFRMP;
481 break;
482 case SND_SOC_DAIFMT_NB_IF:
483 break;
484 case SND_SOC_DAIFMT_IB_IF:
485 sspsp |= SSPSP_SCMODE(2);
486 break;
487 case SND_SOC_DAIFMT_IB_NF:
488 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
489 break;
490 default:
491 return -EINVAL;
492 }
493
494 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
495 case SND_SOC_DAIFMT_I2S:
496 sscr0 |= SSCR0_PSP;
497 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
498 /* See hw_params() */
499 break;
500
501 case SND_SOC_DAIFMT_DSP_A:
502 sspsp |= SSPSP_FSRT;
503 case SND_SOC_DAIFMT_DSP_B:
504 sscr0 |= SSCR0_MOD | SSCR0_PSP;
505 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
506 break;
507
508 default:
509 return -EINVAL;
510 }
511
512 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
513 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
514 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
515
516 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
517 case SND_SOC_DAIFMT_CBM_CFM:
518 case SND_SOC_DAIFMT_CBM_CFS:
519 scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR;
520 pxa_ssp_write_reg(ssp, SSCR1, scfr);
521
522 while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY)
523 cpu_relax();
524 break;
525 }
526
527 dump_registers(ssp);
528
529 /* Since we are configuring the timings for the format by hand
530 * we have to defer some things until hw_params() where we
531 * know parameters like the sample size.
532 */
533 priv->dai_fmt = fmt;
534
535 return 0;
536 }
537
538 /*
539 * Set the SSP audio DMA parameters and sample size.
540 * Can be called multiple times by oss emulation.
541 */
542 static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
543 struct snd_pcm_hw_params *params,
544 struct snd_soc_dai *cpu_dai)
545 {
546 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
547 struct ssp_device *ssp = priv->ssp;
548 int chn = params_channels(params);
549 u32 sscr0;
550 u32 sspsp;
551 int width = snd_pcm_format_physical_width(params_format(params));
552 int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf;
553 struct snd_dmaengine_dai_dma_data *dma_data;
554
555 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
556
557 /* Network mode with one active slot (ttsa == 1) can be used
558 * to force 16-bit frame width on the wire (for S16_LE), even
559 * with two channels. Use 16-bit DMA transfers for this case.
560 */
561 pxa_ssp_set_dma_params(ssp,
562 ((chn == 2) && (ttsa != 1)) || (width == 32),
563 substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data);
564
565 /* we can only change the settings if the port is not in use */
566 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
567 return 0;
568
569 /* clear selected SSP bits */
570 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
571
572 /* bit size */
573 switch (params_format(params)) {
574 case SNDRV_PCM_FORMAT_S16_LE:
575 if (ssp->type == PXA3xx_SSP)
576 sscr0 |= SSCR0_FPCKE;
577 sscr0 |= SSCR0_DataSize(16);
578 break;
579 case SNDRV_PCM_FORMAT_S24_LE:
580 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
581 break;
582 case SNDRV_PCM_FORMAT_S32_LE:
583 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
584 break;
585 }
586 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
587
588 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
589 case SND_SOC_DAIFMT_I2S:
590 sspsp = pxa_ssp_read_reg(ssp, SSPSP);
591
592 if ((pxa_ssp_get_scr(ssp) == 4) && (width == 16)) {
593 /* This is a special case where the bitclk is 64fs
594 * and we're not dealing with 2*32 bits of audio
595 * samples.
596 *
597 * The SSP values used for that are all found out by
598 * trying and failing a lot; some of the registers
599 * needed for that mode are only available on PXA3xx.
600 */
601 if (ssp->type != PXA3xx_SSP)
602 return -EINVAL;
603
604 sspsp |= SSPSP_SFRMWDTH(width * 2);
605 sspsp |= SSPSP_SFRMDLY(width * 4);
606 sspsp |= SSPSP_EDMYSTOP(3);
607 sspsp |= SSPSP_DMYSTOP(3);
608 sspsp |= SSPSP_DMYSTRT(1);
609 } else {
610 /* The frame width is the width the LRCLK is
611 * asserted for; the delay is expressed in
612 * half cycle units. We need the extra cycle
613 * because the data starts clocking out one BCLK
614 * after LRCLK changes polarity.
615 */
616 sspsp |= SSPSP_SFRMWDTH(width + 1);
617 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
618 sspsp |= SSPSP_DMYSTRT(1);
619 }
620
621 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
622 break;
623 default:
624 break;
625 }
626
627 /* When we use a network mode, we always require TDM slots
628 * - complain loudly and fail if they've not been set up yet.
629 */
630 if ((sscr0 & SSCR0_MOD) && !ttsa) {
631 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
632 return -EINVAL;
633 }
634
635 dump_registers(ssp);
636
637 return 0;
638 }
639
640 static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream,
641 struct ssp_device *ssp, int value)
642 {
643 uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
644 uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
645 uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP);
646 uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR);
647
648 if (value && (sscr0 & SSCR0_SSE))
649 pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE);
650
651 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
652 if (value)
653 sscr1 |= SSCR1_TSRE;
654 else
655 sscr1 &= ~SSCR1_TSRE;
656 } else {
657 if (value)
658 sscr1 |= SSCR1_RSRE;
659 else
660 sscr1 &= ~SSCR1_RSRE;
661 }
662
663 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
664
665 if (value) {
666 pxa_ssp_write_reg(ssp, SSSR, sssr);
667 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
668 pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE);
669 }
670 }
671
672 static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
673 struct snd_soc_dai *cpu_dai)
674 {
675 int ret = 0;
676 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
677 struct ssp_device *ssp = priv->ssp;
678 int val;
679
680 switch (cmd) {
681 case SNDRV_PCM_TRIGGER_RESUME:
682 pxa_ssp_enable(ssp);
683 break;
684 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
685 pxa_ssp_set_running_bit(substream, ssp, 1);
686 val = pxa_ssp_read_reg(ssp, SSSR);
687 pxa_ssp_write_reg(ssp, SSSR, val);
688 break;
689 case SNDRV_PCM_TRIGGER_START:
690 pxa_ssp_set_running_bit(substream, ssp, 1);
691 break;
692 case SNDRV_PCM_TRIGGER_STOP:
693 pxa_ssp_set_running_bit(substream, ssp, 0);
694 break;
695 case SNDRV_PCM_TRIGGER_SUSPEND:
696 pxa_ssp_disable(ssp);
697 break;
698 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
699 pxa_ssp_set_running_bit(substream, ssp, 0);
700 break;
701
702 default:
703 ret = -EINVAL;
704 }
705
706 dump_registers(ssp);
707
708 return ret;
709 }
710
711 static int pxa_ssp_probe(struct snd_soc_dai *dai)
712 {
713 struct device *dev = dai->dev;
714 struct ssp_priv *priv;
715 int ret;
716
717 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
718 if (!priv)
719 return -ENOMEM;
720
721 if (dev->of_node) {
722 struct device_node *ssp_handle;
723
724 ssp_handle = of_parse_phandle(dev->of_node, "port", 0);
725 if (!ssp_handle) {
726 dev_err(dev, "unable to get 'port' phandle\n");
727 ret = -ENODEV;
728 goto err_priv;
729 }
730
731 priv->ssp = pxa_ssp_request_of(ssp_handle, "SoC audio");
732 if (priv->ssp == NULL) {
733 ret = -ENODEV;
734 goto err_priv;
735 }
736 } else {
737 priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio");
738 if (priv->ssp == NULL) {
739 ret = -ENODEV;
740 goto err_priv;
741 }
742 }
743
744 priv->dai_fmt = (unsigned int) -1;
745 snd_soc_dai_set_drvdata(dai, priv);
746
747 return 0;
748
749 err_priv:
750 kfree(priv);
751 return ret;
752 }
753
754 static int pxa_ssp_remove(struct snd_soc_dai *dai)
755 {
756 struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai);
757
758 pxa_ssp_free(priv->ssp);
759 kfree(priv);
760 return 0;
761 }
762
763 #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
764 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
765 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
766 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
767 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
768
769 #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
770
771 static const struct snd_soc_dai_ops pxa_ssp_dai_ops = {
772 .startup = pxa_ssp_startup,
773 .shutdown = pxa_ssp_shutdown,
774 .trigger = pxa_ssp_trigger,
775 .hw_params = pxa_ssp_hw_params,
776 .set_sysclk = pxa_ssp_set_dai_sysclk,
777 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
778 .set_pll = pxa_ssp_set_dai_pll,
779 .set_fmt = pxa_ssp_set_dai_fmt,
780 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
781 .set_tristate = pxa_ssp_set_dai_tristate,
782 };
783
784 static struct snd_soc_dai_driver pxa_ssp_dai = {
785 .probe = pxa_ssp_probe,
786 .remove = pxa_ssp_remove,
787 .suspend = pxa_ssp_suspend,
788 .resume = pxa_ssp_resume,
789 .playback = {
790 .channels_min = 1,
791 .channels_max = 8,
792 .rates = PXA_SSP_RATES,
793 .formats = PXA_SSP_FORMATS,
794 },
795 .capture = {
796 .channels_min = 1,
797 .channels_max = 8,
798 .rates = PXA_SSP_RATES,
799 .formats = PXA_SSP_FORMATS,
800 },
801 .ops = &pxa_ssp_dai_ops,
802 };
803
804 static const struct snd_soc_component_driver pxa_ssp_component = {
805 .name = "pxa-ssp",
806 };
807
808 #ifdef CONFIG_OF
809 static const struct of_device_id pxa_ssp_of_ids[] = {
810 { .compatible = "mrvl,pxa-ssp-dai" },
811 {}
812 };
813 MODULE_DEVICE_TABLE(of, pxa_ssp_of_ids);
814 #endif
815
816 static int asoc_ssp_probe(struct platform_device *pdev)
817 {
818 return devm_snd_soc_register_component(&pdev->dev, &pxa_ssp_component,
819 &pxa_ssp_dai, 1);
820 }
821
822 static struct platform_driver asoc_ssp_driver = {
823 .driver = {
824 .name = "pxa-ssp-dai",
825 .of_match_table = of_match_ptr(pxa_ssp_of_ids),
826 },
827
828 .probe = asoc_ssp_probe,
829 };
830
831 module_platform_driver(asoc_ssp_driver);
832
833 /* Module information */
834 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
835 MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
836 MODULE_LICENSE("GPL");
837 MODULE_ALIAS("platform:pxa-ssp-dai");
CRIS linux kernel tree