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lib/interval-tree: correct comment wrt generic flavor
[cris-mirror.git] / drivers / usb / chipidea / core.c
blob43ea5fb87b9a8e9493ae38d5a0352f5920fc5d8f
1 /*
2 * core.c - ChipIdea USB IP core family device controller
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 /*
14 * Description: ChipIdea USB IP core family device controller
15 *
16 * This driver is composed of several blocks:
17 * - HW: hardware interface
18 * - DBG: debug facilities (optional)
19 * - UTIL: utilities
20 * - ISR: interrupts handling
21 * - ENDPT: endpoint operations (Gadget API)
22 * - GADGET: gadget operations (Gadget API)
23 * - BUS: bus glue code, bus abstraction layer
24 *
25 * Compile Options
26 * - STALL_IN: non-empty bulk-in pipes cannot be halted
27 * if defined mass storage compliance succeeds but with warnings
28 * => case 4: Hi > Dn
29 * => case 5: Hi > Di
30 * => case 8: Hi <> Do
31 * if undefined usbtest 13 fails
32 * - TRACE: enable function tracing (depends on DEBUG)
33 *
34 * Main Features
35 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
36 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
37 * - Normal & LPM support
38 *
39 * USBTEST Report
40 * - OK: 0-12, 13 (STALL_IN defined) & 14
41 * - Not Supported: 15 & 16 (ISO)
42 *
43 * TODO List
44 * - Suspend & Remote Wakeup
45 */
46 #include <linux/delay.h>
47 #include <linux/device.h>
48 #include <linux/dma-mapping.h>
49 #include <linux/extcon.h>
50 #include <linux/phy/phy.h>
51 #include <linux/platform_device.h>
52 #include <linux/module.h>
53 #include <linux/idr.h>
54 #include <linux/interrupt.h>
55 #include <linux/io.h>
56 #include <linux/kernel.h>
57 #include <linux/slab.h>
58 #include <linux/pm_runtime.h>
59 #include <linux/usb/ch9.h>
60 #include <linux/usb/gadget.h>
61 #include <linux/usb/otg.h>
62 #include <linux/usb/chipidea.h>
63 #include <linux/usb/of.h>
64 #include <linux/of.h>
65 #include <linux/regulator/consumer.h>
66 #include <linux/usb/ehci_def.h>
67
68 #include "ci.h"
69 #include "udc.h"
70 #include "bits.h"
71 #include "host.h"
72 #include "otg.h"
73 #include "otg_fsm.h"
74
75 /* Controller register map */
76 static const u8 ci_regs_nolpm[] = {
77 [CAP_CAPLENGTH] = 0x00U,
78 [CAP_HCCPARAMS] = 0x08U,
79 [CAP_DCCPARAMS] = 0x24U,
80 [CAP_TESTMODE] = 0x38U,
81 [OP_USBCMD] = 0x00U,
82 [OP_USBSTS] = 0x04U,
83 [OP_USBINTR] = 0x08U,
84 [OP_DEVICEADDR] = 0x14U,
85 [OP_ENDPTLISTADDR] = 0x18U,
86 [OP_TTCTRL] = 0x1CU,
87 [OP_BURSTSIZE] = 0x20U,
88 [OP_ULPI_VIEWPORT] = 0x30U,
89 [OP_PORTSC] = 0x44U,
90 [OP_DEVLC] = 0x84U,
91 [OP_OTGSC] = 0x64U,
92 [OP_USBMODE] = 0x68U,
93 [OP_ENDPTSETUPSTAT] = 0x6CU,
94 [OP_ENDPTPRIME] = 0x70U,
95 [OP_ENDPTFLUSH] = 0x74U,
96 [OP_ENDPTSTAT] = 0x78U,
97 [OP_ENDPTCOMPLETE] = 0x7CU,
98 [OP_ENDPTCTRL] = 0x80U,
99 };
100
101 static const u8 ci_regs_lpm[] = {
102 [CAP_CAPLENGTH] = 0x00U,
103 [CAP_HCCPARAMS] = 0x08U,
104 [CAP_DCCPARAMS] = 0x24U,
105 [CAP_TESTMODE] = 0xFCU,
106 [OP_USBCMD] = 0x00U,
107 [OP_USBSTS] = 0x04U,
108 [OP_USBINTR] = 0x08U,
109 [OP_DEVICEADDR] = 0x14U,
110 [OP_ENDPTLISTADDR] = 0x18U,
111 [OP_TTCTRL] = 0x1CU,
112 [OP_BURSTSIZE] = 0x20U,
113 [OP_ULPI_VIEWPORT] = 0x30U,
114 [OP_PORTSC] = 0x44U,
115 [OP_DEVLC] = 0x84U,
116 [OP_OTGSC] = 0xC4U,
117 [OP_USBMODE] = 0xC8U,
118 [OP_ENDPTSETUPSTAT] = 0xD8U,
119 [OP_ENDPTPRIME] = 0xDCU,
120 [OP_ENDPTFLUSH] = 0xE0U,
121 [OP_ENDPTSTAT] = 0xE4U,
122 [OP_ENDPTCOMPLETE] = 0xE8U,
123 [OP_ENDPTCTRL] = 0xECU,
124 };
125
126 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
127 {
128 int i;
129
130 for (i = 0; i < OP_ENDPTCTRL; i++)
131 ci->hw_bank.regmap[i] =
132 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
133 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
134
135 for (; i <= OP_LAST; i++)
136 ci->hw_bank.regmap[i] = ci->hw_bank.op +
137 4 * (i - OP_ENDPTCTRL) +
138 (is_lpm
139 ? ci_regs_lpm[OP_ENDPTCTRL]
140 : ci_regs_nolpm[OP_ENDPTCTRL]);
141
142 }
143
144 static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
145 {
146 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
147 enum ci_revision rev = CI_REVISION_UNKNOWN;
148
149 if (ver == 0x2) {
150 rev = hw_read_id_reg(ci, ID_ID, REVISION)
151 >> __ffs(REVISION);
152 rev += CI_REVISION_20;
153 } else if (ver == 0x0) {
154 rev = CI_REVISION_1X;
155 }
156
157 return rev;
158 }
159
160 /**
161 * hw_read_intr_enable: returns interrupt enable register
162 *
163 * @ci: the controller
164 *
165 * This function returns register data
166 */
167 u32 hw_read_intr_enable(struct ci_hdrc *ci)
168 {
169 return hw_read(ci, OP_USBINTR, ~0);
170 }
171
172 /**
173 * hw_read_intr_status: returns interrupt status register
174 *
175 * @ci: the controller
176 *
177 * This function returns register data
178 */
179 u32 hw_read_intr_status(struct ci_hdrc *ci)
180 {
181 return hw_read(ci, OP_USBSTS, ~0);
182 }
183
184 /**
185 * hw_port_test_set: writes port test mode (execute without interruption)
186 * @mode: new value
187 *
188 * This function returns an error code
189 */
190 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
191 {
192 const u8 TEST_MODE_MAX = 7;
193
194 if (mode > TEST_MODE_MAX)
195 return -EINVAL;
196
197 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
198 return 0;
199 }
200
201 /**
202 * hw_port_test_get: reads port test mode value
203 *
204 * @ci: the controller
205 *
206 * This function returns port test mode value
207 */
208 u8 hw_port_test_get(struct ci_hdrc *ci)
209 {
210 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
211 }
212
213 static void hw_wait_phy_stable(void)
214 {
215 /*
216 * The phy needs some delay to output the stable status from low
217 * power mode. And for OTGSC, the status inputs are debounced
218 * using a 1 ms time constant, so, delay 2ms for controller to get
219 * the stable status, like vbus and id when the phy leaves low power.
220 */
221 usleep_range(2000, 2500);
222 }
223
224 /* The PHY enters/leaves low power mode */
225 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
226 {
227 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
228 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
229
230 if (enable && !lpm)
231 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
232 PORTSC_PHCD(ci->hw_bank.lpm));
233 else if (!enable && lpm)
234 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
235 0);
236 }
237
238 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
239 {
240 u32 reg;
241
242 /* bank is a module variable */
243 ci->hw_bank.abs = base;
244
245 ci->hw_bank.cap = ci->hw_bank.abs;
246 ci->hw_bank.cap += ci->platdata->capoffset;
247 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
248
249 hw_alloc_regmap(ci, false);
250 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
251 __ffs(HCCPARAMS_LEN);
252 ci->hw_bank.lpm = reg;
253 if (reg)
254 hw_alloc_regmap(ci, !!reg);
255 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
256 ci->hw_bank.size += OP_LAST;
257 ci->hw_bank.size /= sizeof(u32);
258
259 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
260 __ffs(DCCPARAMS_DEN);
261 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
262
263 if (ci->hw_ep_max > ENDPT_MAX)
264 return -ENODEV;
265
266 ci_hdrc_enter_lpm(ci, false);
267
268 /* Disable all interrupts bits */
269 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
270
271 /* Clear all interrupts status bits*/
272 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
273
274 ci->rev = ci_get_revision(ci);
275
276 dev_dbg(ci->dev,
277 "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n",
278 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
279
280 /* setup lock mode ? */
281
282 /* ENDPTSETUPSTAT is '0' by default */
283
284 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
285
286 return 0;
287 }
288
289 void hw_phymode_configure(struct ci_hdrc *ci)
290 {
291 u32 portsc, lpm, sts = 0;
292
293 switch (ci->platdata->phy_mode) {
294 case USBPHY_INTERFACE_MODE_UTMI:
295 portsc = PORTSC_PTS(PTS_UTMI);
296 lpm = DEVLC_PTS(PTS_UTMI);
297 break;
298 case USBPHY_INTERFACE_MODE_UTMIW:
299 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
300 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
301 break;
302 case USBPHY_INTERFACE_MODE_ULPI:
303 portsc = PORTSC_PTS(PTS_ULPI);
304 lpm = DEVLC_PTS(PTS_ULPI);
305 break;
306 case USBPHY_INTERFACE_MODE_SERIAL:
307 portsc = PORTSC_PTS(PTS_SERIAL);
308 lpm = DEVLC_PTS(PTS_SERIAL);
309 sts = 1;
310 break;
311 case USBPHY_INTERFACE_MODE_HSIC:
312 portsc = PORTSC_PTS(PTS_HSIC);
313 lpm = DEVLC_PTS(PTS_HSIC);
314 break;
315 default:
316 return;
317 }
318
319 if (ci->hw_bank.lpm) {
320 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
321 if (sts)
322 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
323 } else {
324 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
325 if (sts)
326 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
327 }
328 }
329 EXPORT_SYMBOL_GPL(hw_phymode_configure);
330
331 /**
332 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
333 * interfaces
334 * @ci: the controller
335 *
336 * This function returns an error code if the phy failed to init
337 */
338 static int _ci_usb_phy_init(struct ci_hdrc *ci)
339 {
340 int ret;
341
342 if (ci->phy) {
343 ret = phy_init(ci->phy);
344 if (ret)
345 return ret;
346
347 ret = phy_power_on(ci->phy);
348 if (ret) {
349 phy_exit(ci->phy);
350 return ret;
351 }
352 } else {
353 ret = usb_phy_init(ci->usb_phy);
354 }
355
356 return ret;
357 }
358
359 /**
360 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
361 * interfaces
362 * @ci: the controller
363 */
364 static void ci_usb_phy_exit(struct ci_hdrc *ci)
365 {
366 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
367 return;
368
369 if (ci->phy) {
370 phy_power_off(ci->phy);
371 phy_exit(ci->phy);
372 } else {
373 usb_phy_shutdown(ci->usb_phy);
374 }
375 }
376
377 /**
378 * ci_usb_phy_init: initialize phy according to different phy type
379 * @ci: the controller
380 *
381 * This function returns an error code if usb_phy_init has failed
382 */
383 static int ci_usb_phy_init(struct ci_hdrc *ci)
384 {
385 int ret;
386
387 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
388 return 0;
389
390 switch (ci->platdata->phy_mode) {
391 case USBPHY_INTERFACE_MODE_UTMI:
392 case USBPHY_INTERFACE_MODE_UTMIW:
393 case USBPHY_INTERFACE_MODE_HSIC:
394 ret = _ci_usb_phy_init(ci);
395 if (!ret)
396 hw_wait_phy_stable();
397 else
398 return ret;
399 hw_phymode_configure(ci);
400 break;
401 case USBPHY_INTERFACE_MODE_ULPI:
402 case USBPHY_INTERFACE_MODE_SERIAL:
403 hw_phymode_configure(ci);
404 ret = _ci_usb_phy_init(ci);
405 if (ret)
406 return ret;
407 break;
408 default:
409 ret = _ci_usb_phy_init(ci);
410 if (!ret)
411 hw_wait_phy_stable();
412 }
413
414 return ret;
415 }
416
417
418 /**
419 * ci_platform_configure: do controller configure
420 * @ci: the controller
421 *
422 */
423 void ci_platform_configure(struct ci_hdrc *ci)
424 {
425 bool is_device_mode, is_host_mode;
426
427 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
428 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
429
430 if (is_device_mode) {
431 phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE);
432
433 if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
434 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
435 USBMODE_CI_SDIS);
436 }
437
438 if (is_host_mode) {
439 phy_set_mode(ci->phy, PHY_MODE_USB_HOST);
440
441 if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
442 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
443 USBMODE_CI_SDIS);
444 }
445
446 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
447 if (ci->hw_bank.lpm)
448 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
449 else
450 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
451 }
452
453 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
454 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
455
456 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
457
458 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
459 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
460 ci->platdata->ahb_burst_config);
461
462 /* override burst size, take effect only when ahb_burst_config is 0 */
463 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
464 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
465 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
466 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
467
468 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
469 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
470 ci->platdata->rx_burst_size);
471 }
472 }
473
474 /**
475 * hw_controller_reset: do controller reset
476 * @ci: the controller
477 *
478 * This function returns an error code
479 */
480 static int hw_controller_reset(struct ci_hdrc *ci)
481 {
482 int count = 0;
483
484 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
485 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
486 udelay(10);
487 if (count++ > 1000)
488 return -ETIMEDOUT;
489 }
490
491 return 0;
492 }
493
494 /**
495 * hw_device_reset: resets chip (execute without interruption)
496 * @ci: the controller
497 *
498 * This function returns an error code
499 */
500 int hw_device_reset(struct ci_hdrc *ci)
501 {
502 int ret;
503
504 /* should flush & stop before reset */
505 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
506 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
507
508 ret = hw_controller_reset(ci);
509 if (ret) {
510 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
511 return ret;
512 }
513
514 if (ci->platdata->notify_event) {
515 ret = ci->platdata->notify_event(ci,
516 CI_HDRC_CONTROLLER_RESET_EVENT);
517 if (ret)
518 return ret;
519 }
520
521 /* USBMODE should be configured step by step */
522 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
523 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
524 /* HW >= 2.3 */
525 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
526
527 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
528 pr_err("cannot enter in %s device mode", ci_role(ci)->name);
529 pr_err("lpm = %i", ci->hw_bank.lpm);
530 return -ENODEV;
531 }
532
533 ci_platform_configure(ci);
534
535 return 0;
536 }
537
538 static irqreturn_t ci_irq(int irq, void *data)
539 {
540 struct ci_hdrc *ci = data;
541 irqreturn_t ret = IRQ_NONE;
542 u32 otgsc = 0;
543
544 if (ci->in_lpm) {
545 disable_irq_nosync(irq);
546 ci->wakeup_int = true;
547 pm_runtime_get(ci->dev);
548 return IRQ_HANDLED;
549 }
550
551 if (ci->is_otg) {
552 otgsc = hw_read_otgsc(ci, ~0);
553 if (ci_otg_is_fsm_mode(ci)) {
554 ret = ci_otg_fsm_irq(ci);
555 if (ret == IRQ_HANDLED)
556 return ret;
557 }
558 }
559
560 /*
561 * Handle id change interrupt, it indicates device/host function
562 * switch.
563 */
564 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
565 ci->id_event = true;
566 /* Clear ID change irq status */
567 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
568 ci_otg_queue_work(ci);
569 return IRQ_HANDLED;
570 }
571
572 /*
573 * Handle vbus change interrupt, it indicates device connection
574 * and disconnection events.
575 */
576 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
577 ci->b_sess_valid_event = true;
578 /* Clear BSV irq */
579 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
580 ci_otg_queue_work(ci);
581 return IRQ_HANDLED;
582 }
583
584 /* Handle device/host interrupt */
585 if (ci->role != CI_ROLE_END)
586 ret = ci_role(ci)->irq(ci);
587
588 return ret;
589 }
590
591 static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
592 void *ptr)
593 {
594 struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
595 struct ci_hdrc *ci = cbl->ci;
596
597 cbl->connected = event;
598 cbl->changed = true;
599
600 ci_irq(ci->irq, ci);
601 return NOTIFY_DONE;
602 }
603
604 static int ci_get_platdata(struct device *dev,
605 struct ci_hdrc_platform_data *platdata)
606 {
607 struct extcon_dev *ext_vbus, *ext_id;
608 struct ci_hdrc_cable *cable;
609 int ret;
610
611 if (!platdata->phy_mode)
612 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
613
614 if (!platdata->dr_mode)
615 platdata->dr_mode = usb_get_dr_mode(dev);
616
617 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
618 platdata->dr_mode = USB_DR_MODE_OTG;
619
620 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
621 /* Get the vbus regulator */
622 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
623 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
624 return -EPROBE_DEFER;
625 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
626 /* no vbus regulator is needed */
627 platdata->reg_vbus = NULL;
628 } else if (IS_ERR(platdata->reg_vbus)) {
629 dev_err(dev, "Getting regulator error: %ld\n",
630 PTR_ERR(platdata->reg_vbus));
631 return PTR_ERR(platdata->reg_vbus);
632 }
633 /* Get TPL support */
634 if (!platdata->tpl_support)
635 platdata->tpl_support =
636 of_usb_host_tpl_support(dev->of_node);
637 }
638
639 if (platdata->dr_mode == USB_DR_MODE_OTG) {
640 /* We can support HNP and SRP of OTG 2.0 */
641 platdata->ci_otg_caps.otg_rev = 0x0200;
642 platdata->ci_otg_caps.hnp_support = true;
643 platdata->ci_otg_caps.srp_support = true;
644
645 /* Update otg capabilities by DT properties */
646 ret = of_usb_update_otg_caps(dev->of_node,
647 &platdata->ci_otg_caps);
648 if (ret)
649 return ret;
650 }
651
652 if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
653 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
654
655 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
656 &platdata->phy_clkgate_delay_us);
657
658 platdata->itc_setting = 1;
659
660 of_property_read_u32(dev->of_node, "itc-setting",
661 &platdata->itc_setting);
662
663 ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
664 &platdata->ahb_burst_config);
665 if (!ret) {
666 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
667 } else if (ret != -EINVAL) {
668 dev_err(dev, "failed to get ahb-burst-config\n");
669 return ret;
670 }
671
672 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
673 &platdata->tx_burst_size);
674 if (!ret) {
675 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
676 } else if (ret != -EINVAL) {
677 dev_err(dev, "failed to get tx-burst-size-dword\n");
678 return ret;
679 }
680
681 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
682 &platdata->rx_burst_size);
683 if (!ret) {
684 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
685 } else if (ret != -EINVAL) {
686 dev_err(dev, "failed to get rx-burst-size-dword\n");
687 return ret;
688 }
689
690 if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL))
691 platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
692
693 ext_id = ERR_PTR(-ENODEV);
694 ext_vbus = ERR_PTR(-ENODEV);
695 if (of_property_read_bool(dev->of_node, "extcon")) {
696 /* Each one of them is not mandatory */
697 ext_vbus = extcon_get_edev_by_phandle(dev, 0);
698 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
699 return PTR_ERR(ext_vbus);
700
701 ext_id = extcon_get_edev_by_phandle(dev, 1);
702 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
703 return PTR_ERR(ext_id);
704 }
705
706 cable = &platdata->vbus_extcon;
707 cable->nb.notifier_call = ci_cable_notifier;
708 cable->edev = ext_vbus;
709
710 if (!IS_ERR(ext_vbus)) {
711 ret = extcon_get_state(cable->edev, EXTCON_USB);
712 if (ret)
713 cable->connected = true;
714 else
715 cable->connected = false;
716 }
717
718 cable = &platdata->id_extcon;
719 cable->nb.notifier_call = ci_cable_notifier;
720 cable->edev = ext_id;
721
722 if (!IS_ERR(ext_id)) {
723 ret = extcon_get_state(cable->edev, EXTCON_USB_HOST);
724 if (ret)
725 cable->connected = true;
726 else
727 cable->connected = false;
728 }
729 return 0;
730 }
731
732 static int ci_extcon_register(struct ci_hdrc *ci)
733 {
734 struct ci_hdrc_cable *id, *vbus;
735 int ret;
736
737 id = &ci->platdata->id_extcon;
738 id->ci = ci;
739 if (!IS_ERR_OR_NULL(id->edev)) {
740 ret = devm_extcon_register_notifier(ci->dev, id->edev,
741 EXTCON_USB_HOST, &id->nb);
742 if (ret < 0) {
743 dev_err(ci->dev, "register ID failed\n");
744 return ret;
745 }
746 }
747
748 vbus = &ci->platdata->vbus_extcon;
749 vbus->ci = ci;
750 if (!IS_ERR_OR_NULL(vbus->edev)) {
751 ret = devm_extcon_register_notifier(ci->dev, vbus->edev,
752 EXTCON_USB, &vbus->nb);
753 if (ret < 0) {
754 dev_err(ci->dev, "register VBUS failed\n");
755 return ret;
756 }
757 }
758
759 return 0;
760 }
761
762 static DEFINE_IDA(ci_ida);
763
764 struct platform_device *ci_hdrc_add_device(struct device *dev,
765 struct resource *res, int nres,
766 struct ci_hdrc_platform_data *platdata)
767 {
768 struct platform_device *pdev;
769 int id, ret;
770
771 ret = ci_get_platdata(dev, platdata);
772 if (ret)
773 return ERR_PTR(ret);
774
775 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
776 if (id < 0)
777 return ERR_PTR(id);
778
779 pdev = platform_device_alloc("ci_hdrc", id);
780 if (!pdev) {
781 ret = -ENOMEM;
782 goto put_id;
783 }
784
785 pdev->dev.parent = dev;
786
787 ret = platform_device_add_resources(pdev, res, nres);
788 if (ret)
789 goto err;
790
791 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
792 if (ret)
793 goto err;
794
795 ret = platform_device_add(pdev);
796 if (ret)
797 goto err;
798
799 return pdev;
800
801 err:
802 platform_device_put(pdev);
803 put_id:
804 ida_simple_remove(&ci_ida, id);
805 return ERR_PTR(ret);
806 }
807 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
808
809 void ci_hdrc_remove_device(struct platform_device *pdev)
810 {
811 int id = pdev->id;
812 platform_device_unregister(pdev);
813 ida_simple_remove(&ci_ida, id);
814 }
815 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
816
817 static inline void ci_role_destroy(struct ci_hdrc *ci)
818 {
819 ci_hdrc_gadget_destroy(ci);
820 ci_hdrc_host_destroy(ci);
821 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
822 ci_hdrc_otg_destroy(ci);
823 }
824
825 static void ci_get_otg_capable(struct ci_hdrc *ci)
826 {
827 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
828 ci->is_otg = false;
829 else
830 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
831 DCCPARAMS_DC | DCCPARAMS_HC)
832 == (DCCPARAMS_DC | DCCPARAMS_HC));
833 if (ci->is_otg) {
834 dev_dbg(ci->dev, "It is OTG capable controller\n");
835 /* Disable and clear all OTG irq */
836 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
837 OTGSC_INT_STATUS_BITS);
838 }
839 }
840
841 static ssize_t ci_role_show(struct device *dev, struct device_attribute *attr,
842 char *buf)
843 {
844 struct ci_hdrc *ci = dev_get_drvdata(dev);
845
846 if (ci->role != CI_ROLE_END)
847 return sprintf(buf, "%s\n", ci_role(ci)->name);
848
849 return 0;
850 }
851
852 static ssize_t ci_role_store(struct device *dev,
853 struct device_attribute *attr, const char *buf, size_t n)
854 {
855 struct ci_hdrc *ci = dev_get_drvdata(dev);
856 enum ci_role role;
857 int ret;
858
859 if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) {
860 dev_warn(dev, "Current configuration is not dual-role, quit\n");
861 return -EPERM;
862 }
863
864 for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
865 if (!strncmp(buf, ci->roles[role]->name,
866 strlen(ci->roles[role]->name)))
867 break;
868
869 if (role == CI_ROLE_END || role == ci->role)
870 return -EINVAL;
871
872 pm_runtime_get_sync(dev);
873 disable_irq(ci->irq);
874 ci_role_stop(ci);
875 ret = ci_role_start(ci, role);
876 if (!ret && ci->role == CI_ROLE_GADGET)
877 ci_handle_vbus_change(ci);
878 enable_irq(ci->irq);
879 pm_runtime_put_sync(dev);
880
881 return (ret == 0) ? n : ret;
882 }
883 static DEVICE_ATTR(role, 0644, ci_role_show, ci_role_store);
884
885 static struct attribute *ci_attrs[] = {
886 &dev_attr_role.attr,
887 NULL,
888 };
889
890 static const struct attribute_group ci_attr_group = {
891 .attrs = ci_attrs,
892 };
893
894 static int ci_hdrc_probe(struct platform_device *pdev)
895 {
896 struct device *dev = &pdev->dev;
897 struct ci_hdrc *ci;
898 struct resource *res;
899 void __iomem *base;
900 int ret;
901 enum usb_dr_mode dr_mode;
902
903 if (!dev_get_platdata(dev)) {
904 dev_err(dev, "platform data missing\n");
905 return -ENODEV;
906 }
907
908 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
909 base = devm_ioremap_resource(dev, res);
910 if (IS_ERR(base))
911 return PTR_ERR(base);
912
913 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
914 if (!ci)
915 return -ENOMEM;
916
917 spin_lock_init(&ci->lock);
918 ci->dev = dev;
919 ci->platdata = dev_get_platdata(dev);
920 ci->imx28_write_fix = !!(ci->platdata->flags &
921 CI_HDRC_IMX28_WRITE_FIX);
922 ci->supports_runtime_pm = !!(ci->platdata->flags &
923 CI_HDRC_SUPPORTS_RUNTIME_PM);
924 platform_set_drvdata(pdev, ci);
925
926 ret = hw_device_init(ci, base);
927 if (ret < 0) {
928 dev_err(dev, "can't initialize hardware\n");
929 return -ENODEV;
930 }
931
932 ret = ci_ulpi_init(ci);
933 if (ret)
934 return ret;
935
936 if (ci->platdata->phy) {
937 ci->phy = ci->platdata->phy;
938 } else if (ci->platdata->usb_phy) {
939 ci->usb_phy = ci->platdata->usb_phy;
940 } else {
941 ci->phy = devm_phy_get(dev->parent, "usb-phy");
942 ci->usb_phy = devm_usb_get_phy(dev->parent, USB_PHY_TYPE_USB2);
943
944 /* if both generic PHY and USB PHY layers aren't enabled */
945 if (PTR_ERR(ci->phy) == -ENOSYS &&
946 PTR_ERR(ci->usb_phy) == -ENXIO) {
947 ret = -ENXIO;
948 goto ulpi_exit;
949 }
950
951 if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy)) {
952 ret = -EPROBE_DEFER;
953 goto ulpi_exit;
954 }
955
956 if (IS_ERR(ci->phy))
957 ci->phy = NULL;
958 else if (IS_ERR(ci->usb_phy))
959 ci->usb_phy = NULL;
960 }
961
962 ret = ci_usb_phy_init(ci);
963 if (ret) {
964 dev_err(dev, "unable to init phy: %d\n", ret);
965 return ret;
966 }
967
968 ci->hw_bank.phys = res->start;
969
970 ci->irq = platform_get_irq(pdev, 0);
971 if (ci->irq < 0) {
972 dev_err(dev, "missing IRQ\n");
973 ret = ci->irq;
974 goto deinit_phy;
975 }
976
977 ci_get_otg_capable(ci);
978
979 dr_mode = ci->platdata->dr_mode;
980 /* initialize role(s) before the interrupt is requested */
981 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
982 ret = ci_hdrc_host_init(ci);
983 if (ret) {
984 if (ret == -ENXIO)
985 dev_info(dev, "doesn't support host\n");
986 else
987 goto deinit_phy;
988 }
989 }
990
991 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
992 ret = ci_hdrc_gadget_init(ci);
993 if (ret) {
994 if (ret == -ENXIO)
995 dev_info(dev, "doesn't support gadget\n");
996 else
997 goto deinit_host;
998 }
999 }
1000
1001 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
1002 dev_err(dev, "no supported roles\n");
1003 ret = -ENODEV;
1004 goto deinit_gadget;
1005 }
1006
1007 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
1008 ret = ci_hdrc_otg_init(ci);
1009 if (ret) {
1010 dev_err(dev, "init otg fails, ret = %d\n", ret);
1011 goto deinit_gadget;
1012 }
1013 }
1014
1015 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
1016 if (ci->is_otg) {
1017 ci->role = ci_otg_role(ci);
1018 /* Enable ID change irq */
1019 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
1020 } else {
1021 /*
1022 * If the controller is not OTG capable, but support
1023 * role switch, the defalt role is gadget, and the
1024 * user can switch it through debugfs.
1025 */
1026 ci->role = CI_ROLE_GADGET;
1027 }
1028 } else {
1029 ci->role = ci->roles[CI_ROLE_HOST]
1030 ? CI_ROLE_HOST
1031 : CI_ROLE_GADGET;
1032 }
1033
1034 if (!ci_otg_is_fsm_mode(ci)) {
1035 /* only update vbus status for peripheral */
1036 if (ci->role == CI_ROLE_GADGET)
1037 ci_handle_vbus_change(ci);
1038
1039 ret = ci_role_start(ci, ci->role);
1040 if (ret) {
1041 dev_err(dev, "can't start %s role\n",
1042 ci_role(ci)->name);
1043 goto stop;
1044 }
1045 }
1046
1047 ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
1048 ci->platdata->name, ci);
1049 if (ret)
1050 goto stop;
1051
1052 ret = ci_extcon_register(ci);
1053 if (ret)
1054 goto stop;
1055
1056 if (ci->supports_runtime_pm) {
1057 pm_runtime_set_active(&pdev->dev);
1058 pm_runtime_enable(&pdev->dev);
1059 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1060 pm_runtime_mark_last_busy(ci->dev);
1061 pm_runtime_use_autosuspend(&pdev->dev);
1062 }
1063
1064 if (ci_otg_is_fsm_mode(ci))
1065 ci_hdrc_otg_fsm_start(ci);
1066
1067 device_set_wakeup_capable(&pdev->dev, true);
1068 ret = dbg_create_files(ci);
1069 if (ret)
1070 goto stop;
1071
1072 ret = sysfs_create_group(&dev->kobj, &ci_attr_group);
1073 if (ret)
1074 goto remove_debug;
1075
1076 return 0;
1077
1078 remove_debug:
1079 dbg_remove_files(ci);
1080 stop:
1081 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
1082 ci_hdrc_otg_destroy(ci);
1083 deinit_gadget:
1084 ci_hdrc_gadget_destroy(ci);
1085 deinit_host:
1086 ci_hdrc_host_destroy(ci);
1087 deinit_phy:
1088 ci_usb_phy_exit(ci);
1089 ulpi_exit:
1090 ci_ulpi_exit(ci);
1091
1092 return ret;
1093 }
1094
1095 static int ci_hdrc_remove(struct platform_device *pdev)
1096 {
1097 struct ci_hdrc *ci = platform_get_drvdata(pdev);
1098
1099 if (ci->supports_runtime_pm) {
1100 pm_runtime_get_sync(&pdev->dev);
1101 pm_runtime_disable(&pdev->dev);
1102 pm_runtime_put_noidle(&pdev->dev);
1103 }
1104
1105 dbg_remove_files(ci);
1106 sysfs_remove_group(&ci->dev->kobj, &ci_attr_group);
1107 ci_role_destroy(ci);
1108 ci_hdrc_enter_lpm(ci, true);
1109 ci_usb_phy_exit(ci);
1110 ci_ulpi_exit(ci);
1111
1112 return 0;
1113 }
1114
1115 #ifdef CONFIG_PM
1116 /* Prepare wakeup by SRP before suspend */
1117 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1118 {
1119 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1120 !hw_read_otgsc(ci, OTGSC_ID)) {
1121 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1122 PORTSC_PP);
1123 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1124 PORTSC_WKCN);
1125 }
1126 }
1127
1128 /* Handle SRP when wakeup by data pulse */
1129 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1130 {
1131 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1132 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1133 if (!hw_read_otgsc(ci, OTGSC_ID)) {
1134 ci->fsm.a_srp_det = 1;
1135 ci->fsm.a_bus_drop = 0;
1136 } else {
1137 ci->fsm.id = 1;
1138 }
1139 ci_otg_queue_work(ci);
1140 }
1141 }
1142
1143 static void ci_controller_suspend(struct ci_hdrc *ci)
1144 {
1145 disable_irq(ci->irq);
1146 ci_hdrc_enter_lpm(ci, true);
1147 if (ci->platdata->phy_clkgate_delay_us)
1148 usleep_range(ci->platdata->phy_clkgate_delay_us,
1149 ci->platdata->phy_clkgate_delay_us + 50);
1150 usb_phy_set_suspend(ci->usb_phy, 1);
1151 ci->in_lpm = true;
1152 enable_irq(ci->irq);
1153 }
1154
1155 static int ci_controller_resume(struct device *dev)
1156 {
1157 struct ci_hdrc *ci = dev_get_drvdata(dev);
1158 int ret;
1159
1160 dev_dbg(dev, "at %s\n", __func__);
1161
1162 if (!ci->in_lpm) {
1163 WARN_ON(1);
1164 return 0;
1165 }
1166
1167 ci_hdrc_enter_lpm(ci, false);
1168
1169 ret = ci_ulpi_resume(ci);
1170 if (ret)
1171 return ret;
1172
1173 if (ci->usb_phy) {
1174 usb_phy_set_suspend(ci->usb_phy, 0);
1175 usb_phy_set_wakeup(ci->usb_phy, false);
1176 hw_wait_phy_stable();
1177 }
1178
1179 ci->in_lpm = false;
1180 if (ci->wakeup_int) {
1181 ci->wakeup_int = false;
1182 pm_runtime_mark_last_busy(ci->dev);
1183 pm_runtime_put_autosuspend(ci->dev);
1184 enable_irq(ci->irq);
1185 if (ci_otg_is_fsm_mode(ci))
1186 ci_otg_fsm_wakeup_by_srp(ci);
1187 }
1188
1189 return 0;
1190 }
1191
1192 #ifdef CONFIG_PM_SLEEP
1193 static int ci_suspend(struct device *dev)
1194 {
1195 struct ci_hdrc *ci = dev_get_drvdata(dev);
1196
1197 if (ci->wq)
1198 flush_workqueue(ci->wq);
1199 /*
1200 * Controller needs to be active during suspend, otherwise the core
1201 * may run resume when the parent is at suspend if other driver's
1202 * suspend fails, it occurs before parent's suspend has not started,
1203 * but the core suspend has finished.
1204 */
1205 if (ci->in_lpm)
1206 pm_runtime_resume(dev);
1207
1208 if (ci->in_lpm) {
1209 WARN_ON(1);
1210 return 0;
1211 }
1212
1213 if (device_may_wakeup(dev)) {
1214 if (ci_otg_is_fsm_mode(ci))
1215 ci_otg_fsm_suspend_for_srp(ci);
1216
1217 usb_phy_set_wakeup(ci->usb_phy, true);
1218 enable_irq_wake(ci->irq);
1219 }
1220
1221 ci_controller_suspend(ci);
1222
1223 return 0;
1224 }
1225
1226 static int ci_resume(struct device *dev)
1227 {
1228 struct ci_hdrc *ci = dev_get_drvdata(dev);
1229 int ret;
1230
1231 if (device_may_wakeup(dev))
1232 disable_irq_wake(ci->irq);
1233
1234 ret = ci_controller_resume(dev);
1235 if (ret)
1236 return ret;
1237
1238 if (ci->supports_runtime_pm) {
1239 pm_runtime_disable(dev);
1240 pm_runtime_set_active(dev);
1241 pm_runtime_enable(dev);
1242 }
1243
1244 return ret;
1245 }
1246 #endif /* CONFIG_PM_SLEEP */
1247
1248 static int ci_runtime_suspend(struct device *dev)
1249 {
1250 struct ci_hdrc *ci = dev_get_drvdata(dev);
1251
1252 dev_dbg(dev, "at %s\n", __func__);
1253
1254 if (ci->in_lpm) {
1255 WARN_ON(1);
1256 return 0;
1257 }
1258
1259 if (ci_otg_is_fsm_mode(ci))
1260 ci_otg_fsm_suspend_for_srp(ci);
1261
1262 usb_phy_set_wakeup(ci->usb_phy, true);
1263 ci_controller_suspend(ci);
1264
1265 return 0;
1266 }
1267
1268 static int ci_runtime_resume(struct device *dev)
1269 {
1270 return ci_controller_resume(dev);
1271 }
1272
1273 #endif /* CONFIG_PM */
1274 static const struct dev_pm_ops ci_pm_ops = {
1275 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1276 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1277 };
1278
1279 static struct platform_driver ci_hdrc_driver = {
1280 .probe = ci_hdrc_probe,
1281 .remove = ci_hdrc_remove,
1282 .driver = {
1283 .name = "ci_hdrc",
1284 .pm = &ci_pm_ops,
1285 },
1286 };
1287
1288 static int __init ci_hdrc_platform_register(void)
1289 {
1290 ci_hdrc_host_driver_init();
1291 return platform_driver_register(&ci_hdrc_driver);
1292 }
1293 module_init(ci_hdrc_platform_register);
1294
1295 static void __exit ci_hdrc_platform_unregister(void)
1296 {
1297 platform_driver_unregister(&ci_hdrc_driver);
1298 }
1299 module_exit(ci_hdrc_platform_unregister);
1300
1301 MODULE_ALIAS("platform:ci_hdrc");
1302 MODULE_LICENSE("GPL v2");
1303 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
1304 MODULE_DESCRIPTION("ChipIdea HDRC Driver");
CRIS linux kernel tree