arch/i386/kernel/pci-pc.c

   1 /*
   2  *      Low-Level PCI Support for PC
   3  *
   4  *      (c) 1999--2000 Martin Mares <mj@suse.cz>
   5  */
   6
   7 #include <linux/config.h>
   8 #include <linux/types.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/pci.h>
  12 #include <linux/init.h>
  13 #include <linux/ioport.h>
  14
  15 #include <asm/segment.h>
  16 #include <asm/io.h>
  17
  18 #include "pci-i386.h"
  19
  20 unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2;
  21
  22 int pcibios_last_bus = -1;
  23 struct pci_bus *pci_root_bus;
  24 struct pci_ops *pci_root_ops;
  25
  26 /*
  27  * Direct access to PCI hardware...
  28  */
  29
  30 #ifdef CONFIG_PCI_DIRECT
  31
  32 /*
  33  * Functions for accessing PCI configuration space with type 1 accesses
  34  */
  35
  36 #define CONFIG_CMD(dev, where)   (0x80000000 | (dev->bus->number << 16) | (dev->devfn << 8) | (where & ~3))
  37
  38 static int pci_conf1_read_config_byte(struct pci_dev *dev, int where, u8 *value)
  39 {
  40         outl(CONFIG_CMD(dev,where), 0xCF8);
  41         *value = inb(0xCFC + (where&3));
  42         return PCIBIOS_SUCCESSFUL;
  43 }
  44
  45 static int pci_conf1_read_config_word(struct pci_dev *dev, int where, u16 *value)
  46 {
  47         outl(CONFIG_CMD(dev,where), 0xCF8);
  48         *value = inw(0xCFC + (where&2));
  49         return PCIBIOS_SUCCESSFUL;
  50 }
  51
  52 static int pci_conf1_read_config_dword(struct pci_dev *dev, int where, u32 *value)
  53 {
  54         outl(CONFIG_CMD(dev,where), 0xCF8);
  55         *value = inl(0xCFC);
  56         return PCIBIOS_SUCCESSFUL;
  57 }
  58
  59 static int pci_conf1_write_config_byte(struct pci_dev *dev, int where, u8 value)
  60 {
  61         outl(CONFIG_CMD(dev,where), 0xCF8);
  62         outb(value, 0xCFC + (where&3));
  63         return PCIBIOS_SUCCESSFUL;
  64 }
  65
  66 static int pci_conf1_write_config_word(struct pci_dev *dev, int where, u16 value)
  67 {
  68         outl(CONFIG_CMD(dev,where), 0xCF8);
  69         outw(value, 0xCFC + (where&2));
  70         return PCIBIOS_SUCCESSFUL;
  71 }
  72
  73 static int pci_conf1_write_config_dword(struct pci_dev *dev, int where, u32 value)
  74 {
  75         outl(CONFIG_CMD(dev,where), 0xCF8);
  76         outl(value, 0xCFC);
  77         return PCIBIOS_SUCCESSFUL;
  78 }
  79
  80 #undef CONFIG_CMD
  81
  82 static struct pci_ops pci_direct_conf1 = {
  83         pci_conf1_read_config_byte,
  84         pci_conf1_read_config_word,
  85         pci_conf1_read_config_dword,
  86         pci_conf1_write_config_byte,
  87         pci_conf1_write_config_word,
  88         pci_conf1_write_config_dword
  89 };
  90
  91 /*
  92  * Functions for accessing PCI configuration space with type 2 accesses
  93  */
  94
  95 #define IOADDR(devfn, where)    ((0xC000 | ((devfn & 0x78) << 5)) + where)
  96 #define FUNC(devfn)             (((devfn & 7) << 1) | 0xf0)
  97 #define SET(dev)                if (dev->devfn & 0x80) return PCIBIOS_DEVICE_NOT_FOUND;         \
  98                                 outb(FUNC(dev->devfn), 0xCF8);                                  \
  99                                 outb(dev->bus->number, 0xCFA);
 100
 101 static int pci_conf2_read_config_byte(struct pci_dev *dev, int where, u8 *value)
 102 {
 103         SET(dev);
 104         *value = inb(IOADDR(dev->devfn,where));
 105         outb (0, 0xCF8);
 106         return PCIBIOS_SUCCESSFUL;
 107 }
 108
 109 static int pci_conf2_read_config_word(struct pci_dev *dev, int where, u16 *value)
 110 {
 111         SET(dev);
 112         *value = inw(IOADDR(dev->devfn,where));
 113         outb (0, 0xCF8);
 114         return PCIBIOS_SUCCESSFUL;
 115 }
 116
 117 static int pci_conf2_read_config_dword(struct pci_dev *dev, int where, u32 *value)
 118 {
 119         SET(dev);
 120         *value = inl (IOADDR(dev->devfn,where));
 121         outb (0, 0xCF8);
 122         return PCIBIOS_SUCCESSFUL;
 123 }
 124
 125 static int pci_conf2_write_config_byte(struct pci_dev *dev, int where, u8 value)
 126 {
 127         SET(dev);
 128         outb (value, IOADDR(dev->devfn,where));
 129         outb (0, 0xCF8);
 130         return PCIBIOS_SUCCESSFUL;
 131 }
 132
 133 static int pci_conf2_write_config_word(struct pci_dev *dev, int where, u16 value)
 134 {
 135         SET(dev);
 136         outw (value, IOADDR(dev->devfn,where));
 137         outb (0, 0xCF8);
 138         return PCIBIOS_SUCCESSFUL;
 139 }
 140
 141 static int pci_conf2_write_config_dword(struct pci_dev *dev, int where, u32 value)
 142 {
 143         SET(dev);
 144         outl (value, IOADDR(dev->devfn,where));
 145         outb (0, 0xCF8);
 146         return PCIBIOS_SUCCESSFUL;
 147 }
 148
 149 #undef SET
 150 #undef IOADDR
 151 #undef FUNC
 152
 153 static struct pci_ops pci_direct_conf2 = {
 154         pci_conf2_read_config_byte,
 155         pci_conf2_read_config_word,
 156         pci_conf2_read_config_dword,
 157         pci_conf2_write_config_byte,
 158         pci_conf2_write_config_word,
 159         pci_conf2_write_config_dword
 160 };
 161
 162 /*
 163  * Before we decide to use direct hardware access mechanisms, we try to do some
 164  * trivial checks to ensure it at least _seems_ to be working -- we just test
 165  * whether bus 00 contains a host bridge (this is similar to checking
 166  * techniques used in XFree86, but ours should be more reliable since we
 167  * attempt to make use of direct access hints provided by the PCI BIOS).
 168  *
 169  * This should be close to trivial, but it isn't, because there are buggy
 170  * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
 171  */
 172 static int __init pci_sanity_check(struct pci_ops *o)
 173 {
 174         u16 x;
 175         struct pci_bus bus;             /* Fake bus and device */
 176         struct pci_dev dev;
 177
 178         if (pci_probe & PCI_NO_CHECKS)
 179                 return 1;
 180         bus.number = 0;
 181         dev.bus = &bus;
 182         for(dev.devfn=0; dev.devfn < 0x100; dev.devfn++)
 183                 if ((!o->read_word(&dev, PCI_CLASS_DEVICE, &x) &&
 184                      (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)) ||
 185                     (!o->read_word(&dev, PCI_VENDOR_ID, &x) &&
 186                      (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)))
 187                         return 1;
 188         DBG("PCI: Sanity check failed\n");
 189         return 0;
 190 }
 191
 192 static struct pci_ops * __init pci_check_direct(void)
 193 {
 194         unsigned int tmp;
 195         unsigned long flags;
 196
 197         __save_flags(flags); __cli();
 198
 199         /*
 200          * Check if configuration type 1 works.
 201          */
 202         if (pci_probe & PCI_PROBE_CONF1) {
 203                 outb (0x01, 0xCFB);
 204                 tmp = inl (0xCF8);
 205                 outl (0x80000000, 0xCF8);
 206                 if (inl (0xCF8) == 0x80000000 &&
 207                     pci_sanity_check(&pci_direct_conf1)) {
 208                         outl (tmp, 0xCF8);
 209                         __restore_flags(flags);
 210                         printk("PCI: Using configuration type 1\n");
 211                         request_region(0xCF8, 8, "PCI conf1");
 212                         return &pci_direct_conf1;
 213                 }
 214                 outl (tmp, 0xCF8);
 215         }
 216
 217         /*
 218          * Check if configuration type 2 works.
 219          */
 220         if (pci_probe & PCI_PROBE_CONF2) {
 221                 outb (0x00, 0xCFB);
 222                 outb (0x00, 0xCF8);
 223                 outb (0x00, 0xCFA);
 224                 if (inb (0xCF8) == 0x00 && inb (0xCFA) == 0x00 &&
 225                     pci_sanity_check(&pci_direct_conf2)) {
 226                         __restore_flags(flags);
 227                         printk("PCI: Using configuration type 2\n");
 228                         request_region(0xCF8, 4, "PCI conf2");
 229                         return &pci_direct_conf2;
 230                 }
 231         }
 232
 233         __restore_flags(flags);
 234         return NULL;
 235 }
 236
 237 #endif
 238
 239 /*
 240  * BIOS32 and PCI BIOS handling.
 241  */
 242
 243 #ifdef CONFIG_PCI_BIOS
 244
 245 #define PCIBIOS_PCI_FUNCTION_ID         0xb1XX
 246 #define PCIBIOS_PCI_BIOS_PRESENT        0xb101
 247 #define PCIBIOS_FIND_PCI_DEVICE         0xb102
 248 #define PCIBIOS_FIND_PCI_CLASS_CODE     0xb103
 249 #define PCIBIOS_GENERATE_SPECIAL_CYCLE  0xb106
 250 #define PCIBIOS_READ_CONFIG_BYTE        0xb108
 251 #define PCIBIOS_READ_CONFIG_WORD        0xb109
 252 #define PCIBIOS_READ_CONFIG_DWORD       0xb10a
 253 #define PCIBIOS_WRITE_CONFIG_BYTE       0xb10b
 254 #define PCIBIOS_WRITE_CONFIG_WORD       0xb10c
 255 #define PCIBIOS_WRITE_CONFIG_DWORD      0xb10d
 256 #define PCIBIOS_GET_ROUTING_OPTIONS     0xb10e
 257 #define PCIBIOS_SET_PCI_HW_INT          0xb10f
 258
 259 /* BIOS32 signature: "_32_" */
 260 #define BIOS32_SIGNATURE        (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24))
 261
 262 /* PCI signature: "PCI " */
 263 #define PCI_SIGNATURE           (('P' << 0) + ('C' << 8) + ('I' << 16) + (' ' << 24))
 264
 265 /* PCI service signature: "$PCI" */
 266 #define PCI_SERVICE             (('$' << 0) + ('P' << 8) + ('C' << 16) + ('I' << 24))
 267
 268 /* PCI BIOS hardware mechanism flags */
 269 #define PCIBIOS_HW_TYPE1                0x01
 270 #define PCIBIOS_HW_TYPE2                0x02
 271 #define PCIBIOS_HW_TYPE1_SPEC           0x10
 272 #define PCIBIOS_HW_TYPE2_SPEC           0x20
 273
 274 /*
 275  * This is the standard structure used to identify the entry point
 276  * to the BIOS32 Service Directory, as documented in
 277  *      Standard BIOS 32-bit Service Directory Proposal
 278  *      Revision 0.4 May 24, 1993
 279  *      Phoenix Technologies Ltd.
 280  *      Norwood, MA
 281  * and the PCI BIOS specification.
 282  */
 283
 284 union bios32 {
 285         struct {
 286                 unsigned long signature;        /* _32_ */
 287                 unsigned long entry;            /* 32 bit physical address */
 288                 unsigned char revision;         /* Revision level, 0 */
 289                 unsigned char length;           /* Length in paragraphs should be 01 */
 290                 unsigned char checksum;         /* All bytes must add up to zero */
 291                 unsigned char reserved[5];      /* Must be zero */
 292         } fields;
 293         char chars[16];
 294 };
 295
 296 /*
 297  * Physical address of the service directory.  I don't know if we're
 298  * allowed to have more than one of these or not, so just in case
 299  * we'll make pcibios_present() take a memory start parameter and store
 300  * the array there.
 301  */
 302
 303 static struct {
 304         unsigned long address;
 305         unsigned short segment;
 306 } bios32_indirect = { 0, __KERNEL_CS };
 307
 308 /*
 309  * Returns the entry point for the given service, NULL on error
 310  */
 311
 312 static unsigned long bios32_service(unsigned long service)
 313 {
 314         unsigned char return_code;      /* %al */
 315         unsigned long address;          /* %ebx */
 316         unsigned long length;           /* %ecx */
 317         unsigned long entry;            /* %edx */
 318         unsigned long flags;
 319
 320         __save_flags(flags); __cli();
 321         __asm__("lcall (%%edi); cld"
 322                 : "=a" (return_code),
 323                   "=b" (address),
 324                   "=c" (length),
 325                   "=d" (entry)
 326                 : "0" (service),
 327                   "1" (0),
 328                   "D" (&bios32_indirect));
 329         __restore_flags(flags);
 330
 331         switch (return_code) {
 332                 case 0:
 333                         return address + entry;
 334                 case 0x80:      /* Not present */
 335                         printk("bios32_service(0x%lx): not present\n", service);
 336                         return 0;
 337                 default: /* Shouldn't happen */
 338                         printk("bios32_service(0x%lx): returned 0x%x -- BIOS bug!\n",
 339                                 service, return_code);
 340                         return 0;
 341         }
 342 }
 343
 344 static struct {
 345         unsigned long address;
 346         unsigned short segment;
 347 } pci_indirect = { 0, __KERNEL_CS };
 348
 349 static int pci_bios_present;
 350
 351 static int __init check_pcibios(void)
 352 {
 353         u32 signature, eax, ebx, ecx;
 354         u8 status, major_ver, minor_ver, hw_mech;
 355         unsigned long flags, pcibios_entry;
 356
 357         if ((pcibios_entry = bios32_service(PCI_SERVICE))) {
 358                 pci_indirect.address = pcibios_entry + PAGE_OFFSET;
 359
 360                 __save_flags(flags); __cli();
 361                 __asm__(
 362                         "lcall (%%edi); cld\n\t"
 363                         "jc 1f\n\t"
 364                         "xor %%ah, %%ah\n"
 365                         "1:"
 366                         : "=d" (signature),
 367                           "=a" (eax),
 368                           "=b" (ebx),
 369                           "=c" (ecx)
 370                         : "1" (PCIBIOS_PCI_BIOS_PRESENT),
 371                           "D" (&pci_indirect)
 372                         : "memory");
 373                 __restore_flags(flags);
 374
 375                 status = (eax >> 8) & 0xff;
 376                 hw_mech = eax & 0xff;
 377                 major_ver = (ebx >> 8) & 0xff;
 378                 minor_ver = ebx & 0xff;
 379                 if (pcibios_last_bus < 0)
 380                         pcibios_last_bus = ecx & 0xff;
 381                 DBG("PCI: BIOS probe returned s=%02x hw=%02x ver=%02x.%02x l=%02x\n",
 382                         status, hw_mech, major_ver, minor_ver, pcibios_last_bus);
 383                 if (status || signature != PCI_SIGNATURE) {
 384                         printk (KERN_ERR "PCI: BIOS BUG #%x[%08x] found, report to <mj@suse.cz>\n",
 385                                 status, signature);
 386                         return 0;
 387                 }
 388                 printk("PCI: PCI BIOS revision %x.%02x entry at 0x%lx, last bus=%d\n",
 389                         major_ver, minor_ver, pcibios_entry, pcibios_last_bus);
 390 #ifdef CONFIG_PCI_DIRECT
 391                 if (!(hw_mech & PCIBIOS_HW_TYPE1))
 392                         pci_probe &= ~PCI_PROBE_CONF1;
 393                 if (!(hw_mech & PCIBIOS_HW_TYPE2))
 394                         pci_probe &= ~PCI_PROBE_CONF2;
 395 #endif
 396                 return 1;
 397         }
 398         return 0;
 399 }
 400
 401 static int __init pci_bios_find_device (unsigned short vendor, unsigned short device_id,
 402                                         unsigned short index, unsigned char *bus, unsigned char *device_fn)
 403 {
 404         unsigned short bx;
 405         unsigned short ret;
 406
 407         __asm__("lcall (%%edi); cld\n\t"
 408                 "jc 1f\n\t"
 409                 "xor %%ah, %%ah\n"
 410                 "1:"
 411                 : "=b" (bx),
 412                   "=a" (ret)
 413                 : "1" (PCIBIOS_FIND_PCI_DEVICE),
 414                   "c" (device_id),
 415                   "d" (vendor),
 416                   "S" ((int) index),
 417                   "D" (&pci_indirect));
 418         *bus = (bx >> 8) & 0xff;
 419         *device_fn = bx & 0xff;
 420         return (int) (ret & 0xff00) >> 8;
 421 }
 422
 423 static int pci_bios_read_config_byte(struct pci_dev *dev, int where, u8 *value)
 424 {
 425         unsigned long ret;
 426         unsigned long bx = (dev->bus->number << 8) | dev->devfn;
 427
 428         __asm__("lcall (%%esi); cld\n\t"
 429                 "jc 1f\n\t"
 430                 "xor %%ah, %%ah\n"
 431                 "1:"
 432                 : "=c" (*value),
 433                   "=a" (ret)
 434                 : "1" (PCIBIOS_READ_CONFIG_BYTE),
 435                   "b" (bx),
 436                   "D" ((long) where),
 437                   "S" (&pci_indirect));
 438         return (int) (ret & 0xff00) >> 8;
 439 }
 440
 441 static int pci_bios_read_config_word(struct pci_dev *dev, int where, u16 *value)
 442 {
 443         unsigned long ret;
 444         unsigned long bx = (dev->bus->number << 8) | dev->devfn;
 445
 446         __asm__("lcall (%%esi); cld\n\t"
 447                 "jc 1f\n\t"
 448                 "xor %%ah, %%ah\n"
 449                 "1:"
 450                 : "=c" (*value),
 451                   "=a" (ret)
 452                 : "1" (PCIBIOS_READ_CONFIG_WORD),
 453                   "b" (bx),
 454                   "D" ((long) where),
 455                   "S" (&pci_indirect));
 456         return (int) (ret & 0xff00) >> 8;
 457 }
 458
 459 static int pci_bios_read_config_dword(struct pci_dev *dev, int where, u32 *value)
 460 {
 461         unsigned long ret;
 462         unsigned long bx = (dev->bus->number << 8) | dev->devfn;
 463
 464         __asm__("lcall (%%esi); cld\n\t"
 465                 "jc 1f\n\t"
 466                 "xor %%ah, %%ah\n"
 467                 "1:"
 468                 : "=c" (*value),
 469                   "=a" (ret)
 470                 : "1" (PCIBIOS_READ_CONFIG_DWORD),
 471                   "b" (bx),
 472                   "D" ((long) where),
 473                   "S" (&pci_indirect));
 474         return (int) (ret & 0xff00) >> 8;
 475 }
 476
 477 static int pci_bios_write_config_byte(struct pci_dev *dev, int where, u8 value)
 478 {
 479         unsigned long ret;
 480         unsigned long bx = (dev->bus->number << 8) | dev->devfn;
 481
 482         __asm__("lcall (%%esi); cld\n\t"
 483                 "jc 1f\n\t"
 484                 "xor %%ah, %%ah\n"
 485                 "1:"
 486                 : "=a" (ret)
 487                 : "0" (PCIBIOS_WRITE_CONFIG_BYTE),
 488                   "c" (value),
 489                   "b" (bx),
 490                   "D" ((long) where),
 491                   "S" (&pci_indirect));
 492         return (int) (ret & 0xff00) >> 8;
 493 }
 494
 495 static int pci_bios_write_config_word(struct pci_dev *dev, int where, u16 value)
 496 {
 497         unsigned long ret;
 498         unsigned long bx = (dev->bus->number << 8) | dev->devfn;
 499
 500         __asm__("lcall (%%esi); cld\n\t"
 501                 "jc 1f\n\t"
 502                 "xor %%ah, %%ah\n"
 503                 "1:"
 504                 : "=a" (ret)
 505                 : "0" (PCIBIOS_WRITE_CONFIG_WORD),
 506                   "c" (value),
 507                   "b" (bx),
 508                   "D" ((long) where),
 509                   "S" (&pci_indirect));
 510         return (int) (ret & 0xff00) >> 8;
 511 }
 512
 513 static int pci_bios_write_config_dword(struct pci_dev *dev, int where, u32 value)
 514 {
 515         unsigned long ret;
 516         unsigned long bx = (dev->bus->number << 8) | dev->devfn;
 517
 518         __asm__("lcall (%%esi); cld\n\t"
 519                 "jc 1f\n\t"
 520                 "xor %%ah, %%ah\n"
 521                 "1:"
 522                 : "=a" (ret)
 523                 : "0" (PCIBIOS_WRITE_CONFIG_DWORD),
 524                   "c" (value),
 525                   "b" (bx),
 526                   "D" ((long) where),
 527                   "S" (&pci_indirect));
 528         return (int) (ret & 0xff00) >> 8;
 529 }
 530
 531 /*
 532  * Function table for BIOS32 access
 533  */
 534
 535 static struct pci_ops pci_bios_access = {
 536       pci_bios_read_config_byte,
 537       pci_bios_read_config_word,
 538       pci_bios_read_config_dword,
 539       pci_bios_write_config_byte,
 540       pci_bios_write_config_word,
 541       pci_bios_write_config_dword
 542 };
 543
 544 /*
 545  * Try to find PCI BIOS.
 546  */
 547
 548 static struct pci_ops * __init pci_find_bios(void)
 549 {
 550         union bios32 *check;
 551         unsigned char sum;
 552         int i, length;
 553
 554         /*
 555          * Follow the standard procedure for locating the BIOS32 Service
 556          * directory by scanning the permissible address range from
 557          * 0xe0000 through 0xfffff for a valid BIOS32 structure.
 558          */
 559
 560         for (check = (union bios32 *) __va(0xe0000);
 561              check <= (union bios32 *) __va(0xffff0);
 562              ++check) {
 563                 if (check->fields.signature != BIOS32_SIGNATURE)
 564                         continue;
 565                 length = check->fields.length * 16;
 566                 if (!length)
 567                         continue;
 568                 sum = 0;
 569                 for (i = 0; i < length ; ++i)
 570                         sum += check->chars[i];
 571                 if (sum != 0)
 572                         continue;
 573                 if (check->fields.revision != 0) {
 574                         printk("PCI: unsupported BIOS32 revision %d at 0x%p, report to <mj@suse.cz>\n",
 575                                 check->fields.revision, check);
 576                         continue;
 577                 }
 578                 DBG("PCI: BIOS32 Service Directory structure at 0x%p\n", check);
 579                 if (check->fields.entry >= 0x100000) {
 580                         printk("PCI: BIOS32 entry (0x%p) in high memory, cannot use.\n", check);
 581                         return NULL;
 582                 } else {
 583                         unsigned long bios32_entry = check->fields.entry;
 584                         DBG("PCI: BIOS32 Service Directory entry at 0x%lx\n", bios32_entry);
 585                         bios32_indirect.address = bios32_entry + PAGE_OFFSET;
 586                         if (check_pcibios())
 587                                 return &pci_bios_access;
 588                 }
 589                 break;  /* Hopefully more than one BIOS32 cannot happen... */
 590         }
 591
 592         return NULL;
 593 }
 594
 595 /*
 596  * Sort the device list according to PCI BIOS. Nasty hack, but since some
 597  * fool forgot to define the `correct' device order in the PCI BIOS specs
 598  * and we want to be (possibly bug-to-bug ;-]) compatible with older kernels
 599  * which used BIOS ordering, we are bound to do this...
 600  */
 601
 602 static void __init pcibios_sort(void)
 603 {
 604         LIST_HEAD(sorted_devices);
 605         struct list_head *ln;
 606         struct pci_dev *dev, *d;
 607         int idx, found;
 608         unsigned char bus, devfn;
 609
 610         DBG("PCI: Sorting device list...\n");
 611         while (!list_empty(&pci_devices)) {
 612                 ln = pci_devices.next;
 613                 dev = pci_dev_g(ln);
 614                 idx = found = 0;
 615                 while (pci_bios_find_device(dev->vendor, dev->device, idx, &bus, &devfn) == PCIBIOS_SUCCESSFUL) {
 616                         idx++;
 617                         for (ln=pci_devices.next; ln != &pci_devices; ln=ln->next) {
 618                                 d = pci_dev_g(ln);
 619                                 if (d->bus->number == bus && d->devfn == devfn) {
 620                                         list_del(&d->global_list);
 621                                         list_add_tail(&d->global_list, &sorted_devices);
 622                                         if (d == dev)
 623                                                 found = 1;
 624                                         break;
 625                                 }
 626                         }
 627                         if (ln == &pci_devices) {
 628                                 printk("PCI: BIOS reporting unknown device %02x:%02x\n", bus, devfn);
 629                                 /*
 630                                  * We must not continue scanning as several buggy BIOSes
 631                                  * return garbage after the last device. Grr.
 632                                  */
 633                                 break;
 634                         }
 635                 }
 636                 if (!found) {
 637                         printk("PCI: Device %02x:%02x not found by BIOS\n",
 638                                 dev->bus->number, dev->devfn);
 639                         list_del(&dev->global_list);
 640                         list_add_tail(&dev->global_list, &sorted_devices);
 641                 }
 642         }
 643         list_splice(&sorted_devices, &pci_devices);
 644 }
 645
 646 /*
 647  *  BIOS Functions for IRQ Routing
 648  */
 649
 650 struct irq_routing_options {
 651         u16 size;
 652         struct irq_info *table;
 653         u16 segment;
 654 } __attribute__((packed));
 655
 656 struct irq_routing_table * __init pcibios_get_irq_routing_table(void)
 657 {
 658         struct irq_routing_options opt;
 659         struct irq_routing_table *rt = NULL;
 660         int ret, map;
 661         unsigned long page;
 662
 663         if (!pci_bios_present)
 664                 return NULL;
 665         page = __get_free_page(GFP_KERNEL);
 666         if (!page)
 667                 return NULL;
 668         opt.table = (struct irq_info *) page;
 669         opt.size = PAGE_SIZE;
 670         opt.segment = __KERNEL_DS;
 671
 672         DBG("PCI: Fetching IRQ routing table... ");
 673         __asm__("push %%es\n\t"
 674                 "push %%ds\n\t"
 675                 "pop  %%es\n\t"
 676                 "lcall (%%esi); cld\n\t"
 677                 "pop %%es\n\t"
 678                 "jc 1f\n\t"
 679                 "xor %%ah, %%ah\n"
 680                 "1:"
 681                 : "=a" (ret),
 682                   "=b" (map)
 683                 : "0" (PCIBIOS_GET_ROUTING_OPTIONS),
 684                   "1" (0),
 685                   "D" ((long) &opt),
 686                   "S" (&pci_indirect));
 687         DBG("OK  ret=%d, size=%d, map=%x\n", ret, opt.size, map);
 688         if (ret & 0xff00)
 689                 printk(KERN_ERR "PCI: Error %02x when fetching IRQ routing table.\n", (ret >> 8) & 0xff);
 690         else if (opt.size) {
 691                 rt = kmalloc(sizeof(struct irq_routing_table) + opt.size, GFP_KERNEL);
 692                 if (rt) {
 693                         memset(rt, 0, sizeof(struct irq_routing_table));
 694                         rt->size = opt.size + sizeof(struct irq_routing_table);
 695                         rt->exclusive_irqs = map;
 696                         memcpy(rt->slots, (void *) page, opt.size);
 697                         printk("PCI: Using BIOS Interrupt Routing Table\n");
 698                 }
 699         }
 700         free_page(page);
 701         return rt;
 702 }
 703
 704
 705 int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq)
 706 {
 707         int ret;
 708
 709         __asm__("lcall (%%esi); cld\n\t"
 710                 "jc 1f\n\t"
 711                 "xor %%ah, %%ah\n"
 712                 "1:"
 713                 : "=a" (ret)
 714                 : "0" (PCIBIOS_SET_PCI_HW_INT),
 715                   "b" ((dev->bus->number << 8) | dev->devfn),
 716                   "c" ((irq << 8) | (pin + 10)),
 717                   "S" (&pci_indirect));
 718         return !(ret & 0xff00);
 719 }
 720
 721 #endif
 722
 723 /*
 724  * Several buggy motherboards address only 16 devices and mirror
 725  * them to next 16 IDs. We try to detect this `feature' on all
 726  * primary buses (those containing host bridges as they are
 727  * expected to be unique) and remove the ghost devices.
 728  */
 729
 730 static void __init pcibios_fixup_ghosts(struct pci_bus *b)
 731 {
 732         struct list_head *ln, *mn;
 733         struct pci_dev *d, *e;
 734         int mirror = PCI_DEVFN(16,0);
 735         int seen_host_bridge = 0;
 736         int i;
 737
 738         DBG("PCI: Scanning for ghost devices on bus %d\n", b->number);
 739         for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
 740                 d = pci_dev_b(ln);
 741                 if ((d->class >> 8) == PCI_CLASS_BRIDGE_HOST)
 742                         seen_host_bridge++;
 743                 for (mn=ln->next; mn != &b->devices; mn=mn->next) {
 744                         e = pci_dev_b(mn);
 745                         if (e->devfn != d->devfn + mirror ||
 746                             e->vendor != d->vendor ||
 747                             e->device != d->device ||
 748                             e->class != d->class)
 749                                 continue;
 750                         for(i=0; i<PCI_NUM_RESOURCES; i++)
 751                                 if (e->resource[i].start != d->resource[i].start ||
 752                                     e->resource[i].end != d->resource[i].end ||
 753                                     e->resource[i].flags != d->resource[i].flags)
 754                                         continue;
 755                         break;
 756                 }
 757                 if (mn == &b->devices)
 758                         return;
 759         }
 760         if (!seen_host_bridge)
 761                 return;
 762         printk("PCI: Ignoring ghost devices on bus %02x\n", b->number);
 763
 764         ln = &b->devices;
 765         while (ln->next != &b->devices) {
 766                 d = pci_dev_b(ln->next);
 767                 if (d->devfn >= mirror) {
 768                         list_del(&d->global_list);
 769                         list_del(&d->bus_list);
 770                         kfree(d);
 771                 } else
 772                         ln = ln->next;
 773         }
 774 }
 775
 776 /*
 777  * Discover remaining PCI buses in case there are peer host bridges.
 778  * We use the number of last PCI bus provided by the PCI BIOS.
 779  */
 780 static void __init pcibios_fixup_peer_bridges(void)
 781 {
 782         int n;
 783         struct pci_bus bus;
 784         struct pci_dev dev;
 785         u16 l;
 786
 787         if (pcibios_last_bus <= 0 || pcibios_last_bus >= 0xff)
 788                 return;
 789         DBG("PCI: Peer bridge fixup\n");
 790         for (n=0; n <= pcibios_last_bus; n++) {
 791                 if (pci_bus_exists(&pci_root_buses, n))
 792                         continue;
 793                 bus.number = n;
 794                 bus.ops = pci_root_ops;
 795                 dev.bus = &bus;
 796                 for(dev.devfn=0; dev.devfn<256; dev.devfn += 8)
 797                         if (!pci_read_config_word(&dev, PCI_VENDOR_ID, &l) &&
 798                             l != 0x0000 && l != 0xffff) {
 799                                 DBG("Found device at %02x:%02x [%04x]\n", n, dev.devfn, l);
 800                                 printk("PCI: Discovered peer bus %02x\n", n);
 801                                 pci_scan_bus(n, pci_root_ops, NULL);
 802                                 break;
 803                         }
 804         }
 805 }
 806
 807 /*
 808  * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
 809  */
 810
 811 static void __init pci_fixup_i450nx(struct pci_dev *d)
 812 {
 813         /*
 814          * i450NX -- Find and scan all secondary buses on all PXB's.
 815          */
 816         int pxb, reg;
 817         u8 busno, suba, subb;
 818         printk("PCI: Searching for i450NX host bridges on %s\n", d->slot_name);
 819         reg = 0xd0;
 820         for(pxb=0; pxb<2; pxb++) {
 821                 pci_read_config_byte(d, reg++, &busno);
 822                 pci_read_config_byte(d, reg++, &suba);
 823                 pci_read_config_byte(d, reg++, &subb);
 824                 DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
 825                 if (busno)
 826                         pci_scan_bus(busno, pci_root_ops, NULL);        /* Bus A */
 827                 if (suba < subb)
 828                         pci_scan_bus(suba+1, pci_root_ops, NULL);       /* Bus B */
 829         }
 830         pcibios_last_bus = -1;
 831 }
 832
 833 static void __init pci_fixup_i450gx(struct pci_dev *d)
 834 {
 835         /*
 836          * i450GX and i450KX -- Find and scan all secondary buses.
 837          * (called separately for each PCI bridge found)
 838          */
 839         u8 busno;
 840         pci_read_config_byte(d, 0x4a, &busno);
 841         printk("PCI: i440KX/GX host bridge %s: secondary bus %02x\n", d->slot_name, busno);
 842         pci_scan_bus(busno, pci_root_ops, NULL);
 843         pcibios_last_bus = -1;
 844 }
 845
 846 static void __init pci_fixup_serverworks(struct pci_dev *d)
 847 {
 848         /*
 849          * ServerWorks host bridges -- Find and scan all secondary buses.
 850          * Register 0x44 contains first, 0x45 last bus number routed there.
 851          */
 852         u8 busno;
 853         pci_read_config_byte(d, 0x44, &busno);
 854         printk("PCI: ServerWorks host bridge: secondary bus %02x\n", busno);
 855         pci_scan_bus(busno, pci_root_ops, NULL);
 856         pcibios_last_bus = -1;
 857 }
 858
 859 static void __init pci_fixup_compaq(struct pci_dev *d)
 860 {
 861         /*
 862          * Compaq host bridges -- Find and scan all secondary buses.
 863          * This time registers 0xc8 and 0xc9.
 864          */
 865         u8 busno;
 866         pci_read_config_byte(d, 0xc8, &busno);
 867         printk("PCI: Compaq host bridge: secondary bus %02x\n", busno);
 868         pci_scan_bus(busno, pci_root_ops, NULL);
 869         pcibios_last_bus = -1;
 870 }
 871
 872 static void __init pci_fixup_umc_ide(struct pci_dev *d)
 873 {
 874         /*
 875          * UM8886BF IDE controller sets region type bits incorrectly,
 876          * therefore they look like memory despite of them being I/O.
 877          */
 878         int i;
 879
 880         printk("PCI: Fixing base address flags for device %s\n", d->slot_name);
 881         for(i=0; i<4; i++)
 882                 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
 883 }
 884
 885 static void __init pci_fixup_ide_bases(struct pci_dev *d)
 886 {
 887         int i;
 888
 889         /*
 890          * PCI IDE controllers use non-standard I/O port decoding, respect it.
 891          */
 892         if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
 893                 return;
 894         DBG("PCI: IDE base address fixup for %s\n", d->slot_name);
 895         for(i=0; i<4; i++) {
 896                 struct resource *r = &d->resource[i];
 897                 if ((r->start & ~0x80) == 0x374) {
 898                         r->start |= 2;
 899                         r->end = r->start;
 900                 }
 901         }
 902 }
 903
 904 static void __init pci_fixup_ide_trash(struct pci_dev *d)
 905 {
 906         int i;
 907
 908         /*
 909          * There exist PCI IDE controllers which have utter garbage
 910          * in first four base registers. Ignore that.
 911          */
 912         DBG("PCI: IDE base address trash cleared for %s\n", d->slot_name);
 913         for(i=0; i<4; i++)
 914                 d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
 915 }
 916
 917 static void __init pci_fixup_latency(struct pci_dev *d)
 918 {
 919         /*
 920          *  SiS 5597 and 5598 chipsets require latency timer set to
 921          *  at most 32 to avoid lockups.
 922          */
 923         DBG("PCI: Setting max latency to 32\n");
 924         pcibios_max_latency = 32;
 925 }
 926
 927 struct pci_fixup pcibios_fixups[] = {
 928         { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82451NX,    pci_fixup_i450nx },
 929         { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82454GX,    pci_fixup_i450gx },
 930         { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_SERVERWORKS,      PCI_DEVICE_ID_SERVERWORKS_HE,           pci_fixup_serverworks },
 931         { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_SERVERWORKS,      PCI_DEVICE_ID_SERVERWORKS_LE,           pci_fixup_serverworks },
 932         { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_SERVERWORKS,      PCI_DEVICE_ID_SERVERWORKS_CMIC_HE,      pci_fixup_serverworks },
 933         { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_COMPAQ,   PCI_DEVICE_ID_COMPAQ_6010,      pci_fixup_compaq },
 934         { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_UMC,      PCI_DEVICE_ID_UMC_UM8886BF,     pci_fixup_umc_ide },
 935         { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_5513,          pci_fixup_ide_trash },
 936         { PCI_FIXUP_HEADER,     PCI_ANY_ID,             PCI_ANY_ID,                     pci_fixup_ide_bases },
 937         { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_5597,          pci_fixup_latency },
 938         { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_5598,          pci_fixup_latency },
 939         { 0 }
 940 };
 941
 942 /*
 943  *  Called after each bus is probed, but before its children
 944  *  are examined.
 945  */
 946
 947 void __init pcibios_fixup_bus(struct pci_bus *b)
 948 {
 949         pcibios_fixup_ghosts(b);
 950         pci_read_bridge_bases(b);
 951 }
 952
 953 /*
 954  * Initialization. Try all known PCI access methods. Note that we support
 955  * using both PCI BIOS and direct access: in such cases, we use I/O ports
 956  * to access config space, but we still keep BIOS order of cards to be
 957  * compatible with 2.0.X. This should go away some day.
 958  */
 959
 960 void __init pcibios_init(void)
 961 {
 962         struct pci_ops *bios = NULL;
 963         struct pci_ops *dir = NULL;
 964
 965 #ifdef CONFIG_PCI_BIOS
 966         if ((pci_probe & PCI_PROBE_BIOS) && ((bios = pci_find_bios()))) {
 967                 pci_probe |= PCI_BIOS_SORT;
 968                 pci_bios_present = 1;
 969         }
 970 #endif
 971 #ifdef CONFIG_PCI_DIRECT
 972         if (pci_probe & (PCI_PROBE_CONF1 | PCI_PROBE_CONF2))
 973                 dir = pci_check_direct();
 974 #endif
 975         if (dir)
 976                 pci_root_ops = dir;
 977         else if (bios)
 978                 pci_root_ops = bios;
 979         else {
 980                 printk("PCI: No PCI bus detected\n");
 981                 return;
 982         }
 983
 984         printk("PCI: Probing PCI hardware\n");
 985         pci_root_bus = pci_scan_bus(0, pci_root_ops, NULL);
 986
 987         pcibios_irq_init();
 988         pcibios_fixup_peer_bridges();
 989         pcibios_fixup_irqs();
 990         pcibios_resource_survey();
 991
 992 #ifdef CONFIG_PCI_BIOS
 993         if ((pci_probe & PCI_BIOS_SORT) && !(pci_probe & PCI_NO_SORT))
 994                 pcibios_sort();
 995 #endif
 996 }
 997
 998 char * __init pcibios_setup(char *str)
 999 {
1000         if (!strcmp(str, "off")) {
1001                 pci_probe = 0;
1002                 return NULL;
1003         }
1004 #ifdef CONFIG_PCI_BIOS
1005         else if (!strcmp(str, "bios")) {
1006                 pci_probe = PCI_PROBE_BIOS;
1007                 return NULL;
1008         } else if (!strcmp(str, "nobios")) {
1009                 pci_probe &= ~PCI_PROBE_BIOS;
1010                 return NULL;
1011         } else if (!strcmp(str, "nosort")) {
1012                 pci_probe |= PCI_NO_SORT;
1013                 return NULL;
1014         } else if (!strcmp(str, "biosirq")) {
1015                 pci_probe |= PCI_BIOS_IRQ_SCAN;
1016                 return NULL;
1017         }
1018 #endif
1019 #ifdef CONFIG_PCI_DIRECT
1020         else if (!strcmp(str, "conf1")) {
1021                 pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
1022                 return NULL;
1023         }
1024         else if (!strcmp(str, "conf2")) {
1025                 pci_probe = PCI_PROBE_CONF2 | PCI_NO_CHECKS;
1026                 return NULL;
1027         }
1028 #endif
1029         else if (!strcmp(str, "rom")) {
1030                 pci_probe |= PCI_ASSIGN_ROMS;
1031                 return NULL;
1032         } else if (!strncmp(str, "irqmask=", 8)) {
1033                 pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
1034                 return NULL;
1035         } else if (!strncmp(str, "lastbus=", 8)) {
1036                 pcibios_last_bus = simple_strtol(str+8, NULL, 0);
1037                 return NULL;
1038         }
1039         return str;
1040 }
1041
1042 int pcibios_enable_device(struct pci_dev *dev)
1043 {
1044         int err;
1045
1046         if ((err = pcibios_enable_resources(dev)) < 0)
1047                 return err;
1048         pcibios_enable_irq(dev);
1049         return 0;
1050 }