| blob | 37e4ba907f8ce54426f0b8230d36da16c29645ca |
1 /*
2 * File Name:
3 * defxx.c
4 *
5 * Copyright Information:
6 * Copyright Digital Equipment Corporation 1996.
7 *
8 * This software may be used and distributed according to the terms of
9 * the GNU Public License, incorporated herein by reference.
10 *
11 * Abstract:
12 * A Linux device driver supporting the Digital Equipment Corporation
13 * FDDI EISA and PCI controller families. Supported adapters include:
14 *
15 * DEC FDDIcontroller/EISA (DEFEA)
16 * DEC FDDIcontroller/PCI (DEFPA)
17 *
18 * Maintainers:
19 * LVS Lawrence V. Stefani
20 *
21 * Contact:
22 * The author may be reached at:
23 *
24 * Inet: stefani@lkg.dec.com
25 * (NOTE! this address no longer works -jgarzik)
26 *
27 * Mail: Digital Equipment Corporation
28 * 550 King Street
29 * M/S: LKG1-3/M07
30 * Littleton, MA 01460
31 *
32 * Credits:
33 * I'd like to thank Patricia Cross for helping me get started with
34 * Linux, David Davies for a lot of help upgrading and configuring
35 * my development system and for answering many OS and driver
36 * development questions, and Alan Cox for recommendations and
37 * integration help on getting FDDI support into Linux. LVS
38 *
39 * Driver Architecture:
40 * The driver architecture is largely based on previous driver work
41 * for other operating systems. The upper edge interface and
42 * functions were largely taken from existing Linux device drivers
43 * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C
44 * driver.
45 *
46 * Adapter Probe -
47 * The driver scans for supported EISA adapters by reading the
48 * SLOT ID register for each EISA slot and making a match
49 * against the expected value.
50 *
51 * Bus-Specific Initialization -
52 * This driver currently supports both EISA and PCI controller
53 * families. While the custom DMA chip and FDDI logic is similar
54 * or identical, the bus logic is very different. After
55 * initialization, the only bus-specific differences is in how the
56 * driver enables and disables interrupts. Other than that, the
57 * run-time critical code behaves the same on both families.
58 * It's important to note that both adapter families are configured
59 * to I/O map, rather than memory map, the adapter registers.
60 *
61 * Driver Open/Close -
62 * In the driver open routine, the driver ISR (interrupt service
63 * routine) is registered and the adapter is brought to an
64 * operational state. In the driver close routine, the opposite
65 * occurs; the driver ISR is deregistered and the adapter is
66 * brought to a safe, but closed state. Users may use consecutive
67 * commands to bring the adapter up and down as in the following
68 * example:
69 * ifconfig fddi0 up
70 * ifconfig fddi0 down
71 * ifconfig fddi0 up
72 *
73 * Driver Shutdown -
74 * Apparently, there is no shutdown or halt routine support under
75 * Linux. This routine would be called during "reboot" or
76 * "shutdown" to allow the driver to place the adapter in a safe
77 * state before a warm reboot occurs. To be really safe, the user
78 * should close the adapter before shutdown (eg. ifconfig fddi0 down)
79 * to ensure that the adapter DMA engine is taken off-line. However,
80 * the current driver code anticipates this problem and always issues
81 * a soft reset of the adapter at the beginning of driver initialization.
82 * A future driver enhancement in this area may occur in 2.1.X where
83 * Alan indicated that a shutdown handler may be implemented.
84 *
85 * Interrupt Service Routine -
86 * The driver supports shared interrupts, so the ISR is registered for
87 * each board with the appropriate flag and the pointer to that board's
88 * device structure. This provides the context during interrupt
89 * processing to support shared interrupts and multiple boards.
90 *
91 * Interrupt enabling/disabling can occur at many levels. At the host
92 * end, you can disable system interrupts, or disable interrupts at the
93 * PIC (on Intel systems). Across the bus, both EISA and PCI adapters
94 * have a bus-logic chip interrupt enable/disable as well as a DMA
95 * controller interrupt enable/disable.
96 *
97 * The driver currently enables and disables adapter interrupts at the
98 * bus-logic chip and assumes that Linux will take care of clearing or
99 * acknowledging any host-based interrupt chips.
100 *
101 * Control Functions -
102 * Control functions are those used to support functions such as adding
103 * or deleting multicast addresses, enabling or disabling packet
104 * reception filters, or other custom/proprietary commands. Presently,
105 * the driver supports the "get statistics", "set multicast list", and
106 * "set mac address" functions defined by Linux. A list of possible
107 * enhancements include:
108 *
109 * - Custom ioctl interface for executing port interface commands
110 * - Custom ioctl interface for adding unicast addresses to
111 * adapter CAM (to support bridge functions).
112 * - Custom ioctl interface for supporting firmware upgrades.
113 *
114 * Hardware (port interface) Support Routines -
115 * The driver function names that start with "dfx_hw_" represent
116 * low-level port interface routines that are called frequently. They
117 * include issuing a DMA or port control command to the adapter,
118 * resetting the adapter, or reading the adapter state. Since the
119 * driver initialization and run-time code must make calls into the
120 * port interface, these routines were written to be as generic and
121 * usable as possible.
122 *
123 * Receive Path -
124 * The adapter DMA engine supports a 256 entry receive descriptor block
125 * of which up to 255 entries can be used at any given time. The
126 * architecture is a standard producer, consumer, completion model in
127 * which the driver "produces" receive buffers to the adapter, the
128 * adapter "consumes" the receive buffers by DMAing incoming packet data,
129 * and the driver "completes" the receive buffers by servicing the
130 * incoming packet, then "produces" a new buffer and starts the cycle
131 * again. Receive buffers can be fragmented in up to 16 fragments
132 * (descriptor entries). For simplicity, this driver posts
133 * single-fragment receive buffers of 4608 bytes, then allocates a
134 * sk_buff, copies the data, then reposts the buffer. To reduce CPU
135 * utilization, a better approach would be to pass up the receive
136 * buffer (no extra copy) then allocate and post a replacement buffer.
137 * This is a performance enhancement that should be looked into at
138 * some point.
139 *
140 * Transmit Path -
141 * Like the receive path, the adapter DMA engine supports a 256 entry
142 * transmit descriptor block of which up to 255 entries can be used at
143 * any given time. Transmit buffers can be fragmented in up to 255
144 * fragments (descriptor entries). This driver always posts one
145 * fragment per transmit packet request.
146 *
147 * The fragment contains the entire packet from FC to end of data.
148 * Before posting the buffer to the adapter, the driver sets a three-byte
149 * packet request header (PRH) which is required by the Motorola MAC chip
150 * used on the adapters. The PRH tells the MAC the type of token to
151 * receive/send, whether or not to generate and append the CRC, whether
152 * synchronous or asynchronous framing is used, etc. Since the PRH
153 * definition is not necessarily consistent across all FDDI chipsets,
154 * the driver, rather than the common FDDI packet handler routines,
155 * sets these bytes.
156 *
157 * To reduce the amount of descriptor fetches needed per transmit request,
158 * the driver takes advantage of the fact that there are at least three
159 * bytes available before the skb->data field on the outgoing transmit
160 * request. This is guaranteed by having fddi_setup() in net_init.c set
161 * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest
162 * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad"
163 * bytes which we'll use to store the PRH.
164 *
165 * There's a subtle advantage to adding these pad bytes to the
166 * hard_header_len, it ensures that the data portion of the packet for
167 * an 802.2 SNAP frame is longword aligned. Other FDDI driver
168 * implementations may not need the extra padding and can start copying
169 * or DMAing directly from the FC byte which starts at skb->data. Should
170 * another driver implementation need ADDITIONAL padding, the net_init.c
171 * module should be updated and dev->hard_header_len should be increased.
172 * NOTE: To maintain the alignment on the data portion of the packet,
173 * dev->hard_header_len should always be evenly divisible by 4 and at
174 * least 24 bytes in size.
175 *
176 * Modification History:
177 * Date Name Description
178 * 16-Aug-96 LVS Created.
179 * 20-Aug-96 LVS Updated dfx_probe so that version information
180 * string is only displayed if 1 or more cards are
181 * found. Changed dfx_rcv_queue_process to copy
182 * 3 NULL bytes before FC to ensure that data is
183 * longword aligned in receive buffer.
184 * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable
185 * LLC group promiscuous mode if multicast list
186 * is too large. LLC individual/group promiscuous
187 * mode is now disabled if IFF_PROMISC flag not set.
188 * dfx_xmt_queue_pkt no longer checks for NULL skb
189 * on Alan Cox recommendation. Added node address
190 * override support.
191 * 12-Sep-96 LVS Reset current address to factory address during
192 * device open. Updated transmit path to post a
193 * single fragment which includes PRH->end of data.
194 * Mar 2000 AC Did various cleanups for 2.3.x
195 * Jun 2000 jgarzik PCI and resource alloc cleanups
196 * Jul 2000 tjeerd Much cleanup and some bug fixes
197 * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup
198 */
200 /* Include files */
202 #include <linux/module.h>
204 #include <linux/kernel.h>
205 #include <linux/sched.h>
206 #include <linux/string.h>
207 #include <linux/ptrace.h>
208 #include <linux/errno.h>
209 #include <linux/ioport.h>
210 #include <linux/malloc.h>
211 #include <linux/interrupt.h>
212 #include <linux/pci.h>
213 #include <linux/delay.h>
214 #include <linux/init.h>
215 #include <linux/netdevice.h>
216 #include <asm/byteorder.h>
217 #include <asm/bitops.h>
218 #include <asm/io.h>
220 #include <linux/fddidevice.h>
221 #include <linux/skbuff.h>
225 /* Version information string - should be updated prior to each new release!!! */
230 #define DYNAMIC_BUFFERS 1
232 #define SKBUFF_RX_COPYBREAK 200
233 /*
234 * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte
235 * alignment for compatibility with old EISA boards.
236 */
237 #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128)
239 /* Define module-wide (static) routines */
262 static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data);
274 /* Define module-wide (static) variables */
278 \f
279 /*
280 * =======================
281 * = dfx_port_write_byte =
282 * = dfx_port_read_byte =
283 * = dfx_port_write_long =
284 * = dfx_port_read_long =
285 * =======================
286 *
287 * Overview:
288 * Routines for reading and writing values from/to adapter
289 *
290 * Returns:
291 * None
292 *
293 * Arguments:
294 * bp - pointer to board information
295 * offset - register offset from base I/O address
296 * data - for dfx_port_write_byte and dfx_port_write_long, this
297 * is a value to write.
298 * for dfx_port_read_byte and dfx_port_read_byte, this
299 * is a pointer to store the read value.
300 *
301 * Functional Description:
302 * These routines perform the correct operation to read or write
303 * the adapter register.
304 *
305 * EISA port block base addresses are based on the slot number in which the
306 * controller is installed. For example, if the EISA controller is installed
307 * in slot 4, the port block base address is 0x4000. If the controller is
308 * installed in slot 2, the port block base address is 0x2000, and so on.
309 * This port block can be used to access PDQ, ESIC, and DEFEA on-board
310 * registers using the register offsets defined in DEFXX.H.
311 *
312 * PCI port block base addresses are assigned by the PCI BIOS or system
313 * firmware. There is one 128 byte port block which can be accessed. It
314 * allows for I/O mapping of both PDQ and PFI registers using the register
315 * offsets defined in DEFXX.H.
316 *
317 * Return Codes:
318 * None
319 *
320 * Assumptions:
321 * bp->base_addr is a valid base I/O address for this adapter.
322 * offset is a valid register offset for this adapter.
323 *
324 * Side Effects:
325 * Rather than produce macros for these functions, these routines
326 * are defined using "inline" to ensure that the compiler will
327 * generate inline code and not waste a procedure call and return.
328 * This provides all the benefits of macros, but with the
329 * advantage of strict data type checking.
330 */
335 u8 data
336 )
338 {
343 }
348 u8 *data
349 )
351 {
356 }
361 u32 data
362 )
364 {
369 }
374 u32 *data
375 )
377 {
382 }
384 \f
385 /*
386 * =============
387 * = dfx_init_one_pci_or_eisa =
388 * =============
389 *
390 * Overview:
391 * Initializes a supported FDDI EISA or PCI controller
392 *
393 * Returns:
394 * Condition code
395 *
396 * Arguments:
397 * pdev - pointer to pci device information (NULL for EISA)
398 *
399 * Functional Description:
400 *
401 * Return Codes:
402 * 0 - This device (fddi0, fddi1, etc) configured successfully
403 * -EBUSY - Failed to get resources, or dfx_driver_init failed.
404 *
405 * Assumptions:
406 * It compiles so it should work :-( (PCI cards do :-)
407 *
408 * Side Effects:
409 * Device structures for FDDI adapters (fddi0, fddi1, etc) are
410 * initialized and the board resources are read and stored in
411 * the device structure.
412 */
414 {
420 {
423 }
425 /*
426 * init_fddidev() allocates a device structure with private data, clears the device structure and private data,
427 * and calls fddi_setup() and register_netdev(). Not much left to do for us here.
428 */
434 }
442 }
444 /* Initialize new device structure */
456 /* EISA board */
461 /* PCI board */
468 }
475 err_out_region:
477 err_out:
481 }
484 {
486 }
489 {
497 /* Scan for FDDI EISA controllers */
500 {
504 {
508 }
509 }
511 }
512 \f
513 /*
514 * ================
515 * = dfx_bus_init =
516 * ================
517 *
518 * Overview:
519 * Initializes EISA and PCI controller bus-specific logic.
520 *
521 * Returns:
522 * None
523 *
524 * Arguments:
525 * dev - pointer to device information
526 *
527 * Functional Description:
528 * Determine and save adapter IRQ in device table,
529 * then perform bus-specific logic initialization.
530 *
531 * Return Codes:
532 * None
533 *
534 * Assumptions:
535 * dev->base_addr has already been set with the proper
536 * base I/O address for this device.
537 *
538 * Side Effects:
539 * Interrupts are enabled at the adapter bus-specific logic.
540 * Note: Interrupts at the DMA engine (PDQ chip) are not
541 * enabled yet.
542 */
545 {
551 /*
552 * Initialize base I/O address field in bp structure
553 *
554 * Note: bp->base_addr is the same as dev->base_addr.
555 * It's useful because often we'll need to read
556 * or write registers where we already have the
557 * bp pointer instead of the dev pointer. Having
558 * the base address in the bp structure will
559 * save a pointer dereference.
560 *
561 * IMPORTANT!! This field must be defined before
562 * any of the dfx_port_* inline functions are
563 * called.
564 */
568 /* And a pointer back to the net_device struct */
571 /* Initialize adapter based on bus type */
574 {
575 /* Get the interrupt level from the ESIC chip */
579 {
595 }
597 /* Enable access to I/O on the board by writing 0x03 to Function Control Register */
601 /* Set the I/O decode range of the board */
607 /* Enable access to rest of module (including PDQ and packet memory) */
611 /*
612 * Map PDQ registers into I/O space. This is done by clearing a bit
613 * in Burst Holdoff register.
614 */
619 /* Enable interrupts at EISA bus interface chip (ESIC) */
623 }
624 else
625 {
628 /* Get the interrupt level from the PCI Configuration Table */
632 /* Check Latency Timer and set if less than minimal */
636 {
639 }
641 /* Enable interrupts at PCI bus interface chip (PFI) */
644 }
646 }
648 \f
649 /*
650 * ========================
651 * = dfx_bus_config_check =
652 * ========================
653 *
654 * Overview:
655 * Checks the configuration (burst size, full-duplex, etc.) If any parameters
656 * are illegal, then this routine will set new defaults.
657 *
658 * Returns:
659 * None
660 *
661 * Arguments:
662 * bp - pointer to board information
663 *
664 * Functional Description:
665 * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later
666 * PDQ, and all FDDI PCI controllers, all values are legal.
667 *
668 * Return Codes:
669 * None
670 *
671 * Assumptions:
672 * dfx_adap_init has NOT been called yet so burst size and other items have
673 * not been set.
674 *
675 * Side Effects:
676 * None
677 */
680 {
687 /* Configuration check only valid for EISA adapter */
690 {
693 /*
694 * First check if revision 2 EISA controller. Rev. 1 cards used
695 * PDQ revision B, so no workaround needed in this case. Rev. 3
696 * cards used PDQ revision E, so no workaround needed in this
697 * case, either. Only Rev. 2 cards used either Rev. D or E
698 * chips, so we must verify the chip revision on Rev. 2 cards.
699 */
702 {
703 /*
704 * Revision 2 FDDI EISA controller found, so let's check PDQ
705 * revision of adapter.
706 */
709 PI_PCTRL_M_SUB_CMD,
710 PI_SUB_CMD_K_PDQ_REV_GET,
714 {
715 /*
716 * Either we couldn't determine the PDQ revision, or
717 * we determined that it is at revision D. In either case,
718 * we need to implement the workaround.
719 */
721 /* Ensure that the burst size is set to 8 longwords or less */
724 {
732 }
734 /* Ensure that full-duplex mode is not enabled */
737 }
738 }
739 }
741 }
743 \f
744 /*
745 * ===================
746 * = dfx_driver_init =
747 * ===================
748 *
749 * Overview:
750 * Initializes remaining adapter board structure information
751 * and makes sure adapter is in a safe state prior to dfx_open().
752 *
753 * Returns:
754 * Condition code
755 *
756 * Arguments:
757 * dev - pointer to device information
758 *
759 * Functional Description:
760 * This function allocates additional resources such as the host memory
761 * blocks needed by the adapter (eg. descriptor and consumer blocks).
762 * Remaining bus initialization steps are also completed. The adapter
763 * is also reset so that it is in the DMA_UNAVAILABLE state. The OS
764 * must call dfx_open() to open the adapter and bring it on-line.
765 *
766 * Return Codes:
767 * DFX_K_SUCCESS - initialization succeeded
768 * DFX_K_FAILURE - initialization failed - could not allocate memory
769 * or read adapter MAC address
770 *
771 * Assumptions:
772 * Memory allocated from kmalloc() call is physically contiguous, locked
773 * memory whose physical address equals its virtual address.
774 *
775 * Side Effects:
776 * Adapter is reset and should be in DMA_UNAVAILABLE state before
777 * returning from this routine.
778 */
781 {
790 /* Initialize bus-specific hardware registers */
794 /*
795 * Initialize default values for configurable parameters
796 *
797 * Note: All of these parameters are ones that a user may
798 * want to customize. It'd be nice to break these
799 * out into Space.c or someplace else that's more
800 * accessible/understandable than this file.
801 */
808 /*
809 * Ensure that HW configuration is OK
810 *
811 * Note: Depending on the hardware revision, we may need to modify
812 * some of the configurable parameters to workaround hardware
813 * limitations. We'll perform this configuration check AFTER
814 * setting the parameters to their default values.
815 */
819 /* Disable PDQ interrupts first */
823 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
827 /* Read the factory MAC address from the adapter then save it */
830 PI_PCTRL_M_MLA,
831 PI_PDATA_A_MLA_K_LO,
834 {
837 }
841 PI_PCTRL_M_MLA,
842 PI_PDATA_A_MLA_K_HI,
845 {
848 }
851 /*
852 * Set current address to factory address
853 *
854 * Note: Node address override support is handled through
855 * dfx_ctl_set_mac_address.
856 */
860 printk("%s: DEFEA at I/O addr = 0x%lX, IRQ = %d, Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
870 else
871 printk("%s: DEFPA at I/O addr = 0x%lX, IRQ = %d, Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
882 /*
883 * Get memory for descriptor block, consumer block, and other buffers
884 * that need to be DMA read or written to by the adapter.
885 */
888 PI_CMD_REQ_K_SIZE_MAX +
889 PI_CMD_RSP_K_SIZE_MAX +
890 #ifndef DYNAMIC_BUFFERS
892 #endif
897 {
900 }
904 /*
905 * To guarantee the 8K alignment required for the descriptor block, 8K - 1
906 * plus the amount of memory needed was allocated. The physical address
907 * is now 8K aligned. By carving up the memory in a specific order,
908 * we'll guarantee the alignment requirements for all other structures.
909 *
910 * Note: If the assumptions change regarding the non-paged, non-cached,
911 * physically contiguous nature of the memory block or the address
912 * alignments, then we'll need to implement a different algorithm
913 * for allocating the needed memory.
914 */
919 /* Reserve space for descriptor block */
926 /* Reserve space for command request buffer */
933 /* Reserve space for command response buffer */
940 /* Reserve space for the LLC host receive queue buffers */
945 #ifndef DYNAMIC_BUFFERS
948 #endif
950 /* Reserve space for the consumer block */
955 /* Display virtual and physical addresses if debug driver */
957 DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n", dev->name, (long)bp->descr_block_virt, bp->descr_block_phys);
958 DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n", dev->name, (long)bp->cmd_req_virt, bp->cmd_req_phys);
959 DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n", dev->name, (long)bp->cmd_rsp_virt, bp->cmd_rsp_phys);
960 DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n", dev->name, (long)bp->rcv_block_virt, bp->rcv_block_phys);
961 DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n", dev->name, (long)bp->cons_block_virt, bp->cons_block_phys);
964 }
966 \f
967 /*
968 * =================
969 * = dfx_adap_init =
970 * =================
971 *
972 * Overview:
973 * Brings the adapter to the link avail/link unavailable state.
974 *
975 * Returns:
976 * Condition code
977 *
978 * Arguments:
979 * bp - pointer to board information
980 *
981 * Functional Description:
982 * Issues the low-level firmware/hardware calls necessary to bring
983 * the adapter up, or to properly reset and restore adapter during
984 * run-time.
985 *
986 * Return Codes:
987 * DFX_K_SUCCESS - Adapter brought up successfully
988 * DFX_K_FAILURE - Adapter initialization failed
989 *
990 * Assumptions:
991 * bp->reset_type should be set to a valid reset type value before
992 * calling this routine.
993 *
994 * Side Effects:
995 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
996 * upon a successful return of this routine.
997 */
1000 {
1003 /* Disable PDQ interrupts first */
1007 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1010 {
1013 }
1015 /*
1016 * When the PDQ is reset, some false Type 0 interrupts may be pending,
1017 * so we'll acknowledge all Type 0 interrupts now before continuing.
1018 */
1022 /*
1023 * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state
1024 *
1025 * Note: We only need to clear host copies of these registers. The PDQ reset
1026 * takes care of the on-board register values.
1027 */
1033 /* Clear consumer block before going to DMA_AVAILABLE state */
1037 /* Initialize the DMA Burst Size */
1040 PI_PCTRL_M_SUB_CMD,
1041 PI_SUB_CMD_K_BURST_SIZE_SET,
1044 {
1047 }
1049 /*
1050 * Set base address of Consumer Block
1051 *
1052 * Assumption: 32-bit physical address of consumer block is 64 byte
1053 * aligned. That is, bits 0-5 of the address must be zero.
1054 */
1057 PI_PCTRL_M_CONS_BLOCK,
1061 {
1064 }
1066 /*
1067 * Set base address of Descriptor Block and bring adapter to DMA_AVAILABLE state
1068 *
1069 * Note: We also set the literal and data swapping requirements in this
1070 * command. Since this driver presently runs on Intel platforms
1071 * which are Little Endian, we'll tell the adapter to byte swap
1072 * data only. This code will need to change when we support
1073 * Big Endian systems (eg. PowerPC).
1074 *
1075 * Assumption: 32-bit physical address of descriptor block is 8Kbyte
1076 * aligned. That is, bits 0-12 of the address must be zero.
1077 */
1080 PI_PCTRL_M_INIT,
1084 {
1087 }
1089 /* Set transmit flush timeout value */
1097 {
1100 }
1102 /* Set the initial values for eFDXEnable and MACTReq MIB objects */
1113 {
1116 }
1118 /* Initialize adapter CAM */
1121 {
1124 }
1126 /* Initialize adapter filters */
1129 {
1132 }
1134 /* Initialize receive descriptor block and produce buffers */
1138 /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */
1142 {
1145 }
1147 /* Initialization succeeded, reenable PDQ interrupts */
1151 }
1153 \f
1154 /*
1155 * ============
1156 * = dfx_open =
1157 * ============
1158 *
1159 * Overview:
1160 * Opens the adapter
1161 *
1162 * Returns:
1163 * Condition code
1164 *
1165 * Arguments:
1166 * dev - pointer to device information
1167 *
1168 * Functional Description:
1169 * This function brings the adapter to an operational state.
1170 *
1171 * Return Codes:
1172 * 0 - Adapter was successfully opened
1173 * -EAGAIN - Could not register IRQ or adapter initialization failed
1174 *
1175 * Assumptions:
1176 * This routine should only be called for a device that was
1177 * initialized successfully.
1178 *
1179 * Side Effects:
1180 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1181 * if the open is successful.
1182 */
1185 {
1190 MOD_INC_USE_COUNT;
1192 /* Register IRQ - support shared interrupts by passing device ptr */
1195 {
1197 MOD_DEC_USE_COUNT;
1199 }
1201 /*
1202 * Set current address to factory MAC address
1203 *
1204 * Note: We've already done this step in dfx_driver_init.
1205 * However, it's possible that a user has set a node
1206 * address override, then closed and reopened the
1207 * adapter. Unless we reset the device address field
1208 * now, we'll continue to use the existing modified
1209 * address.
1210 */
1214 /* Clear local unicast/multicast address tables and counts */
1221 /* Disable promiscuous filter settings */
1228 /* Reset and initialize adapter */
1232 {
1235 MOD_DEC_USE_COUNT;
1237 }
1239 /* Set device structure info */
1242 }
1244 \f
1245 /*
1246 * =============
1247 * = dfx_close =
1248 * =============
1249 *
1250 * Overview:
1251 * Closes the device/module.
1252 *
1253 * Returns:
1254 * Condition code
1255 *
1256 * Arguments:
1257 * dev - pointer to device information
1258 *
1259 * Functional Description:
1260 * This routine closes the adapter and brings it to a safe state.
1261 * The interrupt service routine is deregistered with the OS.
1262 * The adapter can be opened again with another call to dfx_open().
1263 *
1264 * Return Codes:
1265 * Always return 0.
1266 *
1267 * Assumptions:
1268 * No further requests for this adapter are made after this routine is
1269 * called. dfx_open() can be called to reset and reinitialize the
1270 * adapter.
1271 *
1272 * Side Effects:
1273 * Adapter should be in DMA_UNAVAILABLE state upon completion of this
1274 * routine.
1275 */
1278 {
1283 /* Disable PDQ interrupts first */
1287 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1291 /*
1292 * Flush any pending transmit buffers
1293 *
1294 * Note: It's important that we flush the transmit buffers
1295 * BEFORE we clear our copy of the Type 2 register.
1296 * Otherwise, we'll have no idea how many buffers
1297 * we need to free.
1298 */
1302 /*
1303 * Clear Type 1 and Type 2 registers after adapter reset
1304 *
1305 * Note: Even though we're closing the adapter, it's
1306 * possible that an interrupt will occur after
1307 * dfx_close is called. Without some assurance to
1308 * the contrary we want to make sure that we don't
1309 * process receive and transmit LLC frames and update
1310 * the Type 2 register with bad information.
1311 */
1317 /* Clear consumer block for the same reason given above */
1321 /* Clear device structure flags */
1325 /* Deregister (free) IRQ */
1329 MOD_DEC_USE_COUNT;
1331 }
1333 \f
1334 /*
1335 * ======================
1336 * = dfx_int_pr_halt_id =
1337 * ======================
1338 *
1339 * Overview:
1340 * Displays halt id's in string form.
1341 *
1342 * Returns:
1343 * None
1344 *
1345 * Arguments:
1346 * bp - pointer to board information
1347 *
1348 * Functional Description:
1349 * Determine current halt id and display appropriate string.
1350 *
1351 * Return Codes:
1352 * None
1353 *
1354 * Assumptions:
1355 * None
1356 *
1357 * Side Effects:
1358 * None
1359 */
1362 {
1366 /* Read the latest port status */
1370 /* Display halt state transition information */
1374 {
1414 }
1416 }
1418 \f
1419 /*
1420 * ==========================
1421 * = dfx_int_type_0_process =
1422 * ==========================
1423 *
1424 * Overview:
1425 * Processes Type 0 interrupts.
1426 *
1427 * Returns:
1428 * None
1429 *
1430 * Arguments:
1431 * bp - pointer to board information
1432 *
1433 * Functional Description:
1434 * Processes all enabled Type 0 interrupts. If the reason for the interrupt
1435 * is a serious fault on the adapter, then an error message is displayed
1436 * and the adapter is reset.
1437 *
1438 * One tricky potential timing window is the rapid succession of "link avail"
1439 * "link unavail" state change interrupts. The acknowledgement of the Type 0
1440 * interrupt must be done before reading the state from the Port Status
1441 * register. This is true because a state change could occur after reading
1442 * the data, but before acknowledging the interrupt. If this state change
1443 * does happen, it would be lost because the driver is using the old state,
1444 * and it will never know about the new state because it subsequently
1445 * acknowledges the state change interrupt.
1446 *
1447 * INCORRECT CORRECT
1448 * read type 0 int reasons read type 0 int reasons
1449 * read adapter state ack type 0 interrupts
1450 * ack type 0 interrupts read adapter state
1451 * ... process interrupt ... ... process interrupt ...
1452 *
1453 * Return Codes:
1454 * None
1455 *
1456 * Assumptions:
1457 * None
1458 *
1459 * Side Effects:
1460 * An adapter reset may occur if the adapter has any Type 0 error interrupts
1461 * or if the port status indicates that the adapter is halted. The driver
1462 * is responsible for reinitializing the adapter with the current CAM
1463 * contents and adapter filter settings.
1464 */
1468 {
1472 /*
1473 * Read host interrupt Type 0 register to determine which Type 0
1474 * interrupts are pending. Immediately write it back out to clear
1475 * those interrupts.
1476 */
1481 /* Check for Type 0 error interrupts */
1484 PI_TYPE_0_STAT_M_PM_PAR_ERR |
1485 PI_TYPE_0_STAT_M_BUS_PAR_ERR))
1486 {
1487 /* Check for Non-Existent Memory error */
1492 /* Check for Packet Memory Parity error */
1497 /* Check for Host Bus Parity error */
1502 /* Reset adapter and bring it back on-line */
1508 {
1512 }
1515 }
1517 /* Check for transmit flush interrupt */
1520 {
1521 /* Flush any pending xmt's and acknowledge the flush interrupt */
1526 PI_PCTRL_M_XMT_DATA_FLUSH_DONE,
1529 NULL);
1530 }
1532 /* Check for adapter state change */
1535 {
1536 /* Get latest adapter state */
1540 {
1541 /*
1542 * Adapter has transitioned to HALTED state, try to reset
1543 * adapter to bring it back on-line. If reset fails,
1544 * leave the adapter in the broken state.
1545 */
1550 /* Reset adapter and bring it back on-line */
1556 {
1560 }
1562 }
1564 {
1566 }
1567 }
1569 }
1571 \f
1572 /*
1573 * ==================
1574 * = dfx_int_common =
1575 * ==================
1576 *
1577 * Overview:
1578 * Interrupt service routine (ISR)
1579 *
1580 * Returns:
1581 * None
1582 *
1583 * Arguments:
1584 * bp - pointer to board information
1585 *
1586 * Functional Description:
1587 * This is the ISR which processes incoming adapter interrupts.
1588 *
1589 * Return Codes:
1590 * None
1591 *
1592 * Assumptions:
1593 * This routine assumes PDQ interrupts have not been disabled.
1594 * When interrupts are disabled at the PDQ, the Port Status register
1595 * is automatically cleared. This routine uses the Port Status
1596 * register value to determine whether a Type 0 interrupt occurred,
1597 * so it's important that adapter interrupts are not normally
1598 * enabled/disabled at the PDQ.
1599 *
1600 * It's vital that this routine is NOT reentered for the
1601 * same board and that the OS is not in another section of
1602 * code (eg. dfx_xmt_queue_pkt) for the same board on a
1603 * different thread.
1604 *
1605 * Side Effects:
1606 * Pending interrupts are serviced. Depending on the type of
1607 * interrupt, acknowledging and clearing the interrupt at the
1608 * PDQ involves writing a register to clear the interrupt bit
1609 * or updating completion indices.
1610 */
1613 {
1617 /* Process xmt interrupts - frequent case, so always call this routine */
1622 /* Process rcv interrupts - frequent case, so always call this routine */
1626 /*
1627 * Transmit and receive producer and completion indices are updated on the
1628 * adapter by writing to the Type 2 Producer register. Since the frequent
1629 * case is that we'll be processing either LLC transmit or receive buffers,
1630 * we'll optimize I/O writes by doing a single register write here.
1631 */
1635 /* Read PDQ Port Status register to find out which interrupts need processing */
1639 /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */
1644 }
1646 \f
1647 /*
1648 * =================
1649 * = dfx_interrupt =
1650 * =================
1651 *
1652 * Overview:
1653 * Interrupt processing routine
1654 *
1655 * Returns:
1656 * None
1657 *
1658 * Arguments:
1659 * irq - interrupt vector
1660 * dev_id - pointer to device information
1661 * regs - pointer to registers structure
1662 *
1663 * Functional Description:
1664 * This routine calls the interrupt processing routine for this adapter. It
1665 * disables and reenables adapter interrupts, as appropriate. We can support
1666 * shared interrupts since the incoming dev_id pointer provides our device
1667 * structure context.
1668 *
1669 * Return Codes:
1670 * None
1671 *
1672 * Assumptions:
1673 * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC
1674 * on Intel-based systems) is done by the operating system outside this
1675 * routine.
1676 *
1677 * System interrupts are enabled through this call.
1678 *
1679 * Side Effects:
1680 * Interrupts are disabled, then reenabled at the adapter.
1681 */
1684 {
1689 /* Get board pointer only if device structure is valid */
1695 /* See if we're already servicing an interrupt */
1697 /* Service adapter interrupts */
1700 {
1701 /* Disable PDQ-PFI interrupts at PFI */
1705 /* Call interrupt service routine for this adapter */
1709 /* Clear PDQ interrupt status bit and reenable interrupts */
1714 }
1715 else
1716 {
1717 /* Disable interrupts at the ESIC */
1723 /* Call interrupt service routine for this adapter */
1727 /* Reenable interrupts at the ESIC */
1732 }
1736 }
1738 \f
1739 /*
1740 * =====================
1741 * = dfx_ctl_get_stats =
1742 * =====================
1743 *
1744 * Overview:
1745 * Get statistics for FDDI adapter
1746 *
1747 * Returns:
1748 * Pointer to FDDI statistics structure
1749 *
1750 * Arguments:
1751 * dev - pointer to device information
1752 *
1753 * Functional Description:
1754 * Gets current MIB objects from adapter, then
1755 * returns FDDI statistics structure as defined
1756 * in if_fddi.h.
1757 *
1758 * Note: Since the FDDI statistics structure is
1759 * still new and the device structure doesn't
1760 * have an FDDI-specific get statistics handler,
1761 * we'll return the FDDI statistics structure as
1762 * a pointer to an Ethernet statistics structure.
1763 * That way, at least the first part of the statistics
1764 * structure can be decoded properly, and it allows
1765 * "smart" applications to perform a second cast to
1766 * decode the FDDI-specific statistics.
1767 *
1768 * We'll have to pay attention to this routine as the
1769 * device structure becomes more mature and LAN media
1770 * independent.
1771 *
1772 * Return Codes:
1773 * None
1774 *
1775 * Assumptions:
1776 * None
1777 *
1778 * Side Effects:
1779 * None
1780 */
1783 {
1786 /* Fill the bp->stats structure with driver-maintained counters */
1792 bp->stats.rx_errors = (u32)(bp->rcv_crc_errors + bp->rcv_frame_status_errors + bp->rcv_length_errors);
1799 /* Get FDDI SMT MIB objects */
1805 /* Fill the bp->stats structure with the SMT MIB object values */
1807 memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id));
1811 memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data));
1826 bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag;
1830 bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls;
1831 bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions;
1836 memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN);
1837 memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN);
1838 memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN);
1839 memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN);
1843 memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN);
1860 memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration));
1865 bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0];
1866 bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1];
1871 memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3);
1872 memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3);
1879 bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0];
1880 bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1];
1900 /* Get FDDI counters */
1906 /* Fill the bp->stats structure with the FDDI counter values */
1921 }
1923 \f
1924 /*
1925 * ==============================
1926 * = dfx_ctl_set_multicast_list =
1927 * ==============================
1928 *
1929 * Overview:
1930 * Enable/Disable LLC frame promiscuous mode reception
1931 * on the adapter and/or update multicast address table.
1932 *
1933 * Returns:
1934 * None
1935 *
1936 * Arguments:
1937 * dev - pointer to device information
1938 *
1939 * Functional Description:
1940 * This routine follows a fairly simple algorithm for setting the
1941 * adapter filters and CAM:
1942 *
1943 * if IFF_PROMISC flag is set
1944 * enable LLC individual/group promiscuous mode
1945 * else
1946 * disable LLC individual/group promiscuous mode
1947 * if number of incoming multicast addresses >
1948 * (CAM max size - number of unicast addresses in CAM)
1949 * enable LLC group promiscuous mode
1950 * set driver-maintained multicast address count to zero
1951 * else
1952 * disable LLC group promiscuous mode
1953 * set driver-maintained multicast address count to incoming count
1954 * update adapter CAM
1955 * update adapter filters
1956 *
1957 * Return Codes:
1958 * None
1959 *
1960 * Assumptions:
1961 * Multicast addresses are presented in canonical (LSB) format.
1962 *
1963 * Side Effects:
1964 * On-board adapter CAM and filters are updated.
1965 */
1968 {
1973 /* Enable LLC frame promiscuous mode, if necessary */
1978 /* Else, update multicast address table */
1980 else
1981 {
1983 /*
1984 * Check whether incoming multicast address count exceeds table size
1985 *
1986 * Note: The adapters utilize an on-board 64 entry CAM for
1987 * supporting perfect filtering of multicast packets
1988 * and bridge functions when adding unicast addresses.
1989 * There is no hash function available. To support
1990 * additional multicast addresses, the all multicast
1991 * filter (LLC group promiscuous mode) must be enabled.
1992 *
1993 * The firmware reserves two CAM entries for SMT-related
1994 * multicast addresses, which leaves 62 entries available.
1995 * The following code ensures that we're not being asked
1996 * to add more than 62 addresses to the CAM. If we are,
1997 * the driver will enable the all multicast filter.
1998 * Should the number of multicast addresses drop below
1999 * the high water mark, the filter will be disabled and
2000 * perfect filtering will be used.
2001 */
2004 {
2007 }
2008 else
2009 {
2012 }
2014 /* Copy addresses to multicast address table, then update adapter CAM */
2018 {
2021 }
2023 {
2025 }
2026 else
2027 {
2028 DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count);
2029 }
2030 }
2032 /* Update adapter filters */
2035 {
2037 }
2038 else
2039 {
2041 }
2043 }
2045 \f
2046 /*
2047 * ===========================
2048 * = dfx_ctl_set_mac_address =
2049 * ===========================
2050 *
2051 * Overview:
2052 * Add node address override (unicast address) to adapter
2053 * CAM and update dev_addr field in device table.
2054 *
2055 * Returns:
2056 * None
2057 *
2058 * Arguments:
2059 * dev - pointer to device information
2060 * addr - pointer to sockaddr structure containing unicast address to add
2061 *
2062 * Functional Description:
2063 * The adapter supports node address overrides by adding one or more
2064 * unicast addresses to the adapter CAM. This is similar to adding
2065 * multicast addresses. In this routine we'll update the driver and
2066 * device structures with the new address, then update the adapter CAM
2067 * to ensure that the adapter will copy and strip frames destined and
2068 * sourced by that address.
2069 *
2070 * Return Codes:
2071 * Always returns zero.
2072 *
2073 * Assumptions:
2074 * The address pointed to by addr->sa_data is a valid unicast
2075 * address and is presented in canonical (LSB) format.
2076 *
2077 * Side Effects:
2078 * On-board adapter CAM is updated. On-board adapter filters
2079 * may be updated.
2080 */
2083 {
2087 /* Copy unicast address to driver-maintained structs and update count */
2093 /*
2094 * Verify we're not exceeding the CAM size by adding unicast address
2095 *
2096 * Note: It's possible that before entering this routine we've
2097 * already filled the CAM with 62 multicast addresses.
2098 * Since we need to place the node address override into
2099 * the CAM, we have to check to see that we're not
2100 * exceeding the CAM size. If we are, we have to enable
2101 * the LLC group (multicast) promiscuous mode filter as
2102 * in dfx_ctl_set_multicast_list.
2103 */
2106 {
2110 /* Update adapter filters */
2113 {
2115 }
2116 else
2117 {
2119 }
2120 }
2122 /* Update adapter CAM with new unicast address */
2125 {
2127 }
2128 else
2129 {
2131 }
2133 }
2135 \f
2136 /*
2137 * ======================
2138 * = dfx_ctl_update_cam =
2139 * ======================
2140 *
2141 * Overview:
2142 * Procedure to update adapter CAM (Content Addressable Memory)
2143 * with desired unicast and multicast address entries.
2144 *
2145 * Returns:
2146 * Condition code
2147 *
2148 * Arguments:
2149 * bp - pointer to board information
2150 *
2151 * Functional Description:
2152 * Updates adapter CAM with current contents of board structure
2153 * unicast and multicast address tables. Since there are only 62
2154 * free entries in CAM, this routine ensures that the command
2155 * request buffer is not overrun.
2156 *
2157 * Return Codes:
2158 * DFX_K_SUCCESS - Request succeeded
2159 * DFX_K_FAILURE - Request failed
2160 *
2161 * Assumptions:
2162 * All addresses being added (unicast and multicast) are in canonical
2163 * order.
2164 *
2165 * Side Effects:
2166 * On-board adapter CAM is updated.
2167 */
2170 {
2174 /*
2175 * Fill in command request information
2176 *
2177 * Note: Even though both the unicast and multicast address
2178 * table entries are stored as contiguous 6 byte entries,
2179 * the firmware address filter set command expects each
2180 * entry to be two longwords (8 bytes total). We must be
2181 * careful to only copy the six bytes of each unicast and
2182 * multicast table entry into each command entry. This
2183 * is also why we must first clear the entire command
2184 * request buffer.
2185 */
2191 /* Now add unicast addresses to command request buffer, if any */
2194 {
2196 {
2199 }
2200 }
2202 /* Now add multicast addresses to command request buffer, if any */
2205 {
2207 {
2210 }
2211 }
2213 /* Issue command to update adapter CAM, then return */
2218 }
2220 \f
2221 /*
2222 * ==========================
2223 * = dfx_ctl_update_filters =
2224 * ==========================
2225 *
2226 * Overview:
2227 * Procedure to update adapter filters with desired
2228 * filter settings.
2229 *
2230 * Returns:
2231 * Condition code
2232 *
2233 * Arguments:
2234 * bp - pointer to board information
2235 *
2236 * Functional Description:
2237 * Enables or disables filter using current filter settings.
2238 *
2239 * Return Codes:
2240 * DFX_K_SUCCESS - Request succeeded.
2241 * DFX_K_FAILURE - Request failed.
2242 *
2243 * Assumptions:
2244 * We must always pass up packets destined to the broadcast
2245 * address (FF-FF-FF-FF-FF-FF), so we'll always keep the
2246 * broadcast filter enabled.
2247 *
2248 * Side Effects:
2249 * On-board adapter filters are updated.
2250 */
2253 {
2256 /* Fill in command request information */
2260 /* Initialize Broadcast filter - * ALWAYS ENABLED * */
2265 /* Initialize LLC Individual/Group Promiscuous filter */
2270 /* Initialize LLC Group Promiscuous filter */
2275 /* Terminate the item code list */
2279 /* Issue command to update adapter filters, then return */
2284 }
2286 \f
2287 /*
2288 * ======================
2289 * = dfx_hw_dma_cmd_req =
2290 * ======================
2291 *
2292 * Overview:
2293 * Sends PDQ DMA command to adapter firmware
2294 *
2295 * Returns:
2296 * Condition code
2297 *
2298 * Arguments:
2299 * bp - pointer to board information
2300 *
2301 * Functional Description:
2302 * The command request and response buffers are posted to the adapter in the manner
2303 * described in the PDQ Port Specification:
2304 *
2305 * 1. Command Response Buffer is posted to adapter.
2306 * 2. Command Request Buffer is posted to adapter.
2307 * 3. Command Request consumer index is polled until it indicates that request
2308 * buffer has been DMA'd to adapter.
2309 * 4. Command Response consumer index is polled until it indicates that response
2310 * buffer has been DMA'd from adapter.
2311 *
2312 * This ordering ensures that a response buffer is already available for the firmware
2313 * to use once it's done processing the request buffer.
2314 *
2315 * Return Codes:
2316 * DFX_K_SUCCESS - DMA command succeeded
2317 * DFX_K_OUTSTATE - Adapter is NOT in proper state
2318 * DFX_K_HW_TIMEOUT - DMA command timed out
2319 *
2320 * Assumptions:
2321 * Command request buffer has already been filled with desired DMA command.
2322 *
2323 * Side Effects:
2324 * None
2325 */
2328 {
2332 /* Make sure the adapter is in a state that we can issue the DMA command in */
2341 /* Put response buffer on the command response queue */
2347 /* Bump (and wrap) the producer index and write out to register */
2353 /* Put request buffer on the command request queue */
2359 /* Bump (and wrap) the producer index and write out to register */
2365 /*
2366 * Here we wait for the command request consumer index to be equal
2367 * to the producer, indicating that the adapter has DMAed the request.
2368 */
2371 {
2375 }
2379 /* Bump (and wrap) the completion index and write out to register */
2385 /*
2386 * Here we wait for the command response consumer index to be equal
2387 * to the producer, indicating that the adapter has DMAed the response.
2388 */
2391 {
2395 }
2399 /* Bump (and wrap) the completion index and write out to register */
2405 }
2407 \f
2408 /*
2409 * ========================
2410 * = dfx_hw_port_ctrl_req =
2411 * ========================
2412 *
2413 * Overview:
2414 * Sends PDQ port control command to adapter firmware
2415 *
2416 * Returns:
2417 * Host data register value in host_data if ptr is not NULL
2418 *
2419 * Arguments:
2420 * bp - pointer to board information
2421 * command - port control command
2422 * data_a - port data A register value
2423 * data_b - port data B register value
2424 * host_data - ptr to host data register value
2425 *
2426 * Functional Description:
2427 * Send generic port control command to adapter by writing
2428 * to various PDQ port registers, then polling for completion.
2429 *
2430 * Return Codes:
2431 * DFX_K_SUCCESS - port control command succeeded
2432 * DFX_K_HW_TIMEOUT - port control command timed out
2433 *
2434 * Assumptions:
2435 * None
2436 *
2437 * Side Effects:
2438 * None
2439 */
2443 PI_UINT32 command,
2444 PI_UINT32 data_a,
2445 PI_UINT32 data_b,
2446 PI_UINT32 *host_data
2447 )
2449 {
2453 /* Set Command Error bit in command longword */
2457 /* Issue port command to the adapter */
2463 /* Now wait for command to complete */
2467 else
2471 {
2476 }
2480 /*
2481 * If the address of host_data is non-zero, assume caller has supplied a
2482 * non NULL pointer, and return the contents of the HOST_DATA register in
2483 * it.
2484 */
2489 }
2491 \f
2492 /*
2493 * =====================
2494 * = dfx_hw_adap_reset =
2495 * =====================
2496 *
2497 * Overview:
2498 * Resets adapter
2499 *
2500 * Returns:
2501 * None
2502 *
2503 * Arguments:
2504 * bp - pointer to board information
2505 * type - type of reset to perform
2506 *
2507 * Functional Description:
2508 * Issue soft reset to adapter by writing to PDQ Port Reset
2509 * register. Use incoming reset type to tell adapter what
2510 * kind of reset operation to perform.
2511 *
2512 * Return Codes:
2513 * None
2514 *
2515 * Assumptions:
2516 * This routine merely issues a soft reset to the adapter.
2517 * It is expected that after this routine returns, the caller
2518 * will appropriately poll the Port Status register for the
2519 * adapter to enter the proper state.
2520 *
2521 * Side Effects:
2522 * Internal adapter registers are cleared.
2523 */
2527 PI_UINT32 type
2528 )
2530 {
2531 /* Set Reset type and assert reset */
2536 /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */
2540 /* Deassert reset */
2544 }
2546 \f
2547 /*
2548 * ========================
2549 * = dfx_hw_adap_state_rd =
2550 * ========================
2551 *
2552 * Overview:
2553 * Returns current adapter state
2554 *
2555 * Returns:
2556 * Adapter state per PDQ Port Specification
2557 *
2558 * Arguments:
2559 * bp - pointer to board information
2560 *
2561 * Functional Description:
2562 * Reads PDQ Port Status register and returns adapter state.
2563 *
2564 * Return Codes:
2565 * None
2566 *
2567 * Assumptions:
2568 * None
2569 *
2570 * Side Effects:
2571 * None
2572 */
2575 {
2580 }
2582 \f
2583 /*
2584 * =====================
2585 * = dfx_hw_dma_uninit =
2586 * =====================
2587 *
2588 * Overview:
2589 * Brings adapter to DMA_UNAVAILABLE state
2590 *
2591 * Returns:
2592 * Condition code
2593 *
2594 * Arguments:
2595 * bp - pointer to board information
2596 * type - type of reset to perform
2597 *
2598 * Functional Description:
2599 * Bring adapter to DMA_UNAVAILABLE state by performing the following:
2600 * 1. Set reset type bit in Port Data A Register then reset adapter.
2601 * 2. Check that adapter is in DMA_UNAVAILABLE state.
2602 *
2603 * Return Codes:
2604 * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state
2605 * DFX_K_HW_TIMEOUT - adapter did not reset properly
2606 *
2607 * Assumptions:
2608 * None
2609 *
2610 * Side Effects:
2611 * Internal adapter registers are cleared.
2612 */
2615 {
2618 /* Set reset type bit and reset adapter */
2622 /* Now wait for adapter to enter DMA_UNAVAILABLE state */
2625 {
2629 }
2633 }
2636 /*
2637 * Align an sk_buff to a boundary power of 2
2638 *
2639 */
2642 {
2644 u32 v;
2649 }
2651 \f
2652 /*
2653 * ================
2654 * = dfx_rcv_init =
2655 * ================
2656 *
2657 * Overview:
2658 * Produces buffers to adapter LLC Host receive descriptor block
2659 *
2660 * Returns:
2661 * None
2662 *
2663 * Arguments:
2664 * bp - pointer to board information
2665 *
2666 * Functional Description:
2667 * This routine can be called during dfx_adap_init() or during an adapter
2668 * reset. It initializes the descriptor block and produces all allocated
2669 * LLC Host queue receive buffers.
2670 *
2671 * Return Codes:
2672 * None
2673 *
2674 * Assumptions:
2675 * The PDQ has been reset and the adapter and driver maintained Type 2
2676 * register indices are cleared.
2677 *
2678 * Side Effects:
2679 * Receive buffers are posted to the adapter LLC queue and the adapter
2680 * is notified.
2681 */
2684 {
2687 /*
2688 * Since each receive buffer is a single fragment of same length, initialize
2689 * first longword in each receive descriptor for entire LLC Host descriptor
2690 * block. Also initialize second longword in each receive descriptor with
2691 * physical address of receive buffer. We'll always allocate receive
2692 * buffers in powers of 2 so that we can easily fill the 256 entry descriptor
2693 * block and produce new receive buffers by simply updating the receive
2694 * producer index.
2695 *
2696 * Assumptions:
2697 * To support all shipping versions of PDQ, the receive buffer size
2698 * must be mod 128 in length and the physical address must be 128 byte
2699 * aligned. In other words, bits 0-6 of the length and address must
2700 * be zero for the following descriptor field entries to be correct on
2701 * all PDQ-based boards. We guaranteed both requirements during
2702 * driver initialization when we allocated memory for the receive buffers.
2703 */
2705 #ifdef DYNAMIC_BUFFERS
2708 {
2713 /*
2714 * align to 128 bytes for compatibility with
2715 * the old EISA boards.
2716 */
2720 /*
2721 * p_rcv_buff_va is only used inside the
2722 * kernel so we put the skb pointer here.
2723 */
2725 }
2726 #else
2729 {
2732 bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX));
2734 }
2735 #endif
2737 /* Update receive producer and Type 2 register */
2742 }
2744 \f
2745 /*
2746 * =========================
2747 * = dfx_rcv_queue_process =
2748 * =========================
2749 *
2750 * Overview:
2751 * Process received LLC frames.
2752 *
2753 * Returns:
2754 * None
2755 *
2756 * Arguments:
2757 * bp - pointer to board information
2758 *
2759 * Functional Description:
2760 * Received LLC frames are processed until there are no more consumed frames.
2761 * Once all frames are processed, the receive buffers are returned to the
2762 * adapter. Note that this algorithm fixes the length of time that can be spent
2763 * in this routine, because there are a fixed number of receive buffers to
2764 * process and buffers are not produced until this routine exits and returns
2765 * to the ISR.
2766 *
2767 * Return Codes:
2768 * None
2769 *
2770 * Assumptions:
2771 * None
2772 *
2773 * Side Effects:
2774 * None
2775 */
2778 DFX_board_t *bp
2779 )
2781 {
2787 /* Service all consumed LLC receive frames */
2791 {
2792 /* Process any errors */
2797 #ifdef DYNAMIC_BUFFERS
2799 #else
2801 #endif
2805 {
2808 else
2810 }
2811 else
2812 {
2815 /* The frame was received without errors - verify packet length */
2822 #ifdef DYNAMIC_BUFFERS
2838 #endif
2841 {
2845 }
2847 #ifndef DYNAMIC_BUFFERS
2849 #endif
2850 {
2851 /* Receive buffer allocated, pass receive packet up */
2854 }
2863 /* Update the rcv counters */
2870 }
2871 }
2872 }
2874 /*
2875 * Advance the producer (for recycling) and advance the completion
2876 * (for servicing received frames). Note that it is okay to
2877 * advance the producer without checking that it passes the
2878 * completion index because they are both advanced at the same
2879 * rate.
2880 */
2884 }
2886 }
2888 \f
2889 /*
2890 * =====================
2891 * = dfx_xmt_queue_pkt =
2892 * =====================
2893 *
2894 * Overview:
2895 * Queues packets for transmission
2896 *
2897 * Returns:
2898 * Condition code
2899 *
2900 * Arguments:
2901 * skb - pointer to sk_buff to queue for transmission
2902 * dev - pointer to device information
2903 *
2904 * Functional Description:
2905 * Here we assume that an incoming skb transmit request
2906 * is contained in a single physically contiguous buffer
2907 * in which the virtual address of the start of packet
2908 * (skb->data) can be converted to a physical address
2909 * by using virt_to_bus().
2910 *
2911 * Since the adapter architecture requires a three byte
2912 * packet request header to prepend the start of packet,
2913 * we'll write the three byte field immediately prior to
2914 * the FC byte. This assumption is valid because we've
2915 * ensured that dev->hard_header_len includes three pad
2916 * bytes. By posting a single fragment to the adapter,
2917 * we'll reduce the number of descriptor fetches and
2918 * bus traffic needed to send the request.
2919 *
2920 * Also, we can't free the skb until after it's been DMA'd
2921 * out by the adapter, so we'll queue it in the driver and
2922 * return it in dfx_xmt_done.
2923 *
2924 * Return Codes:
2925 * 0 - driver queued packet, link is unavailable, or skbuff was bad
2926 * 1 - caller should requeue the sk_buff for later transmission
2927 *
2928 * Assumptions:
2929 * First and foremost, we assume the incoming skb pointer
2930 * is NOT NULL and is pointing to a valid sk_buff structure.
2931 *
2932 * The outgoing packet is complete, starting with the
2933 * frame control byte including the last byte of data,
2934 * but NOT including the 4 byte CRC. We'll let the
2935 * adapter hardware generate and append the CRC.
2936 *
2937 * The entire packet is stored in one physically
2938 * contiguous buffer which is not cached and whose
2939 * 32-bit physical address can be determined.
2940 *
2941 * It's vital that this routine is NOT reentered for the
2942 * same board and that the OS is not in another section of
2943 * code (eg. dfx_int_common) for the same board on a
2944 * different thread.
2945 *
2946 * Side Effects:
2947 * None
2948 */
2953 )
2955 {
2964 /*
2965 * Verify that incoming transmit request is OK
2966 *
2967 * Note: The packet size check is consistent with other
2968 * Linux device drivers, although the correct packet
2969 * size should be verified before calling the
2970 * transmit routine.
2971 */
2974 {
2981 }
2982 /*
2983 * See if adapter link is available, if not, free buffer
2984 *
2985 * Note: If the link isn't available, free buffer and return 0
2986 * rather than tell the upper layer to requeue the packet.
2987 * The methodology here is that by the time the link
2988 * becomes available, the packet to be sent will be
2989 * fairly stale. By simply dropping the packet, the
2990 * higher layer protocols will eventually time out
2991 * waiting for response packets which it won't receive.
2992 */
2995 {
2998 else
2999 {
3004 }
3005 }
3009 /* Get the current producer and the next free xmt data descriptor */
3014 /*
3015 * Get pointer to auxiliary queue entry to contain information
3016 * for this packet.
3017 *
3018 * Note: The current xmt producer index will become the
3019 * current xmt completion index when we complete this
3020 * packet later on. So, we'll get the pointer to the
3021 * next auxiliary queue entry now before we bump the
3022 * producer index.
3023 */
3027 /* Write the three PRH bytes immediately before the FC byte */
3034 /*
3035 * Write the descriptor with buffer info and bump producer
3036 *
3037 * Note: Since we need to start DMA from the packet request
3038 * header, we'll add 3 bytes to the DMA buffer length,
3039 * and we'll determine the physical address of the
3040 * buffer from the PRH, not skb->data.
3041 *
3042 * Assumptions:
3043 * 1. Packet starts with the frame control (FC) byte
3044 * at skb->data.
3045 * 2. The 4-byte CRC is not appended to the buffer or
3046 * included in the length.
3047 * 3. Packet length (skb->len) is from FC to end of
3048 * data, inclusive.
3049 * 4. The packet length does not exceed the maximum
3050 * FDDI LLC frame length of 4491 bytes.
3051 * 5. The entire packet is contained in a physically
3052 * contiguous, non-cached, locked memory space
3053 * comprised of a single buffer pointed to by
3054 * skb->data.
3055 * 6. The physical address of the start of packet
3056 * can be determined from the virtual address
3057 * by using virt_to_bus() and is only 32-bits
3058 * wide.
3059 */
3061 p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN));
3064 /*
3065 * Verify that descriptor is actually available
3066 *
3067 * Note: If descriptor isn't available, return 1 which tells
3068 * the upper layer to requeue the packet for later
3069 * transmission.
3070 *
3071 * We need to ensure that the producer never reaches the
3072 * completion, except to indicate that the queue is empty.
3073 */
3076 {
3080 }
3082 /*
3083 * Save info for this packet for xmt done indication routine
3084 *
3085 * Normally, we'd save the producer index in the p_xmt_drv_descr
3086 * structure so that we'd have it handy when we complete this
3087 * packet later (in dfx_xmt_done). However, since the current
3088 * transmit architecture guarantees a single fragment for the
3089 * entire packet, we can simply bump the completion index by
3090 * one (1) for each completed packet.
3091 *
3092 * Note: If this assumption changes and we're presented with
3093 * an inconsistent number of transmit fragments for packet
3094 * data, we'll need to modify this code to save the current
3095 * transmit producer index.
3096 */
3100 /* Update Type 2 register */
3107 }
3109 \f
3110 /*
3111 * ================
3112 * = dfx_xmt_done =
3113 * ================
3114 *
3115 * Overview:
3116 * Processes all frames that have been transmitted.
3117 *
3118 * Returns:
3119 * None
3120 *
3121 * Arguments:
3122 * bp - pointer to board information
3123 *
3124 * Functional Description:
3125 * For all consumed transmit descriptors that have not
3126 * yet been completed, we'll free the skb we were holding
3127 * onto using dev_kfree_skb and bump the appropriate
3128 * counters.
3129 *
3130 * Return Codes:
3131 * None
3132 *
3133 * Assumptions:
3134 * The Type 2 register is not updated in this routine. It is
3135 * assumed that it will be updated in the ISR when dfx_xmt_done
3136 * returns.
3137 *
3138 * Side Effects:
3139 * None
3140 */
3143 {
3148 /* Service all consumed transmit frames */
3152 {
3153 /* Get pointer to the transmit driver descriptor block information */
3157 /* Increment transmit counters */
3162 /* Return skb to operating system */
3166 /*
3167 * Move to start of next packet by updating completion index
3168 *
3169 * Here we assume that a transmit packet request is always
3170 * serviced by posting one fragment. We can therefore
3171 * simplify the completion code by incrementing the
3172 * completion index by one. This code will need to be
3173 * modified if this assumption changes. See comments
3174 * in dfx_xmt_queue_pkt for more details.
3175 */
3178 freed++;
3179 }
3181 }
3183 \f
3184 /*
3185 * =================
3186 * = dfx_xmt_flush =
3187 * =================
3188 *
3189 * Overview:
3190 * Processes all frames whether they've been transmitted
3191 * or not.
3192 *
3193 * Returns:
3194 * None
3195 *
3196 * Arguments:
3197 * bp - pointer to board information
3198 *
3199 * Functional Description:
3200 * For all produced transmit descriptors that have not
3201 * yet been completed, we'll free the skb we were holding
3202 * onto using dev_kfree_skb and bump the appropriate
3203 * counters. Of course, it's possible that some of
3204 * these transmit requests actually did go out, but we
3205 * won't make that distinction here. Finally, we'll
3206 * update the consumer index to match the producer.
3207 *
3208 * Return Codes:
3209 * None
3210 *
3211 * Assumptions:
3212 * This routine does NOT update the Type 2 register. It
3213 * is assumed that this routine is being called during a
3214 * transmit flush interrupt, or a shutdown or close routine.
3215 *
3216 * Side Effects:
3217 * None
3218 */
3221 {
3225 /* Flush all outstanding transmit frames */
3228 {
3229 /* Get pointer to the transmit driver descriptor block information */
3233 /* Return skb to operating system */
3237 /* Increment transmit error counter */
3241 /*
3242 * Move to start of next packet by updating completion index
3243 *
3244 * Here we assume that a transmit packet request is always
3245 * serviced by posting one fragment. We can therefore
3246 * simplify the completion code by incrementing the
3247 * completion index by one. This code will need to be
3248 * modified if this assumption changes. See comments
3249 * in dfx_xmt_queue_pkt for more details.
3250 */
3253 }
3255 /* Update the transmit consumer index in the consumer block */
3261 }
3264 {
3271 }
3274 {
3278 }
3283 };
3291 };
3298 {
3302 {
3310 }
3311 }
3314 {
3324 }
3327 {
3333 }
3338 \f
3339 /*
3340 * Local variables:
3341 * kernel-compile-command: "gcc -D__KERNEL__ -I/root/linux/include -Wall -Wstrict-prototypes -O2 -pipe -fomit-frame-pointer -fno-strength-reduce -m486 -malign-loops=2 -malign-jumps=2 -malign-functions=2 -c defxx.c"
3342 * End:
3343 */