drivers/net/tulip/tulip.h

   1 /*
   2         drivers/net/tulip/tulip.h
   3
   4         Copyright 2000  The Linux Kernel Team
   5         Written/copyright 1994-1999 by Donald Becker.
   6
   7         This software may be used and distributed according to the terms
   8         of the GNU Public License, incorporated herein by reference.
   9
  10 */
  11
  12 #ifndef __NET_TULIP_H__
  13 #define __NET_TULIP_H__
  14
  15 #include <linux/kernel.h>
  16 #include <linux/types.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/netdevice.h>
  19 #include <linux/timer.h>
  20 #include <asm/io.h>
  21
  22
  23
  24 /* undefine, or define to various debugging levels (>4 == obscene levels) */
  25 #undef TULIP_DEBUG
  26
  27
  28 #ifdef TULIP_DEBUG
  29 /* note: prints function name for you */
  30 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
  31 #else
  32 #define DPRINTK(fmt, args...)
  33 #endif
  34
  35
  36
  37
  38 struct tulip_chip_table {
  39         char *chip_name;
  40         int io_size;
  41         int valid_intrs;        /* CSR7 interrupt enable settings */
  42         int flags;
  43         void (*media_timer) (unsigned long data);
  44 };
  45
  46
  47 enum tbl_flag {
  48         HAS_MII = 1,
  49         HAS_MEDIA_TABLE = 2,
  50         CSR12_IN_SROM = 4,
  51         ALWAYS_CHECK_MII = 8,
  52         HAS_ACPI = 0x10,
  53         MC_HASH_ONLY = 0x20,    /* Hash-only multicast filter. */
  54         HAS_PNICNWAY = 0x80,
  55         HAS_NWAY = 0x40,        /* Uses internal NWay xcvr. */
  56         HAS_INTR_MITIGATION = 0x100,
  57         IS_ASIX = 0x200,
  58         HAS_8023X = 0x400,
  59 };
  60
  61
  62 /* chip types.  careful!  order is VERY IMPORTANT here, as these
  63  * are used throughout the driver as indices into arrays */
  64 /* Note 21142 == 21143. */
  65 enum chips {
  66         DC21040 = 0,
  67         DC21041 = 1,
  68         DC21140 = 2,
  69         DC21142 = 3, DC21143 = 3,
  70         LC82C168,
  71         MX98713,
  72         MX98715,
  73         MX98725,
  74         AX88140,
  75         PNIC2,
  76         COMET,
  77         COMPEX9881,
  78         I21145,
  79         DM910X,
  80 };
  81
  82
  83 enum MediaIs {
  84         MediaIsFD = 1,
  85         MediaAlwaysFD = 2,
  86         MediaIsMII = 4,
  87         MediaIsFx = 8,
  88         MediaIs100 = 16
  89 };
  90
  91
  92 /* Offsets to the Command and Status Registers, "CSRs".  All accesses
  93    must be longword instructions and quadword aligned. */
  94 enum tulip_offsets {
  95         CSR0 = 0,
  96         CSR1 = 0x08,
  97         CSR2 = 0x10,
  98         CSR3 = 0x18,
  99         CSR4 = 0x20,
 100         CSR5 = 0x28,
 101         CSR6 = 0x30,
 102         CSR7 = 0x38,
 103         CSR8 = 0x40,
 104         CSR9 = 0x48,
 105         CSR10 = 0x50,
 106         CSR11 = 0x58,
 107         CSR12 = 0x60,
 108         CSR13 = 0x68,
 109         CSR14 = 0x70,
 110         CSR15 = 0x78
 111 };
 112
 113
 114 /* The bits in the CSR5 status registers, mostly interrupt sources. */
 115 enum status_bits {
 116         TimerInt = 0x800,
 117         SytemError = 0x2000,
 118         TPLnkFail = 0x1000,
 119         TPLnkPass = 0x10,
 120         NormalIntr = 0x10000,
 121         AbnormalIntr = 0x8000,
 122         RxJabber = 0x200,
 123         RxDied = 0x100,
 124         RxNoBuf = 0x80,
 125         RxIntr = 0x40,
 126         TxFIFOUnderflow = 0x20,
 127         TxJabber = 0x08,
 128         TxNoBuf = 0x04,
 129         TxDied = 0x02,
 130         TxIntr = 0x01,
 131 };
 132
 133
 134 /* The Tulip Rx and Tx buffer descriptors. */
 135 struct tulip_rx_desc {
 136         s32 status;
 137         s32 length;
 138         u32 buffer1;
 139         u32 buffer2;
 140 };
 141
 142
 143 struct tulip_tx_desc {
 144         s32 status;
 145         s32 length;
 146         u32 buffer1;
 147         u32 buffer2;            /* We use only buffer 1.  */
 148 };
 149
 150
 151 enum desc_status_bits {
 152         DescOwned = 0x80000000,
 153         RxDescFatalErr = 0x8000,
 154         RxWholePkt = 0x0300,
 155 };
 156
 157
 158 enum t21041_csr13_bits {
 159         csr13_eng = (0xEF0<<4), /* for eng. purposes only, hardcode at EF0h */
 160         csr13_aui = (1<<3), /* clear to force 10bT, set to force AUI/BNC */
 161         csr13_cac = (1<<2), /* CSR13/14/15 autoconfiguration */
 162         csr13_srl = (1<<0), /* When reset, resets all SIA functions, machines */
 163
 164         csr13_mask_auibnc = (csr13_eng | csr13_aui | csr13_cac | csr13_srl),
 165         csr13_mask_10bt = (csr13_eng | csr13_cac | csr13_srl),
 166 };
 167
 168 enum t21143_csr6_bits {
 169         csr6_sc = (1<<31),
 170         csr6_ra = (1<<30),
 171         csr6_ign_dest_msb = (1<<26),
 172         csr6_mbo = (1<<25),
 173         csr6_scr = (1<<24),  /* scramble mode flag: can't be set */
 174         csr6_pcs = (1<<23),  /* Enables PCS functions (symbol mode requires csr6_ps be set) default is set */
 175         csr6_ttm = (1<<22),  /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */
 176         csr6_sf = (1<<21),   /* Store and forward. If set ignores TR bits */
 177         csr6_hbd = (1<<19),  /* Heart beat disable. Disables SQE function in 10baseT */
 178         csr6_ps = (1<<18),   /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */
 179         csr6_ca = (1<<17),   /* Collision Offset Enable. If set uses special algorithm in low collision situations */
 180         csr6_trh = (1<<15),  /* Transmit Threshold high bit */
 181         csr6_trl = (1<<14),  /* Transmit Threshold low bit */
 182
 183         /***************************************************************
 184          * This table shows transmit threshold values based on media   *
 185          * and these two registers (from PNIC1 & 2 docs) Note: this is *
 186          * all meaningless if sf is set.                               *
 187          ***************************************************************/
 188
 189         /***********************************
 190          * (trh,trl) * 100BaseTX * 10BaseT *
 191          ***********************************
 192          *   (0,0)   *     128   *    72   *
 193          *   (0,1)   *     256   *    96   *
 194          *   (1,0)   *     512   *   128   *
 195          *   (1,1)   *    1024   *   160   *
 196          ***********************************/
 197
 198         csr6_st = (1<<13),   /* Transmit conrol: 1 = transmit, 0 = stop */
 199         csr6_fc = (1<<12),   /* Forces a collision in next transmission (for testing in loopback mode) */
 200         csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */
 201         csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */
 202         /* set both and you get (PHY) loopback */
 203         csr6_fd = (1<<9),    /* Full duplex mode, disables hearbeat, no loopback */
 204         csr6_pm = (1<<7),    /* Pass All Multicast */
 205         csr6_pr = (1<<6),    /* Promiscuous mode */
 206         csr6_sb = (1<<5),    /* Start(1)/Stop(0) backoff counter */
 207         csr6_if = (1<<4),    /* Inverse Filtering, rejects only addresses in address table: can't be set */
 208         csr6_pb = (1<<3),    /* Pass Bad Frames, (1) causes even bad frames to be passed on */
 209         csr6_ho = (1<<2),    /* Hash-only filtering mode: can't be set */
 210         csr6_sr = (1<<1),    /* Start(1)/Stop(0) Receive */
 211         csr6_hp = (1<<0),    /* Hash/Perfect Receive Filtering Mode: can't be set */
 212
 213         csr6_mask_capture = (csr6_sc | csr6_ca),
 214         csr6_mask_defstate = (csr6_mask_capture | csr6_mbo),
 215         csr6_mask_hdcap = (csr6_mask_defstate | csr6_hbd | csr6_ps),
 216         csr6_mask_hdcaptt = (csr6_mask_hdcap  | csr6_trh | csr6_trl),
 217         csr6_mask_fullcap = (csr6_mask_hdcaptt | csr6_fd),
 218         csr6_mask_fullpromisc = (csr6_pr | csr6_pm),
 219         csr6_mask_filters = (csr6_hp | csr6_ho | csr6_if),
 220         csr6_mask_100bt = (csr6_scr | csr6_pcs | csr6_hbd),
 221 };
 222
 223
 224 /* Keep the ring sizes a power of two for efficiency.
 225    Making the Tx ring too large decreases the effectiveness of channel
 226    bonding and packet priority.
 227    There are no ill effects from too-large receive rings. */
 228 #define TX_RING_SIZE    16
 229 #define RX_RING_SIZE    32
 230
 231
 232 #define PKT_BUF_SZ              1536    /* Size of each temporary Rx buffer. */
 233
 234
 235 /* Ring-wrap flag in length field, use for last ring entry.
 236         0x01000000 means chain on buffer2 address,
 237         0x02000000 means use the ring start address in CSR2/3.
 238    Note: Some work-alike chips do not function correctly in chained mode.
 239    The ASIX chip works only in chained mode.
 240    Thus we indicates ring mode, but always write the 'next' field for
 241    chained mode as well.
 242 */
 243 #define DESC_RING_WRAP 0x02000000
 244
 245
 246 /*  EEPROM_Ctrl bits. */
 247 #define EE_SHIFT_CLK    0x02    /* EEPROM shift clock. */
 248 #define EE_CS                   0x01    /* EEPROM chip select. */
 249 #define EE_DATA_WRITE   0x04    /* Data from the Tulip to EEPROM. */
 250 #define EE_WRITE_0              0x01
 251 #define EE_WRITE_1              0x05
 252 #define EE_DATA_READ    0x08    /* Data from the EEPROM chip. */
 253 #define EE_ENB                  (0x4800 | EE_CS)
 254
 255 /* Delay between EEPROM clock transitions.
 256    Even at 33Mhz current PCI implementations don't overrun the EEPROM clock.
 257    We add a bus turn-around to insure that this remains true. */
 258 #define eeprom_delay()  inl(ee_addr)
 259
 260 /* The EEPROM commands include the alway-set leading bit. */
 261 #define EE_READ_CMD             (6)
 262
 263 #define EEPROM_SIZE 128         /* 2 << EEPROM_ADDRLEN */
 264
 265
 266 /* The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually
 267    met by back-to-back PCI I/O cycles, but we insert a delay to avoid
 268    "overclocking" issues or future 66Mhz PCI. */
 269 #define mdio_delay() inl(mdio_addr)
 270
 271 /* Read and write the MII registers using software-generated serial
 272    MDIO protocol.  It is just different enough from the EEPROM protocol
 273    to not share code.  The maxium data clock rate is 2.5 Mhz. */
 274 #define MDIO_SHIFT_CLK  0x10000
 275 #define MDIO_DATA_WRITE0 0x00000
 276 #define MDIO_DATA_WRITE1 0x20000
 277 #define MDIO_ENB                0x00000         /* Ignore the 0x02000 databook setting. */
 278 #define MDIO_ENB_IN             0x40000
 279 #define MDIO_DATA_READ  0x80000
 280
 281
 282 #define RUN_AT(x) (jiffies + (x))
 283
 284
 285 #if defined(__i386__)                   /* AKA get_unaligned() */
 286 #define get_u16(ptr) (*(u16 *)(ptr))
 287 #else
 288 #define get_u16(ptr) (((u8*)(ptr))[0] + (((u8*)(ptr))[1]<<8))
 289 #endif
 290
 291 struct medialeaf {
 292         u8 type;
 293         u8 media;
 294         unsigned char *leafdata;
 295 };
 296
 297
 298 struct mediatable {
 299         u16 defaultmedia;
 300         u8 leafcount;
 301         u8 csr12dir;            /* General purpose pin directions. */
 302         unsigned has_mii:1;
 303         unsigned has_nonmii:1;
 304         unsigned has_reset:6;
 305         u32 csr15dir;
 306         u32 csr15val;           /* 21143 NWay setting. */
 307         struct medialeaf mleaf[0];
 308 };
 309
 310
 311 struct mediainfo {
 312         struct mediainfo *next;
 313         int info_type;
 314         int index;
 315         unsigned char *info;
 316 };
 317
 318 struct ring_info {
 319         struct sk_buff  *skb;
 320         dma_addr_t      mapping;
 321 };
 322
 323
 324 struct tulip_private {
 325         const char *product_name;
 326         struct net_device *next_module;
 327         struct tulip_rx_desc *rx_ring;
 328         struct tulip_tx_desc *tx_ring;
 329         dma_addr_t rx_ring_dma;
 330         dma_addr_t tx_ring_dma;
 331         /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 332         struct ring_info tx_buffers[TX_RING_SIZE];
 333         /* The addresses of receive-in-place skbuffs. */
 334         struct ring_info rx_buffers[RX_RING_SIZE];
 335         u16 setup_frame[96];    /* Pseudo-Tx frame to init address table. */
 336         int chip_id;
 337         int revision;
 338         int flags;
 339         struct net_device_stats stats;
 340         struct timer_list timer;        /* Media selection timer. */
 341         spinlock_t lock;
 342         unsigned int cur_rx, cur_tx;    /* The next free ring entry */
 343         unsigned int dirty_rx, dirty_tx;        /* The ring entries to be free()ed. */
 344         unsigned int full_duplex:1;     /* Full-duplex operation requested. */
 345         unsigned int full_duplex_lock:1;
 346         unsigned int fake_addr:1;       /* Multiport board faked address. */
 347         unsigned int default_port:4;    /* Last dev->if_port value. */
 348         unsigned int media2:4;  /* Secondary monitored media port. */
 349         unsigned int medialock:1;       /* Don't sense media type. */
 350         unsigned int mediasense:1;      /* Media sensing in progress. */
 351         unsigned int nway:1, nwayset:1;         /* 21143 internal NWay. */
 352         unsigned int csr0;      /* CSR0 setting. */
 353         unsigned int csr6;      /* Current CSR6 control settings. */
 354         unsigned char eeprom[EEPROM_SIZE];      /* Serial EEPROM contents. */
 355         void (*link_change) (struct net_device * dev, int csr5);
 356         u16 to_advertise;       /* NWay capabilities advertised.  */
 357         u16 lpar;               /* 21143 Link partner ability. */
 358         u16 advertising[4];
 359         signed char phys[4], mii_cnt;   /* MII device addresses. */
 360         struct mediatable *mtable;
 361         int cur_index;          /* Current media index. */
 362         int saved_if_port;
 363         struct pci_dev *pdev;
 364         int ttimer;
 365         int susp_rx;
 366         unsigned long nir;
 367         unsigned long base_addr;
 368         int pad0, pad1;         /* Used for 8-byte alignment */
 369 };
 370
 371
 372 struct eeprom_fixup {
 373         char *name;
 374         unsigned char addr0;
 375         unsigned char addr1;
 376         unsigned char addr2;
 377         u16 newtable[32];       /* Max length below. */
 378 };
 379
 380
 381 /* 21142.c */
 382 extern u16 t21142_csr14[];
 383 void t21142_timer(unsigned long data);
 384 void t21142_start_nway(struct net_device *dev);
 385 void t21142_lnk_change(struct net_device *dev, int csr5);
 386
 387 /* eeprom.c */
 388 void tulip_parse_eeprom(struct net_device *dev);
 389 int tulip_read_eeprom(long ioaddr, int location, int addr_len);
 390
 391 /* interrupt.c */
 392 extern unsigned int tulip_max_interrupt_work;
 393 extern int tulip_rx_copybreak;
 394 void tulip_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
 395
 396 /* media.c */
 397 int tulip_mdio_read(struct net_device *dev, int phy_id, int location);
 398 void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int value);
 399 void tulip_select_media(struct net_device *dev, int startup);
 400 int tulip_check_duplex(struct net_device *dev);
 401
 402 /* pnic.c */
 403 void pnic_do_nway(struct net_device *dev);
 404 void pnic_lnk_change(struct net_device *dev, int csr5);
 405 void pnic_timer(unsigned long data);
 406
 407 /* timer.c */
 408 void tulip_timer(unsigned long data);
 409 void mxic_timer(unsigned long data);
 410 void comet_timer(unsigned long data);
 411
 412 /* tulip_core.c */
 413 extern int tulip_debug;
 414 extern const char * const medianame[];
 415 extern const char tulip_media_cap[];
 416 extern struct tulip_chip_table tulip_tbl[];
 417 extern u8 t21040_csr13[];
 418 extern u16 t21041_csr13[];
 419 extern u16 t21041_csr14[];
 420 extern u16 t21041_csr15[];
 421
 422
 423 static inline void tulip_outl_csr (struct tulip_private *tp, u32 newValue, enum tulip_offsets offset)
 424 {
 425         outl (newValue, tp->base_addr + offset);
 426 }
 427
 428 static inline void tulip_stop_rxtx(struct tulip_private *tp, u32 csr6mask)
 429 {
 430         tulip_outl_csr(tp, csr6mask & ~(csr6_st | csr6_sr), CSR6);
 431 }
 432
 433 static inline void tulip_restart_rxtx(struct tulip_private *tp, u32 csr6mask)
 434 {
 435         tulip_outl_csr(tp, csr6mask | csr6_sr, CSR6);
 436         tulip_outl_csr(tp, csr6mask | csr6_st | csr6_sr, CSR6);
 437 }
 438
 439 #endif /* __NET_TULIP_H__ */