drivers/ahci.c

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
   3  * Author: Jason Jin<Jason.jin@freescale.com>
   4  *         Zhang Wei<wei.zhang@freescale.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  *
  24  * with the reference on libata and ahci drvier in kernel
  25  *
  26  */
  27 /* #define DEBUG */
  28 #include <common.h>
  29
  30 #ifdef CONFIG_SCSI_AHCI
  31
  32 #include <command.h>
  33 #include <pci.h>
  34 #include <asm/processor.h>
  35 #include <asm/errno.h>
  36 #include <asm/io.h>
  37 #include <malloc.h>
  38 #include <scsi.h>
  39 #include <ata.h>
  40 #include <linux/ctype.h>
  41 #include <ahci.h>
  42
  43 struct ahci_probe_ent *probe_ent = NULL;
  44 hd_driveid_t *ataid[AHCI_MAX_PORTS];
  45
  46 #define writel_with_flush(a,b)  do { writel(a,b); readl(b); } while (0)
  47
  48
  49 static inline u32 ahci_port_base(u32 base, u32 port)
  50 {
  51         return base + 0x100 + (port * 0x80);
  52 }
  53
  54
  55 static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
  56                             unsigned int port_idx)
  57 {
  58         base = ahci_port_base(base, port_idx);
  59
  60         port->cmd_addr = base;
  61         port->scr_addr = base + PORT_SCR;
  62 }
  63
  64
  65 #define msleep(a) udelay(a * 1000)
  66 #define ssleep(a) msleep(a * 1000)
  67
  68 static int waiting_for_cmd_completed(volatile u8 *offset,
  69                                      int timeout_msec,
  70                                      u32 sign)
  71 {
  72         int i;
  73         u32 status;
  74
  75         for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
  76                 msleep(1);
  77
  78         return (i < timeout_msec) ? 0 : -1;
  79 }
  80
  81
  82 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
  83 {
  84         pci_dev_t pdev = probe_ent->dev;
  85         volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
  86         u32 tmp, cap_save;
  87         u16 tmp16;
  88         int i, j;
  89         volatile u8 *port_mmio;
  90         unsigned short vendor;
  91
  92         cap_save = readl(mmio + HOST_CAP);
  93         cap_save &= ((1 << 28) | (1 << 17));
  94         cap_save |= (1 << 27);
  95
  96         /* global controller reset */
  97         tmp = readl(mmio + HOST_CTL);
  98         if ((tmp & HOST_RESET) == 0)
  99                 writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
 100
 101         /* reset must complete within 1 second, or
 102          * the hardware should be considered fried.
 103          */
 104         ssleep(1);
 105
 106         tmp = readl(mmio + HOST_CTL);
 107         if (tmp & HOST_RESET) {
 108                 debug("controller reset failed (0x%x) addr (0x%x) \n", tmp, (mmio + HOST_CTL));
 109                 return -1;
 110         }
 111
 112         writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
 113         writel(cap_save, mmio + HOST_CAP);
 114         writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
 115
 116         pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
 117
 118         if (vendor == PCI_VENDOR_ID_INTEL) {
 119                 u16 tmp16;
 120                 pci_read_config_word(pdev, 0x92, &tmp16);
 121                 tmp16 |= 0xf;
 122                 pci_write_config_word(pdev, 0x92, tmp16);
 123         }
 124
 125         probe_ent->cap = readl(mmio + HOST_CAP);
 126         probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
 127         probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
 128
 129         debug("cap 0x%x  port_map 0x%x  n_ports %d\n",
 130               probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
 131
 132         for (i = 0; i < probe_ent->n_ports; i++) {
 133                 probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
 134                 port_mmio = (u8 *) probe_ent->port[i].port_mmio;
 135                 ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
 136
 137                 /* make sure port is not active */
 138                 tmp = readl(port_mmio + PORT_CMD);
 139                 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
 140                            PORT_CMD_FIS_RX | PORT_CMD_START)) {
 141                         tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
 142                                  PORT_CMD_FIS_RX | PORT_CMD_START);
 143                         writel_with_flush(tmp, port_mmio + PORT_CMD);
 144
 145                         /* spec says 500 msecs for each bit, so
 146                          * this is slightly incorrect.
 147                          */
 148                         msleep(500);
 149                 }
 150
 151                 /* writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); Yotam */
 152
 153                 j = 0;
 154                 while (j < 100) {
 155                         msleep(10);
 156                         tmp = readl(port_mmio + PORT_SCR_STAT);
 157                         if ((tmp & 0xf) == 0x3)
 158                                 break;
 159                         j++;
 160                 }
 161
 162                 tmp = readl(port_mmio + PORT_SCR_ERR);
 163                 debug("PORT_SCR_ERR 0x%x\n", tmp);
 164                 writel(tmp, port_mmio + PORT_SCR_ERR);
 165
 166                 /* ack any pending irq events for this port */
 167                 tmp = readl(port_mmio + PORT_IRQ_STAT);
 168                 debug("PORT_IRQ_STAT 0x%x\n", tmp);
 169                 if (tmp)
 170                         writel(tmp, port_mmio + PORT_IRQ_STAT);
 171
 172                 writel(1 << i, mmio + HOST_IRQ_STAT);
 173
 174                 /* set irq mask (enables interrupts) */
 175                 /* writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); yotam */
 176
 177                 /*register linkup ports */
 178                 tmp = readl(port_mmio + PORT_SCR_STAT);
 179                 debug("Port %d status: 0x%x\n", i, tmp);
 180                 if ((tmp & 0xf) == 0x03)
 181                         probe_ent->link_port_map |= (0x01 << i);
 182         }
 183
 184         tmp = readl(mmio + HOST_CTL);
 185         debug("HOST_CTL 0x%x\n", tmp);
 186         /* writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); yotam */
 187         tmp = readl(mmio + HOST_CTL);
 188         debug("HOST_CTL 0x%x\n", tmp);
 189
 190         pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
 191         tmp |= PCI_COMMAND_MASTER;
 192         pci_write_config_word(pdev, PCI_COMMAND, tmp16);
 193
 194         return 0;
 195 }
 196
 197
 198 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
 199 {
 200         pci_dev_t pdev = probe_ent->dev;
 201         volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
 202         u32 vers, cap, impl, speed;
 203         const char *speed_s;
 204         u16 cc;
 205         const char *scc_s;
 206
 207         vers = readl(mmio + HOST_VERSION);
 208         cap = probe_ent->cap;
 209         impl = probe_ent->port_map;
 210
 211         speed = (cap >> 20) & 0xf;
 212         if (speed == 1)
 213                 speed_s = "1.5";
 214         else if (speed == 2)
 215                 speed_s = "3";
 216         else
 217                 speed_s = "?";
 218
 219         pci_read_config_word(pdev, 0x0a, &cc);
 220         if (cc == 0x0101)
 221                 scc_s = "IDE";
 222         else if (cc == 0x0106)
 223                 scc_s = "SATA";
 224         else if (cc == 0x0104)
 225                 scc_s = "RAID";
 226         else
 227                 scc_s = "unknown";
 228
 229         printf("AHCI %02x%02x.%02x%02x "
 230                "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
 231                (vers >> 24) & 0xff,
 232                (vers >> 16) & 0xff,
 233                (vers >> 8) & 0xff,
 234                vers & 0xff,
 235                ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
 236
 237         printf("flags: "
 238                "%s%s%s%s%s%s"
 239                "%s%s%s%s%s%s%s\n",
 240                cap & (1 << 31) ? "64bit " : "",
 241                cap & (1 << 30) ? "ncq " : "",
 242                cap & (1 << 28) ? "ilck " : "",
 243                cap & (1 << 27) ? "stag " : "",
 244                cap & (1 << 26) ? "pm " : "",
 245                cap & (1 << 25) ? "led " : "",
 246                cap & (1 << 24) ? "clo " : "",
 247                cap & (1 << 19) ? "nz " : "",
 248                cap & (1 << 18) ? "only " : "",
 249                cap & (1 << 17) ? "pmp " : "",
 250                cap & (1 << 15) ? "pio " : "",
 251                cap & (1 << 14) ? "slum " : "",
 252                cap & (1 << 13) ? "part " : "");
 253 }
 254
 255 #if (defined(CONFIG_MARVELL) && defined(__ARM__))
 256 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)pdev, a)
 257 #define phys_to_bus(a) (a)
 258 #else
 259 #define bus_to_phys(a)  pci_mem_to_phys((pci_dev_t)pdev, a)
 260 #define phys_to_bus(a)  pci_phys_to_mem((pci_dev_t)pdev, a)
 261 #endif
 262
 263 static int ahci_init_one(pci_dev_t pdev)
 264 {
 265         u32 iobase, vendor, device, rmw;
 266         int rc;
 267
 268         memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
 269
 270         probe_ent = malloc(sizeof(probe_ent));
 271         memset(probe_ent, 0, sizeof(probe_ent));
 272         probe_ent->dev = pdev;
 273
 274         pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase);
 275         iobase &= ~0xf;
 276
 277         probe_ent->host_flags = ATA_FLAG_SATA
 278                                 | ATA_FLAG_NO_LEGACY
 279                                 | ATA_FLAG_MMIO
 280                                 | ATA_FLAG_PIO_DMA
 281                                 | ATA_FLAG_NO_ATAPI;
 282         probe_ent->pio_mask = 0x1f;
 283         probe_ent->udma_mask = 0x7f;    /*Fixme,assume to support UDMA6 */
 284
 285         probe_ent->mmio_base = bus_to_phys (iobase);
 286
 287         /* Take from kernel:
 288          * JMicron-specific fixup:
 289          * make sure we're in AHCI mode
 290          */
 291         pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
 292         if (vendor == 0x197b)
 293                 pci_write_config_byte(pdev, 0x41, 0xa1);
 294
 295         /* Take from kernel:
 296          * Marvell specific fixup:
 297          * Change SATA phy to scontroller mode
 298          */
 299 /*
 300         pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
 301         printf ("ahci_match : vendor 0x%x\n",vendor);
 302         if (vendor == 0x11ab)
 303         {
 304                 pci_read_config_word(pdev, PCI_DEVICE_ID, &device);
 305                 device &= 0xffff;
 306                 printf ("ahci_match : device 0x%x\n",device);
 307
 308                 if ((device == 0x6121) || (device == 0x6145))
 309                 {
 310                         printf ("ahci_match : Switching SATA phy to be controlled by Scontrol\n");
 311                         pci_read_config_word(pdev, PCI_CB_SUBSYSTEM_VENDOR_ID, &rmw);
 312                         printf ("ahci_match addr 0x40 value 0x%x\n", rmw);
 313 */
 314 //                      rmw = rmw & 0xff3fffff; /* Clear bit 22 and 23 */
 315 /*                      printf ("ahci_match addr 0x40 value 0x%x\n", rmw);
 316                         pci_write_config_byte(pdev, PCI_CB_SUBSYSTEM_VENDOR_ID, rmw);
 317                 }
 318         }
 319 */
 320         /* initialize adapter */
 321         rc = ahci_host_init(probe_ent);
 322         if (rc)
 323                 goto err_out;
 324
 325         ahci_print_info(probe_ent);
 326
 327         return 0;
 328
 329       err_out:
 330         return rc;
 331 }
 332
 333
 334 #define MAX_DATA_BYTE_COUNT  (4*1024*1024)
 335
 336 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
 337 {
 338         struct ahci_ioports *pp = &(probe_ent->port[port]);
 339         struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
 340         u32 sg_count;
 341         int i;
 342
 343         sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
 344         if (sg_count > AHCI_MAX_SG) {
 345                 printf("Error:Too much sg!\n");
 346                 return -1;
 347         }
 348
 349         for (i = 0; i < sg_count; i++) {
 350                 ahci_sg->addr =
 351                     cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
 352                 ahci_sg->addr_hi = 0;
 353                 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
 354                                           (buf_len < MAX_DATA_BYTE_COUNT
 355                                            ? (buf_len - 1)
 356                                            : (MAX_DATA_BYTE_COUNT - 1)));
 357                 ahci_sg++;
 358                 buf_len -= MAX_DATA_BYTE_COUNT;
 359         }
 360
 361         return sg_count;
 362 }
 363
 364
 365 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
 366 {
 367         pp->cmd_slot->opts = cpu_to_le32(opts);
 368         pp->cmd_slot->status = 0;
 369         pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
 370         pp->cmd_slot->tbl_addr_hi = 0;
 371 }
 372
 373
 374 static void ahci_set_feature(u8 port)
 375 {
 376         struct ahci_ioports *pp = &(probe_ent->port[port]);
 377         volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
 378         u32 cmd_fis_len = 5;    /* five dwords */
 379         u8 fis[20];
 380
 381         /*set feature */
 382         memset(fis, 0, 20);
 383         fis[0] = 0x27;
 384         fis[1] = 1 << 7;
 385         fis[2] = ATA_CMD_SETF;
 386         fis[3] = SETFEATURES_XFER;
 387         fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
 388
 389         memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
 390         ahci_fill_cmd_slot(pp, cmd_fis_len);
 391         writel(1, port_mmio + PORT_CMD_ISSUE);
 392         readl(port_mmio + PORT_CMD_ISSUE);
 393
 394         if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
 395                 printf("set feature error!\n");
 396         }
 397 }
 398
 399
 400 static int ahci_port_start(u8 port)
 401 {
 402         struct ahci_ioports *pp = &(probe_ent->port[port]);
 403         volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
 404         u32 port_status;
 405         u32 mem;
 406
 407         debug("Enter start port: %d\n", port);
 408         port_status = readl(port_mmio + PORT_SCR_STAT);
 409         debug("Port %d status: %x\n", port, port_status);
 410         if ((port_status & 0xf) != 0x03) {
 411                 printf("No Link on this port!\n");
 412                 return -1;
 413         }
 414
 415         mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 4096);
 416         if (!mem) {
 417                 free(pp);
 418                 printf("No mem for table!\n");
 419                 return -ENOMEM;
 420         }
 421
 422         mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
 423         memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
 424
 425         /*
 426          * First item in chunk of DMA memory: 32-slot command table,
 427          * 32 bytes each in size
 428          */
 429         pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
 430         debug("cmd_slot = 0x%x\n", pp->cmd_slot);
 431         /* mem += (AHCI_CMD_SLOT_SZ + 224); */
 432         mem += 2048;
 433
 434         /*
 435          * Second item: Received-FIS area
 436          */
 437         pp->rx_fis = mem;
 438         /* mem += AHCI_RX_FIS_SZ; */
 439         mem += 1024;
 440
 441         /*
 442          * Third item: data area for storing a single command
 443          * and its scatter-gather table
 444          */
 445         pp->cmd_tbl = mem;
 446         debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
 447
 448         mem += AHCI_CMD_TBL_HDR;
 449         pp->cmd_tbl_sg = (struct ahci_sg *)mem;
 450
 451         writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
 452
 453         writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
 454
 455 /*      writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
 456                           PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
 457                           PORT_CMD_START, port_mmio + PORT_CMD);
 458 */
 459         writel_with_flush(PORT_CMD_FIS_RX | PORT_CMD_START | 0x20, port_mmio + PORT_CMD);
 460         debug("Exit start port %d\n", port);
 461
 462         return 0;
 463 }
 464
 465
 466 static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf,
 467                                 int buf_len)
 468 {
 469
 470         struct ahci_ioports *pp = &(probe_ent->port[port]);
 471         volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
 472         u32 opts;
 473         u32 port_status;
 474         int sg_count;
 475         int i;
 476
 477         debug("Enter get_ahci_device_data: for port %d addr mmio 0x%x\n", port, port_mmio);
 478
 479         if (port > probe_ent->n_ports) {
 480                 printf("Invaild port number %d\n", port);
 481                 return -1;
 482         }
 483
 484         port_status = readl(port_mmio + PORT_SCR_STAT);
 485         if ((port_status & 0xf) != 0x03) {
 486                 debug("No Link on port %d!\n", port);
 487                 return -1;
 488         }
 489
 490         debug("Enter get_ahci_device_data: fis data\n");
 491         for (i=0; i < fis_len; i++)
 492         {
 493                 debug("%p:%02x\n", &fis[i], fis[i]);
 494         }
 495
 496         memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
 497
 498         debug("Enter get_ahci_device_data: pp->cmd_tbl 0x%p \n",pp->cmd_tbl );
 499         for (i=0; i < fis_len; i++)
 500         {
 501                 debug("%p:%02x\n", &(((unsigned char *)(pp->cmd_tbl))[i]), ((unsigned char *)(pp->cmd_tbl))[i]);
 502         }
 503         debug("Enter get_ahci_device_data: buf 0x%x buf_len 0x%x\n",buf,buf_len );
 504         sg_count = ahci_fill_sg(port, buf, buf_len);
 505         opts = (fis_len >> 2) | (sg_count << 16);
 506         ahci_fill_cmd_slot(pp, opts);
 507
 508         writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
 509
 510         if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 1500, 0x1)) {
 511                 printf("timeout exit!\n");
 512                 return -1;
 513         }
 514         debug("get_ahci_device_data: %d byte transferred.\n",
 515               pp->cmd_slot->status);
 516
 517         return 0;
 518 }
 519
 520
 521 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
 522 {
 523         int i;
 524         for (i = 0; i < len / 2; i++)
 525                 /* Swap 16bit for display - on memory this data is */
 526                 /* in big endian */
 527                 target[i] = __swab16(src[i]);
 528         return (char *)target;
 529 }
 530
 531
 532 static void dump_ataid(hd_driveid_t *ataid)
 533 {
 534         debug("(49)ataid->capability = 0x%x\n", ataid->capability);
 535         debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
 536         debug("(60)ataid->lba_capacity =0x%x\n", ataid->lba_capacity);
 537         debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
 538         debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
 539         debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
 540         debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
 541         debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
 542         debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
 543         debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
 544         debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
 545         debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
 546         debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
 547         debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
 548         debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
 549         debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
 550 }
 551
 552
 553 /*
 554  * SCSI INQUIRY command operation.
 555  */
 556 static int ata_scsiop_inquiry(ccb *pccb)
 557 {
 558         u8 hdr[] = {
 559                 0,
 560                 0,
 561                 0x5,            /* claim SPC-3 version compatibility */
 562                 2,
 563                 95 - 4,
 564         };
 565         u8 fis[20];
 566         u8 *tmpid;
 567         u8 port;
 568         u16 i;
 569
 570         /* Clean ccb data buffer */
 571         memset(pccb->pdata, 0, pccb->datalen);
 572
 573         memcpy(pccb->pdata, hdr, sizeof(hdr));
 574
 575         if (pccb->datalen <= 35)
 576                 return 0;
 577
 578         memset(fis, 0, 20);
 579         /* Construct the FIS */
 580         fis[0] = 0x27;          /* Host to device FIS. */
 581         fis[1] = 1 << 7;        /* Command FIS. */
 582         fis[2] = ATA_CMD_IDENT; /* Command byte. */
 583
 584         /* Read id from sata */
 585         port = pccb->target;
 586         if (!(tmpid = malloc(sizeof(hd_driveid_t))))
 587                 return -ENOMEM;
 588
 589         if (get_ahci_device_data(port, (u8 *) & fis, 20,
 590                                  tmpid, sizeof(hd_driveid_t))) {
 591                 debug("scsi_ahci: SCSI inquiry command failure.\n");
 592                 return -EIO;
 593         }
 594
 595         if (ataid[port])
 596                 free(ataid[port]);
 597         ataid[port] = (hd_driveid_t *) tmpid;
 598
 599         short* tmp = (short *)tmpid;
 600
 601         memcpy(&pccb->pdata[8], "ATA     ", 8);
 602         ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);
 603         ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);
 604
 605         dump_ataid(ataid[port]);
 606         return 0;
 607 }
 608
 609
 610 /*
 611  * SCSI READ10 command operation.
 612  */
 613 static int ata_scsiop_read10(ccb * pccb)
 614 {
 615         u64 lba = 0;
 616         u32 len = 0;
 617         u8 fis[20];
 618
 619         lba = (((u64) pccb->cmd[2]) << 24) | (((u64) pccb->cmd[3]) << 16)
 620             | (((u64) pccb->cmd[4]) << 8) | ((u64) pccb->cmd[5]);
 621         len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]);
 622
 623         /* For 10-byte and 16-byte SCSI R/W commands, transfer
 624          * length 0 means transfer 0 block of data.
 625          * However, for ATA R/W commands, sector count 0 means
 626          * 256 or 65536 sectors, not 0 sectors as in SCSI.
 627          *
 628          * WARNING: one or two older ATA drives treat 0 as 0...
 629          */
 630         if (!len)
 631                 return 0;
 632         memset(fis, 0, 20);
 633
 634         /* Construct the FIS */
 635         fis[0] = 0x27;          /* Host to device FIS. */
 636         fis[1] = 1 << 7;        /* Command FIS. */
 637         fis[2] = ATA_CMD_RD_DMA;        /* Command byte. */
 638
 639         /* LBA address, only support LBA28 in this driver */
 640         fis[4] = pccb->cmd[5];
 641         fis[5] = pccb->cmd[4];
 642         fis[6] = pccb->cmd[3];
 643         fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0;
 644
 645         /* Sector Count */
 646         fis[12] = pccb->cmd[8];
 647         fis[13] = pccb->cmd[7];
 648
 649         /* Read from ahci */
 650         if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20,
 651                                  pccb->pdata, pccb->datalen)) {
 652                 debug("scsi_ahci: SCSI READ10 command failure.\n");
 653                 return -EIO;
 654         }
 655
 656         return 0;
 657 }
 658
 659
 660 /*
 661  * SCSI READ CAPACITY10 command operation.
 662  */
 663 static int ata_scsiop_read_capacity10(ccb *pccb)
 664 {
 665         u8 buf[8];
 666
 667         if (!ataid[pccb->target]) {
 668                 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
 669                        "\tNo ATA info!\n"
 670                        "\tPlease run SCSI commmand INQUIRY firstly!\n");
 671                 return -EPERM;
 672         }
 673
 674         memset(buf, 0, 8);
 675
 676         /* Swap 32bit for display - on memory this data is */
 677         /* in little endian but this field in the buffer is in big endian format */
 678         *(u32 *) buf = __swab32(ataid[pccb->target]->lba_capacity);
 679
 680         buf[6] = 512 >> 8;
 681         buf[7] = 512 & 0xff;
 682
 683         memcpy(pccb->pdata, buf, 8);
 684
 685         return 0;
 686 }
 687
 688
 689 /*
 690  * SCSI TEST UNIT READY command operation.
 691  */
 692 static int ata_scsiop_test_unit_ready(ccb *pccb)
 693 {
 694         return (ataid[pccb->target]) ? 0 : -EPERM;
 695 }
 696
 697
 698 int scsi_exec(ccb *pccb)
 699 {
 700         int ret;
 701
 702         switch (pccb->cmd[0]) {
 703         case SCSI_READ10:
 704                 ret = ata_scsiop_read10(pccb);
 705                 break;
 706         case SCSI_RD_CAPAC:
 707                 ret = ata_scsiop_read_capacity10(pccb);
 708                 break;
 709         case SCSI_TST_U_RDY:
 710                 ret = ata_scsiop_test_unit_ready(pccb);
 711                 break;
 712         case SCSI_INQUIRY:
 713                 ret = ata_scsiop_inquiry(pccb);
 714                 break;
 715         default:
 716                 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
 717                 return FALSE;
 718         }
 719
 720         if (ret) {
 721                 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
 722                 return FALSE;
 723         }
 724         return TRUE;
 725
 726 }
 727
 728
 729 void scsi_low_level_init(int busdevfunc)
 730 {
 731         int i;
 732         u32 linkmap;
 733
 734         ahci_init_one(busdevfunc);
 735
 736         linkmap = probe_ent->link_port_map;
 737
 738         for (i = 0; i < CFG_SCSI_MAX_SCSI_ID; i++) {
 739                 if (((linkmap >> i) & 0x01)) {
 740                         if (ahci_port_start((u8) i)) {
 741                                 printf("Can not start port %d\n", i);
 742                                 continue;
 743                         }
 744                         /* ahci_set_feature((u8) i); yotam */
 745                 }
 746         }
 747 }
 748
 749
 750 void scsi_bus_reset(void)
 751 {
 752         /*Not implement*/
 753 }
 754
 755
 756 void scsi_print_error(ccb * pccb)
 757 {
 758         /*The ahci error info can be read in the ahci driver*/
 759 }
 760 #endif