drivers/eepro100.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <malloc.h>
  26 #include <net.h>
  27 #include <asm/io.h>
  28 #include <pci.h>
  29 #include <miiphy.h>
  30
  31 #undef DEBUG
  32
  33 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
  34         defined(CONFIG_EEPRO100)
  35
  36         /* Ethernet chip registers.
  37          */
  38 #define SCBStatus               0       /* Rx/Command Unit Status *Word* */
  39 #define SCBIntAckByte           1       /* Rx/Command Unit STAT/ACK byte */
  40 #define SCBCmd                  2       /* Rx/Command Unit Command *Word* */
  41 #define SCBIntrCtlByte          3       /* Rx/Command Unit Intr.Control Byte */
  42 #define SCBPointer              4       /* General purpose pointer. */
  43 #define SCBPort                 8       /* Misc. commands and operands. */
  44 #define SCBflash                12      /* Flash memory control. */
  45 #define SCBeeprom               14      /* EEPROM memory control. */
  46 #define SCBCtrlMDI              16      /* MDI interface control. */
  47 #define SCBEarlyRx              20      /* Early receive byte count. */
  48 #define SCBGenControl           28      /* 82559 General Control Register */
  49 #define SCBGenStatus            29      /* 82559 General Status register */
  50
  51         /* 82559 SCB status word defnitions
  52          */
  53 #define SCB_STATUS_CX           0x8000  /* CU finished command (transmit) */
  54 #define SCB_STATUS_FR           0x4000  /* frame received */
  55 #define SCB_STATUS_CNA          0x2000  /* CU left active state */
  56 #define SCB_STATUS_RNR          0x1000  /* receiver left ready state */
  57 #define SCB_STATUS_MDI          0x0800  /* MDI read/write cycle done */
  58 #define SCB_STATUS_SWI          0x0400  /* software generated interrupt */
  59 #define SCB_STATUS_FCP          0x0100  /* flow control pause interrupt */
  60
  61 #define SCB_INTACK_MASK         0xFD00  /* all the above */
  62
  63 #define SCB_INTACK_TX           (SCB_STATUS_CX | SCB_STATUS_CNA)
  64 #define SCB_INTACK_RX           (SCB_STATUS_FR | SCB_STATUS_RNR)
  65
  66         /* System control block commands
  67          */
  68 /* CU Commands */
  69 #define CU_NOP                  0x0000
  70 #define CU_START                0x0010
  71 #define CU_RESUME               0x0020
  72 #define CU_STATSADDR            0x0040  /* Load Dump Statistics ctrs addr */
  73 #define CU_SHOWSTATS            0x0050  /* Dump statistics counters. */
  74 #define CU_ADDR_LOAD            0x0060  /* Base address to add to CU commands */
  75 #define CU_DUMPSTATS            0x0070  /* Dump then reset stats counters. */
  76
  77 /* RUC Commands */
  78 #define RUC_NOP                 0x0000
  79 #define RUC_START               0x0001
  80 #define RUC_RESUME              0x0002
  81 #define RUC_ABORT               0x0004
  82 #define RUC_ADDR_LOAD           0x0006  /* (seems not to clear on acceptance) */
  83 #define RUC_RESUMENR            0x0007
  84
  85 #define CU_CMD_MASK             0x00f0
  86 #define RU_CMD_MASK             0x0007
  87
  88 #define SCB_M                   0x0100  /* 0 = enable interrupt, 1 = disable */
  89 #define SCB_SWI                 0x0200  /* 1 - cause device to interrupt */
  90
  91 #define CU_STATUS_MASK          0x00C0
  92 #define RU_STATUS_MASK          0x003C
  93
  94 #define RU_STATUS_IDLE          (0<<2)
  95 #define RU_STATUS_SUS           (1<<2)
  96 #define RU_STATUS_NORES         (2<<2)
  97 #define RU_STATUS_READY         (4<<2)
  98 #define RU_STATUS_NO_RBDS_SUS   ((1<<2)|(8<<2))
  99 #define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))
 100 #define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))
 101
 102         /* 82559 Port interface commands.
 103          */
 104 #define I82559_RESET            0x00000000      /* Software reset */
 105 #define I82559_SELFTEST         0x00000001      /* 82559 Selftest command */
 106 #define I82559_SELECTIVE_RESET  0x00000002
 107 #define I82559_DUMP             0x00000003
 108 #define I82559_DUMP_WAKEUP      0x00000007
 109
 110         /* 82559 Eeprom interface.
 111          */
 112 #define EE_SHIFT_CLK            0x01    /* EEPROM shift clock. */
 113 #define EE_CS                   0x02    /* EEPROM chip select. */
 114 #define EE_DATA_WRITE           0x04    /* EEPROM chip data in. */
 115 #define EE_WRITE_0              0x01
 116 #define EE_WRITE_1              0x05
 117 #define EE_DATA_READ            0x08    /* EEPROM chip data out. */
 118 #define EE_ENB                  (0x4800 | EE_CS)
 119 #define EE_CMD_BITS             3
 120 #define EE_DATA_BITS            16
 121
 122         /* The EEPROM commands include the alway-set leading bit.
 123          */
 124 #define EE_EWENB_CMD            (4 << addr_len)
 125 #define EE_WRITE_CMD            (5 << addr_len)
 126 #define EE_READ_CMD             (6 << addr_len)
 127 #define EE_ERASE_CMD            (7 << addr_len)
 128
 129         /* Receive frame descriptors.
 130          */
 131 struct RxFD {
 132         volatile u16 status;
 133         volatile u16 control;
 134         volatile u32 link;              /* struct RxFD * */
 135         volatile u32 rx_buf_addr;       /* void * */
 136         volatile u32 count;
 137
 138         volatile u8 data[PKTSIZE_ALIGN];
 139 };
 140
 141 #define RFD_STATUS_C            0x8000  /* completion of received frame */
 142 #define RFD_STATUS_OK           0x2000  /* frame received with no errors */
 143
 144 #define RFD_CONTROL_EL          0x8000  /* 1=last RFD in RFA */
 145 #define RFD_CONTROL_S           0x4000  /* 1=suspend RU after receiving frame */
 146 #define RFD_CONTROL_H           0x0010  /* 1=RFD is a header RFD */
 147 #define RFD_CONTROL_SF          0x0008  /* 0=simplified, 1=flexible mode */
 148
 149 #define RFD_COUNT_MASK          0x3fff
 150 #define RFD_COUNT_F             0x4000
 151 #define RFD_COUNT_EOF           0x8000
 152
 153 #define RFD_RX_CRC              0x0800  /* crc error */
 154 #define RFD_RX_ALIGNMENT        0x0400  /* alignment error */
 155 #define RFD_RX_RESOURCE         0x0200  /* out of space, no resources */
 156 #define RFD_RX_DMA_OVER         0x0100  /* DMA overrun */
 157 #define RFD_RX_SHORT            0x0080  /* short frame error */
 158 #define RFD_RX_LENGTH           0x0020
 159 #define RFD_RX_ERROR            0x0010  /* receive error */
 160 #define RFD_RX_NO_ADR_MATCH     0x0004  /* no address match */
 161 #define RFD_RX_IA_MATCH         0x0002  /* individual address does not match */
 162 #define RFD_RX_TCO              0x0001  /* TCO indication */
 163
 164         /* Transmit frame descriptors
 165          */
 166 struct TxFD {                           /* Transmit frame descriptor set. */
 167         volatile u16 status;
 168         volatile u16 command;
 169         volatile u32 link;              /* void * */
 170         volatile u32 tx_desc_addr;      /* Always points to the tx_buf_addr element. */
 171         volatile s32 count;
 172
 173         volatile u32 tx_buf_addr0;      /* void *, frame to be transmitted.  */
 174         volatile s32 tx_buf_size0;      /* Length of Tx frame. */
 175         volatile u32 tx_buf_addr1;      /* void *, frame to be transmitted.  */
 176         volatile s32 tx_buf_size1;      /* Length of Tx frame. */
 177 };
 178
 179 #define TxCB_CMD_TRANSMIT       0x0004  /* transmit command */
 180 #define TxCB_CMD_SF             0x0008  /* 0=simplified, 1=flexible mode */
 181 #define TxCB_CMD_NC             0x0010  /* 0=CRC insert by controller */
 182 #define TxCB_CMD_I              0x2000  /* generate interrupt on completion */
 183 #define TxCB_CMD_S              0x4000  /* suspend on completion */
 184 #define TxCB_CMD_EL             0x8000  /* last command block in CBL */
 185
 186 #define TxCB_COUNT_MASK         0x3fff
 187 #define TxCB_COUNT_EOF          0x8000
 188
 189         /* The Speedo3 Rx and Tx frame/buffer descriptors.
 190          */
 191 struct descriptor {                     /* A generic descriptor. */
 192         volatile u16 status;
 193         volatile u16 command;
 194         volatile u32 link;              /* struct descriptor *  */
 195
 196         unsigned char params[0];
 197 };
 198
 199 #define CFG_CMD_EL              0x8000
 200 #define CFG_CMD_SUSPEND         0x4000
 201 #define CFG_CMD_INT             0x2000
 202 #define CFG_CMD_IAS             0x0001  /* individual address setup */
 203 #define CFG_CMD_CONFIGURE       0x0002  /* configure */
 204
 205 #define CFG_STATUS_C            0x8000
 206 #define CFG_STATUS_OK           0x2000
 207
 208         /* Misc.
 209          */
 210 #define NUM_RX_DESC             PKTBUFSRX
 211 #define NUM_TX_DESC             1       /* Number of TX descriptors   */
 212
 213 #define TOUT_LOOP               1000000
 214
 215 #define ETH_ALEN                6
 216
 217 static struct RxFD rx_ring[NUM_RX_DESC];        /* RX descriptor ring         */
 218 static struct TxFD tx_ring[NUM_TX_DESC];        /* TX descriptor ring         */
 219 static int rx_next;                     /* RX descriptor ring pointer */
 220 static int tx_next;                     /* TX descriptor ring pointer */
 221 static int tx_threshold;
 222
 223 /*
 224  * The parameters for a CmdConfigure operation.
 225  * There are so many options that it would be difficult to document
 226  * each bit. We mostly use the default or recommended settings.
 227  */
 228 static const char i82557_config_cmd[] = {
 229         22, 0x08, 0, 0, 0, 0, 0x32, 0x03, 1,    /* 1=Use MII  0=Use AUI */
 230         0, 0x2E, 0, 0x60, 0,
 231         0xf2, 0x48, 0, 0x40, 0xf2, 0x80,        /* 0x40=Force full-duplex */
 232         0x3f, 0x05,
 233 };
 234 static const char i82558_config_cmd[] = {
 235         22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1,    /* 1=Use MII  0=Use AUI */
 236         0, 0x2E, 0, 0x60, 0x08, 0x88,
 237         0x68, 0, 0x40, 0xf2, 0x84,              /* Disable FC */
 238         0x31, 0x05,
 239 };
 240
 241 static void init_rx_ring (struct eth_device *dev);
 242 static void purge_tx_ring (struct eth_device *dev);
 243
 244 static void read_hw_addr (struct eth_device *dev, bd_t * bis);
 245
 246 static int eepro100_init (struct eth_device *dev, bd_t * bis);
 247 static int eepro100_send (struct eth_device *dev, volatile void *packet,
 248                                                   int length);
 249 static int eepro100_recv (struct eth_device *dev);
 250 static void eepro100_halt (struct eth_device *dev);
 251
 252 #if defined(CONFIG_E500) || (defined(CONFIG_MARVELL) && defined(__ARM__))
 253 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
 254 #define phys_to_bus(a) (a)
 255 #elif defined(CONFIG_MARVELL) && defined(__MIPS__)
 256 #define bus_to_phys(a) (a |  (0xa0000000))
 257 #define phys_to_bus(a) (a & ~(0xa0000000))
 258 #else
 259 #define bus_to_phys(a)  pci_mem_to_phys((pci_dev_t)dev->priv, a)
 260 #define phys_to_bus(a)  pci_phys_to_mem((pci_dev_t)dev->priv, a)
 261 #endif
 262
 263 static inline int INW (struct eth_device *dev, u_long addr)
 264 {
 265         return le16_to_cpu (*(volatile u16 *) (addr + dev->iobase));
 266 }
 267
 268 static inline void OUTW (struct eth_device *dev, int command, u_long addr)
 269 {
 270         *(volatile u16 *) ((addr + dev->iobase)) = cpu_to_le16 (command);
 271 }
 272
 273 static inline void OUTL (struct eth_device *dev, int command, u_long addr)
 274 {
 275         *(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command);
 276 }
 277
 278 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
 279 static inline int INL (struct eth_device *dev, u_long addr)
 280 {
 281         return le32_to_cpu (*(volatile u32 *) (addr + dev->iobase));
 282 }
 283
 284 static int get_phyreg (struct eth_device *dev, unsigned char addr,
 285                 unsigned char reg, unsigned short *value)
 286 {
 287         int cmd;
 288         int timeout = 50;
 289
 290         /* read requested data */
 291         cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
 292         OUTL (dev, cmd, SCBCtrlMDI);
 293
 294         do {
 295                 udelay(1000);
 296                 cmd = INL (dev, SCBCtrlMDI);
 297         } while (!(cmd & (1 << 28)) && (--timeout));
 298
 299         if (timeout == 0)
 300                 return -1;
 301
 302         *value = (unsigned short) (cmd & 0xffff);
 303
 304         return 0;
 305 }
 306
 307 static int set_phyreg (struct eth_device *dev, unsigned char addr,
 308                 unsigned char reg, unsigned short value)
 309 {
 310         int cmd;
 311         int timeout = 50;
 312
 313         /* write requested data */
 314         cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
 315         OUTL (dev, cmd | value, SCBCtrlMDI);
 316
 317         while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout))
 318                 udelay(1000);
 319
 320         if (timeout == 0)
 321                 return -1;
 322
 323         return 0;
 324 }
 325
 326 /* Check if given phyaddr is valid, i.e. there is a PHY connected.
 327  * Do this by checking model value field from ID2 register.
 328  */
 329 static struct eth_device* verify_phyaddr (char *devname, unsigned char addr)
 330 {
 331         struct eth_device *dev;
 332         unsigned short value;
 333         unsigned char model;
 334
 335         dev = eth_get_dev_by_name(devname);
 336         if (dev == NULL) {
 337                 printf("%s: no such device\n", devname);
 338                 return NULL;
 339         }
 340
 341         /* read id2 register */
 342         if (get_phyreg(dev, addr, PHY_PHYIDR2, &value) != 0) {
 343                 printf("%s: mii read timeout!\n", devname);
 344                 return NULL;
 345         }
 346
 347         /* get model */
 348         model = (unsigned char)((value >> 4) & 0x003f);
 349
 350         if (model == 0) {
 351                 printf("%s: no PHY at address %d\n", devname, addr);
 352                 return NULL;
 353         }
 354
 355         return dev;
 356 }
 357
 358 static int eepro100_miiphy_read (char *devname, unsigned char addr,
 359                 unsigned char reg, unsigned short *value)
 360 {
 361         struct eth_device *dev;
 362
 363         dev = verify_phyaddr(devname, addr);
 364         if (dev == NULL)
 365                 return -1;
 366
 367         if (get_phyreg(dev, addr, reg, value) != 0) {
 368                 printf("%s: mii read timeout!\n", devname);
 369                 return -1;
 370         }
 371
 372         return 0;
 373 }
 374
 375 static int eepro100_miiphy_write (char *devname, unsigned char addr,
 376                 unsigned char reg, unsigned short value)
 377 {
 378         struct eth_device *dev;
 379
 380         dev = verify_phyaddr(devname, addr);
 381         if (dev == NULL)
 382                 return -1;
 383
 384         if (set_phyreg(dev, addr, reg, value) != 0) {
 385                 printf("%s: mii write timeout!\n", devname);
 386                 return -1;
 387         }
 388
 389         return 0;
 390 }
 391
 392 #endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */
 393
 394 /* Wait for the chip get the command.
 395 */
 396 static int wait_for_eepro100 (struct eth_device *dev)
 397 {
 398         int i;
 399
 400         for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
 401                 if (i >= TOUT_LOOP) {
 402                         return 0;
 403                 }
 404         }
 405
 406         return 1;
 407 }
 408
 409 static struct pci_device_id supported[] = {
 410         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557},
 411         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559},
 412         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER},
 413         {}
 414 };
 415
 416 int eepro100_initialize (bd_t * bis)
 417 {
 418         pci_dev_t devno;
 419         int card_number = 0;
 420         struct eth_device *dev;
 421         u32 iobase, status;
 422         int idx = 0;
 423
 424         while (1) {
 425                 /* Find PCI device
 426                  */
 427                 if ((devno = pci_find_devices (supported, idx++)) < 0) {
 428                         break;
 429                 }
 430
 431                 pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase);
 432                 iobase &= ~0xf;
 433
 434 #ifdef DEBUG
 435                 printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
 436                                 iobase);
 437 #endif
 438
 439                 pci_write_config_dword (devno,
 440                                         PCI_COMMAND,
 441                                         PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 442
 443                 /* Check if I/O accesses and Bus Mastering are enabled.
 444                  */
 445                 pci_read_config_dword (devno, PCI_COMMAND, &status);
 446                 if (!(status & PCI_COMMAND_MEMORY)) {
 447                         printf ("Error: Can not enable MEM access.\n");
 448                         continue;
 449                 }
 450
 451                 if (!(status & PCI_COMMAND_MASTER)) {
 452                         printf ("Error: Can not enable Bus Mastering.\n");
 453                         continue;
 454                 }
 455
 456                 dev = (struct eth_device *) malloc (sizeof *dev);
 457
 458                 sprintf (dev->name, "i82559#%d", card_number);
 459                 dev->priv = (void *) devno; /* this have to come before bus_to_phys() */
 460                 dev->iobase = bus_to_phys (iobase);
 461                 dev->init = eepro100_init;
 462                 dev->halt = eepro100_halt;
 463                 dev->send = eepro100_send;
 464                 dev->recv = eepro100_recv;
 465
 466                 eth_register (dev);
 467
 468 #if defined (CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
 469                 /* register mii command access routines */
 470                 miiphy_register(dev->name,
 471                                 eepro100_miiphy_read, eepro100_miiphy_write);
 472 #endif
 473
 474                 card_number++;
 475
 476                 /* Set the latency timer for value.
 477                  */
 478                 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
 479
 480                 udelay (10 * 1000);
 481
 482                 read_hw_addr (dev, bis);
 483         }
 484
 485         return card_number;
 486 }
 487
 488
 489 static int eepro100_init (struct eth_device *dev, bd_t * bis)
 490 {
 491         int i, status = 0;
 492         int tx_cur;
 493         struct descriptor *ias_cmd, *cfg_cmd;
 494
 495         /* Reset the ethernet controller
 496          */
 497         OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
 498         udelay (20);
 499
 500         OUTL (dev, I82559_RESET, SCBPort);
 501         udelay (20);
 502
 503         if (!wait_for_eepro100 (dev)) {
 504                 printf ("Error: Can not reset ethernet controller.\n");
 505                 goto Done;
 506         }
 507         OUTL (dev, 0, SCBPointer);
 508         OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
 509
 510         if (!wait_for_eepro100 (dev)) {
 511                 printf ("Error: Can not reset ethernet controller.\n");
 512                 goto Done;
 513         }
 514         OUTL (dev, 0, SCBPointer);
 515         OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
 516
 517         /* Initialize Rx and Tx rings.
 518          */
 519         init_rx_ring (dev);
 520         purge_tx_ring (dev);
 521
 522         /* Tell the adapter where the RX ring is located.
 523          */
 524         if (!wait_for_eepro100 (dev)) {
 525                 printf ("Error: Can not reset ethernet controller.\n");
 526                 goto Done;
 527         }
 528
 529         OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
 530         OUTW (dev, SCB_M | RUC_START, SCBCmd);
 531
 532         /* Send the Configure frame */
 533         tx_cur = tx_next;
 534         tx_next = ((tx_next + 1) % NUM_TX_DESC);
 535
 536         cfg_cmd = (struct descriptor *) &tx_ring[tx_cur];
 537         cfg_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_CONFIGURE));
 538         cfg_cmd->status = 0;
 539         cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
 540
 541         memcpy (cfg_cmd->params, i82558_config_cmd,
 542                         sizeof (i82558_config_cmd));
 543
 544         if (!wait_for_eepro100 (dev)) {
 545                 printf ("Error---CFG_CMD_CONFIGURE: Can not reset ethernet controller.\n");
 546                 goto Done;
 547         }
 548
 549         OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
 550         OUTW (dev, SCB_M | CU_START, SCBCmd);
 551
 552         for (i = 0;
 553              !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
 554              i++) {
 555                 if (i >= TOUT_LOOP) {
 556                         printf ("%s: Tx error buffer not ready\n", dev->name);
 557                         goto Done;
 558                 }
 559         }
 560
 561         if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
 562                 printf ("TX error status = 0x%08X\n",
 563                         le16_to_cpu (tx_ring[tx_cur].status));
 564                 goto Done;
 565         }
 566
 567         /* Send the Individual Address Setup frame
 568          */
 569         tx_cur = tx_next;
 570         tx_next = ((tx_next + 1) % NUM_TX_DESC);
 571
 572         ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
 573         ias_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_IAS));
 574         ias_cmd->status = 0;
 575         ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
 576
 577         memcpy (ias_cmd->params, dev->enetaddr, 6);
 578
 579         /* Tell the adapter where the TX ring is located.
 580          */
 581         if (!wait_for_eepro100 (dev)) {
 582                 printf ("Error: Can not reset ethernet controller.\n");
 583                 goto Done;
 584         }
 585
 586         OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
 587         OUTW (dev, SCB_M | CU_START, SCBCmd);
 588
 589         for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
 590                  i++) {
 591                 if (i >= TOUT_LOOP) {
 592                         printf ("%s: Tx error buffer not ready\n",
 593                                 dev->name);
 594                         goto Done;
 595                 }
 596         }
 597
 598         if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
 599                 printf ("TX error status = 0x%08X\n",
 600                         le16_to_cpu (tx_ring[tx_cur].status));
 601                 goto Done;
 602         }
 603
 604         status = 1;
 605
 606   Done:
 607         return status;
 608 }
 609
 610 static int eepro100_send (struct eth_device *dev, volatile void *packet, int length)
 611 {
 612         int i, status = -1;
 613         int tx_cur;
 614
 615         if (length <= 0) {
 616                 printf ("%s: bad packet size: %d\n", dev->name, length);
 617                 goto Done;
 618         }
 619
 620         tx_cur = tx_next;
 621         tx_next = (tx_next + 1) % NUM_TX_DESC;
 622
 623         tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT |
 624                                                 TxCB_CMD_SF     |
 625                                                 TxCB_CMD_S      |
 626                                                 TxCB_CMD_EL );
 627         tx_ring[tx_cur].status = 0;
 628         tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold);
 629         tx_ring[tx_cur].link =
 630                 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
 631         tx_ring[tx_cur].tx_desc_addr =
 632                 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0));
 633         tx_ring[tx_cur].tx_buf_addr0 =
 634                 cpu_to_le32 (phys_to_bus ((u_long) packet));
 635         tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length);
 636
 637         if (!wait_for_eepro100 (dev)) {
 638                 printf ("%s: Tx error ethernet controller not ready.\n",
 639                                 dev->name);
 640                 goto Done;
 641         }
 642
 643         /* Send the packet.
 644          */
 645         OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
 646         OUTW (dev, SCB_M | CU_START, SCBCmd);
 647
 648         for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
 649                  i++) {
 650                 if (i >= TOUT_LOOP) {
 651                         printf ("%s: Tx error buffer not ready\n", dev->name);
 652                         goto Done;
 653                 }
 654         }
 655
 656         if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
 657                 printf ("TX error status = 0x%08X\n",
 658                         le16_to_cpu (tx_ring[tx_cur].status));
 659                 goto Done;
 660         }
 661
 662         status = length;
 663
 664   Done:
 665         return status;
 666 }
 667
 668 static int eepro100_recv (struct eth_device *dev)
 669 {
 670         u16 status, stat;
 671         int rx_prev, length = 0;
 672
 673         stat = INW (dev, SCBStatus);
 674         OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus);
 675
 676         for (;;) {
 677                 status = le16_to_cpu (rx_ring[rx_next].status);
 678
 679                 if (!(status & RFD_STATUS_C)) {
 680                         break;
 681                 }
 682
 683                 /* Valid frame status.
 684                  */
 685                 if ((status & RFD_STATUS_OK)) {
 686                         /* A valid frame received.
 687                          */
 688                         length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff;
 689
 690                         /* Pass the packet up to the protocol
 691                          * layers.
 692                          */
 693                         NetReceive (rx_ring[rx_next].data, length);
 694                 } else {
 695                         /* There was an error.
 696                          */
 697                         printf ("RX error status = 0x%08X\n", status);
 698                 }
 699
 700                 rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S);
 701                 rx_ring[rx_next].status = 0;
 702                 rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
 703
 704                 rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
 705                 rx_ring[rx_prev].control = 0;
 706
 707                 /* Update entry information.
 708                  */
 709                 rx_next = (rx_next + 1) % NUM_RX_DESC;
 710         }
 711
 712         if (stat & SCB_STATUS_RNR) {
 713
 714                 printf ("%s: Receiver is not ready, restart it !\n", dev->name);
 715
 716                 /* Reinitialize Rx ring.
 717                  */
 718                 init_rx_ring (dev);
 719
 720                 if (!wait_for_eepro100 (dev)) {
 721                         printf ("Error: Can not restart ethernet controller.\n");
 722                         goto Done;
 723                 }
 724
 725                 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
 726                 OUTW (dev, SCB_M | RUC_START, SCBCmd);
 727         }
 728
 729   Done:
 730         return length;
 731 }
 732
 733 static void eepro100_halt (struct eth_device *dev)
 734 {
 735         /* Reset the ethernet controller
 736          */
 737         OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
 738         udelay (20);
 739
 740         OUTL (dev, I82559_RESET, SCBPort);
 741         udelay (20);
 742
 743         if (!wait_for_eepro100 (dev)) {
 744                 printf ("Error: Can not reset ethernet controller.\n");
 745                 goto Done;
 746         }
 747         OUTL (dev, 0, SCBPointer);
 748         OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
 749
 750         if (!wait_for_eepro100 (dev)) {
 751                 printf ("Error: Can not reset ethernet controller.\n");
 752                 goto Done;
 753         }
 754         OUTL (dev, 0, SCBPointer);
 755         OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
 756
 757   Done:
 758         return;
 759 }
 760
 761         /* SROM Read.
 762          */
 763 static int read_eeprom (struct eth_device *dev, int location, int addr_len)
 764 {
 765         unsigned short retval = 0;
 766         int read_cmd = location | EE_READ_CMD;
 767         int i;
 768
 769         OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
 770         OUTW (dev, EE_ENB, SCBeeprom);
 771
 772         /* Shift the read command bits out. */
 773         for (i = 12; i >= 0; i--) {
 774                 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
 775
 776                 OUTW (dev, EE_ENB | dataval, SCBeeprom);
 777                 udelay (1);
 778                 OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
 779                 udelay (1);
 780         }
 781         OUTW (dev, EE_ENB, SCBeeprom);
 782
 783         for (i = 15; i >= 0; i--) {
 784                 OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom);
 785                 udelay (1);
 786                 retval = (retval << 1) |
 787                                 ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0);
 788                 OUTW (dev, EE_ENB, SCBeeprom);
 789                 udelay (1);
 790         }
 791
 792         /* Terminate the EEPROM access. */
 793         OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
 794         return retval;
 795 }
 796
 797 #ifdef CONFIG_EEPRO100_SROM_WRITE
 798 int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data)
 799 {
 800     unsigned short dataval;
 801     int enable_cmd = 0x3f | EE_EWENB_CMD;
 802     int write_cmd  = location | EE_WRITE_CMD;
 803     int i;
 804     unsigned long datalong, tmplong;
 805
 806     OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
 807     udelay(1);
 808     OUTW(dev, EE_ENB, SCBeeprom);
 809
 810     /* Shift the enable command bits out. */
 811     for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
 812     {
 813         dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
 814         OUTW(dev, EE_ENB | dataval, SCBeeprom);
 815         udelay(1);
 816         OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
 817         udelay(1);
 818     }
 819
 820     OUTW(dev, EE_ENB, SCBeeprom);
 821     udelay(1);
 822     OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
 823     udelay(1);
 824     OUTW(dev, EE_ENB, SCBeeprom);
 825
 826
 827     /* Shift the write command bits out. */
 828     for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
 829     {
 830         dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
 831         OUTW(dev, EE_ENB | dataval, SCBeeprom);
 832         udelay(1);
 833         OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
 834         udelay(1);
 835     }
 836
 837     /* Write the data */
 838     datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8));
 839
 840     for (i = 0; i< EE_DATA_BITS; i++)
 841     {
 842     /* Extract and move data bit to bit DI */
 843     dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0;
 844
 845     OUTW(dev, EE_ENB | dataval, SCBeeprom);
 846     udelay(1);
 847     OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
 848     udelay(1);
 849     OUTW(dev, EE_ENB | dataval, SCBeeprom);
 850     udelay(1);
 851
 852     datalong = datalong << 1;   /* Adjust significant data bit*/
 853     }
 854
 855     /* Finish up command  (toggle CS) */
 856     OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
 857     udelay(1);                  /* delay for more than 250 ns */
 858     OUTW(dev, EE_ENB, SCBeeprom);
 859
 860     /* Wait for programming ready (D0 = 1) */
 861     tmplong = 10;
 862     do
 863     {
 864         dataval = INW(dev, SCBeeprom);
 865         if (dataval & EE_DATA_READ)
 866             break;
 867         udelay(10000);
 868     }
 869     while (-- tmplong);
 870
 871     if (tmplong == 0)
 872     {
 873         printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n");
 874         return -1;
 875     }
 876
 877     /* Terminate the EEPROM access. */
 878     OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
 879
 880     return 0;
 881 }
 882 #endif
 883
 884 static void init_rx_ring (struct eth_device *dev)
 885 {
 886         int i;
 887
 888         for (i = 0; i < NUM_RX_DESC; i++) {
 889                 rx_ring[i].status = 0;
 890                 rx_ring[i].control =
 891                                 (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0;
 892                 rx_ring[i].link =
 893                                 cpu_to_le32 (phys_to_bus
 894                                                          ((u32) & rx_ring[(i + 1) % NUM_RX_DESC]));
 895                 rx_ring[i].rx_buf_addr = 0xffffffff;
 896                 rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
 897         }
 898
 899         rx_next = 0;
 900 }
 901
 902 static void purge_tx_ring (struct eth_device *dev)
 903 {
 904         int i;
 905
 906         tx_next = 0;
 907         tx_threshold = 0x01208000;
 908
 909         for (i = 0; i < NUM_TX_DESC; i++) {
 910                 tx_ring[i].status = 0;
 911                 tx_ring[i].command = 0;
 912                 tx_ring[i].link = 0;
 913                 tx_ring[i].tx_desc_addr = 0;
 914                 tx_ring[i].count = 0;
 915
 916                 tx_ring[i].tx_buf_addr0 = 0;
 917                 tx_ring[i].tx_buf_size0 = 0;
 918                 tx_ring[i].tx_buf_addr1 = 0;
 919                 tx_ring[i].tx_buf_size1 = 0;
 920         }
 921 }
 922
 923 static void read_hw_addr (struct eth_device *dev, bd_t * bis)
 924 {
 925         u16 eeprom[0x40];
 926         u16 sum = 0;
 927         int i, j;
 928         int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6;
 929
 930         for (j = 0, i = 0; i < 0x40; i++) {
 931                 u16 value = read_eeprom (dev, i, addr_len);
 932
 933                 eeprom[i] = value;
 934                 sum += value;
 935                 if (i < 3) {
 936                         dev->enetaddr[j++] = value;
 937                         dev->enetaddr[j++] = value >> 8;
 938                 }
 939         }
 940
 941         if (sum != 0xBABA) {
 942                 memset (dev->enetaddr, 0, ETH_ALEN);
 943 #ifdef DEBUG
 944                 printf ("%s: Invalid EEPROM checksum %#4.4x, "
 945                         "check settings before activating this device!\n",
 946                         dev->name, sum);
 947 #endif
 948         }
 949 }
 950
 951 #endif