drivers/pci.c

   1 /*
   2  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   3  * Andreas Heppel <aheppel@sysgo.de>
   4  *
   5  * (C) Copyright 2002, 2003
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * PCI routines
  29  */
  30
  31 /* #define DEBUG */
  32 #include <common.h>
  33 #ifdef CONFIG_PCI
  34 #include <command.h>
  35 #include <asm/processor.h>
  36 #include <asm/io.h>
  37 #include <pci.h>
  38
  39 /* #define DEBUG */
  40 #ifdef DEBUG
  41 #define debug(x...) printf(x)
  42 #else
  43 #define debug(x...)
  44 #endif /* DEBUG */
  45
  46 #define PCI_HOSE_OP(rw, size, type)                                     \
  47 int pci_hose_##rw##_config_##size(struct pci_controller *hose,          \
  48                                   pci_dev_t dev,                        \
  49                                   int offset, type value)               \
  50 {                                                                       \
  51         return hose->rw##_##size(hose, dev, offset, value);             \
  52 }
  53
  54 PCI_HOSE_OP(read, byte, u8 *)
  55 PCI_HOSE_OP(read, word, u16 *)
  56 PCI_HOSE_OP(read, dword, u32 *)
  57 PCI_HOSE_OP(write, byte, u8)
  58 PCI_HOSE_OP(write, word, u16)
  59 PCI_HOSE_OP(write, dword, u32)
  60
  61 #ifndef CONFIG_IXP425
  62 #define PCI_OP(rw, size, type, error_code)                              \
  63 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value)     \
  64 {                                                                       \
  65         struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev));    \
  66                                                                         \
  67         if (!hose)                                                      \
  68         {                                                               \
  69                 error_code;                                             \
  70                 return -1;                                              \
  71         }                                                               \
  72                                                                         \
  73         return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
  74 }
  75
  76 PCI_OP(read, byte, u8 *, *value = 0xff)
  77 PCI_OP(read, word, u16 *, *value = 0xffff)
  78 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
  79 PCI_OP(write, byte, u8, )
  80 PCI_OP(write, word, u16, )
  81 PCI_OP(write, dword, u32, )
  82 #endif  /* CONFIG_IXP425 */
  83
  84 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask)                     \
  85 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
  86                                         pci_dev_t dev,                  \
  87                                         int offset, type val)           \
  88 {                                                                       \
  89         u32 val32;                                                      \
  90                                                                         \
  91         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
  92                 return -1;                                              \
  93                                                                         \
  94         *val = (val32 >> ((offset & (int)off_mask) * 8));               \
  95                                                                         \
  96         return 0;                                                       \
  97 }
  98
  99 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask)          \
 100 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
 101                                              pci_dev_t dev,             \
 102                                              int offset, type val)      \
 103 {                                                                       \
 104         u32 val32, mask, ldata, shift;                                  \
 105                                                                         \
 106         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
 107                 return -1;                                              \
 108                                                                         \
 109         shift = ((offset & (int)off_mask) * 8);                         \
 110         ldata = (((unsigned long)val) & val_mask) << shift;             \
 111         mask = val_mask << shift;                                       \
 112         val32 = (val32 & ~mask) | ldata;                                \
 113                                                                         \
 114         if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
 115                 return -1;                                              \
 116                                                                         \
 117         return 0;                                                       \
 118 }
 119
 120 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
 121 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
 122 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
 123 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
 124
 125 /*
 126  *
 127  */
 128
 129 static struct pci_controller* hose_head = NULL;
 130
 131 void pci_register_hose(struct pci_controller* hose)
 132 {
 133         struct pci_controller **phose = &hose_head;
 134
 135         while(*phose)
 136                 phose = &(*phose)->next;
 137
 138         hose->next = NULL;
 139
 140         *phose = hose;
 141 }
 142
 143 struct pci_controller *pci_bus_to_hose (int bus)
 144 {
 145         struct pci_controller *hose;
 146
 147         for (hose = hose_head; hose; hose = hose->next)
 148                 if (bus >= hose->first_busno && bus <= hose->last_busno)
 149                         return hose;
 150 #ifndef CONFIG_MARVELL
 151         printf("pci_bus_to_hose() failed\n");
 152 #endif
 153         return NULL;
 154 }
 155
 156 #ifndef CONFIG_IXP425
 157 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
 158 {
 159         struct pci_controller * hose;
 160         u16 vendor, device;
 161         u8 header_type;
 162         pci_dev_t bdf;
 163         int i, bus, found_multi = 0;
 164
 165         for (hose = hose_head; hose; hose = hose->next)
 166         {
 167 #ifdef CFG_SCSI_SCAN_BUS_REVERSE
 168                 for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
 169 #else
 170                 for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
 171 #endif
 172                         for (bdf = PCI_BDF(bus,0,0);
 173 #ifdef CONFIG_ELPPC
 174                              bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
 175 #else
 176                              bdf < PCI_BDF(bus+1,0,0);
 177 #endif
 178                              bdf += PCI_BDF(0,0,1))
 179                         {
 180                                 if (!PCI_FUNC(bdf)) {
 181                                         pci_read_config_byte(bdf,
 182                                                              PCI_HEADER_TYPE,
 183                                                              &header_type);
 184
 185                                         found_multi = header_type & 0x80;
 186                                 } else {
 187                                         if (!found_multi)
 188                                                 continue;
 189                                 }
 190
 191                                 pci_read_config_word(bdf,
 192                                                      PCI_VENDOR_ID,
 193                                                      &vendor);
 194                                 pci_read_config_word(bdf,
 195                                                      PCI_DEVICE_ID,
 196                                                      &device);
 197
 198                                 for (i=0; ids[i].vendor != 0; i++)
 199                                         if (vendor == ids[i].vendor &&
 200                                             device == ids[i].device)
 201                                         {
 202                                                 if (index <= 0)
 203                                                         return bdf;
 204
 205                                                 index--;
 206                                         }
 207                         }
 208         }
 209
 210         return (-1);
 211 }
 212 #endif  /* CONFIG_IXP425 */
 213
 214 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
 215 {
 216         static struct pci_device_id ids[2] = {{}, {0, 0}};
 217
 218         ids[0].vendor = vendor;
 219         ids[0].device = device;
 220
 221         return pci_find_devices(ids, index);
 222 }
 223
 224 /*
 225  *
 226  */
 227
 228 unsigned long pci_hose_phys_to_bus (struct pci_controller *hose,
 229                                     unsigned long phys_addr,
 230                                     unsigned long flags)
 231 {
 232         struct pci_region *res;
 233         unsigned long bus_addr;
 234         int i;
 235
 236         if (!hose) {
 237                 printf ("pci_hose_phys_to_bus: %s\n", "invalid hose");
 238                 goto Done;
 239         }
 240
 241         for (i = 0; i < hose->region_count; i++) {
 242                 res = &hose->regions[i];
 243
 244                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 245                         continue;
 246
 247                 bus_addr = phys_addr - res->phys_start + res->bus_start;
 248
 249                 if (bus_addr >= res->bus_start &&
 250                         bus_addr < res->bus_start + res->size) {
 251                         return bus_addr;
 252                 }
 253         }
 254
 255         printf ("pci_hose_phys_to_bus: %s\n", "invalid physical address");
 256
 257 Done:
 258         return 0;
 259 }
 260
 261 unsigned long pci_hose_bus_to_phys(struct pci_controller* hose,
 262                                    unsigned long bus_addr,
 263                                    unsigned long flags)
 264 {
 265         struct pci_region *res;
 266         int i;
 267
 268         if (!hose) {
 269                 printf ("pci_hose_bus_to_phys: %s\n", "invalid hose");
 270                 goto Done;
 271         }
 272
 273         for (i = 0; i < hose->region_count; i++) {
 274                 res = &hose->regions[i];
 275
 276                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 277                         continue;
 278
 279                 if (bus_addr >= res->bus_start &&
 280                         bus_addr < res->bus_start + res->size) {
 281                         return bus_addr - res->bus_start + res->phys_start;
 282                 }
 283         }
 284
 285         printf ("pci_hose_bus_to_phys: %s\n", "invalid physical address");
 286
 287 Done:
 288         return 0;
 289 }
 290
 291 /*
 292  *
 293  */
 294
 295 int pci_hose_config_device(struct pci_controller *hose,
 296                            pci_dev_t dev,
 297                            unsigned long io,
 298                            unsigned long mem,
 299                            unsigned long command)
 300 {
 301         unsigned int bar_response, bar_size, bar_value, old_command;
 302         unsigned char pin;
 303         int bar, found_mem64;
 304
 305         debug ("PCI Config: I/O=0x%lx, Memory=0x%lx, Command=0x%lx\n",
 306                 io, mem, command);
 307
 308         pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);
 309
 310         for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_5; bar += 4) {
 311                 pci_hose_write_config_dword (hose, dev, bar, 0xffffffff);
 312                 pci_hose_read_config_dword (hose, dev, bar, &bar_response);
 313
 314                 if (!bar_response)
 315                         continue;
 316
 317                 found_mem64 = 0;
 318
 319                 /* Check the BAR type and set our address mask */
 320                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 321                         bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
 322                         /* round up region base address to a multiple of size */
 323                         io = ((io - 1) | (bar_size - 1)) + 1;
 324                         bar_value = io;
 325                         /* compute new region base address */
 326                         io = io + bar_size;
 327                 } else {
 328                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 329                                 PCI_BASE_ADDRESS_MEM_TYPE_64)
 330                                 found_mem64 = 1;
 331
 332                         bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
 333
 334                         /* round up region base address to multiple of size */
 335                         mem = ((mem - 1) | (bar_size - 1)) + 1;
 336                         bar_value = mem;
 337                         /* compute new region base address */
 338                         mem = mem + bar_size;
 339                 }
 340
 341                 /* Write it out and update our limit */
 342                 pci_hose_write_config_dword (hose, dev, bar, bar_value);
 343
 344                 if (found_mem64) {
 345                         bar += 4;
 346                         pci_hose_write_config_dword (hose, dev, bar, 0x00000000);
 347                 }
 348         }
 349
 350         /* Configure Cache Line Size Register */
 351         pci_hose_write_config_byte (hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
 352
 353         /* Configure Latency Timer */
 354         pci_hose_write_config_byte (hose, dev, PCI_LATENCY_TIMER, 0x80);
 355
 356         /* Disable interrupt line, if device says it wants to use interrupts */
 357         pci_hose_read_config_byte (hose, dev, PCI_INTERRUPT_PIN, &pin);
 358         if (pin != 0) {
 359                 pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, 0xff);
 360         }
 361
 362         pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &old_command);
 363         pci_hose_write_config_dword (hose, dev, PCI_COMMAND,
 364                                      (old_command & 0xffff0000) | command);
 365
 366         return 0;
 367 }
 368
 369 /*
 370  *
 371  */
 372
 373 struct pci_config_table *pci_find_config(struct pci_controller *hose,
 374                                          unsigned short class,
 375                                          unsigned int vendor,
 376                                          unsigned int device,
 377                                          unsigned int bus,
 378                                          unsigned int dev,
 379                                          unsigned int func)
 380 {
 381         struct pci_config_table *table;
 382
 383         for (table = hose->config_table; table && table->vendor; table++) {
 384                 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
 385                     (table->device == PCI_ANY_ID || table->device == device) &&
 386                     (table->class  == PCI_ANY_ID || table->class  == class)  &&
 387                     (table->bus    == PCI_ANY_ID || table->bus    == bus)    &&
 388                     (table->dev    == PCI_ANY_ID || table->dev    == dev)    &&
 389                     (table->func   == PCI_ANY_ID || table->func   == func)) {
 390                         return table;
 391                 }
 392         }
 393
 394         return NULL;
 395 }
 396
 397 void pci_cfgfunc_config_device(struct pci_controller *hose,
 398                                pci_dev_t dev,
 399                                struct pci_config_table *entry)
 400 {
 401         pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]);
 402 }
 403
 404 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
 405                             pci_dev_t dev, struct pci_config_table *entry)
 406 {
 407 }
 408
 409 /*
 410  *
 411  */
 412
 413 /* HJF: Changed this to return int. I think this is required
 414  * to get the correct result when scanning bridges
 415  */
 416 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
 417 extern void pciauto_config_init(struct pci_controller *hose);
 418
 419 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
 420 {
 421         unsigned int sub_bus, found_multi=0;
 422         unsigned short vendor, device, class;
 423         unsigned char header_type;
 424         struct pci_config_table *cfg;
 425         pci_dev_t dev;
 426
 427         sub_bus = bus;
 428
 429         for (dev =  PCI_BDF(bus,0,0);
 430              dev <  PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
 431              dev += PCI_BDF(0,0,1))
 432         {
 433
 434 #ifndef CONFIG_MARVELL
 435                 /* Skip our host bridge */
 436                 if ( dev == PCI_BDF(hose->first_busno,0,0) ) {
 437 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE)              /* don't skip host bridge */
 438                         /*
 439                          * Only skip hostbridge configuration if "pciconfighost" is not set
 440                          */
 441                         if (getenv("pciconfighost") == NULL) {
 442                                 continue; /* Skip our host bridge */
 443                         }
 444 #else
 445                         continue; /* Skip our host bridge */
 446 #endif
 447                 }
 448 #endif /* CONFIG_MARVELL */
 449                 if (PCI_FUNC(dev) && !found_multi)
 450                         continue;
 451
 452                 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
 453
 454                 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
 455
 456                 if (vendor != 0xffff && vendor != 0x0000) {
 457
 458                         if (!PCI_FUNC(dev))
 459                                 found_multi = header_type & 0x80;
 460
 461                         debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n",
 462                                 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
 463
 464                         pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
 465                         pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 466
 467                         cfg = pci_find_config(hose, class, vendor, device,
 468                                               PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
 469                         if (cfg) {
 470                                 cfg->config_device(hose, dev, cfg);
 471 #ifdef CONFIG_PCI_PNP
 472                         } else {
 473                                 int n = pciauto_config_device(hose, dev);
 474
 475                                 sub_bus = max(sub_bus, n);
 476 #endif
 477                         }
 478                         if (hose->fixup_irq)
 479                                 hose->fixup_irq(hose, dev);
 480
 481 #ifdef CONFIG_PCI_SCAN_SHOW
 482                         /* Skip our host bridge */
 483                         if ( dev != PCI_BDF(hose->first_busno,0,0) ) {
 484                             unsigned char int_line;
 485
 486                             pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_LINE,
 487                                                       &int_line);
 488                             printf("        %02x  %02x  %04x  %04x  %04x  %02x\n",
 489                                    PCI_BUS(dev), PCI_DEV(dev), vendor, device, class,
 490                                    int_line);
 491                         }
 492 #endif
 493                 }
 494         }
 495
 496         return sub_bus;
 497 }
 498
 499 int pci_hose_scan(struct pci_controller *hose)
 500 {
 501 #ifdef CONFIG_PCI_PNP
 502         pciauto_config_init(hose);
 503 #endif
 504         return pci_hose_scan_bus(hose, hose->first_busno);
 505 }
 506
 507 void pci_init(void)
 508 {
 509 #if defined(CONFIG_PCI_BOOTDELAY)
 510         char *s;
 511         int i;
 512
 513         /* wait "pcidelay" ms (if defined)... */
 514         s = getenv ("pcidelay");
 515         if (s) {
 516                 int val = simple_strtoul (s, NULL, 10);
 517                 for (i=0; i<val; i++)
 518                         udelay (1000);
 519         }
 520 #endif /* CONFIG_PCI_BOOTDELAY */
 521
 522         /* now call board specific pci_init()... */
 523         pci_init_board();
 524 }
 525
 526 #endif /* CONFIG_PCI */