sys/boot/common/isapnp.h

   1 /*
   2  * Copyright (c) 1996, Sujal M. Patel
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Sujal M. Patel
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  *
  32  * $FreeBSD: src/sys/boot/common/isapnp.h,v 1.7 2002/03/20 07:59:37 alfred Exp $
  33  * $DragonFly: src/sys/boot/common/isapnp.h,v 1.6 2006/10/23 21:50:31 dillon Exp $
  34  */
  35
  36 #ifndef _BOOT_COMMON_ISAPNP_H_
  37 #define _BOOT_COMMON_ISAPNP_H_
  38
  39 /* Maximum Number of PnP Devices.  8 should be plenty */
  40 #define MAX_PNP_CARDS 8
  41 /*
  42  * the following is the maximum number of PnP Logical devices that
  43  * userconfig can handle.
  44  */
  45 #define MAX_PNP_LDN     20
  46
  47 /* Static ports to access PnP state machine */
  48 #ifndef _KERNEL
  49 #define _PNP_ADDRESS            0x279
  50 #define _PNP_WRITE_DATA         0xa79
  51 #endif
  52
  53 /* PnP Registers.  Write to ADDRESS and then use WRITE/READ_DATA */
  54 #define SET_RD_DATA             0x00
  55         /***
  56         Writing to this location modifies the address of the port used for
  57         reading from the Plug and Play ISA cards.   Bits[7:0] become I/O
  58         read port address bits[9:2].  Reads from this register are ignored.
  59         ***/
  60
  61 #define SERIAL_ISOLATION        0x01
  62         /***
  63         A read to this register causes a Plug and Play cards in the Isolation
  64         state to compare one bit of the boards ID.
  65         This register is read only.
  66         ***/
  67
  68 #define CONFIG_CONTROL          0x02
  69         /***
  70         Bit[2]  Reset CSN to 0
  71         Bit[1]  Return to the Wait for Key state
  72         Bit[0]  Reset all logical devices and restore configuration
  73                 registers to their power-up values.
  74
  75         A write to bit[0] of this register performs a reset function on
  76         all logical devices.  This resets the contents of configuration
  77         registers to  their default state.  All card's logical devices
  78         enter their default state and the CSN is preserved.
  79
  80         A write to bit[1] of this register causes all cards to enter the
  81         Wait for Key state but all CSNs are preserved and logical devices
  82         are not affected.
  83
  84         A write to bit[2] of this register causes all cards to reset their
  85         CSN to zero .
  86
  87         This register is write-only.  The values are not sticky, that is,
  88         hardware will automatically clear them and there is no need for
  89         software to clear the bits.
  90         ***/
  91
  92 #define WAKE                    0x03
  93         /***
  94         A write to this port will cause all cards that have a CSN that
  95         matches the write data[7:0] to go from the Sleep state to the either
  96         the Isolation state if the write data for this command is zero or
  97         the Config state if the write data is not zero.  Additionally, the
  98         pointer to the byte-serial device is reset.  This register is
  99         writeonly.
 100         ***/
 101
 102 #define RESOURCE_DATA           0x04
 103         /***
 104         A read from this address reads the next byte of resource information.
 105         The Status register must be polled until bit[0] is set before this
 106         register may be read.  This register is read only.
 107         ***/
 108
 109 #define STATUS                  0x05
 110         /***
 111         Bit[0] when set indicates it is okay to read the next data byte
 112         from the Resource Data register.  This register is readonly.
 113         ***/
 114
 115 #define SET_CSN                 0x06
 116         /***
 117         A write to this port sets a card's CSN.  The CSN is a value uniquely
 118         assigned to each ISA card after the serial identification process
 119         so that each card may be individually selected during a Wake[CSN]
 120         command. This register is read/write.
 121         ***/
 122
 123 #define SET_LDN                 0x07
 124         /***
 125         Selects the current logical device.  All reads and writes of memory,
 126         I/O, interrupt and DMA configuration information access the registers
 127         of the logical device written here.  In addition, the I/O Range
 128         Check and Activate  commands operate only on the selected logical
 129         device.  This register is read/write. If a card has only 1 logical
 130         device, this location should be a read-only value of 0x00.
 131         ***/
 132
 133 /*** addresses 0x08 - 0x1F Card Level Reserved for future use ***/
 134 /*** addresses 0x20 - 0x2F Card Level, Vendor Defined ***/
 135
 136 #define ACTIVATE                0x30
 137         /***
 138         For each logical device there is one activate register that controls
 139         whether or not the logical device is active on the ISA bus.  Bit[0],
 140         if set, activates the logical device.  Bits[7:1] are reserved and
 141         must return 0 on reads.  This is a read/write register. Before a
 142         logical device is activated, I/O range check must be disabled.
 143         ***/
 144
 145 #define IO_RANGE_CHECK          0x31
 146         /***
 147         This register is used to perform a conflict check on the I/O port
 148         range programmed for use by a logical device.
 149
 150         Bit[7:2]  Reserved and must return 0 on reads
 151         Bit[1]    Enable I/O Range check, if set then I/O Range Check
 152         is enabled. I/O range check is only valid when the logical
 153         device is inactive.
 154
 155         Bit[0], if set, forces the logical device to respond to I/O reads
 156         of the logical device's assigned I/O range with a 0x55 when I/O
 157         range check is in operation.  If clear, the logical device drives
 158         0xAA.  This register is read/write.
 159         ***/
 160
 161 /*** addr 0x32 - 0x37 Logical Device Control Reserved for future use ***/
 162 /*** addr 0x38 - 0x3F Logical Device Control Vendor Define ***/
 163
 164 #define MEM_CONFIG              0x40
 165         /***
 166         Four memory resource registers per range, four ranges.
 167         Fill with 0 if no ranges are enabled.
 168
 169         Offset 0:       RW Memory base address bits[23:16]
 170         Offset 1:       RW Memory base address bits[15:8]
 171         Offset 2:       Memory control
 172             Bit[1] specifies 8/16-bit control.  This bit is set to indicate
 173             16-bit memory, and cleared to indicate 8-bit memory.
 174             Bit[0], if cleared, indicates the next field can be used as a range
 175             length for decode (implies range length and base alignment of memory
 176             descriptor are equal).
 177             Bit[0], if set, indicates the next field is the upper limit for
 178             the address. -  - Bit[0] is read-only.
 179         Offset 3:       RW upper limit or range len, bits[23:16]
 180         Offset 4:       RW upper limit or range len, bits[15:8]
 181         Offset 5-Offset 7: filler, unused.
 182         ***/
 183
 184 #define IO_CONFIG_BASE          0x60
 185         /***
 186         Eight ranges, two bytes per range.
 187         Offset 0:               I/O port base address bits[15:8]
 188         Offset 1:               I/O port base address bits[7:0]
 189         ***/
 190
 191 #define IRQ_CONFIG              0x70
 192         /***
 193         Two entries, two bytes per entry.
 194         Offset 0:       RW interrupt level (1..15, 0=unused).
 195         Offset 1:       Bit[1]: level(1:hi, 0:low),
 196                         Bit[0]: type (1:level, 0:edge)
 197                 byte 1 can be readonly if 1 type of int is used.
 198         ***/
 199
 200 #define DRQ_CONFIG              0x74
 201         /***
 202         Two entries, one byte per entry. Bits[2:0] select
 203         which DMA channel is in use for DMA 0.  Zero selects DMA channel
 204         0, seven selects DMA channel 7. DMA channel 4, the cascade channel
 205         is used to indicate no DMA channel is active.
 206         ***/
 207
 208 /*** 32-bit memory accesses are at 0x76 ***/
 209
 210 /* Macros to parse Resource IDs */
 211 #define PNP_RES_TYPE(a)         (a >> 7)
 212 #define PNP_SRES_NUM(a)         (a >> 3)
 213 #define PNP_SRES_LEN(a)         (a & 0x07)
 214 #define PNP_LRES_NUM(a)         (a & 0x7f)
 215
 216 /* Small Resource Item names */
 217 #define PNP_VERSION             0x1
 218 #define LOG_DEVICE_ID           0x2
 219 #define COMP_DEVICE_ID          0x3
 220 #define IRQ_FORMAT              0x4
 221 #define DMA_FORMAT              0x5
 222 #define START_DEPEND_FUNC       0x6
 223 #define END_DEPEND_FUNC         0x7
 224 #define IO_PORT_DESC            0x8
 225 #define FIXED_IO_PORT_DESC      0x9
 226 #define SM_RES_RESERVED         0xa-0xd
 227 #define SM_VENDOR_DEFINED       0xe
 228 #define END_TAG                 0xf
 229
 230 /* Large Resource Item names */
 231 #define MEMORY_RANGE_DESC       0x1
 232 #define ID_STRING_ANSI          0x2
 233 #define ID_STRING_UNICODE       0x3
 234 #define LG_VENDOR_DEFINED       0x4
 235 #define _32BIT_MEM_RANGE_DESC   0x5
 236 #define _32BIT_FIXED_LOC_DESC   0x6
 237 #define LG_RES_RESERVED         0x7-0x7f
 238
 239 /*
 240  * pnp_cinfo contains Configuration Information. They are used
 241  * to communicate to the device driver the actual configuration
 242  * of the device, and also by the userconfig menu to let the
 243  * operating system override any configuration set by the bios.
 244  *
 245  */
 246 struct pnp_cinfo {
 247         u_int vendor_id;        /* board id */
 248         u_int serial;           /* Board's Serial Number */
 249         u_long flags;           /* OS-reserved flags */
 250         u_char csn;             /* assigned Card Select Number */
 251         u_char ldn;             /* Logical Device Number */
 252         u_char enable;          /* pnp enable */
 253         u_char override;        /* override bios parms (in userconfig) */
 254         u_char irq[2];          /* IRQ Number */
 255         u_char irq_type[2];     /* IRQ Type */
 256         u_char drq[2];
 257         u_short port[8];        /* The Base Address of the Port */
 258         struct {
 259                 u_long base;    /* Memory Base Address */
 260                 int control;    /* Memory Control Register */
 261                 u_long range;   /* Memory Range *OR* Upper Limit */
 262         } mem[4];
 263 };
 264
 265 #ifdef _KERNEL
 266
 267 struct pnp_device {
 268     char *pd_name;
 269     char * (*pd_probe ) (u_long csn, u_long vendor_id);
 270     void (*pd_attach ) (u_long csn, u_long vend_id, char * name,
 271         struct isa_device *dev);
 272     u_long      *pd_count;
 273     u_int *imask ;
 274 };
 275
 276 struct _pnp_id {
 277     u_long vendor_id;
 278     u_long serial;
 279     u_char checksum;
 280 } ;
 281
 282 struct pnp_dlist_node {
 283     struct pnp_device *pnp;
 284     struct isa_device dev;
 285     struct pnp_dlist_node *next;
 286 };
 287
 288 typedef struct _pnp_id pnp_id;
 289 extern struct pnp_dlist_node *pnp_device_list;
 290 extern pnp_id pnp_devices[MAX_PNP_CARDS];
 291 extern struct pnp_cinfo pnp_ldn_overrides[MAX_PNP_LDN];
 292 extern int pnp_overrides_valid;
 293
 294 /*
 295  * these two functions are for use in drivers
 296  */
 297 int read_pnp_parms(struct pnp_cinfo *d, int ldn);
 298 int write_pnp_parms(struct pnp_cinfo *d, int ldn);
 299 int enable_pnp_card(void);
 300
 301 /*
 302  * used by autoconfigure to actually probe and attach drivers
 303  */
 304 void pnp_configure(void);
 305
 306 #endif /* _KERNEL */
 307
 308 #endif /* !_BOOT_COMMON_ISAPNP_H_ */