sound/apu.h

   1 ;
   2 ;    Copyright (C) 2004, 2005 Kent Hansen.
   3 ;
   4 ;    This file is part of Neotoxin.
   5 ;
   6 ;    Neotoxin is free software; you can redistribute it and/or modify
   7 ;    it under the terms of the GNU General Public License as published by
   8 ;    the Free Software Foundation; either version 2 of the License, or
   9 ;    (at your option) any later version.
  10 ;
  11 ;    Neotoxin is distributed in the hope that it will be useful,
  12 ;    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;    GNU General Public License for more details.
  15 ;
  16 ;    You should have received a copy of the GNU General Public License
  17 ;    along with this program; if not, write to the Free Software
  18 ;    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19 ;
  20
  21 .ifndef APU_H
  22 .define APU_H
  23
  24 ; Hardware regs.
  25 APU_SQUARE0_BASE_REG    .equ $4000
  26 APU_SQUARE1_BASE_REG    .equ $4004
  27 APU_TRI_BASE_REG        .equ $4008
  28 APU_NOISE_BASE_REG      .equ $400C
  29 APU_DMC_BASE_REG        .equ $4010
  30 APU_STATUS_REG          .equ $4015  ; read
  31 APU_CTRL_REG            .equ $4015  ; write
  32 APU_FRAME_CTRL_REG      .equ $4017
  33
  34 .record apu_frame_ctrl mode:1, irq:1, pad0:6
  35
  36 APU_FRAME_CTRL_MODE     .equ mask apu_frame_ctrl::mode
  37 APU_FRAME_CTRL_IRQ      .equ mask apu_frame_ctrl::irq
  38
  39 .record apu_status dmc_irq:1, frame_irq:1, pad0:1, dmc_ctr:1, noise_ctr:1, tri_ctr:1, sq1_ctr:1, sq0_ctr:1
  40 .record apu_ctrl pad0:3, dmc_on:1, noise_on:1, tri_on:1, sq1_on:1, sq0_on:1
  41
  42 ; Bitmasks to interpret APU_STATUS_REG.
  43 APU_STATUS_DMC_IRQ      .equ mask apu_status::dmc_irq
  44 APU_STATUS_FRAME_IRQ    .equ mask apu_status::frame_irq
  45 APU_STATUS_DMC_CTR      .equ mask apu_status::dmc_ctr
  46 APU_STATUS_NOISE_CTR    .equ mask apu_status::noise_ctr
  47 APU_STATUS_TRI_CTR      .equ mask apu_status::tri_ctr
  48 APU_STATUS_SQUARE1_CTR  .equ mask apu_status::sq1_ctr
  49 APU_STATUS_SQUARE0_CTR  .equ mask apu_status::sq0_ctr
  50
  51 ; Bitmasks that can be OR'ed together to create APU_CTRL_REG-compatible value.
  52 APU_CTRL_DMC_ON         .equ APU_STATUS_DMC_CTR
  53 APU_CTRL_NOISE_ON       .equ APU_STATUS_NOISE_CTR
  54 APU_CTRL_TRI_ON         .equ APU_STATUS_TRI_CTR
  55 APU_CTRL_SQUARE1_ON     .equ APU_STATUS_SQ1_CTR
  56 APU_CTRL_SQUARE0_ON     .equ APU_STATUS_SQ0_CTR
  57
  58 .record square_ctrl duty:2, loop:1, env:1, vol:4
  59 .record square_sweep enable:1, period:3, neg:1, shift:3
  60
  61 APU_SQUARE_CTRL_DUTY    .equ mask square_ctrl::duty ; Duty cycle
  62 APU_SQUARE_CTRL_LOOP    .equ mask square_ctrl::loop ; Loop envelope
  63 APU_SQUARE_CTRL_HALT    .equ mask square_ctrl::loop ; Halt length (NB: shared with loop)
  64 APU_SQUARE_CTRL_ENV     .equ mask square_ctrl::env  ; Disable envelope
  65 APU_SQUARE_CTRL_VOL     .equ mask square_ctrl::vol  ; Volume / envelope period
  66
  67 APU_SQUARE_SWEEP_ENABLE .equ mask square_sweep::enable
  68 APU_SQUARE_SWEEP_PERIOD .equ mask square_sweep::period
  69 APU_SQUARE_SWEEP_NEG    .equ mask square_sweep::neg
  70 APU_SQUARE_SWEEP_SHIFT  .equ mask square_sweep::shift
  71
  72 .record noise_ctrl pad0:2, loop:1, env:1, vol:4
  73 .record noise_reg2 short:1, pad0:3, period_idx:4
  74 .record noise_reg3 length_idx:5, pad0:3
  75
  76 APU_NOISE_CTRL_LOOP .equ mask noise_ctrl::loop  ; Loop enable
  77 APU_NOISE_CTRL_ENV  .equ mask noise_ctrl::env   ; Envelope disable
  78 APU_NOISE_CTRL_VOL  .equ mask noise_ctrl::vol   ; Volume / envelope period
  79
  80 .record dmc_ctrl irq:1, loop:1, pad0:2, freq_idx:4
  81
  82 APU_DMC_CTRL_IRQ            .equ mask dmc_ctrl::irq         ; IRQ enable
  83 APU_DMC_CTRL_LOOP           .equ mask dmc_ctrl::loop        ; Loop
  84 APU_DMC_CTRL_FREQ_INDEX     .equ mask dmc_ctrl::freq_idx    ; Frequency index
  85
  86 .endif  ; !APU_H