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More minor IPI work.
[dragonfly/vkernel-mp.git] / sys / dev / agp / agp_nvidia.c
blob9d8e1145ec0872170b8c2fb5cb8d2d428ed0aedf
1 /*-
2 * Copyright (c) 2003 Matthew N. Dodd <winter@jurai.net>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * Based on FreeBSD v1.2.
27 * $DragonFly: src/sys/dev/agp/agp_nvidia.c,v 1.4 2006/10/25 22:55:52 dillon Exp $
28 */
29
30 /*
31 * Written using information gleaned from the
32 * NVIDIA nForce/nForce2 AGPGART Linux Kernel Patch.
33 */
34
35 #include "opt_bus.h"
36 #include "opt_pci.h"
37
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/malloc.h>
41 #include <sys/kernel.h>
42 #include <sys/bus.h>
43 #include <sys/lock.h>
44 #include <sys/rman.h>
45
46 #include <bus/pci/pcivar.h>
47 #include <bus/pci/pcireg.h>
48 #include "agppriv.h"
49 #include "agpreg.h"
50
51 #include <vm/vm.h>
52 #include <vm/vm_object.h>
53 #include <vm/pmap.h>
54
55 #define NVIDIA_VENDORID 0x10de
56 #define NVIDIA_DEVICEID_NFORCE 0x01a4
57 #define NVIDIA_DEVICEID_NFORCE2 0x01e0
58
59 struct agp_nvidia_softc {
60 struct agp_softc agp;
61 u_int32_t initial_aperture; /* aperture size at startup */
62 struct agp_gatt * gatt;
63
64 device_t dev; /* AGP Controller */
65 device_t mc1_dev; /* Memory Controller */
66 device_t mc2_dev; /* Memory Controller */
67 device_t bdev; /* Bridge */
68
69 u_int32_t wbc_mask;
70 int num_dirs;
71 int num_active_entries;
72 off_t pg_offset;
73 };
74
75 static const char * agp_nvidia_match (device_t dev);
76 static int agp_nvidia_probe (device_t);
77 static int agp_nvidia_attach (device_t);
78 static int agp_nvidia_detach (device_t);
79 static u_int32_t agp_nvidia_get_aperture (device_t);
80 static int agp_nvidia_set_aperture (device_t, u_int32_t);
81 static int agp_nvidia_bind_page (device_t, int, vm_offset_t);
82 static int agp_nvidia_unbind_page (device_t, int);
83
84 static int nvidia_init_iorr (u_int32_t, u_int32_t);
85
86 static const char *
87 agp_nvidia_match (device_t dev)
88 {
89 if (pci_get_class(dev) != PCIC_BRIDGE ||
90 pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
91 pci_get_vendor(dev) != NVIDIA_VENDORID)
92 return (NULL);
93
94 switch (pci_get_device(dev)) {
95 case NVIDIA_DEVICEID_NFORCE:
96 return ("NVIDIA nForce AGP Controller");
97 case NVIDIA_DEVICEID_NFORCE2:
98 return ("NVIDIA nForce2 AGP Controller");
99 }
100 return ("NVIDIA Generic AGP Controller");
101 }
102
103 static int
104 agp_nvidia_probe (device_t dev)
105 {
106 const char *desc;
107
108 desc = agp_nvidia_match(dev);
109 if (desc) {
110 device_verbose(dev);
111 device_set_desc(dev, desc);
112 return (0);
113 }
114 return (ENXIO);
115 }
116
117 static int
118 agp_nvidia_attach (device_t dev)
119 {
120 struct agp_nvidia_softc *sc = device_get_softc(dev);
121 struct agp_gatt *gatt;
122 u_int32_t apbase;
123 u_int32_t aplimit;
124 u_int32_t temp;
125 int size;
126 int i;
127 int error;
128
129 switch (pci_get_device(dev)) {
130 case NVIDIA_DEVICEID_NFORCE:
131 sc->wbc_mask = 0x00010000;
132 break;
133 case NVIDIA_DEVICEID_NFORCE2:
134 sc->wbc_mask = 0x80000000;
135 break;
136 default:
137 sc->wbc_mask = 0;
138 break;
139 }
140
141 /* AGP Controller */
142 sc->dev = dev;
143
144 /* Memory Controller 1 */
145 sc->mc1_dev = pci_find_bsf(pci_get_bus(dev), 0, 1);
146 if (sc->mc1_dev == NULL) {
147 device_printf(dev,
148 "Unable to find NVIDIA Memory Controller 1.\n");
149 return (ENODEV);
150 }
151
152 /* Memory Controller 2 */
153 sc->mc2_dev = pci_find_bsf(pci_get_bus(dev), 0, 2);
154 if (sc->mc2_dev == NULL) {
155 device_printf(dev,
156 "Unable to find NVIDIA Memory Controller 2.\n");
157 return (ENODEV);
158 }
159
160 /* AGP Host to PCI Bridge */
161 sc->bdev = pci_find_bsf(pci_get_bus(dev), 30, 0);
162 if (sc->bdev == NULL) {
163 device_printf(dev,
164 "Unable to find NVIDIA AGP Host to PCI Bridge.\n");
165 return (ENODEV);
166 }
167
168 error = agp_generic_attach(dev);
169 if (error)
170 return (error);
171
172 sc->initial_aperture = AGP_GET_APERTURE(dev);
173
174 for (;;) {
175 gatt = agp_alloc_gatt(dev);
176 if (gatt)
177 break;
178 /*
179 * Probably contigmalloc failure. Try reducing the
180 * aperture so that the gatt size reduces.
181 */
182 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2))
183 goto fail;
184 }
185 sc->gatt = gatt;
186
187 apbase = rman_get_start(sc->agp.as_aperture);
188 aplimit = apbase + AGP_GET_APERTURE(dev) - 1;
189 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APBASE, apbase, 4);
190 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APLIMIT, aplimit, 4);
191 pci_write_config(sc->bdev, AGP_NVIDIA_3_APBASE, apbase, 4);
192 pci_write_config(sc->bdev, AGP_NVIDIA_3_APLIMIT, aplimit, 4);
193
194 error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(dev));
195 if (error) {
196 device_printf(dev, "Failed to setup IORRs\n");
197 goto fail;
198 }
199
200 /* directory size is 64k */
201 size = AGP_GET_APERTURE(dev) / 1024 / 1024;
202 sc->num_dirs = size / 64;
203 sc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4);
204 sc->pg_offset = 0;
205 if (sc->num_dirs == 0) {
206 sc->num_dirs = 1;
207 sc->num_active_entries /= (64 / size);
208 sc->pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
209 ~(AGP_GET_APERTURE(dev) - 1)) / PAGE_SIZE;
210 }
211
212 /* (G)ATT Base Address */
213 for (i = 0; i < 8; i++) {
214 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_ATTBASE(i),
215 (sc->gatt->ag_physical +
216 (i % sc->num_dirs) * 64 * 1024),
217 4);
218 }
219
220 /* GTLB Control */
221 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
222 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp | 0x11, 4);
223
224 /* GART Control */
225 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
226 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp | 0x100, 4);
227
228 return (0);
229 fail:
230 agp_generic_detach(dev);
231 return (ENOMEM);
232 }
233
234 static int
235 agp_nvidia_detach (device_t dev)
236 {
237 struct agp_nvidia_softc *sc = device_get_softc(dev);
238 int error;
239 u_int32_t temp;
240
241 error = agp_generic_detach(dev);
242 if (error)
243 return (error);
244
245 /* GART Control */
246 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
247 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp & ~(0x100), 4);
248
249 /* GTLB Control */
250 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
251 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11), 4);
252
253 /* Put the aperture back the way it started. */
254 AGP_SET_APERTURE(dev, sc->initial_aperture);
255
256 /* restore iorr for previous aperture size */
257 nvidia_init_iorr(rman_get_start(sc->agp.as_aperture),
258 sc->initial_aperture);
259
260 agp_free_gatt(sc->gatt);
261
262 return (0);
263 }
264
265 static u_int32_t
266 agp_nvidia_get_aperture(device_t dev)
267 {
268 u_int8_t key;
269
270 key = ffs(pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f);
271 return (1 << (24 + (key ? key : 5)));
272 }
273
274 static int
275 agp_nvidia_set_aperture(device_t dev, u_int32_t aperture)
276 {
277 u_int8_t val;
278 u_int8_t key;
279
280 switch (aperture) {
281 case (512 * 1024 * 1024): key = 0; break;
282 case (256 * 1024 * 1024): key = 8; break;
283 case (128 * 1024 * 1024): key = 12; break;
284 case (64 * 1024 * 1024): key = 14; break;
285 case (32 * 1024 * 1024): key = 15; break;
286 default:
287 device_printf(dev, "Invalid aperture size (%dMb)\n",
288 aperture / 1024 / 1024);
289 return (EINVAL);
290 }
291 val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1);
292 pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1);
293
294 return (0);
295 }
296
297 static int
298 agp_nvidia_bind_page(device_t dev, int offset, vm_offset_t physical)
299 {
300 struct agp_nvidia_softc *sc = device_get_softc(dev);
301 u_int32_t index;
302
303 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
304 return (EINVAL);
305
306 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
307 sc->gatt->ag_virtual[index] = physical;
308
309 return (0);
310 }
311
312 static int
313 agp_nvidia_unbind_page(device_t dev, int offset)
314 {
315 struct agp_nvidia_softc *sc = device_get_softc(dev);
316 u_int32_t index;
317
318 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
319 return (EINVAL);
320
321 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
322 sc->gatt->ag_virtual[index] = 0;
323
324 return (0);
325 }
326
327 static int
328 agp_nvidia_flush_tlb (device_t dev, int offset)
329 {
330 struct agp_nvidia_softc *sc;
331 u_int32_t wbc_reg, temp;
332 int i;
333
334 sc = (struct agp_nvidia_softc *)device_get_softc(dev);
335
336 if (sc->wbc_mask) {
337 wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4);
338 wbc_reg |= sc->wbc_mask;
339 pci_write_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, wbc_reg, 4);
340
341 /* Wait no more than 3 seconds. */
342 for (i = 0; i < 3000; i++) {
343 wbc_reg = pci_read_config(sc->mc1_dev,
344 AGP_NVIDIA_1_WBC, 4);
345 if ((sc->wbc_mask & wbc_reg) == 0)
346 break;
347 else
348 DELAY(1000);
349 }
350 if (i == 3000)
351 device_printf(dev,
352 "TLB flush took more than 3 seconds.\n");
353 }
354
355 /* Flush TLB entries. */
356 for(i = 0; i < 32 + 1; i++)
357 temp = sc->gatt->ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
358 for(i = 0; i < 32 + 1; i++)
359 temp = sc->gatt->ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
360
361 return (0);
362 }
363
364 #define SYSCFG 0xC0010010
365 #define IORR_BASE0 0xC0010016
366 #define IORR_MASK0 0xC0010017
367 #define AMD_K7_NUM_IORR 2
368
369 static int
370 nvidia_init_iorr(u_int32_t addr, u_int32_t size)
371 {
372 quad_t base, mask, sys;
373 u_int32_t iorr_addr, free_iorr_addr;
374
375 /* Find the iorr that is already used for the addr */
376 /* If not found, determine the uppermost available iorr */
377 free_iorr_addr = AMD_K7_NUM_IORR;
378 for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
379 base = rdmsr(IORR_BASE0 + 2 * iorr_addr);
380 mask = rdmsr(IORR_MASK0 + 2 * iorr_addr);
381
382 if ((base & 0xfffff000ULL) == (addr & 0xfffff000))
383 break;
384
385 if ((mask & 0x00000800ULL) == 0)
386 free_iorr_addr = iorr_addr;
387 }
388
389 if (iorr_addr >= AMD_K7_NUM_IORR) {
390 iorr_addr = free_iorr_addr;
391 if (iorr_addr >= AMD_K7_NUM_IORR)
392 return (EINVAL);
393 }
394
395 base = (addr & ~0xfff) | 0x18;
396 mask = (0xfULL << 32) | ((~(size - 1)) & 0xfffff000) | 0x800;
397 wrmsr(IORR_BASE0 + 2 * iorr_addr, base);
398 wrmsr(IORR_MASK0 + 2 * iorr_addr, mask);
399
400 sys = rdmsr(SYSCFG);
401 sys |= 0x00100000ULL;
402 wrmsr(SYSCFG, sys);
403
404 return (0);
405 }
406
407 static device_method_t agp_nvidia_methods[] = {
408 /* Device interface */
409 DEVMETHOD(device_probe, agp_nvidia_probe),
410 DEVMETHOD(device_attach, agp_nvidia_attach),
411 DEVMETHOD(device_detach, agp_nvidia_detach),
412 DEVMETHOD(device_shutdown, bus_generic_shutdown),
413 DEVMETHOD(device_suspend, bus_generic_suspend),
414 DEVMETHOD(device_resume, bus_generic_resume),
415
416 /* AGP interface */
417 DEVMETHOD(agp_get_aperture, agp_nvidia_get_aperture),
418 DEVMETHOD(agp_set_aperture, agp_nvidia_set_aperture),
419 DEVMETHOD(agp_bind_page, agp_nvidia_bind_page),
420 DEVMETHOD(agp_unbind_page, agp_nvidia_unbind_page),
421 DEVMETHOD(agp_flush_tlb, agp_nvidia_flush_tlb),
422
423 DEVMETHOD(agp_enable, agp_generic_enable),
424 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
425 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
426 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
427 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
428
429 { 0, 0 }
430 };
431
432 static driver_t agp_nvidia_driver = {
433 "agp",
434 agp_nvidia_methods,
435 sizeof(struct agp_nvidia_softc),
436 };
437
438 static devclass_t agp_devclass;
439
440 DRIVER_MODULE(agp_nvidia, pci, agp_nvidia_driver, agp_devclass, 0, 0);
441 MODULE_DEPEND(agp_nvidia, agp, 1, 1, 1);
442 MODULE_DEPEND(agp_nvidia, pci, 1, 1, 1);
DragonFly vkernel multiprocessor port