1 // SPDX-License-Identifier: GPL-2.0
3 * linux/arch/alpha/kernel/sys_mikasa.c
5 * Copyright (C) 1995 David A Rusling
6 * Copyright (C) 1996 Jay A Estabrook
7 * Copyright (C) 1998, 1999 Richard Henderson
9 * Code supporting the MIKASA (AlphaServer 1000).
12 #include <linux/kernel.h>
13 #include <linux/types.h>
15 #include <linux/sched.h>
16 #include <linux/pci.h>
17 #include <linux/init.h>
18 #include <linux/bitops.h>
20 #include <asm/ptrace.h>
24 #include <asm/mmu_context.h>
26 #include <asm/core_cia.h>
27 #include <asm/tlbflush.h>
32 #include "machvec_impl.h"
35 /* Note mask bit is true for ENABLED irqs. */
36 static int cached_irq_mask
;
39 mikasa_update_irq_hw(int mask
)
45 mikasa_enable_irq(struct irq_data
*d
)
47 mikasa_update_irq_hw(cached_irq_mask
|= 1 << (d
->irq
- 16));
51 mikasa_disable_irq(struct irq_data
*d
)
53 mikasa_update_irq_hw(cached_irq_mask
&= ~(1 << (d
->irq
- 16)));
56 static struct irq_chip mikasa_irq_type
= {
58 .irq_unmask
= mikasa_enable_irq
,
59 .irq_mask
= mikasa_disable_irq
,
60 .irq_mask_ack
= mikasa_disable_irq
,
64 mikasa_device_interrupt(unsigned long vector
)
69 /* Read the interrupt summary registers */
70 pld
= (((~inw(0x534) & 0x0000ffffUL
) << 16)
71 | (((unsigned long) inb(0xa0)) << 8)
75 * Now for every possible bit set, work through them and call
76 * the appropriate interrupt handler.
80 pld
&= pld
- 1; /* clear least bit set */
82 isa_device_interrupt(vector
);
95 alpha_mv
.device_interrupt
= srm_device_interrupt
;
97 mikasa_update_irq_hw(0);
99 for (i
= 16; i
< 32; ++i
) {
100 irq_set_chip_and_handler(i
, &mikasa_irq_type
,
102 irq_set_status_flags(i
, IRQ_LEVEL
);
106 common_init_isa_dma();
111 * PCI Fixup configuration.
115 * 0 Interrupt Line A from slot 0
116 * 1 Interrupt Line B from slot 0
117 * 2 Interrupt Line C from slot 0
118 * 3 Interrupt Line D from slot 0
119 * 4 Interrupt Line A from slot 1
120 * 5 Interrupt line B from slot 1
121 * 6 Interrupt Line C from slot 1
122 * 7 Interrupt Line D from slot 1
123 * 8 Interrupt Line A from slot 2
124 * 9 Interrupt Line B from slot 2
125 *10 Interrupt Line C from slot 2
126 *11 Interrupt Line D from slot 2
128 *13 Power Supply Fail
132 * The device to slot mapping looks like:
135 * 6 NCR SCSI controller
136 * 7 Intel PCI-EISA bridge chip
137 * 11 PCI on board slot 0
138 * 12 PCI on board slot 1
139 * 13 PCI on board slot 2
142 * This two layered interrupt approach means that we allocate IRQ 16 and
143 * above for PCI interrupts. The IRQ relates to which bit the interrupt
144 * comes in on. This makes interrupt processing much easier.
148 mikasa_map_irq(const struct pci_dev
*dev
, u8 slot
, u8 pin
)
150 static char irq_tab
[8][5] = {
151 /*INT INTA INTB INTC INTD */
152 {16+12, 16+12, 16+12, 16+12, 16+12}, /* IdSel 17, SCSI */
153 { -1, -1, -1, -1, -1}, /* IdSel 18, PCEB */
154 { -1, -1, -1, -1, -1}, /* IdSel 19, ???? */
155 { -1, -1, -1, -1, -1}, /* IdSel 20, ???? */
156 { -1, -1, -1, -1, -1}, /* IdSel 21, ???? */
157 { 16+0, 16+0, 16+1, 16+2, 16+3}, /* IdSel 22, slot 0 */
158 { 16+4, 16+4, 16+5, 16+6, 16+7}, /* IdSel 23, slot 1 */
159 { 16+8, 16+8, 16+9, 16+10, 16+11}, /* IdSel 24, slot 2 */
161 const long min_idsel
= 6, max_idsel
= 13, irqs_per_slot
= 5;
162 return COMMON_TABLE_LOOKUP
;
169 struct alpha_machine_vector mikasa_primo_mv __initmv
= {
170 .vector_name
= "Mikasa-Primo",
174 .machine_check
= cia_machine_check
,
175 .max_isa_dma_address
= ALPHA_MAX_ISA_DMA_ADDRESS
,
176 .min_io_address
= DEFAULT_IO_BASE
,
177 .min_mem_address
= CIA_DEFAULT_MEM_BASE
,
180 .device_interrupt
= mikasa_device_interrupt
,
182 .init_arch
= cia_init_arch
,
183 .init_irq
= mikasa_init_irq
,
184 .init_rtc
= common_init_rtc
,
185 .init_pci
= cia_init_pci
,
186 .kill_arch
= cia_kill_arch
,
187 .pci_map_irq
= mikasa_map_irq
,
188 .pci_swizzle
= common_swizzle
,
190 ALIAS_MV(mikasa_primo
)