1 // SPDX-License-Identifier: GPL-2.0-only
3 * max98090.c -- MAX98090 ALSA SoC Audio driver
5 * Copyright 2011-2012 Maxim Integrated Products
8 #include <linux/delay.h>
10 #include <linux/module.h>
13 #include <linux/regmap.h>
14 #include <linux/slab.h>
15 #include <linux/acpi.h>
16 #include <linux/clk.h>
17 #include <sound/jack.h>
18 #include <sound/pcm.h>
19 #include <sound/pcm_params.h>
20 #include <sound/soc.h>
21 #include <sound/tlv.h>
22 #include <sound/max98090.h>
25 /* Allows for sparsely populated register maps */
26 static const struct reg_default max98090_reg
[] = {
27 { 0x00, 0x00 }, /* 00 Software Reset */
28 { 0x03, 0x04 }, /* 03 Interrupt Masks */
29 { 0x04, 0x00 }, /* 04 System Clock Quick */
30 { 0x05, 0x00 }, /* 05 Sample Rate Quick */
31 { 0x06, 0x00 }, /* 06 DAI Interface Quick */
32 { 0x07, 0x00 }, /* 07 DAC Path Quick */
33 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
34 { 0x09, 0x00 }, /* 09 Line to ADC Quick */
35 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
36 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
37 { 0x0C, 0x00 }, /* 0C Reserved */
38 { 0x0D, 0x00 }, /* 0D Input Config */
39 { 0x0E, 0x1B }, /* 0E Line Input Level */
40 { 0x0F, 0x00 }, /* 0F Line Config */
42 { 0x10, 0x14 }, /* 10 Mic1 Input Level */
43 { 0x11, 0x14 }, /* 11 Mic2 Input Level */
44 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */
45 { 0x13, 0x00 }, /* 13 Digital Mic Config */
46 { 0x14, 0x00 }, /* 14 Digital Mic Mode */
47 { 0x15, 0x00 }, /* 15 Left ADC Mixer */
48 { 0x16, 0x00 }, /* 16 Right ADC Mixer */
49 { 0x17, 0x03 }, /* 17 Left ADC Level */
50 { 0x18, 0x03 }, /* 18 Right ADC Level */
51 { 0x19, 0x00 }, /* 19 ADC Biquad Level */
52 { 0x1A, 0x00 }, /* 1A ADC Sidetone */
53 { 0x1B, 0x00 }, /* 1B System Clock */
54 { 0x1C, 0x00 }, /* 1C Clock Mode */
55 { 0x1D, 0x00 }, /* 1D Any Clock 1 */
56 { 0x1E, 0x00 }, /* 1E Any Clock 2 */
57 { 0x1F, 0x00 }, /* 1F Any Clock 3 */
59 { 0x20, 0x00 }, /* 20 Any Clock 4 */
60 { 0x21, 0x00 }, /* 21 Master Mode */
61 { 0x22, 0x00 }, /* 22 Interface Format */
62 { 0x23, 0x00 }, /* 23 TDM Format 1*/
63 { 0x24, 0x00 }, /* 24 TDM Format 2*/
64 { 0x25, 0x00 }, /* 25 I/O Configuration */
65 { 0x26, 0x80 }, /* 26 Filter Config */
66 { 0x27, 0x00 }, /* 27 DAI Playback Level */
67 { 0x28, 0x00 }, /* 28 EQ Playback Level */
68 { 0x29, 0x00 }, /* 29 Left HP Mixer */
69 { 0x2A, 0x00 }, /* 2A Right HP Mixer */
70 { 0x2B, 0x00 }, /* 2B HP Control */
71 { 0x2C, 0x1A }, /* 2C Left HP Volume */
72 { 0x2D, 0x1A }, /* 2D Right HP Volume */
73 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */
74 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */
76 { 0x30, 0x00 }, /* 30 Spk Control */
77 { 0x31, 0x2C }, /* 31 Left Spk Volume */
78 { 0x32, 0x2C }, /* 32 Right Spk Volume */
79 { 0x33, 0x00 }, /* 33 ALC Timing */
80 { 0x34, 0x00 }, /* 34 ALC Compressor */
81 { 0x35, 0x00 }, /* 35 ALC Expander */
82 { 0x36, 0x00 }, /* 36 ALC Gain */
83 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
84 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
85 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
86 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */
87 { 0x3B, 0x00 }, /* 3B Line OutR Control */
88 { 0x3C, 0x15 }, /* 3C Line OutR Volume */
89 { 0x3D, 0x00 }, /* 3D Jack Detect */
90 { 0x3E, 0x00 }, /* 3E Input Enable */
91 { 0x3F, 0x00 }, /* 3F Output Enable */
93 { 0x40, 0x00 }, /* 40 Level Control */
94 { 0x41, 0x00 }, /* 41 DSP Filter Enable */
95 { 0x42, 0x00 }, /* 42 Bias Control */
96 { 0x43, 0x00 }, /* 43 DAC Control */
97 { 0x44, 0x06 }, /* 44 ADC Control */
98 { 0x45, 0x00 }, /* 45 Device Shutdown */
99 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
100 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
101 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
102 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
103 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
104 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
105 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
106 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
107 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
108 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
110 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
111 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
112 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
113 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
114 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
115 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
116 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
117 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
118 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
119 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
120 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
121 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
122 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
123 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
124 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
125 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
127 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
128 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
129 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
130 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
131 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
132 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
133 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
134 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
135 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
136 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
137 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
138 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
139 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
140 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
141 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
142 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
144 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
145 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
146 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
147 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
148 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
149 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
150 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
151 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
152 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
153 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
154 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
155 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
156 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
157 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
158 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
159 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
161 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
162 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
163 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
164 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
165 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
166 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
167 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
168 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
169 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
170 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
171 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
172 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
173 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
174 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
175 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
176 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
178 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
179 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
180 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
181 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
182 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
183 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
184 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
185 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
186 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
187 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
188 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
189 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
190 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
191 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
192 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
193 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
195 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
196 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
197 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
198 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
199 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
200 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
201 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
202 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
203 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
204 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
205 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
206 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
207 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
208 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
209 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
210 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
212 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
213 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
214 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
215 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
216 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
217 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
218 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
219 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
220 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
221 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
222 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
223 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
224 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
225 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
226 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
227 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
229 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
230 { 0xC1, 0x00 }, /* C1 Record TDM Slot */
231 { 0xC2, 0x00 }, /* C2 Sample Rate */
232 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
233 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
234 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
235 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
236 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
237 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
238 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
239 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
240 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
241 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
242 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
243 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
244 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
246 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
247 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
250 static bool max98090_volatile_register(struct device
*dev
, unsigned int reg
)
253 case M98090_REG_SOFTWARE_RESET
:
254 case M98090_REG_DEVICE_STATUS
:
255 case M98090_REG_JACK_STATUS
:
256 case M98090_REG_REVISION_ID
:
263 static bool max98090_readable_register(struct device
*dev
, unsigned int reg
)
266 case M98090_REG_DEVICE_STATUS
... M98090_REG_INTERRUPT_S
:
267 case M98090_REG_LINE_INPUT_CONFIG
... 0xD1:
268 case M98090_REG_REVISION_ID
:
275 static int max98090_reset(struct max98090_priv
*max98090
)
279 /* Reset the codec by writing to this write-only reset register */
280 ret
= regmap_write(max98090
->regmap
, M98090_REG_SOFTWARE_RESET
,
281 M98090_SWRESET_MASK
);
283 dev_err(max98090
->component
->dev
,
284 "Failed to reset codec: %d\n", ret
);
292 static const DECLARE_TLV_DB_RANGE(max98090_micboost_tlv
,
293 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
294 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
297 static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv
, 0, 100, 0);
299 static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv
,
302 static const DECLARE_TLV_DB_RANGE(max98090_line_tlv
,
303 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
304 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0)
307 static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv
, 0, 600, 0);
308 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv
, -1200, 100, 0);
310 static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv
, 0, 600, 0);
311 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv
, -1500, 100, 0);
313 static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv
, 0, 100, 0);
314 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv
, -3100, 100, 0);
315 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv
, -6600, 100, 0);
316 static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv
, 50, 200, 0);
318 static const DECLARE_TLV_DB_RANGE(max98090_mixout_tlv
,
319 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
320 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0)
323 static const DECLARE_TLV_DB_RANGE(max98090_hp_tlv
,
324 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
325 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
326 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
327 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
328 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
331 static const DECLARE_TLV_DB_RANGE(max98090_spk_tlv
,
332 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
333 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
334 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
335 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
336 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0)
339 static const DECLARE_TLV_DB_RANGE(max98090_rcv_lout_tlv
,
340 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
341 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
342 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
343 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
344 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
347 static int max98090_get_enab_tlv(struct snd_kcontrol
*kcontrol
,
348 struct snd_ctl_elem_value
*ucontrol
)
350 struct snd_soc_component
*component
= snd_soc_kcontrol_component(kcontrol
);
351 struct max98090_priv
*max98090
= snd_soc_component_get_drvdata(component
);
352 struct soc_mixer_control
*mc
=
353 (struct soc_mixer_control
*)kcontrol
->private_value
;
354 unsigned int mask
= (1 << fls(mc
->max
)) - 1;
355 unsigned int val
= snd_soc_component_read(component
, mc
->reg
);
356 unsigned int *select
;
359 case M98090_REG_MIC1_INPUT_LEVEL
:
360 select
= &(max98090
->pa1en
);
362 case M98090_REG_MIC2_INPUT_LEVEL
:
363 select
= &(max98090
->pa2en
);
365 case M98090_REG_ADC_SIDETONE
:
366 select
= &(max98090
->sidetone
);
372 val
= (val
>> mc
->shift
) & mask
;
375 /* If on, return the volume */
379 /* If off, return last stored value */
383 ucontrol
->value
.integer
.value
[0] = val
;
387 static int max98090_put_enab_tlv(struct snd_kcontrol
*kcontrol
,
388 struct snd_ctl_elem_value
*ucontrol
)
390 struct snd_soc_component
*component
= snd_soc_kcontrol_component(kcontrol
);
391 struct max98090_priv
*max98090
= snd_soc_component_get_drvdata(component
);
392 struct soc_mixer_control
*mc
=
393 (struct soc_mixer_control
*)kcontrol
->private_value
;
394 unsigned int mask
= (1 << fls(mc
->max
)) - 1;
395 int sel_unchecked
= ucontrol
->value
.integer
.value
[0];
397 unsigned int val
= snd_soc_component_read(component
, mc
->reg
);
398 unsigned int *select
;
402 case M98090_REG_MIC1_INPUT_LEVEL
:
403 select
= &(max98090
->pa1en
);
405 case M98090_REG_MIC2_INPUT_LEVEL
:
406 select
= &(max98090
->pa2en
);
408 case M98090_REG_ADC_SIDETONE
:
409 select
= &(max98090
->sidetone
);
415 val
= (val
>> mc
->shift
) & mask
;
417 if (sel_unchecked
< 0 || sel_unchecked
> mc
->max
)
421 change
= *select
!= sel
;
424 /* Setting a volume is only valid if it is already On */
428 /* Write what was already there */
432 snd_soc_component_update_bits(component
, mc
->reg
,
439 static const char *max98090_perf_pwr_text
[] =
440 { "High Performance", "Low Power" };
441 static const char *max98090_pwr_perf_text
[] =
442 { "Low Power", "High Performance" };
444 static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum
,
445 M98090_REG_BIAS_CONTROL
,
446 M98090_VCM_MODE_SHIFT
,
447 max98090_pwr_perf_text
);
449 static const char *max98090_osr128_text
[] = { "64*fs", "128*fs" };
451 static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum
,
452 M98090_REG_ADC_CONTROL
,
454 max98090_osr128_text
);
456 static const char *max98090_mode_text
[] = { "Voice", "Music" };
458 static SOC_ENUM_SINGLE_DECL(max98090_mode_enum
,
459 M98090_REG_FILTER_CONFIG
,
463 static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum
,
464 M98090_REG_FILTER_CONFIG
,
465 M98090_FLT_DMIC34MODE_SHIFT
,
468 static const char *max98090_drcatk_text
[] =
469 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
471 static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum
,
472 M98090_REG_DRC_TIMING
,
474 max98090_drcatk_text
);
476 static const char *max98090_drcrls_text
[] =
477 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
479 static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum
,
480 M98090_REG_DRC_TIMING
,
482 max98090_drcrls_text
);
484 static const char *max98090_alccmp_text
[] =
485 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
487 static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum
,
488 M98090_REG_DRC_COMPRESSOR
,
490 max98090_alccmp_text
);
492 static const char *max98090_drcexp_text
[] = { "1:1", "2:1", "3:1" };
494 static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum
,
495 M98090_REG_DRC_EXPANDER
,
497 max98090_drcexp_text
);
499 static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum
,
500 M98090_REG_DAC_CONTROL
,
501 M98090_PERFMODE_SHIFT
,
502 max98090_perf_pwr_text
);
504 static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum
,
505 M98090_REG_DAC_CONTROL
,
507 max98090_pwr_perf_text
);
509 static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum
,
510 M98090_REG_ADC_CONTROL
,
512 max98090_pwr_perf_text
);
514 static const struct snd_kcontrol_new max98090_snd_controls
[] = {
515 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum
),
517 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG
,
518 M98090_DMIC_COMP_SHIFT
, M98090_DMIC_COMP_NUM
- 1, 0),
520 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
521 M98090_REG_MIC1_INPUT_LEVEL
, M98090_MIC_PA1EN_SHIFT
,
522 M98090_MIC_PA1EN_NUM
- 1, 0, max98090_get_enab_tlv
,
523 max98090_put_enab_tlv
, max98090_micboost_tlv
),
525 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
526 M98090_REG_MIC2_INPUT_LEVEL
, M98090_MIC_PA2EN_SHIFT
,
527 M98090_MIC_PA2EN_NUM
- 1, 0, max98090_get_enab_tlv
,
528 max98090_put_enab_tlv
, max98090_micboost_tlv
),
530 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL
,
531 M98090_MIC_PGAM1_SHIFT
, M98090_MIC_PGAM1_NUM
- 1, 1,
534 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL
,
535 M98090_MIC_PGAM2_SHIFT
, M98090_MIC_PGAM2_NUM
- 1, 1,
538 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
539 M98090_REG_LINE_INPUT_LEVEL
, M98090_MIXG135_SHIFT
, 0,
540 M98090_MIXG135_NUM
- 1, 1, max98090_line_single_ended_tlv
),
542 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
543 M98090_REG_LINE_INPUT_LEVEL
, M98090_MIXG246_SHIFT
, 0,
544 M98090_MIXG246_NUM
- 1, 1, max98090_line_single_ended_tlv
),
546 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL
,
547 M98090_LINAPGA_SHIFT
, 0, M98090_LINAPGA_NUM
- 1, 1,
550 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL
,
551 M98090_LINBPGA_SHIFT
, 0, M98090_LINBPGA_NUM
- 1, 1,
554 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE
,
555 M98090_EXTBUFA_SHIFT
, M98090_EXTBUFA_NUM
- 1, 0),
556 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE
,
557 M98090_EXTBUFB_SHIFT
, M98090_EXTBUFB_NUM
- 1, 0),
559 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL
,
560 M98090_AVLG_SHIFT
, M98090_AVLG_NUM
- 1, 0,
562 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL
,
563 M98090_AVRG_SHIFT
, M98090_AVLG_NUM
- 1, 0,
566 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL
,
567 M98090_AVL_SHIFT
, M98090_AVL_NUM
- 1, 1,
569 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL
,
570 M98090_AVR_SHIFT
, M98090_AVR_NUM
- 1, 1,
573 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum
),
574 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL
,
575 M98090_ADCDITHER_SHIFT
, M98090_ADCDITHER_NUM
- 1, 0),
576 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum
),
578 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION
,
579 M98090_DMONO_SHIFT
, M98090_DMONO_NUM
- 1, 0),
580 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION
,
581 M98090_SDIEN_SHIFT
, M98090_SDIEN_NUM
- 1, 0),
582 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION
,
583 M98090_SDOEN_SHIFT
, M98090_SDOEN_NUM
- 1, 0),
584 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION
,
585 M98090_HIZOFF_SHIFT
, M98090_HIZOFF_NUM
- 1, 1),
586 SOC_ENUM("Filter Mode", max98090_mode_enum
),
587 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG
,
588 M98090_AHPF_SHIFT
, M98090_AHPF_NUM
- 1, 0),
589 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG
,
590 M98090_DHPF_SHIFT
, M98090_DHPF_NUM
- 1, 0),
591 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL
,
592 M98090_AVBQ_SHIFT
, M98090_AVBQ_NUM
- 1, 1, max98090_dv_tlv
),
593 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
594 M98090_REG_ADC_SIDETONE
, M98090_DVST_SHIFT
,
595 M98090_DVST_NUM
- 1, 1, max98090_get_enab_tlv
,
596 max98090_put_enab_tlv
, max98090_sdg_tlv
),
597 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL
,
598 M98090_DVG_SHIFT
, M98090_DVG_NUM
- 1, 0,
600 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL
,
601 M98090_DV_SHIFT
, M98090_DV_NUM
- 1, 1,
603 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE
, 105),
604 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE
,
605 M98090_EQ3BANDEN_SHIFT
, M98090_EQ3BANDEN_NUM
- 1, 0),
606 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE
,
607 M98090_EQ5BANDEN_SHIFT
, M98090_EQ5BANDEN_NUM
- 1, 0),
608 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE
,
609 M98090_EQ7BANDEN_SHIFT
, M98090_EQ7BANDEN_NUM
- 1, 0),
610 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ
,
611 M98090_EQCLPN_SHIFT
, M98090_EQCLPN_NUM
- 1,
613 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ
,
614 M98090_DVEQ_SHIFT
, M98090_DVEQ_NUM
- 1, 1,
617 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING
,
618 M98090_DRCEN_SHIFT
, M98090_DRCEN_NUM
- 1, 0),
619 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum
),
620 SOC_ENUM("ALC Release Time", max98090_drcrls_enum
),
621 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN
,
622 M98090_DRCG_SHIFT
, M98090_DRCG_NUM
- 1, 0,
623 max98090_alcmakeup_tlv
),
624 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum
),
625 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum
),
626 SOC_SINGLE_TLV("ALC Compression Threshold Volume",
627 M98090_REG_DRC_COMPRESSOR
, M98090_DRCTHC_SHIFT
,
628 M98090_DRCTHC_NUM
- 1, 1, max98090_alccomp_tlv
),
629 SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
630 M98090_REG_DRC_EXPANDER
, M98090_DRCTHE_SHIFT
,
631 M98090_DRCTHE_NUM
- 1, 1, max98090_drcexp_tlv
),
633 SOC_ENUM("DAC HP Playback Performance Mode",
634 max98090_dac_perfmode_enum
),
635 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum
),
637 SOC_SINGLE_TLV("Headphone Left Mixer Volume",
638 M98090_REG_HP_CONTROL
, M98090_MIXHPLG_SHIFT
,
639 M98090_MIXHPLG_NUM
- 1, 1, max98090_mixout_tlv
),
640 SOC_SINGLE_TLV("Headphone Right Mixer Volume",
641 M98090_REG_HP_CONTROL
, M98090_MIXHPRG_SHIFT
,
642 M98090_MIXHPRG_NUM
- 1, 1, max98090_mixout_tlv
),
644 SOC_SINGLE_TLV("Speaker Left Mixer Volume",
645 M98090_REG_SPK_CONTROL
, M98090_MIXSPLG_SHIFT
,
646 M98090_MIXSPLG_NUM
- 1, 1, max98090_mixout_tlv
),
647 SOC_SINGLE_TLV("Speaker Right Mixer Volume",
648 M98090_REG_SPK_CONTROL
, M98090_MIXSPRG_SHIFT
,
649 M98090_MIXSPRG_NUM
- 1, 1, max98090_mixout_tlv
),
651 SOC_SINGLE_TLV("Receiver Left Mixer Volume",
652 M98090_REG_RCV_LOUTL_CONTROL
, M98090_MIXRCVLG_SHIFT
,
653 M98090_MIXRCVLG_NUM
- 1, 1, max98090_mixout_tlv
),
654 SOC_SINGLE_TLV("Receiver Right Mixer Volume",
655 M98090_REG_LOUTR_CONTROL
, M98090_MIXRCVRG_SHIFT
,
656 M98090_MIXRCVRG_NUM
- 1, 1, max98090_mixout_tlv
),
658 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME
,
659 M98090_REG_RIGHT_HP_VOLUME
, M98090_HPVOLL_SHIFT
,
660 M98090_HPVOLL_NUM
- 1, 0, max98090_hp_tlv
),
662 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
663 M98090_REG_LEFT_SPK_VOLUME
, M98090_REG_RIGHT_SPK_VOLUME
,
664 M98090_SPVOLL_SHIFT
, 24, M98090_SPVOLL_NUM
- 1 + 24,
665 0, max98090_spk_tlv
),
667 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME
,
668 M98090_REG_LOUTR_VOLUME
, M98090_RCVLVOL_SHIFT
,
669 M98090_RCVLVOL_NUM
- 1, 0, max98090_rcv_lout_tlv
),
671 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME
,
672 M98090_HPLM_SHIFT
, 1, 1),
673 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME
,
674 M98090_HPRM_SHIFT
, 1, 1),
676 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME
,
677 M98090_SPLM_SHIFT
, 1, 1),
678 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME
,
679 M98090_SPRM_SHIFT
, 1, 1),
681 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME
,
682 M98090_RCVLM_SHIFT
, 1, 1),
683 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME
,
684 M98090_RCVRM_SHIFT
, 1, 1),
686 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL
,
687 M98090_ZDENN_SHIFT
, M98090_ZDENN_NUM
- 1, 1),
688 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL
,
689 M98090_VS2ENN_SHIFT
, M98090_VS2ENN_NUM
- 1, 1),
690 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL
,
691 M98090_VSENN_SHIFT
, M98090_VSENN_NUM
- 1, 1),
693 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE
, 15),
694 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE
,
695 M98090_ADCBQEN_SHIFT
, M98090_ADCBQEN_NUM
- 1, 0),
698 static const struct snd_kcontrol_new max98091_snd_controls
[] = {
700 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE
,
701 M98090_DMIC34_ZEROPAD_SHIFT
,
702 M98090_DMIC34_ZEROPAD_NUM
- 1, 0),
704 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum
),
705 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG
,
706 M98090_FLT_DMIC34HPF_SHIFT
,
707 M98090_FLT_DMIC34HPF_NUM
- 1, 0),
709 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME
,
710 M98090_DMIC_AV3G_SHIFT
, M98090_DMIC_AV3G_NUM
- 1, 0,
712 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME
,
713 M98090_DMIC_AV4G_SHIFT
, M98090_DMIC_AV4G_NUM
- 1, 0,
716 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME
,
717 M98090_DMIC_AV3_SHIFT
, M98090_DMIC_AV3_NUM
- 1, 1,
719 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME
,
720 M98090_DMIC_AV4_SHIFT
, M98090_DMIC_AV4_NUM
- 1, 1,
723 SND_SOC_BYTES("DMIC34 Biquad Coefficients",
724 M98090_REG_DMIC34_BIQUAD_BASE
, 15),
725 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE
,
726 M98090_DMIC34BQEN_SHIFT
, M98090_DMIC34BQEN_NUM
- 1, 0),
728 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
729 M98090_REG_DMIC34_BQ_PREATTEN
, M98090_AV34BQ_SHIFT
,
730 M98090_AV34BQ_NUM
- 1, 1, max98090_dv_tlv
),
733 static int max98090_micinput_event(struct snd_soc_dapm_widget
*w
,
734 struct snd_kcontrol
*kcontrol
, int event
)
736 struct snd_soc_component
*component
= snd_soc_dapm_to_component(w
->dapm
);
737 struct max98090_priv
*max98090
= snd_soc_component_get_drvdata(component
);
739 unsigned int val
= snd_soc_component_read(component
, w
->reg
);
741 if (w
->reg
== M98090_REG_MIC1_INPUT_LEVEL
)
742 val
= (val
& M98090_MIC_PA1EN_MASK
) >> M98090_MIC_PA1EN_SHIFT
;
744 val
= (val
& M98090_MIC_PA2EN_MASK
) >> M98090_MIC_PA2EN_SHIFT
;
747 if (w
->reg
== M98090_REG_MIC1_INPUT_LEVEL
) {
748 max98090
->pa1en
= val
- 1; /* Update for volatile */
750 max98090
->pa2en
= val
- 1; /* Update for volatile */
755 case SND_SOC_DAPM_POST_PMU
:
756 /* If turning on, set to most recently selected volume */
757 if (w
->reg
== M98090_REG_MIC1_INPUT_LEVEL
)
758 val
= max98090
->pa1en
+ 1;
760 val
= max98090
->pa2en
+ 1;
762 case SND_SOC_DAPM_POST_PMD
:
763 /* If turning off, turn off */
770 if (w
->reg
== M98090_REG_MIC1_INPUT_LEVEL
)
771 snd_soc_component_update_bits(component
, w
->reg
, M98090_MIC_PA1EN_MASK
,
772 val
<< M98090_MIC_PA1EN_SHIFT
);
774 snd_soc_component_update_bits(component
, w
->reg
, M98090_MIC_PA2EN_MASK
,
775 val
<< M98090_MIC_PA2EN_SHIFT
);
780 static int max98090_shdn_event(struct snd_soc_dapm_widget
*w
,
781 struct snd_kcontrol
*kcontrol
, int event
)
783 struct snd_soc_component
*component
= snd_soc_dapm_to_component(w
->dapm
);
784 struct max98090_priv
*max98090
= snd_soc_component_get_drvdata(component
);
786 if (event
& SND_SOC_DAPM_POST_PMU
)
787 max98090
->shdn_pending
= true;
793 static const char *mic1_mux_text
[] = { "IN12", "IN56" };
795 static SOC_ENUM_SINGLE_DECL(mic1_mux_enum
,
796 M98090_REG_INPUT_MODE
,
797 M98090_EXTMIC1_SHIFT
,
800 static const struct snd_kcontrol_new max98090_mic1_mux
=
801 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum
);
803 static const char *mic2_mux_text
[] = { "IN34", "IN56" };
805 static SOC_ENUM_SINGLE_DECL(mic2_mux_enum
,
806 M98090_REG_INPUT_MODE
,
807 M98090_EXTMIC2_SHIFT
,
810 static const struct snd_kcontrol_new max98090_mic2_mux
=
811 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum
);
813 static const char *dmic_mux_text
[] = { "ADC", "DMIC" };
815 static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum
, dmic_mux_text
);
817 static const struct snd_kcontrol_new max98090_dmic_mux
=
818 SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum
);
820 /* LINEA mixer switch */
821 static const struct snd_kcontrol_new max98090_linea_mixer_controls
[] = {
822 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG
,
823 M98090_IN1SEEN_SHIFT
, 1, 0),
824 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG
,
825 M98090_IN3SEEN_SHIFT
, 1, 0),
826 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG
,
827 M98090_IN5SEEN_SHIFT
, 1, 0),
828 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG
,
829 M98090_IN34DIFF_SHIFT
, 1, 0),
832 /* LINEB mixer switch */
833 static const struct snd_kcontrol_new max98090_lineb_mixer_controls
[] = {
834 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG
,
835 M98090_IN2SEEN_SHIFT
, 1, 0),
836 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG
,
837 M98090_IN4SEEN_SHIFT
, 1, 0),
838 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG
,
839 M98090_IN6SEEN_SHIFT
, 1, 0),
840 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG
,
841 M98090_IN56DIFF_SHIFT
, 1, 0),
844 /* Left ADC mixer switch */
845 static const struct snd_kcontrol_new max98090_left_adc_mixer_controls
[] = {
846 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER
,
847 M98090_MIXADL_IN12DIFF_SHIFT
, 1, 0),
848 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER
,
849 M98090_MIXADL_IN34DIFF_SHIFT
, 1, 0),
850 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER
,
851 M98090_MIXADL_IN65DIFF_SHIFT
, 1, 0),
852 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER
,
853 M98090_MIXADL_LINEA_SHIFT
, 1, 0),
854 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER
,
855 M98090_MIXADL_LINEB_SHIFT
, 1, 0),
856 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER
,
857 M98090_MIXADL_MIC1_SHIFT
, 1, 0),
858 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER
,
859 M98090_MIXADL_MIC2_SHIFT
, 1, 0),
862 /* Right ADC mixer switch */
863 static const struct snd_kcontrol_new max98090_right_adc_mixer_controls
[] = {
864 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER
,
865 M98090_MIXADR_IN12DIFF_SHIFT
, 1, 0),
866 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER
,
867 M98090_MIXADR_IN34DIFF_SHIFT
, 1, 0),
868 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER
,
869 M98090_MIXADR_IN65DIFF_SHIFT
, 1, 0),
870 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER
,
871 M98090_MIXADR_LINEA_SHIFT
, 1, 0),
872 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER
,
873 M98090_MIXADR_LINEB_SHIFT
, 1, 0),
874 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER
,
875 M98090_MIXADR_MIC1_SHIFT
, 1, 0),
876 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER
,
877 M98090_MIXADR_MIC2_SHIFT
, 1, 0),
880 static const char *lten_mux_text
[] = { "Normal", "Loopthrough" };
882 static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum
,
883 M98090_REG_IO_CONFIGURATION
,
887 static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum
,
888 M98090_REG_IO_CONFIGURATION
,
892 static const struct snd_kcontrol_new max98090_ltenl_mux
=
893 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum
);
895 static const struct snd_kcontrol_new max98090_ltenr_mux
=
896 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum
);
898 static const char *lben_mux_text
[] = { "Normal", "Loopback" };
900 static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum
,
901 M98090_REG_IO_CONFIGURATION
,
905 static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum
,
906 M98090_REG_IO_CONFIGURATION
,
910 static const struct snd_kcontrol_new max98090_lbenl_mux
=
911 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum
);
913 static const struct snd_kcontrol_new max98090_lbenr_mux
=
914 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum
);
916 static const char *stenl_mux_text
[] = { "Normal", "Sidetone Left" };
918 static const char *stenr_mux_text
[] = { "Normal", "Sidetone Right" };
920 static SOC_ENUM_SINGLE_DECL(stenl_mux_enum
,
921 M98090_REG_ADC_SIDETONE
,
925 static SOC_ENUM_SINGLE_DECL(stenr_mux_enum
,
926 M98090_REG_ADC_SIDETONE
,
930 static const struct snd_kcontrol_new max98090_stenl_mux
=
931 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum
);
933 static const struct snd_kcontrol_new max98090_stenr_mux
=
934 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum
);
936 /* Left speaker mixer switch */
938 snd_kcontrol_new max98090_left_speaker_mixer_controls
[] = {
939 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER
,
940 M98090_MIXSPL_DACL_SHIFT
, 1, 0),
941 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER
,
942 M98090_MIXSPL_DACR_SHIFT
, 1, 0),
943 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER
,
944 M98090_MIXSPL_LINEA_SHIFT
, 1, 0),
945 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER
,
946 M98090_MIXSPL_LINEB_SHIFT
, 1, 0),
947 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER
,
948 M98090_MIXSPL_MIC1_SHIFT
, 1, 0),
949 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER
,
950 M98090_MIXSPL_MIC2_SHIFT
, 1, 0),
953 /* Right speaker mixer switch */
955 snd_kcontrol_new max98090_right_speaker_mixer_controls
[] = {
956 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER
,
957 M98090_MIXSPR_DACL_SHIFT
, 1, 0),
958 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER
,
959 M98090_MIXSPR_DACR_SHIFT
, 1, 0),
960 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER
,
961 M98090_MIXSPR_LINEA_SHIFT
, 1, 0),
962 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER
,
963 M98090_MIXSPR_LINEB_SHIFT
, 1, 0),
964 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER
,
965 M98090_MIXSPR_MIC1_SHIFT
, 1, 0),
966 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER
,
967 M98090_MIXSPR_MIC2_SHIFT
, 1, 0),
970 /* Left headphone mixer switch */
971 static const struct snd_kcontrol_new max98090_left_hp_mixer_controls
[] = {
972 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER
,
973 M98090_MIXHPL_DACL_SHIFT
, 1, 0),
974 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER
,
975 M98090_MIXHPL_DACR_SHIFT
, 1, 0),
976 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER
,
977 M98090_MIXHPL_LINEA_SHIFT
, 1, 0),
978 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER
,
979 M98090_MIXHPL_LINEB_SHIFT
, 1, 0),
980 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER
,
981 M98090_MIXHPL_MIC1_SHIFT
, 1, 0),
982 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER
,
983 M98090_MIXHPL_MIC2_SHIFT
, 1, 0),
986 /* Right headphone mixer switch */
987 static const struct snd_kcontrol_new max98090_right_hp_mixer_controls
[] = {
988 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER
,
989 M98090_MIXHPR_DACL_SHIFT
, 1, 0),
990 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER
,
991 M98090_MIXHPR_DACR_SHIFT
, 1, 0),
992 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER
,
993 M98090_MIXHPR_LINEA_SHIFT
, 1, 0),
994 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER
,
995 M98090_MIXHPR_LINEB_SHIFT
, 1, 0),
996 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER
,
997 M98090_MIXHPR_MIC1_SHIFT
, 1, 0),
998 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER
,
999 M98090_MIXHPR_MIC2_SHIFT
, 1, 0),
1002 /* Left receiver mixer switch */
1003 static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls
[] = {
1004 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER
,
1005 M98090_MIXRCVL_DACL_SHIFT
, 1, 0),
1006 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER
,
1007 M98090_MIXRCVL_DACR_SHIFT
, 1, 0),
1008 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER
,
1009 M98090_MIXRCVL_LINEA_SHIFT
, 1, 0),
1010 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER
,
1011 M98090_MIXRCVL_LINEB_SHIFT
, 1, 0),
1012 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER
,
1013 M98090_MIXRCVL_MIC1_SHIFT
, 1, 0),
1014 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER
,
1015 M98090_MIXRCVL_MIC2_SHIFT
, 1, 0),
1018 /* Right receiver mixer switch */
1019 static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls
[] = {
1020 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER
,
1021 M98090_MIXRCVR_DACL_SHIFT
, 1, 0),
1022 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER
,
1023 M98090_MIXRCVR_DACR_SHIFT
, 1, 0),
1024 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER
,
1025 M98090_MIXRCVR_LINEA_SHIFT
, 1, 0),
1026 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER
,
1027 M98090_MIXRCVR_LINEB_SHIFT
, 1, 0),
1028 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER
,
1029 M98090_MIXRCVR_MIC1_SHIFT
, 1, 0),
1030 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER
,
1031 M98090_MIXRCVR_MIC2_SHIFT
, 1, 0),
1034 static const char *linmod_mux_text
[] = { "Left Only", "Left and Right" };
1036 static SOC_ENUM_SINGLE_DECL(linmod_mux_enum
,
1037 M98090_REG_LOUTR_MIXER
,
1038 M98090_LINMOD_SHIFT
,
1041 static const struct snd_kcontrol_new max98090_linmod_mux
=
1042 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum
);
1044 static const char *mixhpsel_mux_text
[] = { "DAC Only", "HP Mixer" };
1047 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
1049 static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum
,
1050 M98090_REG_HP_CONTROL
,
1051 M98090_MIXHPLSEL_SHIFT
,
1054 static const struct snd_kcontrol_new max98090_mixhplsel_mux
=
1055 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum
);
1057 static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum
,
1058 M98090_REG_HP_CONTROL
,
1059 M98090_MIXHPRSEL_SHIFT
,
1062 static const struct snd_kcontrol_new max98090_mixhprsel_mux
=
1063 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum
);
1065 static const struct snd_soc_dapm_widget max98090_dapm_widgets
[] = {
1066 SND_SOC_DAPM_INPUT("MIC1"),
1067 SND_SOC_DAPM_INPUT("MIC2"),
1068 SND_SOC_DAPM_INPUT("DMICL"),
1069 SND_SOC_DAPM_INPUT("DMICR"),
1070 SND_SOC_DAPM_INPUT("IN1"),
1071 SND_SOC_DAPM_INPUT("IN2"),
1072 SND_SOC_DAPM_INPUT("IN3"),
1073 SND_SOC_DAPM_INPUT("IN4"),
1074 SND_SOC_DAPM_INPUT("IN5"),
1075 SND_SOC_DAPM_INPUT("IN6"),
1076 SND_SOC_DAPM_INPUT("IN12"),
1077 SND_SOC_DAPM_INPUT("IN34"),
1078 SND_SOC_DAPM_INPUT("IN56"),
1080 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE
,
1081 M98090_MBEN_SHIFT
, 0, NULL
, 0),
1082 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN
,
1083 M98090_SHDNN_SHIFT
, 0, NULL
, 0),
1084 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION
,
1085 M98090_SDIEN_SHIFT
, 0, NULL
, 0),
1086 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION
,
1087 M98090_SDOEN_SHIFT
, 0, NULL
, 0),
1088 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE
,
1089 M98090_DIGMICL_SHIFT
, 0, max98090_shdn_event
,
1090 SND_SOC_DAPM_POST_PMU
),
1091 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE
,
1092 M98090_DIGMICR_SHIFT
, 0, max98090_shdn_event
,
1093 SND_SOC_DAPM_POST_PMU
),
1094 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG
,
1095 M98090_AHPF_SHIFT
, 0, NULL
, 0),
1098 * Note: Sysclk and misc power supplies are taken care of by SHDN
1101 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM
,
1102 0, 0, &max98090_mic1_mux
),
1104 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM
,
1105 0, 0, &max98090_mic2_mux
),
1107 SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM
, 0, 0, &max98090_dmic_mux
),
1109 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL
,
1110 M98090_MIC_PA1EN_SHIFT
, 0, NULL
, 0, max98090_micinput_event
,
1111 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1113 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL
,
1114 M98090_MIC_PA2EN_SHIFT
, 0, NULL
, 0, max98090_micinput_event
,
1115 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1117 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM
, 0, 0,
1118 &max98090_linea_mixer_controls
[0],
1119 ARRAY_SIZE(max98090_linea_mixer_controls
)),
1121 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM
, 0, 0,
1122 &max98090_lineb_mixer_controls
[0],
1123 ARRAY_SIZE(max98090_lineb_mixer_controls
)),
1125 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE
,
1126 M98090_LINEAEN_SHIFT
, 0, NULL
, 0),
1127 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE
,
1128 M98090_LINEBEN_SHIFT
, 0, NULL
, 0),
1130 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM
, 0, 0,
1131 &max98090_left_adc_mixer_controls
[0],
1132 ARRAY_SIZE(max98090_left_adc_mixer_controls
)),
1134 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM
, 0, 0,
1135 &max98090_right_adc_mixer_controls
[0],
1136 ARRAY_SIZE(max98090_right_adc_mixer_controls
)),
1138 SND_SOC_DAPM_ADC_E("ADCL", NULL
, M98090_REG_INPUT_ENABLE
,
1139 M98090_ADLEN_SHIFT
, 0, max98090_shdn_event
,
1140 SND_SOC_DAPM_POST_PMU
),
1141 SND_SOC_DAPM_ADC_E("ADCR", NULL
, M98090_REG_INPUT_ENABLE
,
1142 M98090_ADREN_SHIFT
, 0, max98090_shdn_event
,
1143 SND_SOC_DAPM_POST_PMU
),
1145 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1146 SND_SOC_NOPM
, 0, 0),
1147 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1148 SND_SOC_NOPM
, 0, 0),
1150 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM
,
1151 0, 0, &max98090_lbenl_mux
),
1153 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM
,
1154 0, 0, &max98090_lbenr_mux
),
1156 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM
,
1157 0, 0, &max98090_ltenl_mux
),
1159 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM
,
1160 0, 0, &max98090_ltenr_mux
),
1162 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM
,
1163 0, 0, &max98090_stenl_mux
),
1165 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM
,
1166 0, 0, &max98090_stenr_mux
),
1168 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM
, 0, 0),
1169 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM
, 0, 0),
1171 SND_SOC_DAPM_DAC("DACL", NULL
, M98090_REG_OUTPUT_ENABLE
,
1172 M98090_DALEN_SHIFT
, 0),
1173 SND_SOC_DAPM_DAC("DACR", NULL
, M98090_REG_OUTPUT_ENABLE
,
1174 M98090_DAREN_SHIFT
, 0),
1176 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM
, 0, 0,
1177 &max98090_left_hp_mixer_controls
[0],
1178 ARRAY_SIZE(max98090_left_hp_mixer_controls
)),
1180 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM
, 0, 0,
1181 &max98090_right_hp_mixer_controls
[0],
1182 ARRAY_SIZE(max98090_right_hp_mixer_controls
)),
1184 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM
, 0, 0,
1185 &max98090_left_speaker_mixer_controls
[0],
1186 ARRAY_SIZE(max98090_left_speaker_mixer_controls
)),
1188 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM
, 0, 0,
1189 &max98090_right_speaker_mixer_controls
[0],
1190 ARRAY_SIZE(max98090_right_speaker_mixer_controls
)),
1192 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM
, 0, 0,
1193 &max98090_left_rcv_mixer_controls
[0],
1194 ARRAY_SIZE(max98090_left_rcv_mixer_controls
)),
1196 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM
, 0, 0,
1197 &max98090_right_rcv_mixer_controls
[0],
1198 ARRAY_SIZE(max98090_right_rcv_mixer_controls
)),
1200 SND_SOC_DAPM_MUX("LINMOD Mux", SND_SOC_NOPM
, 0, 0,
1201 &max98090_linmod_mux
),
1203 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", SND_SOC_NOPM
, 0, 0,
1204 &max98090_mixhplsel_mux
),
1206 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", SND_SOC_NOPM
, 0, 0,
1207 &max98090_mixhprsel_mux
),
1209 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE
,
1210 M98090_HPLEN_SHIFT
, 0, NULL
, 0),
1211 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE
,
1212 M98090_HPREN_SHIFT
, 0, NULL
, 0),
1214 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE
,
1215 M98090_SPLEN_SHIFT
, 0, NULL
, 0),
1216 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE
,
1217 M98090_SPREN_SHIFT
, 0, NULL
, 0),
1219 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE
,
1220 M98090_RCVLEN_SHIFT
, 0, NULL
, 0),
1221 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE
,
1222 M98090_RCVREN_SHIFT
, 0, NULL
, 0),
1224 SND_SOC_DAPM_OUTPUT("HPL"),
1225 SND_SOC_DAPM_OUTPUT("HPR"),
1226 SND_SOC_DAPM_OUTPUT("SPKL"),
1227 SND_SOC_DAPM_OUTPUT("SPKR"),
1228 SND_SOC_DAPM_OUTPUT("RCVL"),
1229 SND_SOC_DAPM_OUTPUT("RCVR"),
1232 static const struct snd_soc_dapm_widget max98091_dapm_widgets
[] = {
1233 SND_SOC_DAPM_INPUT("DMIC3"),
1234 SND_SOC_DAPM_INPUT("DMIC4"),
1236 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE
,
1237 M98090_DIGMIC3_SHIFT
, 0, NULL
, 0),
1238 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE
,
1239 M98090_DIGMIC4_SHIFT
, 0, NULL
, 0),
1242 static const struct snd_soc_dapm_route max98090_dapm_routes
[] = {
1243 {"MIC1 Input", NULL
, "MIC1"},
1244 {"MIC2 Input", NULL
, "MIC2"},
1246 {"DMICL", NULL
, "DMICL_ENA"},
1247 {"DMICL", NULL
, "DMICR_ENA"},
1248 {"DMICR", NULL
, "DMICL_ENA"},
1249 {"DMICR", NULL
, "DMICR_ENA"},
1250 {"DMICL", NULL
, "AHPF"},
1251 {"DMICR", NULL
, "AHPF"},
1253 /* MIC1 input mux */
1254 {"MIC1 Mux", "IN12", "IN12"},
1255 {"MIC1 Mux", "IN56", "IN56"},
1257 /* MIC2 input mux */
1258 {"MIC2 Mux", "IN34", "IN34"},
1259 {"MIC2 Mux", "IN56", "IN56"},
1261 {"MIC1 Input", NULL
, "MIC1 Mux"},
1262 {"MIC2 Input", NULL
, "MIC2 Mux"},
1264 /* Left ADC input mixer */
1265 {"Left ADC Mixer", "IN12 Switch", "IN12"},
1266 {"Left ADC Mixer", "IN34 Switch", "IN34"},
1267 {"Left ADC Mixer", "IN56 Switch", "IN56"},
1268 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1269 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1270 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1271 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1273 /* Right ADC input mixer */
1274 {"Right ADC Mixer", "IN12 Switch", "IN12"},
1275 {"Right ADC Mixer", "IN34 Switch", "IN34"},
1276 {"Right ADC Mixer", "IN56 Switch", "IN56"},
1277 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1278 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1279 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1280 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1282 /* Line A input mixer */
1283 {"LINEA Mixer", "IN1 Switch", "IN1"},
1284 {"LINEA Mixer", "IN3 Switch", "IN3"},
1285 {"LINEA Mixer", "IN5 Switch", "IN5"},
1286 {"LINEA Mixer", "IN34 Switch", "IN34"},
1288 /* Line B input mixer */
1289 {"LINEB Mixer", "IN2 Switch", "IN2"},
1290 {"LINEB Mixer", "IN4 Switch", "IN4"},
1291 {"LINEB Mixer", "IN6 Switch", "IN6"},
1292 {"LINEB Mixer", "IN56 Switch", "IN56"},
1294 {"LINEA Input", NULL
, "LINEA Mixer"},
1295 {"LINEB Input", NULL
, "LINEB Mixer"},
1298 {"ADCL", NULL
, "Left ADC Mixer"},
1299 {"ADCR", NULL
, "Right ADC Mixer"},
1300 {"ADCL", NULL
, "SHDN"},
1301 {"ADCR", NULL
, "SHDN"},
1303 {"DMIC Mux", "ADC", "ADCL"},
1304 {"DMIC Mux", "ADC", "ADCR"},
1305 {"DMIC Mux", "DMIC", "DMICL"},
1306 {"DMIC Mux", "DMIC", "DMICR"},
1308 {"LBENL Mux", "Normal", "DMIC Mux"},
1309 {"LBENL Mux", "Loopback", "LTENL Mux"},
1310 {"LBENR Mux", "Normal", "DMIC Mux"},
1311 {"LBENR Mux", "Loopback", "LTENR Mux"},
1313 {"AIFOUTL", NULL
, "LBENL Mux"},
1314 {"AIFOUTR", NULL
, "LBENR Mux"},
1315 {"AIFOUTL", NULL
, "SHDN"},
1316 {"AIFOUTR", NULL
, "SHDN"},
1317 {"AIFOUTL", NULL
, "SDOEN"},
1318 {"AIFOUTR", NULL
, "SDOEN"},
1320 {"LTENL Mux", "Normal", "AIFINL"},
1321 {"LTENL Mux", "Loopthrough", "LBENL Mux"},
1322 {"LTENR Mux", "Normal", "AIFINR"},
1323 {"LTENR Mux", "Loopthrough", "LBENR Mux"},
1325 {"DACL", NULL
, "LTENL Mux"},
1326 {"DACR", NULL
, "LTENR Mux"},
1328 {"STENL Mux", "Sidetone Left", "ADCL"},
1329 {"STENL Mux", "Sidetone Left", "DMICL"},
1330 {"STENR Mux", "Sidetone Right", "ADCR"},
1331 {"STENR Mux", "Sidetone Right", "DMICR"},
1332 {"DACL", NULL
, "STENL Mux"},
1333 {"DACR", NULL
, "STENR Mux"},
1335 {"AIFINL", NULL
, "SHDN"},
1336 {"AIFINR", NULL
, "SHDN"},
1337 {"AIFINL", NULL
, "SDIEN"},
1338 {"AIFINR", NULL
, "SDIEN"},
1339 {"DACL", NULL
, "SHDN"},
1340 {"DACR", NULL
, "SHDN"},
1342 /* Left headphone output mixer */
1343 {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1344 {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1345 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1346 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1347 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1348 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1350 /* Right headphone output mixer */
1351 {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1352 {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1353 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1354 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1355 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1356 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1358 /* Left speaker output mixer */
1359 {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1360 {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1361 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1362 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1363 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1364 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1366 /* Right speaker output mixer */
1367 {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1368 {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1369 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1370 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1371 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1372 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1374 /* Left Receiver output mixer */
1375 {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1376 {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1377 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1378 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1379 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1380 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1382 /* Right Receiver output mixer */
1383 {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1384 {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1385 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1386 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1387 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1388 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1390 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
1393 * Disable this for lowest power if bypassing
1394 * the DAC with an analog signal
1396 {"HP Left Out", NULL
, "DACL"},
1397 {"HP Left Out", NULL
, "MIXHPLSEL Mux"},
1399 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
1402 * Disable this for lowest power if bypassing
1403 * the DAC with an analog signal
1405 {"HP Right Out", NULL
, "DACR"},
1406 {"HP Right Out", NULL
, "MIXHPRSEL Mux"},
1408 {"SPK Left Out", NULL
, "Left Speaker Mixer"},
1409 {"SPK Right Out", NULL
, "Right Speaker Mixer"},
1410 {"RCV Left Out", NULL
, "Left Receiver Mixer"},
1412 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
1413 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"},
1414 {"RCV Right Out", NULL
, "LINMOD Mux"},
1416 {"HPL", NULL
, "HP Left Out"},
1417 {"HPR", NULL
, "HP Right Out"},
1418 {"SPKL", NULL
, "SPK Left Out"},
1419 {"SPKR", NULL
, "SPK Right Out"},
1420 {"RCVL", NULL
, "RCV Left Out"},
1421 {"RCVR", NULL
, "RCV Right Out"},
1424 static const struct snd_soc_dapm_route max98091_dapm_routes
[] = {
1426 {"DMIC3", NULL
, "DMIC3_ENA"},
1427 {"DMIC4", NULL
, "DMIC4_ENA"},
1428 {"DMIC3", NULL
, "AHPF"},
1429 {"DMIC4", NULL
, "AHPF"},
1432 static int max98090_add_widgets(struct snd_soc_component
*component
)
1434 struct max98090_priv
*max98090
= snd_soc_component_get_drvdata(component
);
1435 struct snd_soc_dapm_context
*dapm
= snd_soc_component_get_dapm(component
);
1437 snd_soc_add_component_controls(component
, max98090_snd_controls
,
1438 ARRAY_SIZE(max98090_snd_controls
));
1440 if (max98090
->devtype
== MAX98091
) {
1441 snd_soc_add_component_controls(component
, max98091_snd_controls
,
1442 ARRAY_SIZE(max98091_snd_controls
));
1445 snd_soc_dapm_new_controls(dapm
, max98090_dapm_widgets
,
1446 ARRAY_SIZE(max98090_dapm_widgets
));
1448 snd_soc_dapm_add_routes(dapm
, max98090_dapm_routes
,
1449 ARRAY_SIZE(max98090_dapm_routes
));
1451 if (max98090
->devtype
== MAX98091
) {
1452 snd_soc_dapm_new_controls(dapm
, max98091_dapm_widgets
,
1453 ARRAY_SIZE(max98091_dapm_widgets
));
1455 snd_soc_dapm_add_routes(dapm
, max98091_dapm_routes
,
1456 ARRAY_SIZE(max98091_dapm_routes
));
1462 static const int pclk_rates
[] = {
1463 12000000, 12000000, 13000000, 13000000,
1464 16000000, 16000000, 19200000, 19200000
1467 static const int lrclk_rates
[] = {
1468 8000, 16000, 8000, 16000,
1469 8000, 16000, 8000, 16000
1472 static const int user_pclk_rates
[] = {
1473 13000000, 13000000, 19200000, 19200000,
1476 static const int user_lrclk_rates
[] = {
1477 44100, 48000, 44100, 48000,
1480 static const unsigned long long ni_value
[] = {
1484 static const unsigned long long mi_value
[] = {
1485 8125, 1625, 1500, 25
1488 static void max98090_configure_bclk(struct snd_soc_component
*component
)
1490 struct max98090_priv
*max98090
= snd_soc_component_get_drvdata(component
);
1491 unsigned long long ni
;
1494 if (!max98090
->sysclk
) {
1495 dev_err(component
->dev
, "No SYSCLK configured\n");
1499 if (!max98090
->bclk
|| !max98090
->lrclk
) {
1500 dev_err(component
->dev
, "No audio clocks configured\n");
1504 /* Skip configuration when operating as slave */
1505 if (!(snd_soc_component_read(component
, M98090_REG_MASTER_MODE
) &
1510 /* Check for supported PCLK to LRCLK ratios */
1511 for (i
= 0; i
< ARRAY_SIZE(pclk_rates
); i
++) {
1512 if ((pclk_rates
[i
] == max98090
->sysclk
) &&
1513 (lrclk_rates
[i
] == max98090
->lrclk
)) {
1514 dev_dbg(component
->dev
,
1515 "Found supported PCLK to LRCLK rates 0x%x\n",
1518 snd_soc_component_update_bits(component
, M98090_REG_CLOCK_MODE
,
1520 (i
+ 0x8) << M98090_FREQ_SHIFT
);
1521 snd_soc_component_update_bits(component
, M98090_REG_CLOCK_MODE
,
1522 M98090_USE_M1_MASK
, 0);
1527 /* Check for user calculated MI and NI ratios */
1528 for (i
= 0; i
< ARRAY_SIZE(user_pclk_rates
); i
++) {
1529 if ((user_pclk_rates
[i
] == max98090
->sysclk
) &&
1530 (user_lrclk_rates
[i
] == max98090
->lrclk
)) {
1531 dev_dbg(component
->dev
,
1532 "Found user supported PCLK to LRCLK rates\n");
1533 dev_dbg(component
->dev
, "i %d ni %lld mi %lld\n",
1534 i
, ni_value
[i
], mi_value
[i
]);
1536 snd_soc_component_update_bits(component
, M98090_REG_CLOCK_MODE
,
1537 M98090_FREQ_MASK
, 0);
1538 snd_soc_component_update_bits(component
, M98090_REG_CLOCK_MODE
,
1540 1 << M98090_USE_M1_SHIFT
);
1542 snd_soc_component_write(component
, M98090_REG_CLOCK_RATIO_NI_MSB
,
1543 (ni_value
[i
] >> 8) & 0x7F);
1544 snd_soc_component_write(component
, M98090_REG_CLOCK_RATIO_NI_LSB
,
1545 ni_value
[i
] & 0xFF);
1546 snd_soc_component_write(component
, M98090_REG_CLOCK_RATIO_MI_MSB
,
1547 (mi_value
[i
] >> 8) & 0x7F);
1548 snd_soc_component_write(component
, M98090_REG_CLOCK_RATIO_MI_LSB
,
1549 mi_value
[i
] & 0xFF);
1556 * Calculate based on MI = 65536 (not as good as either method above)
1558 snd_soc_component_update_bits(component
, M98090_REG_CLOCK_MODE
,
1559 M98090_FREQ_MASK
, 0);
1560 snd_soc_component_update_bits(component
, M98090_REG_CLOCK_MODE
,
1561 M98090_USE_M1_MASK
, 0);
1564 * Configure NI when operating as master
1565 * Note: There is a small, but significant audio quality improvement
1566 * by calculating ni and mi.
1568 ni
= 65536ULL * (max98090
->lrclk
< 50000 ? 96ULL : 48ULL)
1569 * (unsigned long long int)max98090
->lrclk
;
1570 do_div(ni
, (unsigned long long int)max98090
->sysclk
);
1571 dev_info(component
->dev
, "No better method found\n");
1572 dev_info(component
->dev
, "Calculating ni %lld with mi 65536\n", ni
);
1573 snd_soc_component_write(component
, M98090_REG_CLOCK_RATIO_NI_MSB
,
1575 snd_soc_component_write(component
, M98090_REG_CLOCK_RATIO_NI_LSB
, ni
& 0xFF);
1578 static int max98090_dai_set_fmt(struct snd_soc_dai
*codec_dai
,
1581 struct snd_soc_component
*component
= codec_dai
->component
;
1582 struct max98090_priv
*max98090
= snd_soc_component_get_drvdata(component
);
1583 struct max98090_cdata
*cdata
;
1584 u8 regval
, tdm_regval
;
1586 max98090
->dai_fmt
= fmt
;
1587 cdata
= &max98090
->dai
[0];
1589 if (fmt
!= cdata
->fmt
) {
1594 switch (fmt
& SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK
) {
1595 case SND_SOC_DAIFMT_CBC_CFC
:
1596 /* Set to consumer mode PLL - MAS mode off */
1597 snd_soc_component_write(component
,
1598 M98090_REG_CLOCK_RATIO_NI_MSB
, 0x00);
1599 snd_soc_component_write(component
,
1600 M98090_REG_CLOCK_RATIO_NI_LSB
, 0x00);
1601 snd_soc_component_update_bits(component
, M98090_REG_CLOCK_MODE
,
1602 M98090_USE_M1_MASK
, 0);
1603 max98090
->master
= false;
1605 case SND_SOC_DAIFMT_CBP_CFP
:
1606 /* Set to provider mode */
1607 if (max98090
->tdm_slots
== 4) {
1609 regval
|= M98090_MAS_MASK
|
1611 } else if (max98090
->tdm_slots
== 3) {
1613 regval
|= M98090_MAS_MASK
|
1616 /* Few TDM slots, or No TDM */
1617 regval
|= M98090_MAS_MASK
|
1620 max98090
->master
= true;
1623 dev_err(component
->dev
, "DAI clock mode unsupported");
1626 snd_soc_component_write(component
, M98090_REG_MASTER_MODE
, regval
);
1629 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1630 case SND_SOC_DAIFMT_I2S
:
1631 regval
|= M98090_DLY_MASK
;
1633 case SND_SOC_DAIFMT_LEFT_J
:
1635 case SND_SOC_DAIFMT_RIGHT_J
:
1636 regval
|= M98090_RJ_MASK
;
1638 case SND_SOC_DAIFMT_DSP_A
:
1639 tdm_regval
|= M98090_TDM_MASK
;
1642 dev_err(component
->dev
, "DAI format unsupported");
1646 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1647 case SND_SOC_DAIFMT_NB_NF
:
1649 case SND_SOC_DAIFMT_NB_IF
:
1650 regval
|= M98090_WCI_MASK
;
1652 case SND_SOC_DAIFMT_IB_NF
:
1653 regval
|= M98090_BCI_MASK
;
1655 case SND_SOC_DAIFMT_IB_IF
:
1656 regval
|= M98090_BCI_MASK
|M98090_WCI_MASK
;
1659 dev_err(component
->dev
, "DAI invert mode unsupported");
1664 * This accommodates an inverted logic in the MAX98090 chip
1665 * for Bit Clock Invert (BCI). The inverted logic is only
1666 * seen for the case of TDM mode. The remaining cases have
1670 regval
^= M98090_BCI_MASK
;
1672 snd_soc_component_write(component
,
1673 M98090_REG_INTERFACE_FORMAT
, regval
);
1677 regval
= max98090
->tdm_lslot
<< M98090_TDM_SLOTL_SHIFT
|
1678 max98090
->tdm_rslot
<< M98090_TDM_SLOTR_SHIFT
|
1679 0 << M98090_TDM_SLOTDLY_SHIFT
;
1681 snd_soc_component_write(component
, M98090_REG_TDM_FORMAT
, regval
);
1682 snd_soc_component_write(component
, M98090_REG_TDM_CONTROL
, tdm_regval
);
1688 static int max98090_set_tdm_slot(struct snd_soc_dai
*codec_dai
,
1689 unsigned int tx_mask
, unsigned int rx_mask
, int slots
, int slot_width
)
1691 struct snd_soc_component
*component
= codec_dai
->component
;
1692 struct max98090_priv
*max98090
= snd_soc_component_get_drvdata(component
);
1694 if (slots
< 0 || slots
> 4)
1697 if (slot_width
!= 16)
1700 if (rx_mask
!= tx_mask
)
1706 max98090
->tdm_slots
= slots
;
1707 max98090
->tdm_lslot
= ffs(rx_mask
) - 1;
1708 max98090
->tdm_rslot
= fls(rx_mask
) - 1;
1713 static int max98090_set_bias_level(struct snd_soc_component
*component
,
1714 enum snd_soc_bias_level level
)
1716 struct max98090_priv
*max98090
= snd_soc_component_get_drvdata(component
);
1720 case SND_SOC_BIAS_ON
:
1723 case SND_SOC_BIAS_PREPARE
:
1725 * SND_SOC_BIAS_PREPARE is called while preparing for a
1726 * transition to ON or away from ON. If current bias_level
1727 * is SND_SOC_BIAS_ON, then it is preparing for a transition
1728 * away from ON. Disable the clock in that case, otherwise
1731 if (IS_ERR(max98090
->mclk
))
1734 if (snd_soc_component_get_bias_level(component
) == SND_SOC_BIAS_ON
) {
1735 clk_disable_unprepare(max98090
->mclk
);
1737 ret
= clk_prepare_enable(max98090
->mclk
);
1743 case SND_SOC_BIAS_STANDBY
:
1744 if (snd_soc_component_get_bias_level(component
) == SND_SOC_BIAS_OFF
) {
1745 ret
= regcache_sync(max98090
->regmap
);
1747 dev_err(component
->dev
,
1748 "Failed to sync cache: %d\n", ret
);
1754 case SND_SOC_BIAS_OFF
:
1755 /* Set internal pull-up to lowest power mode */
1756 snd_soc_component_update_bits(component
, M98090_REG_JACK_DETECT
,
1757 M98090_JDWK_MASK
, M98090_JDWK_MASK
);
1758 regcache_mark_dirty(max98090
->regmap
);
1764 static const int dmic_divisors
[] = { 2, 3, 4, 5, 6, 8 };
1766 static const int comp_lrclk_rates
[] = {
1767 8000, 16000, 32000, 44100, 48000, 96000
1774 int comp
[6]; /* One each for 8, 16, 32, 44.1, 48, and 96 kHz */
1775 } settings
[6]; /* One for each dmic divisor. */
1778 static const struct dmic_table dmic_table
[] = { /* One for each pclk freq. */
1782 { .freq
= 2, .comp
= { 7, 8, 3, 3, 3, 3 } },
1783 { .freq
= 1, .comp
= { 7, 8, 2, 2, 2, 2 } },
1784 { .freq
= 0, .comp
= { 7, 8, 3, 3, 3, 3 } },
1785 { .freq
= 0, .comp
= { 7, 8, 6, 6, 6, 6 } },
1786 { .freq
= 0, .comp
= { 7, 8, 3, 3, 3, 3 } },
1787 { .freq
= 0, .comp
= { 7, 8, 3, 3, 3, 3 } },
1793 { .freq
= 2, .comp
= { 7, 8, 3, 3, 3, 3 } },
1794 { .freq
= 1, .comp
= { 7, 8, 2, 2, 2, 2 } },
1795 { .freq
= 0, .comp
= { 7, 8, 3, 3, 3, 3 } },
1796 { .freq
= 0, .comp
= { 7, 8, 5, 5, 6, 6 } },
1797 { .freq
= 0, .comp
= { 7, 8, 3, 3, 3, 3 } },
1798 { .freq
= 0, .comp
= { 7, 8, 3, 3, 3, 3 } },
1804 { .freq
= 2, .comp
= { 7, 8, 3, 3, 3, 3 } },
1805 { .freq
= 1, .comp
= { 7, 8, 2, 2, 2, 2 } },
1806 { .freq
= 0, .comp
= { 7, 8, 3, 3, 3, 3 } },
1807 { .freq
= 0, .comp
= { 7, 8, 6, 6, 6, 6 } },
1808 { .freq
= 0, .comp
= { 7, 8, 3, 3, 3, 3 } },
1809 { .freq
= 0, .comp
= { 7, 8, 3, 3, 3, 3 } },
1815 { .freq
= 2, .comp
= { 7, 8, 1, 1, 1, 1 } },
1816 { .freq
= 1, .comp
= { 7, 8, 0, 0, 0, 0 } },
1817 { .freq
= 0, .comp
= { 7, 8, 1, 1, 1, 1 } },
1818 { .freq
= 0, .comp
= { 7, 8, 4, 4, 5, 5 } },
1819 { .freq
= 0, .comp
= { 7, 8, 1, 1, 1, 1 } },
1820 { .freq
= 0, .comp
= { 7, 8, 1, 1, 1, 1 } },
1826 { .freq
= 2, .comp
= { 0, 0, 0, 0, 0, 0 } },
1827 { .freq
= 1, .comp
= { 7, 8, 1, 1, 1, 1 } },
1828 { .freq
= 0, .comp
= { 7, 8, 5, 5, 6, 6 } },
1829 { .freq
= 0, .comp
= { 7, 8, 2, 2, 3, 3 } },
1830 { .freq
= 0, .comp
= { 7, 8, 1, 1, 2, 2 } },
1831 { .freq
= 0, .comp
= { 7, 8, 5, 5, 6, 6 } },
1836 static int max98090_find_divisor(int target_freq
, int pclk
)
1838 int current_diff
= INT_MAX
;
1840 int divisor_index
= 0;
1843 for (i
= 0; i
< ARRAY_SIZE(dmic_divisors
); i
++) {
1844 test_diff
= abs(target_freq
- (pclk
/ dmic_divisors
[i
]));
1845 if (test_diff
< current_diff
) {
1846 current_diff
= test_diff
;
1851 return divisor_index
;
1854 static int max98090_find_closest_pclk(int pclk
)
1860 for (i
= 0; i
< ARRAY_SIZE(dmic_table
); i
++) {
1861 if (pclk
== dmic_table
[i
].pclk
)
1863 if (pclk
< dmic_table
[i
].pclk
) {
1866 m1
= pclk
- dmic_table
[i
-1].pclk
;
1867 m2
= dmic_table
[i
].pclk
- pclk
;
1878 static int max98090_configure_dmic(struct max98090_priv
*max98090
,
1879 int target_dmic_clk
, int pclk
, int fs
)
1887 pclk_index
= max98090_find_closest_pclk(pclk
);
1891 micclk_index
= max98090_find_divisor(target_dmic_clk
, pclk
);
1893 for (i
= 0; i
< ARRAY_SIZE(comp_lrclk_rates
) - 1; i
++) {
1894 if (fs
<= (comp_lrclk_rates
[i
] + comp_lrclk_rates
[i
+1]) / 2)
1898 dmic_freq
= dmic_table
[pclk_index
].settings
[micclk_index
].freq
;
1899 dmic_comp
= dmic_table
[pclk_index
].settings
[micclk_index
].comp
[i
];
1901 regmap_update_bits(max98090
->regmap
, M98090_REG_DIGITAL_MIC_ENABLE
,
1903 micclk_index
<< M98090_MICCLK_SHIFT
);
1905 regmap_update_bits(max98090
->regmap
, M98090_REG_DIGITAL_MIC_CONFIG
,
1906 M98090_DMIC_COMP_MASK
| M98090_DMIC_FREQ_MASK
,
1907 dmic_comp
<< M98090_DMIC_COMP_SHIFT
|
1908 dmic_freq
<< M98090_DMIC_FREQ_SHIFT
);
1913 static int max98090_dai_startup(struct snd_pcm_substream
*substream
,
1914 struct snd_soc_dai
*dai
)
1916 struct snd_soc_component
*component
= dai
->component
;
1917 struct max98090_priv
*max98090
= snd_soc_component_get_drvdata(component
);
1918 unsigned int fmt
= max98090
->dai_fmt
;
1920 /* Remove 24-bit format support if it is not in right justified mode. */
1921 if ((fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) != SND_SOC_DAIFMT_RIGHT_J
) {
1922 substream
->runtime
->hw
.formats
= SNDRV_PCM_FMTBIT_S16_LE
;
1923 snd_pcm_hw_constraint_msbits(substream
->runtime
, 0, 16, 16);
1928 static int max98090_dai_hw_params(struct snd_pcm_substream
*substream
,
1929 struct snd_pcm_hw_params
*params
,
1930 struct snd_soc_dai
*dai
)
1932 struct snd_soc_component
*component
= dai
->component
;
1933 struct max98090_priv
*max98090
= snd_soc_component_get_drvdata(component
);
1934 struct max98090_cdata
*cdata
;
1936 cdata
= &max98090
->dai
[0];
1937 max98090
->bclk
= snd_soc_params_to_bclk(params
);
1938 if (params_channels(params
) == 1)
1939 max98090
->bclk
*= 2;
1941 max98090
->lrclk
= params_rate(params
);
1943 switch (params_width(params
)) {
1945 snd_soc_component_update_bits(component
, M98090_REG_INTERFACE_FORMAT
,
1952 if (max98090
->master
)
1953 max98090_configure_bclk(component
);
1955 cdata
->rate
= max98090
->lrclk
;
1957 /* Update filter mode */
1958 if (max98090
->lrclk
< 24000)
1959 snd_soc_component_update_bits(component
, M98090_REG_FILTER_CONFIG
,
1960 M98090_MODE_MASK
, 0);
1962 snd_soc_component_update_bits(component
, M98090_REG_FILTER_CONFIG
,
1963 M98090_MODE_MASK
, M98090_MODE_MASK
);
1965 /* Update sample rate mode */
1966 if (max98090
->lrclk
< 50000)
1967 snd_soc_component_update_bits(component
, M98090_REG_FILTER_CONFIG
,
1968 M98090_DHF_MASK
, 0);
1970 snd_soc_component_update_bits(component
, M98090_REG_FILTER_CONFIG
,
1971 M98090_DHF_MASK
, M98090_DHF_MASK
);
1973 max98090_configure_dmic(max98090
, max98090
->dmic_freq
, max98090
->pclk
,
1982 static int max98090_dai_set_sysclk(struct snd_soc_dai
*dai
,
1983 int clk_id
, unsigned int freq
, int dir
)
1985 struct snd_soc_component
*component
= dai
->component
;
1986 struct max98090_priv
*max98090
= snd_soc_component_get_drvdata(component
);
1988 /* Requested clock frequency is already setup */
1989 if (freq
== max98090
->sysclk
)
1992 if (!IS_ERR(max98090
->mclk
)) {
1993 freq
= clk_round_rate(max98090
->mclk
, freq
);
1994 clk_set_rate(max98090
->mclk
, freq
);
1997 /* Setup clocks for slave mode, and using the PLL
1998 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1999 * 0x02 (when master clk is 20MHz to 40MHz)..
2000 * 0x03 (when master clk is 40MHz to 60MHz)..
2002 if ((freq
>= 10000000) && (freq
<= 20000000)) {
2003 snd_soc_component_write(component
, M98090_REG_SYSTEM_CLOCK
,
2005 max98090
->pclk
= freq
;
2006 } else if ((freq
> 20000000) && (freq
<= 40000000)) {
2007 snd_soc_component_write(component
, M98090_REG_SYSTEM_CLOCK
,
2009 max98090
->pclk
= freq
>> 1;
2010 } else if ((freq
> 40000000) && (freq
<= 60000000)) {
2011 snd_soc_component_write(component
, M98090_REG_SYSTEM_CLOCK
,
2013 max98090
->pclk
= freq
>> 2;
2015 dev_err(component
->dev
, "Invalid master clock frequency\n");
2019 max98090
->sysclk
= freq
;
2024 static int max98090_dai_mute(struct snd_soc_dai
*codec_dai
, int mute
,
2027 struct snd_soc_component
*component
= codec_dai
->component
;
2030 regval
= mute
? M98090_DVM_MASK
: 0;
2031 snd_soc_component_update_bits(component
, M98090_REG_DAI_PLAYBACK_LEVEL
,
2032 M98090_DVM_MASK
, regval
);
2037 static int max98090_dai_trigger(struct snd_pcm_substream
*substream
, int cmd
,
2038 struct snd_soc_dai
*dai
)
2040 struct snd_soc_component
*component
= dai
->component
;
2041 struct max98090_priv
*max98090
= snd_soc_component_get_drvdata(component
);
2044 case SNDRV_PCM_TRIGGER_START
:
2045 case SNDRV_PCM_TRIGGER_RESUME
:
2046 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
2047 if (!max98090
->master
&& snd_soc_dai_active(dai
) == 1)
2048 queue_delayed_work(system_power_efficient_wq
,
2049 &max98090
->pll_det_enable_work
,
2050 msecs_to_jiffies(10));
2052 case SNDRV_PCM_TRIGGER_STOP
:
2053 case SNDRV_PCM_TRIGGER_SUSPEND
:
2054 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
2055 if (!max98090
->master
&& snd_soc_dai_active(dai
) == 1)
2056 schedule_work(&max98090
->pll_det_disable_work
);
2065 static void max98090_pll_det_enable_work(struct work_struct
*work
)
2067 struct max98090_priv
*max98090
=
2068 container_of(work
, struct max98090_priv
,
2069 pll_det_enable_work
.work
);
2070 struct snd_soc_component
*component
= max98090
->component
;
2071 unsigned int status
, mask
;
2074 * Clear status register in order to clear possibly already occurred
2075 * PLL unlock. If PLL hasn't still locked, the status will be set
2076 * again and PLL unlock interrupt will occur.
2077 * Note this will clear all status bits
2079 regmap_read(max98090
->regmap
, M98090_REG_DEVICE_STATUS
, &status
);
2082 * Queue jack work in case jack state has just changed but handler
2085 regmap_read(max98090
->regmap
, M98090_REG_INTERRUPT_S
, &mask
);
2087 if (status
& M98090_JDET_MASK
)
2088 queue_delayed_work(system_power_efficient_wq
,
2089 &max98090
->jack_work
,
2090 msecs_to_jiffies(100));
2092 /* Enable PLL unlock interrupt */
2093 snd_soc_component_update_bits(component
, M98090_REG_INTERRUPT_S
,
2095 1 << M98090_IULK_SHIFT
);
2098 static void max98090_pll_det_disable_work(struct work_struct
*work
)
2100 struct max98090_priv
*max98090
=
2101 container_of(work
, struct max98090_priv
, pll_det_disable_work
);
2102 struct snd_soc_component
*component
= max98090
->component
;
2104 cancel_delayed_work_sync(&max98090
->pll_det_enable_work
);
2106 /* Disable PLL unlock interrupt */
2107 snd_soc_component_update_bits(component
, M98090_REG_INTERRUPT_S
,
2108 M98090_IULK_MASK
, 0);
2111 static void max98090_pll_work(struct max98090_priv
*max98090
)
2113 struct snd_soc_component
*component
= max98090
->component
;
2117 if (!snd_soc_component_active(component
))
2120 dev_info_ratelimited(component
->dev
, "PLL unlocked\n");
2123 * As the datasheet suggested, the maximum PLL lock time should be
2124 * 7 msec. The workaround resets the codec softly by toggling SHDN
2125 * off and on if PLL failed to lock for 10 msec. Notably, there is
2126 * no suggested hold time for SHDN off.
2129 /* Toggle shutdown OFF then ON */
2130 snd_soc_component_update_bits(component
, M98090_REG_DEVICE_SHUTDOWN
,
2131 M98090_SHDNN_MASK
, 0);
2132 snd_soc_component_update_bits(component
, M98090_REG_DEVICE_SHUTDOWN
,
2133 M98090_SHDNN_MASK
, M98090_SHDNN_MASK
);
2135 for (i
= 0; i
< 10; ++i
) {
2136 /* Give PLL time to lock */
2137 usleep_range(1000, 1200);
2139 /* Check lock status */
2140 pll
= snd_soc_component_read(
2141 component
, M98090_REG_DEVICE_STATUS
);
2142 if (!(pll
& M98090_ULK_MASK
))
2147 static void max98090_jack_work(struct work_struct
*work
)
2149 struct max98090_priv
*max98090
= container_of(work
,
2150 struct max98090_priv
,
2152 struct snd_soc_component
*component
= max98090
->component
;
2156 /* Read a second time */
2157 if (max98090
->jack_state
== M98090_JACK_STATE_NO_HEADSET
) {
2159 /* Strong pull up allows mic detection */
2160 snd_soc_component_update_bits(component
, M98090_REG_JACK_DETECT
,
2161 M98090_JDWK_MASK
, 0);
2165 snd_soc_component_read(component
, M98090_REG_JACK_STATUS
);
2167 /* Weak pull up allows only insertion detection */
2168 snd_soc_component_update_bits(component
, M98090_REG_JACK_DETECT
,
2169 M98090_JDWK_MASK
, M98090_JDWK_MASK
);
2172 reg
= snd_soc_component_read(component
, M98090_REG_JACK_STATUS
);
2174 switch (reg
& (M98090_LSNS_MASK
| M98090_JKSNS_MASK
)) {
2175 case M98090_LSNS_MASK
| M98090_JKSNS_MASK
:
2176 dev_dbg(component
->dev
, "No Headset Detected\n");
2178 max98090
->jack_state
= M98090_JACK_STATE_NO_HEADSET
;
2185 if (max98090
->jack_state
==
2186 M98090_JACK_STATE_HEADSET
) {
2188 dev_dbg(component
->dev
,
2189 "Headset Button Down Detected\n");
2192 * max98090_headset_button_event(codec)
2193 * could be defined, then called here.
2196 status
|= SND_JACK_HEADSET
;
2197 status
|= SND_JACK_BTN_0
;
2202 /* Line is reported as Headphone */
2203 /* Nokia Headset is reported as Headphone */
2204 /* Mono Headphone is reported as Headphone */
2205 dev_dbg(component
->dev
, "Headphone Detected\n");
2207 max98090
->jack_state
= M98090_JACK_STATE_HEADPHONE
;
2209 status
|= SND_JACK_HEADPHONE
;
2213 case M98090_JKSNS_MASK
:
2214 dev_dbg(component
->dev
, "Headset Detected\n");
2216 max98090
->jack_state
= M98090_JACK_STATE_HEADSET
;
2218 status
|= SND_JACK_HEADSET
;
2223 dev_dbg(component
->dev
, "Unrecognized Jack Status\n");
2227 snd_soc_jack_report(max98090
->jack
, status
,
2228 SND_JACK_HEADSET
| SND_JACK_BTN_0
);
2231 static irqreturn_t
max98090_interrupt(int irq
, void *data
)
2233 struct max98090_priv
*max98090
= data
;
2234 struct snd_soc_component
*component
= max98090
->component
;
2237 unsigned int active
;
2239 /* Treat interrupt before codec is initialized as spurious */
2240 if (component
== NULL
)
2243 dev_dbg(component
->dev
, "***** max98090_interrupt *****\n");
2245 ret
= regmap_read(max98090
->regmap
, M98090_REG_INTERRUPT_S
, &mask
);
2248 dev_err(component
->dev
,
2249 "failed to read M98090_REG_INTERRUPT_S: %d\n",
2254 ret
= regmap_read(max98090
->regmap
, M98090_REG_DEVICE_STATUS
, &active
);
2257 dev_err(component
->dev
,
2258 "failed to read M98090_REG_DEVICE_STATUS: %d\n",
2263 dev_dbg(component
->dev
, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
2264 active
, mask
, active
& mask
);
2271 if (active
& M98090_CLD_MASK
)
2272 dev_err(component
->dev
, "M98090_CLD_MASK\n");
2274 if (active
& M98090_SLD_MASK
)
2275 dev_dbg(component
->dev
, "M98090_SLD_MASK\n");
2277 if (active
& M98090_ULK_MASK
) {
2278 dev_dbg(component
->dev
, "M98090_ULK_MASK\n");
2279 max98090_pll_work(max98090
);
2282 if (active
& M98090_JDET_MASK
) {
2283 dev_dbg(component
->dev
, "M98090_JDET_MASK\n");
2285 pm_wakeup_event(component
->dev
, 100);
2287 queue_delayed_work(system_power_efficient_wq
,
2288 &max98090
->jack_work
,
2289 msecs_to_jiffies(100));
2292 if (active
& M98090_DRCACT_MASK
)
2293 dev_dbg(component
->dev
, "M98090_DRCACT_MASK\n");
2295 if (active
& M98090_DRCCLP_MASK
)
2296 dev_err(component
->dev
, "M98090_DRCCLP_MASK\n");
2302 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2304 * @component: MAX98090 component
2305 * @jack: jack to report detection events on
2307 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are
2308 * being used to bring out signals to the processor then only platform
2309 * data configuration is needed for MAX98090 and processor GPIOs should
2310 * be configured using snd_soc_jack_add_gpios() instead.
2312 * If no jack is supplied detection will be disabled.
2314 int max98090_mic_detect(struct snd_soc_component
*component
,
2315 struct snd_soc_jack
*jack
)
2317 struct max98090_priv
*max98090
= snd_soc_component_get_drvdata(component
);
2319 dev_dbg(component
->dev
, "max98090_mic_detect\n");
2321 max98090
->jack
= jack
;
2323 snd_soc_component_update_bits(component
, M98090_REG_INTERRUPT_S
,
2325 1 << M98090_IJDET_SHIFT
);
2327 snd_soc_component_update_bits(component
, M98090_REG_INTERRUPT_S
,
2332 /* Send an initial empty report */
2333 snd_soc_jack_report(max98090
->jack
, 0,
2334 SND_JACK_HEADSET
| SND_JACK_BTN_0
);
2336 queue_delayed_work(system_power_efficient_wq
,
2337 &max98090
->jack_work
,
2338 msecs_to_jiffies(100));
2342 EXPORT_SYMBOL_GPL(max98090_mic_detect
);
2344 #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
2345 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
2347 static const struct snd_soc_dai_ops max98090_dai_ops
= {
2348 .startup
= max98090_dai_startup
,
2349 .set_sysclk
= max98090_dai_set_sysclk
,
2350 .set_fmt
= max98090_dai_set_fmt
,
2351 .set_tdm_slot
= max98090_set_tdm_slot
,
2352 .hw_params
= max98090_dai_hw_params
,
2353 .mute_stream
= max98090_dai_mute
,
2354 .trigger
= max98090_dai_trigger
,
2355 .no_capture_mute
= 1,
2358 static struct snd_soc_dai_driver max98090_dai
= {
2361 .stream_name
= "HiFi Playback",
2364 .rates
= MAX98090_RATES
,
2365 .formats
= MAX98090_FORMATS
,
2368 .stream_name
= "HiFi Capture",
2371 .rates
= MAX98090_RATES
,
2372 .formats
= MAX98090_FORMATS
,
2374 .ops
= &max98090_dai_ops
,
2377 static int max98090_probe(struct snd_soc_component
*component
)
2379 struct max98090_priv
*max98090
= snd_soc_component_get_drvdata(component
);
2380 struct max98090_cdata
*cdata
;
2381 enum max98090_type devtype
;
2384 unsigned int micbias
;
2386 dev_dbg(component
->dev
, "max98090_probe\n");
2388 max98090
->mclk
= devm_clk_get(component
->dev
, "mclk");
2389 if (PTR_ERR(max98090
->mclk
) == -EPROBE_DEFER
)
2390 return -EPROBE_DEFER
;
2392 max98090
->component
= component
;
2394 /* Reset the codec, the DSP core, and disable all interrupts */
2395 max98090_reset(max98090
);
2397 /* Initialize private data */
2399 max98090
->sysclk
= (unsigned)-1;
2400 max98090
->pclk
= (unsigned)-1;
2401 max98090
->master
= false;
2403 cdata
= &max98090
->dai
[0];
2404 cdata
->rate
= (unsigned)-1;
2405 cdata
->fmt
= (unsigned)-1;
2407 max98090
->lin_state
= 0;
2408 max98090
->pa1en
= 0;
2409 max98090
->pa2en
= 0;
2411 max98090
->tdm_lslot
= 0;
2412 max98090
->tdm_rslot
= 1;
2414 ret
= snd_soc_component_read(component
, M98090_REG_REVISION_ID
);
2416 dev_err(component
->dev
, "Failed to read device revision: %d\n",
2421 if ((ret
>= M98090_REVA
) && (ret
<= M98090_REVA
+ 0x0f)) {
2423 dev_info(component
->dev
, "MAX98090 REVID=0x%02x\n", ret
);
2424 } else if ((ret
>= M98091_REVA
) && (ret
<= M98091_REVA
+ 0x0f)) {
2426 dev_info(component
->dev
, "MAX98091 REVID=0x%02x\n", ret
);
2429 dev_err(component
->dev
, "Unrecognized revision 0x%02x\n", ret
);
2432 if (max98090
->devtype
!= devtype
) {
2433 dev_warn(component
->dev
, "Mismatch in DT specified CODEC type.\n");
2434 max98090
->devtype
= devtype
;
2437 max98090
->jack_state
= M98090_JACK_STATE_NO_HEADSET
;
2439 INIT_DELAYED_WORK(&max98090
->jack_work
, max98090_jack_work
);
2440 INIT_DELAYED_WORK(&max98090
->pll_det_enable_work
,
2441 max98090_pll_det_enable_work
);
2442 INIT_WORK(&max98090
->pll_det_disable_work
,
2443 max98090_pll_det_disable_work
);
2445 /* Enable jack detection */
2446 snd_soc_component_write(component
, M98090_REG_JACK_DETECT
,
2447 M98090_JDETEN_MASK
| M98090_JDEB_25MS
);
2450 * Clear any old interrupts.
2451 * An old interrupt ocurring prior to installing the ISR
2452 * can keep a new interrupt from generating a trigger.
2454 snd_soc_component_read(component
, M98090_REG_DEVICE_STATUS
);
2456 /* High Performance is default */
2457 snd_soc_component_update_bits(component
, M98090_REG_DAC_CONTROL
,
2459 1 << M98090_DACHP_SHIFT
);
2460 snd_soc_component_update_bits(component
, M98090_REG_DAC_CONTROL
,
2461 M98090_PERFMODE_MASK
,
2462 0 << M98090_PERFMODE_SHIFT
);
2463 snd_soc_component_update_bits(component
, M98090_REG_ADC_CONTROL
,
2465 1 << M98090_ADCHP_SHIFT
);
2467 /* Turn on VCM bandgap reference */
2468 snd_soc_component_write(component
, M98090_REG_BIAS_CONTROL
,
2469 M98090_VCM_MODE_MASK
);
2471 err
= device_property_read_u32(component
->dev
, "maxim,micbias", &micbias
);
2473 micbias
= M98090_MBVSEL_2V8
;
2474 dev_info(component
->dev
, "use default 2.8v micbias\n");
2475 } else if (micbias
> M98090_MBVSEL_2V8
) {
2476 dev_err(component
->dev
, "micbias out of range 0x%x\n", micbias
);
2477 micbias
= M98090_MBVSEL_2V8
;
2480 snd_soc_component_update_bits(component
, M98090_REG_MIC_BIAS_VOLTAGE
,
2481 M98090_MBVSEL_MASK
, micbias
);
2483 max98090_add_widgets(component
);
2489 static void max98090_remove(struct snd_soc_component
*component
)
2491 struct max98090_priv
*max98090
= snd_soc_component_get_drvdata(component
);
2493 cancel_delayed_work_sync(&max98090
->jack_work
);
2494 cancel_delayed_work_sync(&max98090
->pll_det_enable_work
);
2495 cancel_work_sync(&max98090
->pll_det_disable_work
);
2496 max98090
->component
= NULL
;
2499 static void max98090_seq_notifier(struct snd_soc_component
*component
,
2500 enum snd_soc_dapm_type event
, int subseq
)
2502 struct max98090_priv
*max98090
= snd_soc_component_get_drvdata(component
);
2504 if (max98090
->shdn_pending
) {
2505 snd_soc_component_update_bits(component
, M98090_REG_DEVICE_SHUTDOWN
,
2506 M98090_SHDNN_MASK
, 0);
2508 snd_soc_component_update_bits(component
, M98090_REG_DEVICE_SHUTDOWN
,
2509 M98090_SHDNN_MASK
, M98090_SHDNN_MASK
);
2510 max98090
->shdn_pending
= false;
2514 static const struct snd_soc_component_driver soc_component_dev_max98090
= {
2515 .probe
= max98090_probe
,
2516 .remove
= max98090_remove
,
2517 .seq_notifier
= max98090_seq_notifier
,
2518 .set_bias_level
= max98090_set_bias_level
,
2520 .use_pmdown_time
= 1,
2524 static const struct regmap_config max98090_regmap
= {
2528 .max_register
= MAX98090_MAX_REGISTER
,
2529 .reg_defaults
= max98090_reg
,
2530 .num_reg_defaults
= ARRAY_SIZE(max98090_reg
),
2531 .volatile_reg
= max98090_volatile_register
,
2532 .readable_reg
= max98090_readable_register
,
2533 .cache_type
= REGCACHE_RBTREE
,
2536 static const struct i2c_device_id max98090_i2c_id
[] = {
2537 { "max98090", MAX98090
},
2538 { "max98091", MAX98091
},
2541 MODULE_DEVICE_TABLE(i2c
, max98090_i2c_id
);
2543 static int max98090_i2c_probe(struct i2c_client
*i2c
)
2545 struct max98090_priv
*max98090
;
2546 const struct acpi_device_id
*acpi_id
;
2547 kernel_ulong_t driver_data
= 0;
2550 pr_debug("max98090_i2c_probe\n");
2552 max98090
= devm_kzalloc(&i2c
->dev
, sizeof(struct max98090_priv
),
2554 if (max98090
== NULL
)
2557 if (ACPI_HANDLE(&i2c
->dev
)) {
2558 acpi_id
= acpi_match_device(i2c
->dev
.driver
->acpi_match_table
,
2561 dev_err(&i2c
->dev
, "No driver data\n");
2564 driver_data
= acpi_id
->driver_data
;
2566 const struct i2c_device_id
*i2c_id
=
2567 i2c_match_id(max98090_i2c_id
, i2c
);
2568 driver_data
= i2c_id
->driver_data
;
2571 max98090
->devtype
= driver_data
;
2572 i2c_set_clientdata(i2c
, max98090
);
2573 max98090
->pdata
= i2c
->dev
.platform_data
;
2575 ret
= of_property_read_u32(i2c
->dev
.of_node
, "maxim,dmic-freq",
2576 &max98090
->dmic_freq
);
2578 max98090
->dmic_freq
= MAX98090_DEFAULT_DMIC_FREQ
;
2580 max98090
->regmap
= devm_regmap_init_i2c(i2c
, &max98090_regmap
);
2581 if (IS_ERR(max98090
->regmap
)) {
2582 ret
= PTR_ERR(max98090
->regmap
);
2583 dev_err(&i2c
->dev
, "Failed to allocate regmap: %d\n", ret
);
2587 ret
= devm_request_threaded_irq(&i2c
->dev
, i2c
->irq
, NULL
,
2588 max98090_interrupt
, IRQF_TRIGGER_FALLING
| IRQF_ONESHOT
,
2589 "max98090_interrupt", max98090
);
2591 dev_err(&i2c
->dev
, "request_irq failed: %d\n",
2596 ret
= devm_snd_soc_register_component(&i2c
->dev
,
2597 &soc_component_dev_max98090
,
2603 static void max98090_i2c_shutdown(struct i2c_client
*i2c
)
2605 struct max98090_priv
*max98090
= dev_get_drvdata(&i2c
->dev
);
2608 * Enable volume smoothing, disable zero cross. This will cause
2609 * a quick 40ms ramp to mute on shutdown.
2611 regmap_write(max98090
->regmap
,
2612 M98090_REG_LEVEL_CONTROL
, M98090_VSENN_MASK
);
2613 regmap_write(max98090
->regmap
,
2614 M98090_REG_DEVICE_SHUTDOWN
, 0x00);
2618 static void max98090_i2c_remove(struct i2c_client
*client
)
2620 max98090_i2c_shutdown(client
);
2624 static int max98090_runtime_resume(struct device
*dev
)
2626 struct max98090_priv
*max98090
= dev_get_drvdata(dev
);
2628 regcache_cache_only(max98090
->regmap
, false);
2630 max98090_reset(max98090
);
2632 regcache_sync(max98090
->regmap
);
2637 static int max98090_runtime_suspend(struct device
*dev
)
2639 struct max98090_priv
*max98090
= dev_get_drvdata(dev
);
2641 regcache_cache_only(max98090
->regmap
, true);
2647 #ifdef CONFIG_PM_SLEEP
2648 static int max98090_resume(struct device
*dev
)
2650 struct max98090_priv
*max98090
= dev_get_drvdata(dev
);
2651 unsigned int status
;
2653 regcache_mark_dirty(max98090
->regmap
);
2655 max98090_reset(max98090
);
2657 /* clear IRQ status */
2658 regmap_read(max98090
->regmap
, M98090_REG_DEVICE_STATUS
, &status
);
2660 regcache_sync(max98090
->regmap
);
2666 static const struct dev_pm_ops max98090_pm
= {
2667 SET_RUNTIME_PM_OPS(max98090_runtime_suspend
,
2668 max98090_runtime_resume
, NULL
)
2669 SET_SYSTEM_SLEEP_PM_OPS(NULL
, max98090_resume
)
2673 static const struct of_device_id max98090_of_match
[] = {
2674 { .compatible
= "maxim,max98090", },
2675 { .compatible
= "maxim,max98091", },
2678 MODULE_DEVICE_TABLE(of
, max98090_of_match
);
2682 static const struct acpi_device_id max98090_acpi_match
[] = {
2683 { "193C9890", MAX98090
},
2686 MODULE_DEVICE_TABLE(acpi
, max98090_acpi_match
);
2689 static struct i2c_driver max98090_i2c_driver
= {
2693 .of_match_table
= of_match_ptr(max98090_of_match
),
2694 .acpi_match_table
= ACPI_PTR(max98090_acpi_match
),
2696 .probe
= max98090_i2c_probe
,
2697 .shutdown
= max98090_i2c_shutdown
,
2698 .remove
= max98090_i2c_remove
,
2699 .id_table
= max98090_i2c_id
,
2702 module_i2c_driver(max98090_i2c_driver
);
2704 MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
2705 MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
2706 MODULE_LICENSE("GPL");