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drm/rockchip: dw_hdmi_qp: Add basic RK3576 HDMI output support
[drm/drm-misc.git] / sound / soc / codecs / mt6357.c
blob988728df15e4a9285be03d3ecd926c7327ffd62a
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MT6357 ALSA SoC audio codec driver
4 *
5 * Copyright (c) 2024 Baylibre
6 * Author: Nicolas Belin <nbelin@baylibre.com>
7 */
8
9 #include <linux/dma-mapping.h>
10 #include <sound/soc.h>
11 #include <sound/tlv.h>
12 #include <linux/mfd/mt6397/core.h>
13 #include <linux/regulator/consumer.h>
14
15 #include "mt6357.h"
16
17 static void set_playback_gpio(struct mt6357_priv *priv, bool enable)
18 {
19 regmap_write(priv->regmap, MT6357_GPIO_MODE2_CLR, MT6357_GPIO_MODE2_CLEAR_ALL);
20 if (enable) {
21 /* set gpio mosi mode */
22 regmap_write(priv->regmap, MT6357_GPIO_MODE2_SET,
23 MT6357_GPIO8_MODE_SET_AUD_CLK_MOSI |
24 MT6357_GPIO9_MODE_SET_AUD_DAT_MOSI0 |
25 MT6357_GPIO10_MODE_SET_AUD_DAT_MOSI1 |
26 MT6357_GPIO11_MODE_SET_AUD_SYNC_MOSI);
27 } else {
28 /* pad_aud_*_mosi are GPIO mode after clear and set them to dir input
29 * reason:
30 * pad_aud_dat_mosi*, because the pin is used as boot strap
31 */
32 regmap_update_bits(priv->regmap, MT6357_GPIO_DIR0,
33 MT6357_GPIO8_DIR_MASK |
34 MT6357_GPIO9_DIR_MASK |
35 MT6357_GPIO10_DIR_MASK |
36 MT6357_GPIO11_DIR_MASK,
37 MT6357_GPIO8_DIR_INPUT |
38 MT6357_GPIO9_DIR_INPUT |
39 MT6357_GPIO10_DIR_INPUT |
40 MT6357_GPIO11_DIR_INPUT);
41 }
42 }
43
44 static void set_capture_gpio(struct mt6357_priv *priv, bool enable)
45 {
46 regmap_write(priv->regmap, MT6357_GPIO_MODE3_CLR, MT6357_GPIO_MODE3_CLEAR_ALL);
47 if (enable) {
48 /* set gpio miso mode */
49 regmap_write(priv->regmap, MT6357_GPIO_MODE3_SET,
50 MT6357_GPIO12_MODE_SET_AUD_CLK_MISO |
51 MT6357_GPIO13_MODE_SET_AUD_DAT_MISO0 |
52 MT6357_GPIO14_MODE_SET_AUD_DAT_MISO1 |
53 MT6357_GPIO15_MODE_SET_AUD_SYNC_MISO);
54 } else {
55 /* pad_aud_*_mosi are GPIO mode after clear and set them to dir input
56 * reason:
57 * pad_aud_clk_miso, because when playback only the miso_clk
58 * will also have 26m, so will have power leak
59 * pad_aud_dat_miso*, because the pin is used as boot strap
60 */
61 regmap_update_bits(priv->regmap, MT6357_GPIO_DIR0,
62 MT6357_GPIO12_DIR_MASK |
63 MT6357_GPIO13_DIR_MASK |
64 MT6357_GPIO14_DIR_MASK |
65 MT6357_GPIO15_DIR_MASK,
66 MT6357_GPIO12_DIR_INPUT |
67 MT6357_GPIO13_DIR_INPUT |
68 MT6357_GPIO14_DIR_INPUT |
69 MT6357_GPIO15_DIR_INPUT);
70 }
71 }
72
73 static void hp_main_output_ramp(struct mt6357_priv *priv, bool up)
74 {
75 int i, stage;
76
77 /* Enable/Reduce HPL/R main output stage step by step */
78 for (i = 0; i <= MT6357_HPLOUT_STG_CTRL_VAUDP15_MAX; i++) {
79 stage = up ? i : MT6357_HPLOUT_STG_CTRL_VAUDP15_MAX - i;
80 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON1,
81 MT6357_HPLOUT_STG_CTRL_VAUDP15_MASK,
82 stage << MT6357_HPLOUT_STG_CTRL_VAUDP15_SFT);
83 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON1,
84 MT6357_HPROUT_STG_CTRL_VAUDP15_MASK,
85 stage << MT6357_HPROUT_STG_CTRL_VAUDP15_SFT);
86 usleep_range(600, 700);
87 }
88 }
89
90 static void hp_aux_feedback_loop_gain_ramp(struct mt6357_priv *priv, bool up)
91 {
92 int i, stage;
93
94 /* Reduce HP aux feedback loop gain step by step */
95 for (i = 0; i <= MT6357_HP_AUX_LOOP_GAIN_MAX; i++) {
96 stage = up ? i : MT6357_HP_AUX_LOOP_GAIN_MAX - i;
97 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON6,
98 MT6357_HP_AUX_LOOP_GAIN_MASK,
99 stage << MT6357_HP_AUX_LOOP_GAIN_SFT);
100 usleep_range(600, 700);
101 }
102 }
103
104 static void hp_pull_down(struct mt6357_priv *priv, bool enable)
105 {
106 if (enable)
107 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON2,
108 MT6357_HPP_SHORT_2VCM_VAUDP15_MASK,
109 MT6357_HPP_SHORT_2VCM_VAUDP15_ENABLE);
110 else
111 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON2,
112 MT6357_HPP_SHORT_2VCM_VAUDP15_MASK,
113 MT6357_HPP_SHORT_2VCM_VAUDP15_DISABLE);
114 }
115
116 static bool is_valid_hp_pga_idx(int reg_idx)
117 {
118 return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_12DB) || reg_idx == DL_GAIN_N_40DB;
119 }
120
121 static void volume_ramp(struct mt6357_priv *priv, int lfrom, int lto,
122 int rfrom, int rto, unsigned int reg_addr)
123 {
124 int lcount, rcount, sleep = 0;
125
126 if (!is_valid_hp_pga_idx(lfrom) || !is_valid_hp_pga_idx(lto))
127 pr_debug("%s(), invalid left volume index, from %d, to %d\n",
128 __func__, lfrom, lto);
129
130 if (!is_valid_hp_pga_idx(rfrom) || !is_valid_hp_pga_idx(rto))
131 pr_debug("%s(), invalid right volume index, from %d, to %d\n",
132 __func__, rfrom, rto);
133
134 if (lto > lfrom)
135 lcount = 1;
136 else
137 lcount = -1;
138
139 if (rto > rfrom)
140 rcount = 1;
141 else
142 rcount = -1;
143
144 while ((lto != lfrom) || (rto != rfrom)) {
145 if (lto != lfrom) {
146 lfrom += lcount;
147 if (is_valid_hp_pga_idx(lfrom)) {
148 regmap_update_bits(priv->regmap, reg_addr,
149 MT6357_DL_GAIN_REG_LEFT_MASK,
150 lfrom << MT6357_DL_GAIN_REG_LEFT_SHIFT);
151 sleep = 1;
152 }
153 }
154 if (rto != rfrom) {
155 rfrom += rcount;
156 if (is_valid_hp_pga_idx(rfrom)) {
157 regmap_update_bits(priv->regmap, reg_addr,
158 MT6357_DL_GAIN_REG_RIGHT_MASK,
159 rfrom << MT6357_DL_GAIN_REG_RIGHT_SHIFT);
160 sleep = 1;
161 }
162 }
163 if (sleep)
164 usleep_range(200, 300);
165 }
166 }
167
168 static void lo_volume_ramp(struct mt6357_priv *priv, int lfrom, int lto, int rfrom, int rto)
169 {
170 volume_ramp(priv, lfrom, lto, rfrom, rto, MT6357_ZCD_CON1);
171 }
172
173 static void hp_volume_ramp(struct mt6357_priv *priv, int lfrom, int lto, int rfrom, int rto)
174 {
175 volume_ramp(priv, lfrom, lto, rfrom, rto, MT6357_ZCD_CON2);
176 }
177
178 static void hs_volume_ramp(struct mt6357_priv *priv, int from, int to)
179 {
180 volume_ramp(priv, from, to, 0, 0, MT6357_ZCD_CON3);
181 }
182
183 /* Volume and channel swap controls */
184 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
185 static const DECLARE_TLV_DB_SCALE(capture_tlv, 0, 600, 0);
186 static const DECLARE_TLV_DB_SCALE(hp_degain_tlv, -1200, 1200, 0);
187
188 static const struct snd_kcontrol_new mt6357_controls[] = {
189 /* dl pga gain */
190 SOC_DOUBLE_TLV("Headphone Volume",
191 MT6357_ZCD_CON2, MT6357_AUD_HPL_GAIN_SFT,
192 MT6357_AUD_HPR_GAIN_SFT, MT6357_AUD_HP_GAIN_MAX,
193 1, playback_tlv),
194 SOC_SINGLE_TLV("Headphone Vin Volume",
195 MT6357_AUDDEC_ANA_CON7, MT6357_HP_IVBUF_DEGAIN_SFT,
196 MT6357_HP_IVBUF_DEGAIN_MAX, 1, hp_degain_tlv),
197 SOC_DOUBLE_TLV("Lineout Volume",
198 MT6357_ZCD_CON1, MT6357_AUD_LOL_GAIN_SFT,
199 MT6357_AUD_LOR_GAIN_SFT, MT6357_AUD_LO_GAIN_MAX,
200 1, playback_tlv),
201 SOC_SINGLE_TLV("Handset Volume",
202 MT6357_ZCD_CON3, MT6357_AUD_HS_GAIN_SFT,
203 MT6357_AUD_HS_GAIN_MAX, 1, playback_tlv),
204 /* ul pga gain */
205 SOC_DOUBLE_R_TLV("Mic Volume",
206 MT6357_AUDENC_ANA_CON0, MT6357_AUDENC_ANA_CON1,
207 MT6357_AUDPREAMPLGAIN_SFT, MT6357_AUDPREAMPLGAIN_MAX,
208 0, capture_tlv),
209 };
210
211 /* Uplink controls */
212
213 enum {
214 MIC_TYPE_MUX_IDLE,
215 MIC_TYPE_MUX_ACC,
216 MIC_TYPE_MUX_DMIC,
217 MIC_TYPE_MUX_DCC,
218 MIC_TYPE_MUX_DCC_ECM_DIFF,
219 MIC_TYPE_MUX_DCC_ECM_SINGLE,
220 MIC_TYPE_MUX_LPBK,
221 MIC_TYPE_MUX_SGEN,
222 };
223
224 #define IS_DCC_BASE(type) ((type) == MIC_TYPE_MUX_DCC || \
225 (type) == MIC_TYPE_MUX_DCC_ECM_DIFF || \
226 (type) == MIC_TYPE_MUX_DCC_ECM_SINGLE)
227
228 static const char * const mic_type_mux_map[] = {
229 "Idle",
230 "ACC",
231 "DMIC",
232 "DCC",
233 "DCC_ECM_DIFF",
234 "DCC_ECM_SINGLE",
235 "Loopback",
236 "Sine Generator",
237 };
238
239 static SOC_ENUM_SINGLE_DECL(mic_type_mux_map_enum, SND_SOC_NOPM,
240 0, mic_type_mux_map);
241
242 static const struct snd_kcontrol_new mic_type_mux_control =
243 SOC_DAPM_ENUM("Mic Type Select", mic_type_mux_map_enum);
244
245 static const char * const pga_mux_map[] = {
246 "None", "AIN0", "AIN1", "AIN2"
247 };
248
249 static SOC_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
250 MT6357_AUDENC_ANA_CON0,
251 MT6357_AUDPREAMPLINPUTSEL_SFT,
252 pga_mux_map);
253
254 static const struct snd_kcontrol_new pga_left_mux_control =
255 SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);
256
257 static SOC_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
258 MT6357_AUDENC_ANA_CON1,
259 MT6357_AUDPREAMPRINPUTSEL_SFT,
260 pga_mux_map);
261
262 static const struct snd_kcontrol_new pga_right_mux_control =
263 SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);
264
265 /* Downlink controls */
266 static const char * const hslo_mux_map[] = {
267 "Open", "DACR", "Playback", "Test mode"
268 };
269
270 static SOC_ENUM_SINGLE_DECL(lo_mux_map_enum,
271 MT6357_AUDDEC_ANA_CON4,
272 MT6357_AUD_LOL_MUX_INPUT_VAUDP15_SFT,
273 hslo_mux_map);
274
275 static const struct snd_kcontrol_new lo_mux_control =
276 SOC_DAPM_ENUM("Line out source", lo_mux_map_enum);
277
278 static SOC_ENUM_SINGLE_DECL(hs_mux_map_enum,
279 MT6357_AUDDEC_ANA_CON3,
280 MT6357_AUD_HS_MUX_INPUT_VAUDP15_SFT,
281 hslo_mux_map);
282
283 static const struct snd_kcontrol_new hs_mux_control =
284 SOC_DAPM_ENUM("Handset source", hs_mux_map_enum);
285
286 static const char * const hplr_mux_map[] = {
287 "Open", "Line Out", "DAC", "Handset"
288 };
289
290 static SOC_ENUM_SINGLE_DECL(hpr_mux_map_enum,
291 MT6357_AUDDEC_ANA_CON0,
292 MT6357_AUD_HPR_MUX_INPUT_VAUDP15_SFT,
293 hplr_mux_map);
294
295 static const struct snd_kcontrol_new hpr_mux_control =
296 SOC_DAPM_ENUM("Headphone Right source", hpr_mux_map_enum);
297
298 static SOC_ENUM_SINGLE_DECL(hpl_mux_map_enum,
299 MT6357_AUDDEC_ANA_CON0,
300 MT6357_AUD_HPL_MUX_INPUT_VAUDP15_SFT,
301 hplr_mux_map);
302
303 static const struct snd_kcontrol_new hpl_mux_control =
304 SOC_DAPM_ENUM("Headphone Left source", hpl_mux_map_enum);
305
306 static const char * const dac_mux_map[] = {
307 "Normal Path", "Sine Generator"
308 };
309
310 static SOC_ENUM_SINGLE_DECL(dac_mux_map_enum,
311 MT6357_AFE_TOP_CON0,
312 MT6357_DL_SINE_ON_SFT,
313 dac_mux_map);
314
315 static const struct snd_kcontrol_new dac_mux_control =
316 SOC_DAPM_ENUM("DAC Select", dac_mux_map_enum);
317
318 static int mt6357_set_dmic(struct mt6357_priv *priv, bool enable)
319 {
320 if (enable) {
321 /* DMIC enable */
322 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON7,
323 MT6357_AUDDIGMICBIAS_MASK | MT6357_AUDDIGMICEN_MASK,
324 MT6357_AUDDIGMICBIAS_DEFAULT_VALUE | MT6357_AUDDIGMICEN_ENABLE);
325 /* enable aud_pad TX fifos */
326 regmap_update_bits(priv->regmap, MT6357_AFE_AUD_PAD_TOP,
327 MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_MASK,
328 MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_ENABLE);
329 /* UL dmic setting: dual mode */
330 regmap_update_bits(priv->regmap, MT6357_AFE_UL_SRC_CON0_H,
331 MT6357_C_TWO_DIGITAL_MIC_CTL_MASK,
332 MT6357_C_TWO_DIGITAL_MIC_ENABLE);
333 /* UL turn on SDM 3 level mode */
334 regmap_update_bits(priv->regmap, MT6357_AFE_UL_SRC_CON0_L,
335 MT6357_UL_SDM_3_LEVEL_CTL_MASK,
336 MT6357_UL_SDM_3_LEVEL_SELECT);
337 /* UL turn on */
338 regmap_update_bits(priv->regmap, MT6357_AFE_UL_SRC_CON0_L,
339 MT6357_UL_SRC_ON_TMP_CTL_MASK,
340 MT6357_UL_SRC_ENABLE);
341 /* Wait to avoid any pop noises */
342 msleep(100);
343 } else {
344 /* UL turn off */
345 regmap_update_bits(priv->regmap, MT6357_AFE_UL_SRC_CON0_L,
346 MT6357_UL_SRC_ON_TMP_CTL_MASK,
347 MT6357_UL_SRC_DISABLE);
348 /* UL turn on SDM 3 level mode */
349 regmap_update_bits(priv->regmap, MT6357_AFE_UL_SRC_CON0_L,
350 MT6357_UL_SDM_3_LEVEL_CTL_MASK,
351 MT6357_UL_SDM_3_LEVEL_DESELECT);
352 /* disable aud_pad TX fifos */
353 regmap_update_bits(priv->regmap, MT6357_AFE_AUD_PAD_TOP,
354 MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_MASK,
355 MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_DISABLE);
356 /* UL dmic setting: dual mode */
357 regmap_update_bits(priv->regmap, MT6357_AFE_UL_SRC_CON0_H,
358 MT6357_C_TWO_DIGITAL_MIC_CTL_MASK,
359 MT6357_C_TWO_DIGITAL_MIC_DISABLE);
360 /* DMIC disable */
361 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON7,
362 MT6357_AUDDIGMICBIAS_MASK | MT6357_AUDDIGMICEN_MASK,
363 MT6357_AUDDIGMICBIAS_OFF | MT6357_AUDDIGMICEN_DISABLE);
364 }
365 return 0;
366 }
367
368 static int mt6357_set_amic(struct mt6357_priv *priv, bool enable, unsigned int mic_type)
369 {
370 if (enable) {
371 if (IS_DCC_BASE(mic_type)) {
372 regmap_update_bits(priv->regmap, MT6357_AFE_DCCLK_CFG0,
373 MT6357_DCCLK_DIV_MASK, MT6357_DCCLK_DIV_RUN_VALUE);
374 regmap_update_bits(priv->regmap, MT6357_AFE_DCCLK_CFG0,
375 MT6357_DCCLK_PDN_MASK, MT6357_DCCLK_OUTPUT);
376 regmap_update_bits(priv->regmap, MT6357_AFE_DCCLK_CFG0,
377 MT6357_DCCLK_GEN_ON_MASK, MT6357_DCCLK_GEN_ON);
378 regmap_update_bits(priv->regmap, MT6357_AFE_DCCLK_CFG1,
379 MT6357_DCCLK_RESYNC_BYPASS_MASK,
380 MT6357_DCCLK_RESYNC_BYPASS);
381
382 /* mic bias 0: set the correct DC couple*/
383 switch (mic_type) {
384 case MIC_TYPE_MUX_DCC_ECM_DIFF:
385 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON8,
386 MT6357_AUD_MICBIAS0_DC_MASK,
387 MT6357_AUD_MICBIAS0_DC_ENABLE_ALL);
388 break;
389 case MIC_TYPE_MUX_DCC_ECM_SINGLE:
390 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON8,
391 MT6357_AUD_MICBIAS0_DC_MASK,
392 MT6357_AUD_MICBIAS0_DC_ENABLE_P1);
393 break;
394 default:
395 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON8,
396 MT6357_AUD_MICBIAS0_DC_MASK,
397 MT6357_AUD_MICBIAS0_DC_DISABLE_ALL);
398 break;
399 }
400
401 /* mic bias 1: set the correct DC couple */
402 if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE)
403 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON9,
404 MT6357_AUD_MICBIAS1_DCSW1P_EN_MASK,
405 MT6357_AUD_MICBIAS1_DCSW1P_ENABLE);
406
407 /* Audio L/R preamplifier DCC precharge */
408 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON0,
409 MT6357_AUDPREAMPLDCPRECHARGE_MASK,
410 MT6357_AUDPREAMPLDCPRECHARGE_ENABLE);
411 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON1,
412 MT6357_AUDPREAMPRDCPRECHARGE_MASK,
413 MT6357_AUDPREAMPRDCPRECHARGE_ENABLE);
414 /* L preamplifier DCCEN */
415 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON0,
416 MT6357_AUDPREAMPLDCCEN_MASK,
417 MT6357_AUDPREAMPLDCCEN_DC);
418 /* R preamplifier DCCEN */
419 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON1,
420 MT6357_AUDPREAMPRDCCEN_MASK,
421 MT6357_AUDPREAMPRDCCEN_DC);
422 } else {
423 /* Audio L preamplifier DCC precharge disable */
424 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON0,
425 MT6357_AUDPREAMPLDCPRECHARGE_MASK,
426 MT6357_AUDPREAMPLDCPRECHARGE_DISABLE);
427 /* L preamplifier ACC */
428 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON0,
429 MT6357_AUDPREAMPLDCCEN_MASK,
430 MT6357_AUDPREAMPLDCCEN_AC);
431 /* Audio R preamplifier DCC precharge disable */
432 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON1,
433 MT6357_AUDPREAMPRDCPRECHARGE_MASK,
434 MT6357_AUDPREAMPRDCPRECHARGE_DISABLE);
435 /* R preamplifier ACC */
436 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON1,
437 MT6357_AUDPREAMPRDCCEN_MASK,
438 MT6357_AUDPREAMPRDCCEN_AC);
439 }
440 } else {
441 /* disable any Mic Bias 0 DC couple */
442 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON8,
443 MT6357_AUD_MICBIAS0_DC_MASK,
444 MT6357_AUD_MICBIAS0_DC_DISABLE_ALL);
445 /* disable any Mic Bias 1 DC couple */
446 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON9,
447 MT6357_AUD_MICBIAS1_DCSW1P_EN_MASK,
448 MT6357_AUD_MICBIAS1_DCSW1P_DISABLE);
449 if (IS_DCC_BASE(mic_type)) {
450 regmap_update_bits(priv->regmap, MT6357_AFE_DCCLK_CFG0,
451 MT6357_DCCLK_GEN_ON_MASK, MT6357_DCCLK_GEN_OFF);
452 regmap_update_bits(priv->regmap, MT6357_AFE_DCCLK_CFG0,
453 MT6357_DCCLK_PDN_MASK, MT6357_DCCLK_PDN);
454 regmap_update_bits(priv->regmap, MT6357_AFE_DCCLK_CFG0,
455 MT6357_DCCLK_DIV_MASK, MT6357_DCCLK_DIV_STOP_VALUE);
456 }
457 }
458
459 return 0;
460 }
461
462 static int mt6357_set_loopback(struct mt6357_priv *priv, bool enable)
463 {
464 if (enable) {
465 /* enable aud_pad TX fifos */
466 regmap_update_bits(priv->regmap, MT6357_AFE_AUD_PAD_TOP,
467 MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_MASK,
468 MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_ENABLE);
469 /* enable aud_pad lpk TX fifos */
470 regmap_update_bits(priv->regmap, MT6357_AFE_AUD_PAD_TOP,
471 MT6357_AUD_PAD_TX_FIFO_LPBK_MASK,
472 MT6357_AUD_PAD_TX_FIFO_LPBK_ENABLE);
473 /* Set UL Part: enable new lpbk 2 */
474 regmap_update_bits(priv->regmap, MT6357_AFE_ADDA_MTKAIF_CFG0,
475 MT6357_ADDA_MTKAIF_LPBK_CTL_MASK,
476 MT6357_ADDA_MTKAIF_LPBK_ENABLE);
477 /* UL turn on */
478 regmap_update_bits(priv->regmap, MT6357_AFE_UL_SRC_CON0_L,
479 MT6357_UL_SRC_ON_TMP_CTL_MASK,
480 MT6357_UL_SRC_ENABLE);
481 } else {
482 /* UL turn off */
483 regmap_update_bits(priv->regmap, MT6357_AFE_UL_SRC_CON0_L,
484 MT6357_UL_SRC_ON_TMP_CTL_MASK,
485 MT6357_UL_SRC_DISABLE);
486 /* disable new lpbk 2 */
487 regmap_update_bits(priv->regmap, MT6357_AFE_ADDA_MTKAIF_CFG0,
488 MT6357_ADDA_MTKAIF_LPBK_CTL_MASK,
489 MT6357_ADDA_MTKAIF_LPBK_DISABLE);
490 /* disable aud_pad lpbk TX fifos */
491 regmap_update_bits(priv->regmap, MT6357_AFE_AUD_PAD_TOP,
492 MT6357_AUD_PAD_TX_FIFO_LPBK_MASK,
493 MT6357_AUD_PAD_TX_FIFO_LPBK_DISABLE);
494 /* disable aud_pad TX fifos */
495 regmap_update_bits(priv->regmap, MT6357_AFE_AUD_PAD_TOP,
496 MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_MASK,
497 MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_DISABLE);
498 }
499
500 return 0;
501 }
502
503 static int mt6357_set_ul_sine_gen(struct mt6357_priv *priv, bool enable)
504 {
505 if (enable) {
506 /* enable aud_pad TX fifos */
507 regmap_update_bits(priv->regmap, MT6357_AFE_AUD_PAD_TOP,
508 MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_MASK,
509 MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_ENABLE);
510 /* UL turn on */
511 regmap_update_bits(priv->regmap, MT6357_AFE_UL_SRC_CON0_L,
512 MT6357_UL_SRC_ON_TMP_CTL_MASK,
513 MT6357_UL_SRC_ENABLE);
514 } else {
515 /* UL turn off */
516 regmap_update_bits(priv->regmap, MT6357_AFE_UL_SRC_CON0_L,
517 MT6357_UL_SRC_ON_TMP_CTL_MASK,
518 MT6357_UL_SRC_DISABLE);
519 /* disable aud_pad TX fifos */
520 regmap_update_bits(priv->regmap, MT6357_AFE_AUD_PAD_TOP,
521 MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_MASK,
522 MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_DISABLE);
523 }
524
525 return 0;
526 }
527
528 static int mt_aif_out_event(struct snd_soc_dapm_widget *w,
529 struct snd_kcontrol *kcontrol,
530 int event)
531 {
532 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
533 struct mt6357_priv *priv = snd_soc_component_get_drvdata(cmpnt);
534
535 switch (event) {
536 case SND_SOC_DAPM_PRE_PMU:
537 set_capture_gpio(priv, true);
538 break;
539 case SND_SOC_DAPM_POST_PMD:
540 set_capture_gpio(priv, false);
541 break;
542 default:
543 break;
544 }
545
546 return 0;
547 }
548
549 static int mt_adc_supply_event(struct snd_soc_dapm_widget *w,
550 struct snd_kcontrol *kcontrol,
551 int event)
552 {
553 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
554 struct mt6357_priv *priv = snd_soc_component_get_drvdata(cmpnt);
555
556 switch (event) {
557 case SND_SOC_DAPM_PRE_PMU:
558 /* Enable audio ADC CLKGEN */
559 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON11,
560 MT6357_RSTB_ENCODER_VA28_MASK, MT6357_RSTB_ENCODER_VA28_ENABLE);
561 /* Enable LCLDO_ENC 2P8V */
562 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON12,
563 MT6357_LCLDO_ENC_EN_VA28_MASK, MT6357_LCLDO_ENC_EN_VA28_ENABLE);
564 /* LCLDO_ENC remote sense */
565 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON12,
566 MT6357_VA28REFGEN_EN_VA28_MASK |
567 MT6357_LCLDO_ENC_REMOTE_SENSE_VA28_MASK,
568 MT6357_VA28REFGEN_EN_VA28_ENABLE |
569 MT6357_LCLDO_ENC_REMOTE_SENSE_VA28_ENABLE);
570 break;
571 case SND_SOC_DAPM_POST_PMD:
572 /* LCLDO_ENC remote sense off */
573 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON12,
574 MT6357_VA28REFGEN_EN_VA28_MASK |
575 MT6357_LCLDO_ENC_REMOTE_SENSE_VA28_MASK,
576 MT6357_VA28REFGEN_EN_VA28_DISABLE |
577 MT6357_LCLDO_ENC_REMOTE_SENSE_VA28_DISABLE);
578 /* disable LCLDO_ENC 2P8V */
579 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON12,
580 MT6357_LCLDO_ENC_EN_VA28_MASK,
581 MT6357_LCLDO_ENC_EN_VA28_DISABLE);
582 /* disable audio ADC CLKGEN */
583 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON11,
584 MT6357_RSTB_ENCODER_VA28_MASK,
585 MT6357_RSTB_ENCODER_VA28_DISABLE);
586 break;
587 default:
588 break;
589 }
590
591 return 0;
592 }
593
594 static int mt_mic_type_event(struct snd_soc_dapm_widget *w,
595 struct snd_kcontrol *kcontrol,
596 int event)
597 {
598 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
599 struct mt6357_priv *priv = snd_soc_component_get_drvdata(cmpnt);
600 unsigned int mic_type = dapm_kcontrol_get_value(w->kcontrols[0]);
601
602 switch (event) {
603 case SND_SOC_DAPM_PRE_PMU:
604 switch (mic_type) {
605 case MIC_TYPE_MUX_DMIC:
606 mt6357_set_dmic(priv, true);
607 break;
608 case MIC_TYPE_MUX_LPBK:
609 mt6357_set_loopback(priv, true);
610 break;
611 case MIC_TYPE_MUX_SGEN:
612 mt6357_set_ul_sine_gen(priv, true);
613 break;
614 default:
615 mt6357_set_amic(priv, true, mic_type);
616 break;
617 }
618 break;
619 case SND_SOC_DAPM_POST_PMD:
620 switch (mic_type) {
621 case MIC_TYPE_MUX_DMIC:
622 mt6357_set_dmic(priv, false);
623 break;
624 case MIC_TYPE_MUX_LPBK:
625 mt6357_set_loopback(priv, false);
626 break;
627 case MIC_TYPE_MUX_SGEN:
628 mt6357_set_ul_sine_gen(priv, false);
629 break;
630 default:
631 mt6357_set_amic(priv, false, mic_type);
632 break;
633 }
634 break;
635 default:
636 break;
637 }
638
639 return 0;
640 }
641
642 static int mt_pga_left_event(struct snd_soc_dapm_widget *w,
643 struct snd_kcontrol *kcontrol,
644 int event)
645 {
646 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
647 struct mt6357_priv *priv = snd_soc_component_get_drvdata(cmpnt);
648
649 switch (event) {
650 case SND_SOC_DAPM_POST_PMU:
651 /* L preamplifier enable */
652 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON0,
653 MT6357_AUDPREAMPLON_MASK,
654 MT6357_AUDPREAMPLON_ENABLE);
655 /* L ADC input sel : L PGA. Enable audio L ADC */
656 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON0,
657 MT6357_AUDADCLINPUTSEL_MASK,
658 MT6357_AUDADCLINPUTSEL_PREAMPLIFIER);
659 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON0,
660 MT6357_AUDADCLPWRUP_MASK,
661 MT6357_AUDADCLPWRUP);
662 /* Audio L preamplifier DCC precharge off */
663 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON0,
664 MT6357_AUDPREAMPLDCPRECHARGE_MASK,
665 MT6357_AUDPREAMPLDCPRECHARGE_DISABLE);
666 break;
667 case SND_SOC_DAPM_PRE_PMD:
668 /* Audio L ADC input sel : off, disable audio L ADC */
669 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON0,
670 MT6357_AUDADCLPWRUP_MASK,
671 MT6357_AUDADCLPWRDOWN);
672 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON0,
673 MT6357_AUDADCLINPUTSEL_MASK,
674 MT6357_AUDADCLINPUTSEL_IDLE);
675 /* L preamplifier ACC */
676 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON0,
677 MT6357_AUDPREAMPLDCCEN_MASK,
678 MT6357_AUDPREAMPLDCCEN_AC);
679 /* L preamplifier disable */
680 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON0,
681 MT6357_AUDPREAMPLON_MASK,
682 MT6357_AUDPREAMPLON_DISABLE);
683 /* disable Audio L preamplifier DCC precharge */
684 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON0,
685 MT6357_AUDPREAMPLDCPRECHARGE_MASK,
686 MT6357_AUDPREAMPLDCPRECHARGE_DISABLE);
687 break;
688 default:
689 break;
690 }
691
692 return 0;
693 }
694
695 static int mt_pga_right_event(struct snd_soc_dapm_widget *w,
696 struct snd_kcontrol *kcontrol,
697 int event)
698 {
699 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
700 struct mt6357_priv *priv = snd_soc_component_get_drvdata(cmpnt);
701
702 switch (event) {
703 case SND_SOC_DAPM_POST_PMU:
704 /* R preamplifier enable */
705 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON1,
706 MT6357_AUDPREAMPRON_MASK, MT6357_AUDPREAMPRON_ENABLE);
707 /* R ADC input sel : R PGA. Enable audio R ADC */
708 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON1,
709 MT6357_AUDADCRINPUTSEL_MASK,
710 MT6357_AUDADCRINPUTSEL_PREAMPLIFIER);
711 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON1,
712 MT6357_AUDADCRPWRUP_MASK, MT6357_AUDADCRPWRUP);
713 /* Audio R preamplifier DCC precharge off */
714 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON1,
715 MT6357_AUDPREAMPRDCPRECHARGE_MASK,
716 MT6357_AUDPREAMPRDCPRECHARGE_DISABLE);
717 break;
718 case SND_SOC_DAPM_PRE_PMD:
719 /* Audio R ADC input sel : off, disable audio R ADC */
720 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON1,
721 MT6357_AUDADCRPWRUP_MASK, MT6357_AUDADCRPWRDOWN);
722 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON0,
723 MT6357_AUDADCRINPUTSEL_MASK, MT6357_AUDADCRINPUTSEL_IDLE);
724 /* R preamplifier ACC */
725 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON1,
726 MT6357_AUDPREAMPRDCCEN_MASK, MT6357_AUDPREAMPRDCCEN_AC);
727 /* R preamplifier disable */
728 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON1,
729 MT6357_AUDPREAMPRON_MASK, MT6357_AUDPREAMPRON_DISABLE);
730 /* disable Audio R preamplifier DCC precharge */
731 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON1,
732 MT6357_AUDPREAMPRDCPRECHARGE_MASK,
733 MT6357_AUDPREAMPRDCPRECHARGE_DISABLE);
734 break;
735 default:
736 break;
737 }
738
739 return 0;
740 }
741
742 static int adc_enable_event(struct snd_soc_dapm_widget *w,
743 struct snd_kcontrol *kcontrol,
744 int event)
745 {
746 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
747 struct mt6357_priv *priv = snd_soc_component_get_drvdata(cmpnt);
748 int lgain, rgain;
749
750 switch (event) {
751 case SND_SOC_DAPM_PRE_PMU:
752 regmap_read(priv->regmap, MT6357_AUDENC_ANA_CON0, &lgain);
753 regmap_read(priv->regmap, MT6357_AUDENC_ANA_CON1, &rgain);
754 /* L PGA 0 dB gain */
755 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON0,
756 MT6357_AUDPREAMPLGAIN_MASK,
757 UL_GAIN_0DB << MT6357_AUDPREAMPLGAIN_SFT);
758 /* R PGA 0 dB gain */
759 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON1,
760 MT6357_AUDPREAMPRGAIN_MASK,
761 UL_GAIN_0DB << MT6357_AUDPREAMPRGAIN_SFT);
762 /* enable aud_pad TX fifos */
763 regmap_update_bits(priv->regmap, MT6357_AFE_AUD_PAD_TOP,
764 MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_MASK,
765 MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_ENABLE);
766 /* UL turn on */
767 regmap_update_bits(priv->regmap, MT6357_AFE_UL_SRC_CON0_L,
768 MT6357_UL_SRC_ON_TMP_CTL_MASK, MT6357_UL_SRC_ENABLE);
769 /* Wait to avoid any pop noises */
770 msleep(100);
771 /* set the mic gains to the stored values */
772 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON0,
773 MT6357_AUDPREAMPLGAIN_MASK, lgain);
774 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON1,
775 MT6357_AUDPREAMPRGAIN_MASK, rgain);
776 break;
777 case SND_SOC_DAPM_POST_PMD:
778 /* UL turn off */
779 regmap_update_bits(priv->regmap, MT6357_AFE_UL_SRC_CON0_L,
780 MT6357_UL_SRC_ON_TMP_CTL_MASK, MT6357_UL_SRC_DISABLE);
781 /* disable aud_pad TX fifos */
782 regmap_update_bits(priv->regmap, MT6357_AFE_AUD_PAD_TOP,
783 MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_MASK,
784 MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_DISABLE);
785 break;
786 default:
787 break;
788 }
789
790 return 0;
791 }
792
793 static void configure_downlinks(struct mt6357_priv *priv, bool enable)
794 {
795 if (enable) {
796 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ELR_0,
797 MT6357_AUD_HP_TRIM_EN_VAUDP15_MASK,
798 MT6357_AUD_HP_TRIM_EN_VAUDP15_ENABLE);
799 /* Disable headphone short-circuit protection */
800 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON0,
801 MT6357_AUD_HPR_SC_VAUDP15_MASK | MT6357_AUD_HPL_SC_VAUDP15_MASK,
802 MT6357_AUD_HPR_SC_VAUDP15_DISABLE |
803 MT6357_AUD_HPL_SC_VAUDP15_DISABLE);
804 /* Disable handset short-circuit protection */
805 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON3,
806 MT6357_AUD_HS_SC_VAUDP15_MASK,
807 MT6357_AUD_HS_SC_VAUDP15_DISABLE);
808 /* Disable lineout short-circuit protection */
809 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON4,
810 MT6357_AUD_LOL_SC_VAUDP15_MASK,
811 MT6357_AUD_LOL_SC_VAUDP15_DISABLE);
812 /* Reduce ESD resistance of AU_REFN */
813 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON2,
814 MT6357_AUD_REFN_DERES_VAUDP15_MASK,
815 MT6357_AUD_REFN_DERES_VAUDP15_ENABLE);
816 /* Turn on DA_600K_NCP_VA18 */
817 regmap_write(priv->regmap, MT6357_AUDNCP_CLKDIV_CON1, MT6357_DIVCKS_ON);
818 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
819 regmap_write(priv->regmap, MT6357_AUDNCP_CLKDIV_CON2, 0x002c);
820 /* Toggle DIVCKS_CHG */
821 regmap_write(priv->regmap, MT6357_AUDNCP_CLKDIV_CON0, MT6357_DIVCKS_CHG);
822 /* Set NCP soft start mode as default mode: 150us */
823 regmap_write(priv->regmap, MT6357_AUDNCP_CLKDIV_CON4,
824 MT6357_DIVCKS_PWD_NCP_ST_150US);
825 /* Enable NCP */
826 regmap_write(priv->regmap, MT6357_AUDNCP_CLKDIV_CON3,
827 MT6357_DIVCKS_PWD_NCP_ENABLE);
828 usleep_range(250, 270);
829 /* Enable cap-less LDOs (1.5V) */
830 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON12,
831 MT6357_VA33REFGEN_EN_VA18_MASK |
832 MT6357_LCLDO_REMOTE_SENSE_VA18_MASK |
833 MT6357_LCLDO_EN_VA18_MASK |
834 MT6357_HCLDO_REMOTE_SENSE_VA18_MASK |
835 MT6357_HCLDO_EN_VA18_MASK,
836 MT6357_VA33REFGEN_EN_VA18_ENABLE |
837 MT6357_LCLDO_REMOTE_SENSE_VA18_ENABLE |
838 MT6357_LCLDO_EN_VA18_ENABLE |
839 MT6357_HCLDO_REMOTE_SENSE_VA18_ENABLE |
840 MT6357_HCLDO_EN_VA18_ENABLE);
841 /* Enable NV regulator (-1.2V) */
842 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON13,
843 MT6357_NVREG_EN_VAUDP15_MASK, MT6357_NVREG_EN_VAUDP15_ENABLE);
844 usleep_range(100, 120);
845 /* Enable IBIST */
846 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON10,
847 MT6357_AUD_IBIAS_PWRDN_VAUDP15_MASK,
848 MT6357_AUD_IBIAS_PWRDN_VAUDP15_ENABLE);
849 /* Enable AUD_CLK */
850 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON11,
851 MT6357_RSTB_DECODER_VA28_MASK,
852 MT6357_RSTB_DECODER_VA28_ENABLE);
853 /* Enable low-noise mode of DAC */
854 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON6,
855 MT6357_DAC_LOW_NOISE_MODE_MASK,
856 MT6357_DAC_LOW_NOISE_MODE_ENABLE);
857 usleep_range(100, 120);
858 } else {
859 /* Disable low-noise mode of DAC */
860 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON6,
861 MT6357_DAC_LOW_NOISE_MODE_MASK,
862 MT6357_DAC_LOW_NOISE_MODE_DISABLE);
863 /* Disable AUD_CLK */
864 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON11,
865 MT6357_RSTB_DECODER_VA28_MASK,
866 MT6357_RSTB_DECODER_VA28_DISABLE);
867 /* Enable linout short-circuit protection */
868 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON4,
869 MT6357_AUD_LOL_SC_VAUDP15_MASK,
870 MT6357_AUD_LOL_SC_VAUDP15_ENABLE);
871 /* Enable handset short-circuit protection */
872 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON3,
873 MT6357_AUD_HS_SC_VAUDP15_MASK,
874 MT6357_AUD_HS_SC_VAUDP15_ENABLE);
875 /* Enable headphone short-circuit protection */
876 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON0,
877 MT6357_AUD_HPR_SC_VAUDP15_MASK |
878 MT6357_AUD_HPL_SC_VAUDP15_MASK,
879 MT6357_AUD_HPR_SC_VAUDP15_ENABLE |
880 MT6357_AUD_HPL_SC_VAUDP15_ENABLE);
881 /* Disable IBIST */
882 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON10,
883 MT6357_AUD_IBIAS_PWRDN_VAUDP15_MASK,
884 MT6357_AUD_IBIAS_PWRDN_VAUDP15_DISABLE);
885 /* Disable NV regulator (-1.2V) */
886 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON13,
887 MT6357_NVREG_EN_VAUDP15_MASK,
888 MT6357_NVREG_EN_VAUDP15_DISABLE);
889 /* Disable cap-less LDOs (1.5V) */
890 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON12,
891 MT6357_VA33REFGEN_EN_VA18_MASK |
892 MT6357_LCLDO_REMOTE_SENSE_VA18_MASK |
893 MT6357_LCLDO_EN_VA18_MASK |
894 MT6357_HCLDO_REMOTE_SENSE_VA18_MASK |
895 MT6357_HCLDO_EN_VA18_MASK,
896 MT6357_VA33REFGEN_EN_VA18_DISABLE |
897 MT6357_LCLDO_REMOTE_SENSE_VA18_DISABLE |
898 MT6357_LCLDO_EN_VA18_DISABLE |
899 MT6357_HCLDO_REMOTE_SENSE_VA18_DISABLE |
900 MT6357_HCLDO_EN_VA18_DISABLE);
901 /* Disable NCP */
902 regmap_update_bits(priv->regmap, MT6357_AUDNCP_CLKDIV_CON3,
903 MT6357_DIVCKS_PWD_NCP_MASK, MT6357_DIVCKS_PWD_NCP_DISABLE);
904 }
905 }
906
907 static int mt_audio_in_event(struct snd_soc_dapm_widget *w,
908 struct snd_kcontrol *kcontrol,
909 int event)
910 {
911 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
912 struct mt6357_priv *priv = snd_soc_component_get_drvdata(cmpnt);
913
914 switch (event) {
915 case SND_SOC_DAPM_PRE_PMU:
916 set_playback_gpio(priv, true);
917
918 /* Pull-down HPL/R to AVSS28_AUD */
919 if (priv->pull_down_needed)
920 hp_pull_down(priv, true);
921
922 /* Disable HP main CMFB Switch */
923 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON6,
924 MT6357_HPRL_MAIN_CMFB_LOOP_MASK,
925 MT6357_HPRL_MAIN_CMFB_LOOP_DISABLE);
926 /* Audio system digital clock power down release */
927 regmap_write(priv->regmap, MT6357_AFUNC_AUD_CON2,
928 MT6357_CCI_AUDIO_FIFO_DISABLE |
929 MT6357_CCI_ACD_MODE_NORMAL_PATH |
930 MT6357_CCI_AFIFO_CLK_PWDB_ON |
931 MT6357_CCI_ACD_FUNC_RSTB_RESET);
932 /* sdm audio fifo clock power on */
933 regmap_write(priv->regmap, MT6357_AFUNC_AUD_CON0,
934 MT6357_CCI_AUD_ANACK_INVERT |
935 (4 << MT6357_CCI_AUDIO_FIFO_WPTR_SFT) |
936 MT6357_CCI_SCRAMBLER_CG_ENABLE |
937 MT6357_CCI_RAND_ENABLE |
938 MT6357_CCI_SPLT_SCRMB_CLK_ON |
939 MT6357_CCI_SPLT_SCRMB_ON |
940 MT6357_CCI_ZERO_PADDING_DISABLE |
941 MT6357_CCI_SCRAMBLER_ENABLE);
942 /* scrambler clock on enable */
943 regmap_write(priv->regmap, MT6357_AFUNC_AUD_CON2,
944 MT6357_CCI_AUDIO_FIFO_DISABLE |
945 MT6357_CCI_ACD_MODE_TEST_PATH |
946 MT6357_CCI_AFIFO_CLK_PWDB_ON |
947 MT6357_CCI_ACD_FUNC_RSTB_RELEASE);
948 /* sdm power on */
949 regmap_write(priv->regmap, MT6357_AFUNC_AUD_CON2,
950 MT6357_CCI_AUDIO_FIFO_ENABLE |
951 MT6357_CCI_ACD_MODE_TEST_PATH |
952 MT6357_CCI_AFIFO_CLK_PWDB_ON |
953 MT6357_CCI_ACD_FUNC_RSTB_RELEASE);
954
955 configure_downlinks(priv, true);
956 break;
957 case SND_SOC_DAPM_POST_PMD:
958 configure_downlinks(priv, false);
959 /* DL scrambler disabling sequence */
960 regmap_write(priv->regmap, MT6357_AFUNC_AUD_CON2,
961 MT6357_CCI_AUDIO_FIFO_DISABLE |
962 MT6357_CCI_ACD_MODE_TEST_PATH |
963 MT6357_CCI_AFIFO_CLK_PWDB_DOWN |
964 MT6357_CCI_ACD_FUNC_RSTB_RESET);
965 regmap_write(priv->regmap, MT6357_AFUNC_AUD_CON0,
966 MT6357_CCI_AUD_ANACK_INVERT |
967 (4 << MT6357_CCI_AUDIO_FIFO_WPTR_SFT) |
968 MT6357_CCI_SCRAMBLER_CG_ENABLE |
969 MT6357_CCI_RAND_ENABLE |
970 MT6357_CCI_SPLT_SCRMB_CLK_ON |
971 MT6357_CCI_SPLT_SCRMB_ON |
972 MT6357_CCI_ZERO_PADDING_DISABLE |
973 MT6357_CCI_SCRAMBLER_DISABLE);
974
975 set_playback_gpio(priv, false);
976
977 /* disable Pull-down HPL/R to AVSS28_AUD */
978 if (priv->pull_down_needed)
979 hp_pull_down(priv, false);
980 break;
981 default:
982 break;
983 }
984
985 return 0;
986 }
987
988 static int mt_delay_250_event(struct snd_soc_dapm_widget *w,
989 struct snd_kcontrol *kcontrol,
990 int event)
991 {
992 switch (event) {
993 case SND_SOC_DAPM_POST_PMU:
994 usleep_range(250, 270);
995 break;
996 case SND_SOC_DAPM_PRE_PMD:
997 usleep_range(250, 270);
998 break;
999 default:
1000 break;
1001 }
1002
1003 return 0;
1004 }
1005
1006 static int lo_mux_event(struct snd_soc_dapm_widget *w,
1007 struct snd_kcontrol *kcontrol,
1008 int event)
1009 {
1010 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1011 struct mt6357_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1012 int lgain, rgain;
1013
1014 /* Get current gain value */
1015 regmap_read(priv->regmap, MT6357_ZCD_CON1, &lgain);
1016 rgain = (lgain & MT6357_AUD_LOR_GAIN_MASK) >> MT6357_AUD_LOR_GAIN_SFT;
1017 lgain = lgain & MT6357_AUD_LOL_GAIN_MASK;
1018 switch (event) {
1019 case SND_SOC_DAPM_POST_PMU:
1020 /* Set -40dB before enable HS to avoid POP noise */
1021 regmap_update_bits(priv->regmap, MT6357_ZCD_CON1,
1022 MT6357_AUD_LOL_GAIN_MASK |
1023 MT6357_AUD_LOR_GAIN_MASK,
1024 MT6357_DL_GAIN_N_40DB_REG);
1025 /* Set LO STB enhance circuits */
1026 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON4,
1027 MT6357_AUD_LOLOUT_STB_ENH_VAUDP15_MASK,
1028 MT6357_AUD_LOLOUT_STB_ENH_VAUDP15_ENABLE);
1029 /* Enable LO driver bias circuits */
1030 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON4,
1031 MT6357_AUD_LOL_PWRUP_BIAS_VAUDP15_MASK,
1032 MT6357_AUD_LOL_PWRUP_BIAS_VAUDP15_ENABLE);
1033 /* Enable LO driver core circuits */
1034 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON4,
1035 MT6357_AUD_LOL_PWRUP_VAUDP15_MASK,
1036 MT6357_AUD_LOL_PWRUP_VAUDP15_ENABLE);
1037 /* Set LOL gain to normal gain step by step */
1038 lo_volume_ramp(priv, DL_GAIN_N_40DB, lgain,
1039 DL_GAIN_N_40DB, rgain);
1040 break;
1041 case SND_SOC_DAPM_PRE_PMD:
1042 /* decrease LOL gain to minimum gain step by step */
1043
1044 lo_volume_ramp(priv, lgain, DL_GAIN_N_40DB,
1045 rgain, DL_GAIN_N_40DB);
1046 /* Disable LO driver core circuits */
1047 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON4,
1048 MT6357_AUD_LOL_PWRUP_VAUDP15_MASK,
1049 MT6357_AUD_LOL_PWRUP_VAUDP15_DISABLE);
1050 /* Disable LO driver bias circuits */
1051 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON4,
1052 MT6357_AUD_LOL_PWRUP_BIAS_VAUDP15_MASK,
1053 MT6357_AUD_LOL_PWRUP_BIAS_VAUDP15_DISABLE);
1054 /* Clear LO STB enhance circuits */
1055 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON4,
1056 MT6357_AUD_LOLOUT_STB_ENH_VAUDP15_MASK,
1057 MT6357_AUD_LOLOUT_STB_ENH_VAUDP15_DISABLE);
1058 /* Save the gain value into the register*/
1059 regmap_update_bits(priv->regmap, MT6357_ZCD_CON1,
1060 MT6357_AUD_LOL_GAIN_MASK |
1061 MT6357_AUD_LOR_GAIN_MASK,
1062 lgain << MT6357_AUD_LOL_GAIN_SFT |
1063 rgain << MT6357_AUD_LOR_GAIN_SFT);
1064
1065 break;
1066 default:
1067 break;
1068 }
1069
1070 return 0;
1071 }
1072
1073 static int hs_mux_event(struct snd_soc_dapm_widget *w,
1074 struct snd_kcontrol *kcontrol,
1075 int event)
1076 {
1077 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1078 struct mt6357_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1079 int gain; /* HS register has only one gain slot */
1080
1081 /* Get current gain value */
1082 regmap_read(priv->regmap, MT6357_ZCD_CON3, &gain);
1083 switch (event) {
1084 case SND_SOC_DAPM_POST_PMU:
1085 /* Set -40dB before enable HS to avoid POP noise */
1086 regmap_update_bits(priv->regmap, MT6357_ZCD_CON3,
1087 MT6357_AUD_HS_GAIN_MASK,
1088 DL_GAIN_N_40DB);
1089
1090 /* Set HS STB enhance circuits */
1091 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON3,
1092 MT6357_AUD_HSOUT_STB_ENH_VAUDP15_MASK,
1093 MT6357_AUD_HSOUT_STB_ENH_VAUDP15_ENABLE);
1094 /* Enable HS driver bias circuits */
1095 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON3,
1096 MT6357_AUD_HS_PWRUP_BIAS_VAUDP15_MASK,
1097 MT6357_AUD_HS_PWRUP_BIAS_VAUDP15_ENABLE);
1098 /* Enable HS driver core circuits */
1099 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON3,
1100 MT6357_AUD_HS_PWRUP_VAUDP15_MASK,
1101 MT6357_AUD_HS_PWRUP_VAUDP15_ENABLE);
1102 /* Set HS gain to normal gain step by step */
1103 hs_volume_ramp(priv, DL_GAIN_N_40DB, gain);
1104 break;
1105 case SND_SOC_DAPM_PRE_PMD:
1106 /* decrease HS gain to minimum gain step by step */
1107 hs_volume_ramp(priv, gain, DL_GAIN_N_40DB);
1108 /* Disable HS driver core circuits */
1109 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON3,
1110 MT6357_AUD_HS_PWRUP_VAUDP15_MASK,
1111 MT6357_AUD_HS_PWRUP_VAUDP15_DISABLE);
1112 /* Disable HS driver bias circuits */
1113 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON3,
1114 MT6357_AUD_HS_PWRUP_BIAS_VAUDP15_MASK,
1115 MT6357_AUD_HS_PWRUP_BIAS_VAUDP15_ENABLE);
1116 /* Clear HS STB enhance circuits */
1117 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON3,
1118 MT6357_AUD_HSOUT_STB_ENH_VAUDP15_MASK,
1119 MT6357_AUD_HSOUT_STB_ENH_VAUDP15_DISABLE);
1120 /* Save the gain value into the register*/
1121 regmap_update_bits(priv->regmap, MT6357_ZCD_CON3,
1122 MT6357_AUD_HS_GAIN_MASK, gain);
1123 break;
1124 default:
1125 break;
1126 }
1127
1128 return 0;
1129 }
1130
1131 static int hp_main_mux_event(struct snd_soc_dapm_widget *w,
1132 struct snd_kcontrol *kcontrol,
1133 int event)
1134 {
1135 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1136 struct mt6357_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1137 int lgain, rgain;
1138
1139 /* Get current gain value */
1140 regmap_read(priv->regmap, MT6357_ZCD_CON2, &lgain);
1141 rgain = (lgain & MT6357_AUD_HPR_GAIN_MASK) >> MT6357_AUD_HPR_GAIN_SFT;
1142 lgain = lgain & MT6357_AUD_HPL_GAIN_MASK;
1143 switch (event) {
1144 case SND_SOC_DAPM_POST_PMU:
1145 priv->hp_channel_number++;
1146 if (priv->hp_channel_number > 1)
1147 break;
1148 /* Set -40dB before enable HS to avoid POP noise */
1149 regmap_update_bits(priv->regmap, MT6357_ZCD_CON2,
1150 MT6357_AUD_HPL_GAIN_MASK |
1151 MT6357_AUD_HPR_GAIN_MASK,
1152 MT6357_DL_GAIN_N_40DB_REG);
1153 /* Set HPP/N STB enhance circuits */
1154 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON2,
1155 MT6357_HPROUT_STB_ENH_VAUDP15_MASK |
1156 MT6357_HPLOUT_STB_ENH_VAUDP15_MASK,
1157 MT6357_HPROUT_STB_ENH_VAUDP15_N470_P250 |
1158 MT6357_HPLOUT_STB_ENH_VAUDP15_N470_P250);
1159 /* Enable HP aux output stage */
1160 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON1,
1161 MT6357_HPROUT_AUX_PWRUP_VAUDP15_MASK |
1162 MT6357_HPLOUT_AUX_PWRUP_VAUDP15_MASK,
1163 MT6357_HPROUT_AUX_PWRUP_VAUDP15_ENABLE |
1164 MT6357_HPLOUT_AUX_PWRUP_VAUDP15_ENABLE);
1165 /* Enable HP aux feedback loop */
1166 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON1,
1167 MT6357_HPR_AUX_FBRSW_VAUDP15_MASK |
1168 MT6357_HPL_AUX_FBRSW_VAUDP15_MASK,
1169 MT6357_HPR_AUX_FBRSW_VAUDP15_ENABLE |
1170 MT6357_HPL_AUX_FBRSW_VAUDP15_ENABLE);
1171 /* Enable HP aux CMFB loop */
1172 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON6,
1173 MT6357_HP_CMFB_RST_MASK |
1174 MT6357_HPL_AUX_CMFB_LOOP_MASK |
1175 MT6357_HPR_AUX_CMFB_LOOP_MASK,
1176 MT6357_HP_CMFB_RST_NORMAL |
1177 MT6357_HPL_AUX_CMFB_LOOP_ENABLE |
1178 MT6357_HPR_AUX_CMFB_LOOP_ENABLE);
1179 /* Enable HP driver bias circuits */
1180 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON0,
1181 MT6357_AUD_HPR_BIAS_VAUDP15_MASK |
1182 MT6357_AUD_HPL_BIAS_VAUDP15_MASK,
1183 MT6357_AUD_HPR_BIAS_VAUDP15_ENABLE |
1184 MT6357_AUD_HPL_BIAS_VAUDP15_ENABLE);
1185 /* Enable HP driver core circuits */
1186 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON0,
1187 MT6357_AUD_HPR_PWRUP_VAUDP15_MASK |
1188 MT6357_AUD_HPL_PWRUP_VAUDP15_MASK,
1189 MT6357_AUD_HPR_PWRUP_VAUDP15_ENABLE |
1190 MT6357_AUD_HPL_PWRUP_VAUDP15_ENABLE);
1191 /* Short HP main output to HP aux output stage */
1192 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON1,
1193 MT6357_HPR_SHORT2HPR_AUX_VAUDP15_MASK |
1194 MT6357_HPL_SHORT2HPR_AUX_VAUDP15_MASK,
1195 MT6357_HPR_SHORT2HPR_AUX_VAUDP15_ENABLE |
1196 MT6357_HPL_SHORT2HPR_AUX_VAUDP15_ENABLE);
1197 /* Enable HP main CMFB loop */
1198 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON6,
1199 MT6357_HPRL_MAIN_CMFB_LOOP_MASK,
1200 MT6357_HPRL_MAIN_CMFB_LOOP_ENABLE);
1201 /* Disable HP aux CMFB loop */
1202 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON6,
1203 MT6357_HPR_AUX_CMFB_LOOP_MASK |
1204 MT6357_HPL_AUX_CMFB_LOOP_MASK,
1205 MT6357_HPR_AUX_CMFB_LOOP_DISABLE |
1206 MT6357_HPL_AUX_CMFB_LOOP_DISABLE);
1207 /* Enable HP main output stage */
1208 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON1,
1209 MT6357_HPROUT_PWRUP_VAUDP15_MASK |
1210 MT6357_HPLOUT_PWRUP_VAUDP15_MASK,
1211 MT6357_HPROUT_PWRUP_VAUDP15_ENABLE |
1212 MT6357_HPLOUT_PWRUP_VAUDP15_ENABLE);
1213 /* Enable HPR/L main output stage step by step */
1214 hp_main_output_ramp(priv, true);
1215 usleep_range(1000, 1200);
1216 /* Reduce HP aux feedback loop gain */
1217 hp_aux_feedback_loop_gain_ramp(priv, true);
1218 /* Disable HP aux feedback loop */
1219 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON1,
1220 MT6357_HPR_AUX_FBRSW_VAUDP15_MASK |
1221 MT6357_HPL_AUX_FBRSW_VAUDP15_MASK,
1222 MT6357_HPR_AUX_FBRSW_VAUDP15_DISABLE |
1223 MT6357_HPL_AUX_FBRSW_VAUDP15_DISABLE);
1224 /* apply volume setting */
1225 hp_volume_ramp(priv, DL_GAIN_N_40DB, lgain,
1226 DL_GAIN_N_40DB, rgain);
1227 /* Disable HP aux output stage */
1228 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON1,
1229 MT6357_HPROUT_AUX_PWRUP_VAUDP15_MASK |
1230 MT6357_HPLOUT_AUX_PWRUP_VAUDP15_MASK,
1231 MT6357_HPROUT_AUX_PWRUP_VAUDP15_DISABLE |
1232 MT6357_HPLOUT_AUX_PWRUP_VAUDP15_DISABLE);
1233 /* Unshort HP main output to HP aux output stage */
1234 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON1,
1235 MT6357_HPR_SHORT2HPR_AUX_VAUDP15_MASK |
1236 MT6357_HPL_SHORT2HPR_AUX_VAUDP15_MASK,
1237 MT6357_HPR_SHORT2HPR_AUX_VAUDP15_DISABLE |
1238 MT6357_HPL_SHORT2HPR_AUX_VAUDP15_DISABLE);
1239 usleep_range(100, 120);
1240 break;
1241 case SND_SOC_DAPM_PRE_PMD:
1242 priv->hp_channel_number--;
1243 if (priv->hp_channel_number > 0)
1244 break;
1245 /* Short HP main output to HP aux output stage */
1246 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON1,
1247 MT6357_HPR_SHORT2HPR_AUX_VAUDP15_MASK |
1248 MT6357_HPL_SHORT2HPR_AUX_VAUDP15_MASK,
1249 MT6357_HPR_SHORT2HPR_AUX_VAUDP15_ENABLE |
1250 MT6357_HPL_SHORT2HPR_AUX_VAUDP15_ENABLE);
1251 /* Enable HP aux output stage */
1252 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON1,
1253 MT6357_HPROUT_AUX_PWRUP_VAUDP15_MASK |
1254 MT6357_HPLOUT_AUX_PWRUP_VAUDP15_MASK,
1255 MT6357_HPROUT_AUX_PWRUP_VAUDP15_ENABLE |
1256 MT6357_HPLOUT_AUX_PWRUP_VAUDP15_ENABLE);
1257 /* decrease HPL/R gain to normal gain step by step */
1258 hp_volume_ramp(priv, lgain, DL_GAIN_N_40DB,
1259 rgain, DL_GAIN_N_40DB);
1260 /* Enable HP aux feedback loop */
1261 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON1,
1262 MT6357_HPR_AUX_FBRSW_VAUDP15_MASK |
1263 MT6357_HPL_AUX_FBRSW_VAUDP15_MASK,
1264 MT6357_HPR_AUX_FBRSW_VAUDP15_ENABLE |
1265 MT6357_HPL_AUX_FBRSW_VAUDP15_ENABLE);
1266 /* Reduce HP aux feedback loop gain */
1267 hp_aux_feedback_loop_gain_ramp(priv, false);
1268 /* decrease HPR/L main output stage step by step */
1269 hp_main_output_ramp(priv, false);
1270 /* Disable HP main output stage */
1271 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON1,
1272 MT6357_HPROUT_PWRUP_VAUDP15_MASK |
1273 MT6357_HPLOUT_PWRUP_VAUDP15_MASK,
1274 MT6357_HPROUT_PWRUP_VAUDP15_DISABLE |
1275 MT6357_HPLOUT_PWRUP_VAUDP15_DISABLE);
1276 /* Enable HP aux CMFB loop */
1277 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON6,
1278 MT6357_HP_CMFB_RST_MASK |
1279 MT6357_HPL_AUX_CMFB_LOOP_MASK |
1280 MT6357_HPR_AUX_CMFB_LOOP_MASK,
1281 MT6357_HP_CMFB_RST_RESET |
1282 MT6357_HPL_AUX_CMFB_LOOP_ENABLE |
1283 MT6357_HPR_AUX_CMFB_LOOP_ENABLE);
1284 /* Disable HP main CMFB loop */
1285 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON6,
1286 MT6357_HPRL_MAIN_CMFB_LOOP_MASK,
1287 MT6357_HPRL_MAIN_CMFB_LOOP_DISABLE);
1288 /* Unshort HP main output to HP aux output stage */
1289 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON1,
1290 MT6357_HPR_SHORT2HPR_AUX_VAUDP15_MASK |
1291 MT6357_HPL_SHORT2HPR_AUX_VAUDP15_MASK,
1292 MT6357_HPR_SHORT2HPR_AUX_VAUDP15_DISABLE |
1293 MT6357_HPL_SHORT2HPR_AUX_VAUDP15_DISABLE);
1294 /* Disable HP driver core circuits */
1295 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON0,
1296 MT6357_AUD_HPR_PWRUP_VAUDP15_MASK |
1297 MT6357_AUD_HPL_PWRUP_VAUDP15_MASK,
1298 MT6357_AUD_HPR_PWRUP_VAUDP15_DISABLE |
1299 MT6357_AUD_HPL_PWRUP_VAUDP15_DISABLE);
1300 /* Disable HP driver bias circuits */
1301 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON0,
1302 MT6357_AUD_HPR_BIAS_VAUDP15_MASK |
1303 MT6357_AUD_HPL_BIAS_VAUDP15_MASK,
1304 MT6357_AUD_HPR_BIAS_VAUDP15_DISABLE |
1305 MT6357_AUD_HPL_BIAS_VAUDP15_DISABLE);
1306 /* Disable HP aux CMFB loop,
1307 * Enable HP main CMFB for HP off state
1308 */
1309 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON6,
1310 MT6357_HPRL_MAIN_CMFB_LOOP_MASK |
1311 MT6357_HPR_AUX_CMFB_LOOP_MASK |
1312 MT6357_HPL_AUX_CMFB_LOOP_MASK,
1313 MT6357_HPRL_MAIN_CMFB_LOOP_ENABLE |
1314 MT6357_HPR_AUX_CMFB_LOOP_DISABLE |
1315 MT6357_HPL_AUX_CMFB_LOOP_DISABLE);
1316 /* Disable HP aux feedback loop */
1317 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON1,
1318 MT6357_HPR_AUX_FBRSW_VAUDP15_MASK |
1319 MT6357_HPL_AUX_FBRSW_VAUDP15_MASK,
1320 MT6357_HPR_AUX_FBRSW_VAUDP15_DISABLE |
1321 MT6357_HPL_AUX_FBRSW_VAUDP15_DISABLE);
1322 /* Disable HP aux output stage */
1323 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON1,
1324 MT6357_HPROUT_AUX_PWRUP_VAUDP15_MASK |
1325 MT6357_HPLOUT_AUX_PWRUP_VAUDP15_MASK,
1326 MT6357_HPROUT_AUX_PWRUP_VAUDP15_DISABLE |
1327 MT6357_HPLOUT_AUX_PWRUP_VAUDP15_DISABLE);
1328 /* Save the gain value into the register*/
1329 regmap_update_bits(priv->regmap, MT6357_ZCD_CON2,
1330 MT6357_AUD_HPL_GAIN_MASK |
1331 MT6357_AUD_HPR_GAIN_MASK,
1332 lgain << MT6357_AUD_HPL_GAIN_SFT |
1333 rgain << MT6357_AUD_HPR_GAIN_SFT);
1334 break;
1335 default:
1336 break;
1337 }
1338
1339 return 0;
1340 }
1341
1342 static int right_dac_event(struct snd_soc_dapm_widget *w,
1343 struct snd_kcontrol *kcontrol,
1344 int event)
1345 {
1346 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1347 struct mt6357_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1348
1349 switch (event) {
1350 case SND_SOC_DAPM_PRE_PMU:
1351 /* Enable Audio DAC and control audio bias gen */
1352 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON0,
1353 MT6357_AUD_DACR_PWRUP_VA28_MASK |
1354 MT6357_AUD_DACR_PWRUP_VAUDP15_MASK,
1355 MT6357_AUD_DACR_PWRUP_VA28_ENABLE |
1356 MT6357_AUD_DACR_PWRUP_VAUDP15_ENABLE);
1357 break;
1358 case SND_SOC_DAPM_POST_PMU:
1359 /* disable Pull-down HPL/R to AVSS28_AUD */
1360 if (priv->pull_down_needed)
1361 hp_pull_down(priv, false);
1362 break;
1363 case SND_SOC_DAPM_PRE_PMD:
1364 /* Pull-down HPL/R to AVSS28_AUD */
1365 if (priv->pull_down_needed)
1366 hp_pull_down(priv, true);
1367 /* Disable Audio DAC and control audio bias gen */
1368 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON0,
1369 MT6357_AUD_DACR_PWRUP_VA28_MASK |
1370 MT6357_AUD_DACR_PWRUP_VAUDP15_MASK,
1371 MT6357_AUD_DACR_PWRUP_VA28_DISABLE |
1372 MT6357_AUD_DACR_PWRUP_VAUDP15_DISABLE);
1373 break;
1374 default:
1375 break;
1376 }
1377
1378 return 0;
1379 }
1380
1381 static int left_dac_event(struct snd_soc_dapm_widget *w,
1382 struct snd_kcontrol *kcontrol,
1383 int event)
1384 {
1385 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1386 struct mt6357_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1387
1388 switch (event) {
1389 case SND_SOC_DAPM_PRE_PMU:
1390 /* Enable Audio DAC and control audio bias gen */
1391 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON0,
1392 MT6357_AUD_DACL_PWRUP_VA28_MASK |
1393 MT6357_AUD_DACL_PWRUP_VAUDP15_MASK,
1394 MT6357_AUD_DACL_PWRUP_VA28_ENABLE |
1395 MT6357_AUD_DACL_PWRUP_VAUDP15_ENABLE);
1396 break;
1397 case SND_SOC_DAPM_POST_PMU:
1398 /* disable Pull-down HPL/R to AVSS28_AUD */
1399 if (priv->pull_down_needed)
1400 hp_pull_down(priv, false);
1401 break;
1402 case SND_SOC_DAPM_PRE_PMD:
1403 /* Pull-down HPL/R to AVSS28_AUD */
1404 if (priv->pull_down_needed)
1405 hp_pull_down(priv, true);
1406 /* Disable Audio DAC and control audio bias gen */
1407 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON0,
1408 MT6357_AUD_DACL_PWRUP_VA28_MASK |
1409 MT6357_AUD_DACL_PWRUP_VAUDP15_MASK,
1410 MT6357_AUD_DACL_PWRUP_VA28_DISABLE |
1411 MT6357_AUD_DACL_PWRUP_VAUDP15_DISABLE);
1412 break;
1413 default:
1414 break;
1415 }
1416
1417 return 0;
1418 }
1419
1420 /* Supply widgets subsequence */
1421 enum {
1422 /* common */
1423 SUPPLY_SEQ_CLK_BUF,
1424 SUPPLY_SEQ_AUD_GLB,
1425 SUPPLY_SEQ_CLKSQ,
1426 SUPPLY_SEQ_VOW_AUD_LPW,
1427 SUPPLY_SEQ_AUD_VOW,
1428 SUPPLY_SEQ_VOW_CLK,
1429 SUPPLY_SEQ_VOW_LDO,
1430 SUPPLY_SEQ_TOP_CK,
1431 SUPPLY_SEQ_TOP_CK_LAST,
1432 SUPPLY_SEQ_AUD_TOP,
1433 SUPPLY_SEQ_AUD_TOP_LAST,
1434 SUPPLY_SEQ_AFE,
1435 /* capture */
1436 SUPPLY_SEQ_ADC_SUPPLY,
1437 };
1438
1439 /* DAPM Widgets */
1440 static const struct snd_soc_dapm_widget mt6357_dapm_widgets[] = {
1441 /* Analog Clocks */
1442 SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF,
1443 MT6357_DCXO_CW14,
1444 MT6357_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
1445 SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB,
1446 MT6357_AUDDEC_ANA_CON11,
1447 MT6357_AUDGLB_PWRDN_VA28_SFT, 1, NULL, 0),
1448 SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ,
1449 MT6357_AUDENC_ANA_CON6,
1450 MT6357_CLKSQ_EN_SFT, 0, NULL, 0),
1451 SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK,
1452 MT6357_AUD_TOP_CKPDN_CON0,
1453 MT6357_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
1454 SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK,
1455 MT6357_AUD_TOP_CKPDN_CON0,
1456 MT6357_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
1457 SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST,
1458 MT6357_AUD_TOP_CKPDN_CON0,
1459 MT6357_AUD_CK_PDN_SFT, 1,
1460 mt_delay_250_event,
1461 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1462 SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK,
1463 MT6357_AUD_TOP_CKPDN_CON0,
1464 MT6357_AUDIF_CK_PDN_SFT, 1, NULL, 0),
1465
1466 /* Digital Clocks */
1467 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST,
1468 MT6357_AUDIO_TOP_CON0,
1469 MT6357_PDN_AFE_CTL_SFT, 1,
1470 mt_delay_250_event,
1471 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1472 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP,
1473 MT6357_AUDIO_TOP_CON0,
1474 MT6357_PDN_DAC_CTL_SFT, 1, NULL, 0),
1475 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP,
1476 MT6357_AUDIO_TOP_CON0,
1477 MT6357_PDN_ADC_CTL_SFT, 1, NULL, 0),
1478 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP,
1479 MT6357_AUDIO_TOP_CON0,
1480 MT6357_PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
1481 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP,
1482 MT6357_AUDIO_TOP_CON0,
1483 MT6357_PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
1484 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP,
1485 MT6357_AUDIO_TOP_CON0,
1486 MT6357_PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
1487 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP,
1488 MT6357_AUDIO_TOP_CON0,
1489 MT6357_PDN_RESERVED_SFT, 1, NULL, 0),
1490 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_LPBK", SUPPLY_SEQ_AUD_TOP,
1491 MT6357_AUDIO_TOP_CON0,
1492 MT6357_PDN_LPBK_CTL_SFT, 1, NULL, 0),
1493
1494 /* General */
1495 SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE,
1496 MT6357_AFE_UL_DL_CON0,
1497 MT6357_AFE_ON_SFT, 0, NULL, 0),
1498
1499 /* Uplinks */
1500 SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "MT6357 Capture", 0,
1501 SND_SOC_NOPM, 0, 0,
1502 mt_aif_out_event,
1503 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1504 SND_SOC_DAPM_SUPPLY_S("ADC Supply", SUPPLY_SEQ_ADC_SUPPLY,
1505 SND_SOC_NOPM, 0, 0,
1506 mt_adc_supply_event,
1507 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1508 SND_SOC_DAPM_ADC_E("ADC", NULL, SND_SOC_NOPM, 0, 0, adc_enable_event,
1509 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1510 SND_SOC_DAPM_MUX_E("PGA L Mux", SND_SOC_NOPM, 0, 0,
1511 &pga_left_mux_control,
1512 mt_pga_left_event,
1513 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1514 SND_SOC_DAPM_MUX_E("PGA R Mux", SND_SOC_NOPM, 0, 0,
1515 &pga_right_mux_control,
1516 mt_pga_right_event,
1517 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1518 SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOPM, 0, 0, NULL, 0),
1519 SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOPM, 0, 0, NULL, 0),
1520 SND_SOC_DAPM_MUX_E("Mic Type Mux", SND_SOC_NOPM, 0, 0,
1521 &mic_type_mux_control,
1522 mt_mic_type_event,
1523 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1524 SND_SOC_DAPM_SUPPLY("MICBIAS0", MT6357_AUDENC_ANA_CON8,
1525 MT6357_AUD_MICBIAS0_PWD_SFT, 0, NULL, 0),
1526 SND_SOC_DAPM_SUPPLY("MICBIAS1", MT6357_AUDENC_ANA_CON9,
1527 MT6357_AUD_MICBIAS1_PWD_SFT, 0, NULL, 0),
1528
1529 /* UL inputs */
1530 SND_SOC_DAPM_INPUT("AIN0"),
1531 SND_SOC_DAPM_INPUT("AIN1"),
1532 SND_SOC_DAPM_INPUT("AIN2"),
1533 SND_SOC_DAPM_INPUT("LPBK"),
1534 SND_SOC_DAPM_INPUT("SGEN UL"),
1535
1536 /* Downlinks */
1537 SND_SOC_DAPM_AIF_IN_E("AIF_RX", "MT6357 Playback", 0,
1538 SND_SOC_NOPM, 0, 0,
1539 mt_audio_in_event,
1540 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1541 SND_SOC_DAPM_INPUT("SGEN DL"),
1542 SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0, &dac_mux_control),
1543
1544 SND_SOC_DAPM_DAC_E("DACR", NULL, SND_SOC_NOPM, 0, 0, right_dac_event,
1545 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1546 SND_SOC_DAPM_DAC_E("DACL", NULL, SND_SOC_NOPM, 0, 0, left_dac_event,
1547 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1548
1549 SND_SOC_DAPM_SUPPLY("DL Digital Supply", SND_SOC_NOPM, 0, 0, NULL, 0),
1550 SND_SOC_DAPM_SUPPLY("DL Analog Supply", SND_SOC_NOPM, 0, 0, NULL, 0),
1551 SND_SOC_DAPM_SUPPLY("DL SRC", MT6357_AFE_DL_SRC2_CON0_L,
1552 MT6357_DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
1553
1554 SND_SOC_DAPM_MUX_E("Line Out Source", SND_SOC_NOPM, 0, 0, &lo_mux_control,
1555 lo_mux_event,
1556 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1557
1558 SND_SOC_DAPM_MUX_E("Handset Source", SND_SOC_NOPM, 0, 0, &hs_mux_control,
1559 hs_mux_event,
1560 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1561
1562 SND_SOC_DAPM_MUX_E("Headphone Right Source", SND_SOC_NOPM, 0, 0, &hpr_mux_control,
1563 hp_main_mux_event,
1564 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1565
1566 SND_SOC_DAPM_MUX_E("Headphone Left Source", SND_SOC_NOPM, 0, 0, &hpl_mux_control,
1567 hp_main_mux_event,
1568 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1569 /* DL outputs */
1570 SND_SOC_DAPM_OUTPUT("Headphones"),
1571 SND_SOC_DAPM_OUTPUT("Hansdet"),
1572 SND_SOC_DAPM_OUTPUT("Line out"),
1573
1574 /* Sine generator */
1575 SND_SOC_DAPM_SUPPLY("SGEN UL Enable",
1576 MT6357_AFE_TOP_CON0, MT6357_UL_SINE_ON_SFT, 0, NULL, 0),
1577 SND_SOC_DAPM_SUPPLY("SGEN Enable",
1578 MT6357_AFE_SGEN_CFG0,
1579 MT6357_SGEN_DAC_EN_CTL_SFT, 0, mt_audio_in_event,
1580 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1581 SND_SOC_DAPM_SUPPLY("SGEN MUTE",
1582 MT6357_AFE_SGEN_CFG0,
1583 MT6357_SGEN_MUTE_SW_CTL_SFT, 1, NULL, 0)
1584 };
1585
1586 static const struct snd_soc_dapm_route mt6357_dapm_routes[] = {
1587 /* Capture */
1588 {"AIF1TX", NULL, "Mic Type Mux"},
1589 {"AIF1TX", NULL, "CLK_BUF"},
1590 {"AIF1TX", NULL, "AUDGLB"},
1591 {"AIF1TX", NULL, "CLKSQ Audio"},
1592 {"AIF1TX", NULL, "AUD_CK"},
1593 {"AIF1TX", NULL, "AUDIF_CK"},
1594
1595 {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"},
1596 {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"},
1597 {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"},
1598 {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"},
1599 {"AIF1TX", NULL, "AUDIO_TOP_I2S_DL"},
1600 {"AIF1TX", NULL, "AFE_ON"},
1601
1602 {"Mic Type Mux", "ACC", "ADC"},
1603 {"Mic Type Mux", "DCC", "ADC"},
1604 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC"},
1605 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC"},
1606 {"Mic Type Mux", "DMIC", "AIN0"},
1607 {"Mic Type Mux", "DMIC", "AIN2"},
1608 {"Mic Type Mux", "Loopback", "LPBK"},
1609 {"Mic Type Mux", "Sine Generator", "SGEN UL"},
1610
1611 {"SGEN UL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"},
1612 {"SGEN UL", NULL, "SGEN UL Enable"},
1613 {"SGEN UL", NULL, "SGEN MUTE"},
1614 {"SGEN UL", NULL, "SGEN Enable"},
1615
1616 {"ADC", NULL, "PGA L Mux"},
1617 {"ADC", NULL, "PGA R Mux"},
1618 {"ADC", NULL, "ADC Supply"},
1619
1620 {"PGA L Mux", "AIN0", "AIN0"},
1621 {"PGA L Mux", "AIN1", "AIN1"},
1622 {"PGA L Mux", "AIN2", "AIN2"},
1623
1624 {"PGA R Mux", "AIN0", "AIN0"},
1625 {"PGA R Mux", "AIN1", "AIN1"},
1626 {"PGA R Mux", "AIN2", "AIN2"},
1627
1628 {"AIN0", NULL, "MICBIAS0"},
1629 {"AIN1", NULL, "MICBIAS1"},
1630 {"AIN2", NULL, "MICBIAS0"},
1631 {"LPBK", NULL, "AUDIO_TOP_LPBK"},
1632
1633 /* Playback */
1634 {"DAC Mux", "Normal Path", "AIF_RX"},
1635 {"DAC Mux", "Sine Generator", "SGEN DL"},
1636
1637 {"AIF_RX", NULL, "DL SRC"},
1638
1639 {"SGEN DL", NULL, "DL SRC"},
1640 {"SGEN DL", NULL, "SGEN MUTE"},
1641 {"SGEN DL", NULL, "SGEN Enable"},
1642 {"SGEN DL", NULL, "DL Digital Supply"},
1643 {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"},
1644
1645 {"DACL", NULL, "DAC Mux"},
1646 {"DACR", NULL, "DAC Mux"},
1647
1648 {"DL Analog Supply", NULL, "CLK_BUF"},
1649 {"DL Analog Supply", NULL, "AUDGLB"},
1650 {"DL Analog Supply", NULL, "CLKSQ Audio"},
1651 {"DL Analog Supply", NULL, "AUDNCP_CK"},
1652 {"DL Analog Supply", NULL, "ZCD13M_CK"},
1653 {"DL Analog Supply", NULL, "AUD_CK"},
1654 {"DL Analog Supply", NULL, "AUDIF_CK"},
1655
1656 {"DL Digital Supply", NULL, "AUDIO_TOP_AFE_CTL"},
1657 {"DL Digital Supply", NULL, "AUDIO_TOP_DAC_CTL"},
1658 {"DL Digital Supply", NULL, "AUDIO_TOP_PWR_CLK"},
1659 {"DL Digital Supply", NULL, "AFE_ON"},
1660
1661 {"DACR", NULL, "DL Digital Supply"},
1662 {"DACR", NULL, "DL Analog Supply"},
1663 {"DACL", NULL, "DL Digital Supply"},
1664 {"DACL", NULL, "DL Analog Supply"},
1665
1666 {"Line Out Source", "DACR", "DACR"},
1667 {"Line Out Source", "Playback", "DACL"},
1668 {"Line Out Source", "Test mode", "DACL"},
1669
1670 {"Handset Source", "DACR", "DACR"},
1671 {"Handset Source", "Playback", "DACL"},
1672 {"Handset Source", "Test mode", "DACL"},
1673
1674 {"Headphone Right Source", "DAC", "DACR"},
1675 {"Headphone Right Source", "Line Out", "Line Out Source"},
1676 {"Headphone Right Source", "Handset", "Handset Source"},
1677
1678 {"Headphone Left Source", "DAC", "DACL"},
1679 {"Headphone Left Source", "Line Out", "Line Out Source"},
1680 {"Headphone Left Source", "Handset", "Handset Source"},
1681
1682 {"Line out", NULL, "Line Out Source"},
1683 {"Hansdet", NULL, "Handset Source"},
1684
1685 {"Headphones", NULL, "Headphone Right Source"},
1686 {"Headphones", NULL, "Headphone Left Source"},
1687 };
1688
1689 static struct snd_soc_dai_driver mtk_6357_dai_codecs[] = {
1690 {
1691 .name = "mt6357-snd-codec-aif1",
1692 .playback = {
1693 .stream_name = "MT6357 Playback",
1694 .channels_min = 1,
1695 .channels_max = 2,
1696 .rates = SNDRV_PCM_RATE_8000_192000,
1697 .formats = MT6357_SND_SOC_ADV_MT_FMTS,
1698 },
1699 .capture = {
1700 .stream_name = "MT6357 Capture",
1701 .channels_min = 1,
1702 .channels_max = 2,
1703 .rates = MT6357_SOC_HIGH_USE_RATE,
1704 .formats = MT6357_SND_SOC_ADV_MT_FMTS,
1705 },
1706 },
1707 };
1708
1709 static int mt6357_codec_probe(struct snd_soc_component *codec)
1710 {
1711 struct mt6357_priv *priv = snd_soc_component_get_drvdata(codec);
1712
1713 snd_soc_component_init_regmap(codec, priv->regmap);
1714
1715 /* Enable audio part */
1716 regmap_update_bits(priv->regmap, MT6357_DCXO_CW14,
1717 MT6357_XO_AUDIO_EN_M_MASK, MT6357_XO_AUDIO_EN_M_ENABLE);
1718 /* Disable HeadphoneL/HeadphoneR short circuit protection */
1719 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON0,
1720 MT6357_AUD_HPR_SC_VAUDP15_MASK |
1721 MT6357_AUD_HPL_SC_VAUDP15_MASK,
1722 MT6357_AUD_HPR_SC_VAUDP15_DISABLE |
1723 MT6357_AUD_HPL_SC_VAUDP15_DISABLE);
1724 /* Disable voice short circuit protection */
1725 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON3,
1726 MT6357_AUD_HS_SC_VAUDP15_MASK,
1727 MT6357_AUD_HS_SC_VAUDP15_DISABLE);
1728 /* disable LO buffer left short circuit protection */
1729 regmap_update_bits(priv->regmap, MT6357_AUDDEC_ANA_CON4,
1730 MT6357_AUD_LOL_SC_VAUDP15_MASK,
1731 MT6357_AUD_LOL_SC_VAUDP15_DISABLE);
1732 /* set gpio */
1733 set_playback_gpio(priv, false);
1734 set_capture_gpio(priv, false);
1735 /* Disable audio part */
1736 regmap_update_bits(priv->regmap, MT6357_DCXO_CW14,
1737 MT6357_XO_AUDIO_EN_M_MASK,
1738 MT6357_XO_AUDIO_EN_M_DISABLE);
1739
1740 return 0;
1741 }
1742
1743 static const struct snd_soc_component_driver mt6357_soc_component_driver = {
1744 .probe = mt6357_codec_probe,
1745 .read = snd_soc_component_read,
1746 .write = snd_soc_component_write,
1747 .controls = mt6357_controls,
1748 .num_controls = ARRAY_SIZE(mt6357_controls),
1749 .dapm_widgets = mt6357_dapm_widgets,
1750 .num_dapm_widgets = ARRAY_SIZE(mt6357_dapm_widgets),
1751 .dapm_routes = mt6357_dapm_routes,
1752 .num_dapm_routes = ARRAY_SIZE(mt6357_dapm_routes),
1753 };
1754
1755 static const u32 micbias_values[] = {
1756 1700000, 1800000, 1900000, 2000000,
1757 2100000, 2500000, 2600000, 2700000
1758 };
1759
1760 static u32 mt6357_get_micbias_idx(struct device_node *np, const char *micbias)
1761 {
1762 int err;
1763 u32 idx, val;
1764
1765 err = of_property_read_u32(np, micbias, &val);
1766 if (err)
1767 return 0;
1768
1769 for (idx = 0; idx < ARRAY_SIZE(micbias_values); idx++) {
1770 if (val == micbias_values[idx])
1771 return idx;
1772 }
1773 return 0;
1774 }
1775
1776 static int mt6357_parse_dt(struct mt6357_priv *priv)
1777 {
1778 u32 micbias_voltage_index = 0;
1779 struct device_node *np = priv->dev->parent->of_node;
1780
1781 if (!np)
1782 return -EINVAL;
1783
1784 priv->pull_down_needed = false;
1785 if (of_property_read_bool(np, "mediatek,hp-pull-down"))
1786 priv->pull_down_needed = true;
1787
1788 micbias_voltage_index = mt6357_get_micbias_idx(np, "mediatek,micbias0-microvolt");
1789 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON8,
1790 MT6357_AUD_MICBIAS0_VREF_MASK,
1791 micbias_voltage_index << MT6357_AUD_MICBIAS0_VREF_SFT);
1792
1793 micbias_voltage_index = mt6357_get_micbias_idx(np, "mediatek,micbias1-microvolt");
1794 regmap_update_bits(priv->regmap, MT6357_AUDENC_ANA_CON9,
1795 MT6357_AUD_MICBIAS1_VREF_MASK,
1796 micbias_voltage_index << MT6357_AUD_MICBIAS1_VREF_SFT);
1797
1798 return 0;
1799 }
1800
1801 static int mt6357_platform_driver_probe(struct platform_device *pdev)
1802 {
1803 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
1804 struct mt6357_priv *priv;
1805 int ret;
1806
1807 ret = devm_regulator_get_enable(&pdev->dev, "vaud28");
1808 if (ret)
1809 return dev_err_probe(&pdev->dev, ret, "Failed to enable vaud28 regulator\n");
1810
1811 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1812 if (!priv)
1813 return -ENOMEM;
1814
1815 dev_set_drvdata(&pdev->dev, priv);
1816 priv->dev = &pdev->dev;
1817
1818 priv->regmap = mt6397->regmap;
1819 if (IS_ERR(priv->regmap))
1820 return PTR_ERR(priv->regmap);
1821
1822 ret = mt6357_parse_dt(priv);
1823 if (ret)
1824 return dev_err_probe(&pdev->dev, ret, "Failed to parse dts\n");
1825
1826 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64);
1827 if (!pdev->dev.dma_mask)
1828 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
1829
1830 return devm_snd_soc_register_component(&pdev->dev,
1831 &mt6357_soc_component_driver,
1832 mtk_6357_dai_codecs,
1833 ARRAY_SIZE(mtk_6357_dai_codecs));
1834 }
1835
1836 static const struct platform_device_id mt6357_platform_ids[] = {
1837 {"mt6357-sound", 0},
1838 { /* sentinel */ },
1839 };
1840 MODULE_DEVICE_TABLE(platform, mt6357_platform_ids);
1841
1842 static struct platform_driver mt6357_platform_driver = {
1843 .driver = {
1844 .name = "mt6357-sound",
1845 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1846 },
1847 .probe = mt6357_platform_driver_probe,
1848 .id_table = mt6357_platform_ids,
1849 };
1850
1851 module_platform_driver(mt6357_platform_driver)
1852
1853 MODULE_DESCRIPTION("MT6357 ALSA SoC codec driver");
1854 MODULE_AUTHOR("Nicolas Belin <nbelin@baylibre.com>");
1855 MODULE_LICENSE("GPL");
Kernel DRM miscellaneous fixes and cross-tree changes