sound/soc/codecs/rt9120.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 #include <linux/bits.h>
   4 #include <linux/bitfield.h>
   5 #include <linux/delay.h>
   6 #include <linux/gpio/consumer.h>
   7 #include <linux/i2c.h>
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/pm_runtime.h>
  11 #include <linux/regmap.h>
  12 #include <linux/regulator/consumer.h>
  13 #include <sound/pcm.h>
  14 #include <sound/pcm_params.h>
  15 #include <sound/soc.h>
  16 #include <sound/tlv.h>
  17
  18 #define RT9120_REG_DEVID        0x00
  19 #define RT9120_REG_I2SFMT       0x02
  20 #define RT9120_REG_I2SWL        0x03
  21 #define RT9120_REG_SDIOSEL      0x04
  22 #define RT9120_REG_SYSCTL       0x05
  23 #define RT9120_REG_SPKGAIN      0x07
  24 #define RT9120_REG_VOLRAMP      0x0A
  25 #define RT9120_REG_ERRRPT       0x10
  26 #define RT9120_REG_MSVOL        0x20
  27 #define RT9120_REG_SWRESET      0x40
  28 #define RT9120_REG_INTERCFG     0x63
  29 #define RT9120_REG_INTERNAL0    0x65
  30 #define RT9120_REG_INTERNAL1    0x69
  31 #define RT9120_REG_UVPOPT       0x6C
  32 #define RT9120_REG_DIGCFG       0xF8
  33
  34 #define RT9120_VID_MASK         GENMASK(15, 8)
  35 #define RT9120_SWRST_MASK       BIT(7)
  36 #define RT9120_MUTE_MASK        GENMASK(5, 4)
  37 #define RT9120_I2SFMT_MASK      GENMASK(4, 2)
  38 #define RT9120_I2SFMT_SHIFT     2
  39 #define RT9120_CFG_FMT_I2S      0
  40 #define RT9120_CFG_FMT_LEFTJ    1
  41 #define RT9120_CFG_FMT_RIGHTJ   2
  42 #define RT9120_CFG_FMT_DSPA     3
  43 #define RT9120_CFG_FMT_DSPB     7
  44 #define RT9120_AUDBIT_MASK      GENMASK(1, 0)
  45 #define RT9120_CFG_AUDBIT_16    0
  46 #define RT9120_CFG_AUDBIT_20    1
  47 #define RT9120_CFG_AUDBIT_24    2
  48 #define RT9120_AUDWL_MASK       GENMASK(5, 0)
  49 #define RT9120_CFG_WORDLEN_16   16
  50 #define RT9120_CFG_WORDLEN_24   24
  51 #define RT9120_CFG_WORDLEN_32   32
  52 #define RT9120_DVDD_UVSEL_MASK  GENMASK(5, 4)
  53 #define RT9120_AUTOSYNC_MASK    BIT(6)
  54
  55 #define RT9120_VENDOR_ID        0x42
  56 #define RT9120S_VENDOR_ID       0x43
  57 #define RT9120_RESET_WAITMS     20
  58 #define RT9120_CHIPON_WAITMS    20
  59 #define RT9120_AMPON_WAITMS     50
  60 #define RT9120_AMPOFF_WAITMS    100
  61 #define RT9120_LVAPP_THRESUV    2000000
  62
  63 /* 8000 to 192000 supported , only 176400 not support */
  64 #define RT9120_RATES_MASK       (SNDRV_PCM_RATE_8000_192000 &\
  65                                  ~SNDRV_PCM_RATE_176400)
  66 #define RT9120_FMTS_MASK        (SNDRV_PCM_FMTBIT_S16_LE |\
  67                                  SNDRV_PCM_FMTBIT_S24_LE |\
  68                                  SNDRV_PCM_FMTBIT_S32_LE)
  69
  70 enum {
  71         CHIP_IDX_RT9120 = 0,
  72         CHIP_IDX_RT9120S,
  73         CHIP_IDX_MAX
  74 };
  75
  76 struct rt9120_data {
  77         struct device *dev;
  78         struct regmap *regmap;
  79         struct gpio_desc *pwdnn_gpio;
  80         int chip_idx;
  81 };
  82
  83 /* 11bit [min,max,step] = [-103.9375dB, 24dB, 0.0625dB] */
  84 static const DECLARE_TLV_DB_SCALE(digital_tlv, -1039375, 625, 1);
  85
  86 /* {6, 8, 10, 12, 13, 14, 15, 16}dB */
  87 static const DECLARE_TLV_DB_RANGE(classd_tlv,
  88         0, 3, TLV_DB_SCALE_ITEM(600, 200, 0),
  89         4, 7, TLV_DB_SCALE_ITEM(1300, 100, 0)
  90 );
  91
  92 static const char * const sdo_select_text[] = {
  93         "None", "INTF", "Final", "RMS Detect"
  94 };
  95
  96 static const struct soc_enum sdo_select_enum =
  97         SOC_ENUM_SINGLE(RT9120_REG_SDIOSEL, 4, ARRAY_SIZE(sdo_select_text),
  98                         sdo_select_text);
  99
 100 static const struct snd_kcontrol_new rt9120_snd_controls[] = {
 101         SOC_SINGLE_TLV("MS Volume", RT9120_REG_MSVOL, 0, 2047, 1, digital_tlv),
 102         SOC_SINGLE_TLV("SPK Gain Volume", RT9120_REG_SPKGAIN, 0, 7, 0, classd_tlv),
 103         SOC_SINGLE("PBTL Switch", RT9120_REG_SYSCTL, 3, 1, 0),
 104         SOC_ENUM("SDO Select", sdo_select_enum),
 105 };
 106
 107 static int internal_power_event(struct snd_soc_dapm_widget *w,
 108                                 struct snd_kcontrol *kcontrol, int event)
 109 {
 110         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
 111
 112         switch (event) {
 113         case SND_SOC_DAPM_PRE_PMU:
 114                 snd_soc_component_write(comp, RT9120_REG_ERRRPT, 0);
 115                 break;
 116         case SND_SOC_DAPM_POST_PMU:
 117                 msleep(RT9120_AMPON_WAITMS);
 118                 break;
 119         case SND_SOC_DAPM_POST_PMD:
 120                 msleep(RT9120_AMPOFF_WAITMS);
 121                 break;
 122         default:
 123                 break;
 124         }
 125
 126         return 0;
 127 }
 128
 129 static const struct snd_soc_dapm_widget rt9120_dapm_widgets[] = {
 130         SND_SOC_DAPM_MIXER("DMIX", SND_SOC_NOPM, 0, 0, NULL, 0),
 131         SND_SOC_DAPM_DAC("LDAC", NULL, SND_SOC_NOPM, 0, 0),
 132         SND_SOC_DAPM_DAC("RDAC", NULL, SND_SOC_NOPM, 0, 0),
 133         SND_SOC_DAPM_SUPPLY("PWND", RT9120_REG_SYSCTL, 6, 1,
 134                             internal_power_event, SND_SOC_DAPM_PRE_PMU |
 135                             SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 136         SND_SOC_DAPM_PGA("SPKL PA", SND_SOC_NOPM, 0, 0, NULL, 0),
 137         SND_SOC_DAPM_PGA("SPKR PA", SND_SOC_NOPM, 0, 0, NULL, 0),
 138         SND_SOC_DAPM_OUTPUT("SPKL"),
 139         SND_SOC_DAPM_OUTPUT("SPKR"),
 140 };
 141
 142 static const struct snd_soc_dapm_route rt9120_dapm_routes[] = {
 143         { "DMIX", NULL, "AIF Playback" },
 144         /* SPKL */
 145         { "LDAC", NULL, "PWND" },
 146         { "LDAC", NULL, "DMIX" },
 147         { "SPKL PA", NULL, "LDAC" },
 148         { "SPKL", NULL, "SPKL PA" },
 149         /* SPKR */
 150         { "RDAC", NULL, "PWND" },
 151         { "RDAC", NULL, "DMIX" },
 152         { "SPKR PA", NULL, "RDAC" },
 153         { "SPKR", NULL, "SPKR PA" },
 154         /* Cap */
 155         { "AIF Capture", NULL, "LDAC" },
 156         { "AIF Capture", NULL, "RDAC" },
 157 };
 158
 159 static int rt9120_codec_probe(struct snd_soc_component *comp)
 160 {
 161         struct rt9120_data *data = snd_soc_component_get_drvdata(comp);
 162
 163         snd_soc_component_init_regmap(comp, data->regmap);
 164
 165         pm_runtime_get_sync(comp->dev);
 166
 167         /* Internal setting */
 168         if (data->chip_idx == CHIP_IDX_RT9120S) {
 169                 snd_soc_component_write(comp, RT9120_REG_INTERCFG, 0xde);
 170                 snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x66);
 171         } else
 172                 snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x04);
 173
 174         pm_runtime_mark_last_busy(comp->dev);
 175         pm_runtime_put(comp->dev);
 176
 177         return 0;
 178 }
 179
 180 static int rt9120_codec_suspend(struct snd_soc_component *comp)
 181 {
 182         return pm_runtime_force_suspend(comp->dev);
 183 }
 184
 185 static int rt9120_codec_resume(struct snd_soc_component *comp)
 186 {
 187         return pm_runtime_force_resume(comp->dev);
 188 }
 189
 190 static const struct snd_soc_component_driver rt9120_component_driver = {
 191         .probe = rt9120_codec_probe,
 192         .suspend = rt9120_codec_suspend,
 193         .resume = rt9120_codec_resume,
 194         .controls = rt9120_snd_controls,
 195         .num_controls = ARRAY_SIZE(rt9120_snd_controls),
 196         .dapm_widgets = rt9120_dapm_widgets,
 197         .num_dapm_widgets = ARRAY_SIZE(rt9120_dapm_widgets),
 198         .dapm_routes = rt9120_dapm_routes,
 199         .num_dapm_routes = ARRAY_SIZE(rt9120_dapm_routes),
 200         .endianness = 1,
 201 };
 202
 203 static int rt9120_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 204 {
 205         struct snd_soc_component *comp = dai->component;
 206         unsigned int format;
 207
 208         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 209         case SND_SOC_DAIFMT_I2S:
 210                 format = RT9120_CFG_FMT_I2S;
 211                 break;
 212         case SND_SOC_DAIFMT_LEFT_J:
 213                 format = RT9120_CFG_FMT_LEFTJ;
 214                 break;
 215         case SND_SOC_DAIFMT_RIGHT_J:
 216                 format = RT9120_CFG_FMT_RIGHTJ;
 217                 break;
 218         case SND_SOC_DAIFMT_DSP_A:
 219                 format = RT9120_CFG_FMT_DSPA;
 220                 break;
 221         case SND_SOC_DAIFMT_DSP_B:
 222                 format = RT9120_CFG_FMT_DSPB;
 223                 break;
 224         default:
 225                 dev_err(dai->dev, "Unknown dai format\n");
 226                 return -EINVAL;
 227         }
 228
 229         snd_soc_component_update_bits(comp, RT9120_REG_I2SFMT,
 230                                       RT9120_I2SFMT_MASK,
 231                                       format << RT9120_I2SFMT_SHIFT);
 232         return 0;
 233 }
 234
 235 static int rt9120_hw_params(struct snd_pcm_substream *substream,
 236                             struct snd_pcm_hw_params *param,
 237                             struct snd_soc_dai *dai)
 238 {
 239         struct snd_soc_component *comp = dai->component;
 240         unsigned int param_width, param_slot_width, auto_sync;
 241         int width, fs;
 242
 243         switch (width = params_width(param)) {
 244         case 16:
 245                 param_width = RT9120_CFG_AUDBIT_16;
 246                 break;
 247         case 20:
 248                 param_width = RT9120_CFG_AUDBIT_20;
 249                 break;
 250         case 24:
 251         case 32:
 252                 param_width = RT9120_CFG_AUDBIT_24;
 253                 break;
 254         default:
 255                 dev_err(dai->dev, "Unsupported data width [%d]\n", width);
 256                 return -EINVAL;
 257         }
 258
 259         snd_soc_component_update_bits(comp, RT9120_REG_I2SFMT,
 260                                       RT9120_AUDBIT_MASK, param_width);
 261
 262         switch (width = params_physical_width(param)) {
 263         case 16:
 264                 param_slot_width = RT9120_CFG_WORDLEN_16;
 265                 break;
 266         case 24:
 267                 param_slot_width = RT9120_CFG_WORDLEN_24;
 268                 break;
 269         case 32:
 270                 param_slot_width = RT9120_CFG_WORDLEN_32;
 271                 break;
 272         default:
 273                 dev_err(dai->dev, "Unsupported slot width [%d]\n", width);
 274                 return -EINVAL;
 275         }
 276
 277         snd_soc_component_update_bits(comp, RT9120_REG_I2SWL,
 278                                       RT9120_AUDWL_MASK, param_slot_width);
 279
 280         fs = width * params_channels(param);
 281         /* If fs is divided by 48, disable auto sync */
 282         if (fs % 48 == 0)
 283                 auto_sync = 0;
 284         else
 285                 auto_sync = RT9120_AUTOSYNC_MASK;
 286
 287         snd_soc_component_update_bits(comp, RT9120_REG_DIGCFG,
 288                                       RT9120_AUTOSYNC_MASK, auto_sync);
 289         return 0;
 290 }
 291
 292 static const struct snd_soc_dai_ops rt9120_dai_ops = {
 293         .set_fmt = rt9120_set_fmt,
 294         .hw_params = rt9120_hw_params,
 295 };
 296
 297 static struct snd_soc_dai_driver rt9120_dai = {
 298         .name = "rt9120_aif",
 299         .playback = {
 300                 .stream_name = "AIF Playback",
 301                 .rates = RT9120_RATES_MASK,
 302                 .formats = RT9120_FMTS_MASK,
 303                 .rate_max = 192000,
 304                 .rate_min = 8000,
 305                 .channels_min = 1,
 306                 .channels_max = 2,
 307         },
 308         .capture = {
 309                 .stream_name = "AIF Capture",
 310                 .rates = RT9120_RATES_MASK,
 311                 .formats = RT9120_FMTS_MASK,
 312                 .rate_max = 192000,
 313                 .rate_min = 8000,
 314                 .channels_min = 1,
 315                 .channels_max = 2,
 316         },
 317         .ops = &rt9120_dai_ops,
 318         .symmetric_rate = 1,
 319         .symmetric_sample_bits = 1,
 320 };
 321
 322 static const struct regmap_range rt9120_rd_yes_ranges[] = {
 323         regmap_reg_range(0x00, 0x0C),
 324         regmap_reg_range(0x10, 0x15),
 325         regmap_reg_range(0x20, 0x27),
 326         regmap_reg_range(0x30, 0x38),
 327         regmap_reg_range(0x3A, 0x40),
 328         regmap_reg_range(0x63, 0x63),
 329         regmap_reg_range(0x65, 0x65),
 330         regmap_reg_range(0x69, 0x69),
 331         regmap_reg_range(0x6C, 0x6C),
 332         regmap_reg_range(0xF8, 0xF8)
 333 };
 334
 335 static const struct regmap_access_table rt9120_rd_table = {
 336         .yes_ranges = rt9120_rd_yes_ranges,
 337         .n_yes_ranges = ARRAY_SIZE(rt9120_rd_yes_ranges),
 338 };
 339
 340 static const struct regmap_range rt9120_wr_yes_ranges[] = {
 341         regmap_reg_range(0x00, 0x00),
 342         regmap_reg_range(0x02, 0x0A),
 343         regmap_reg_range(0x10, 0x15),
 344         regmap_reg_range(0x20, 0x27),
 345         regmap_reg_range(0x30, 0x38),
 346         regmap_reg_range(0x3A, 0x3D),
 347         regmap_reg_range(0x40, 0x40),
 348         regmap_reg_range(0x63, 0x63),
 349         regmap_reg_range(0x65, 0x65),
 350         regmap_reg_range(0x69, 0x69),
 351         regmap_reg_range(0x6C, 0x6C),
 352         regmap_reg_range(0xF8, 0xF8)
 353 };
 354
 355 static const struct regmap_access_table rt9120_wr_table = {
 356         .yes_ranges = rt9120_wr_yes_ranges,
 357         .n_yes_ranges = ARRAY_SIZE(rt9120_wr_yes_ranges),
 358 };
 359
 360 static bool rt9120_volatile_reg(struct device *dev, unsigned int reg)
 361 {
 362         switch (reg) {
 363         case 0x00 ... 0x01:
 364         case 0x10:
 365         case 0x30 ... 0x40:
 366                 return true;
 367         default:
 368                 return false;
 369         }
 370 }
 371
 372 static int rt9120_get_reg_size(unsigned int reg)
 373 {
 374         switch (reg) {
 375         case 0x00:
 376         case 0x20 ... 0x27:
 377                 return 2;
 378         case 0x30 ... 0x3D:
 379                 return 3;
 380         case 0x3E ... 0x3F:
 381                 return 4;
 382         default:
 383                 return 1;
 384         }
 385 }
 386
 387 static int rt9120_reg_read(void *context, unsigned int reg, unsigned int *val)
 388 {
 389         struct rt9120_data *data = context;
 390         struct i2c_client *i2c = to_i2c_client(data->dev);
 391         int size = rt9120_get_reg_size(reg);
 392         u8 raw[4] = {0};
 393         int ret;
 394
 395         ret = i2c_smbus_read_i2c_block_data(i2c, reg, size, raw);
 396         if (ret < 0)
 397                 return ret;
 398         else if (ret != size)
 399                 return -EIO;
 400
 401         switch (size) {
 402         case 4:
 403                 *val = be32_to_cpup((__be32 *)raw);
 404                 break;
 405         case 3:
 406                 *val = raw[0] << 16 | raw[1] << 8 | raw[2];
 407                 break;
 408         case 2:
 409                 *val = be16_to_cpup((__be16 *)raw);
 410                 break;
 411         default:
 412                 *val = raw[0];
 413         }
 414
 415         return 0;
 416 }
 417
 418 static int rt9120_reg_write(void *context, unsigned int reg, unsigned int val)
 419 {
 420         struct rt9120_data *data = context;
 421         struct i2c_client *i2c = to_i2c_client(data->dev);
 422         int size = rt9120_get_reg_size(reg);
 423         __be32 be32_val;
 424         u8 *rawp = (u8 *)&be32_val;
 425         int offs = 4 - size;
 426
 427         be32_val = cpu_to_be32(val);
 428         return i2c_smbus_write_i2c_block_data(i2c, reg, size, rawp + offs);
 429 }
 430
 431 static const struct reg_default rt9120_reg_defaults[] = {
 432         { .reg = 0x02, .def = 0x02 },
 433         { .reg = 0x03, .def = 0xf2 },
 434         { .reg = 0x04, .def = 0x01 },
 435         { .reg = 0x05, .def = 0xc0 },
 436         { .reg = 0x06, .def = 0x28 },
 437         { .reg = 0x07, .def = 0x04 },
 438         { .reg = 0x08, .def = 0xff },
 439         { .reg = 0x09, .def = 0x01 },
 440         { .reg = 0x0a, .def = 0x01 },
 441         { .reg = 0x0b, .def = 0x00 },
 442         { .reg = 0x0c, .def = 0x04 },
 443         { .reg = 0x11, .def = 0x30 },
 444         { .reg = 0x12, .def = 0x08 },
 445         { .reg = 0x13, .def = 0x12 },
 446         { .reg = 0x14, .def = 0x09 },
 447         { .reg = 0x15, .def = 0x00 },
 448         { .reg = 0x20, .def = 0x7ff },
 449         { .reg = 0x21, .def = 0x180 },
 450         { .reg = 0x22, .def = 0x180 },
 451         { .reg = 0x23, .def = 0x00 },
 452         { .reg = 0x24, .def = 0x80 },
 453         { .reg = 0x25, .def = 0x180 },
 454         { .reg = 0x26, .def = 0x640 },
 455         { .reg = 0x27, .def = 0x180 },
 456         { .reg = 0x63, .def = 0x5e },
 457         { .reg = 0x65, .def = 0x66 },
 458         { .reg = 0x6c, .def = 0xe0 },
 459         { .reg = 0xf8, .def = 0x44 },
 460 };
 461
 462 static const struct regmap_config rt9120_regmap_config = {
 463         .reg_bits = 8,
 464         .val_bits = 32,
 465         .max_register = RT9120_REG_DIGCFG,
 466         .reg_defaults = rt9120_reg_defaults,
 467         .num_reg_defaults = ARRAY_SIZE(rt9120_reg_defaults),
 468         .cache_type = REGCACHE_RBTREE,
 469
 470         .reg_read = rt9120_reg_read,
 471         .reg_write = rt9120_reg_write,
 472
 473         .volatile_reg = rt9120_volatile_reg,
 474         .wr_table = &rt9120_wr_table,
 475         .rd_table = &rt9120_rd_table,
 476 };
 477
 478 static int rt9120_check_vendor_info(struct rt9120_data *data)
 479 {
 480         unsigned int devid;
 481         int ret;
 482
 483         ret = regmap_read(data->regmap, RT9120_REG_DEVID, &devid);
 484         if (ret)
 485                 return ret;
 486
 487         devid = FIELD_GET(RT9120_VID_MASK, devid);
 488         switch (devid) {
 489         case RT9120_VENDOR_ID:
 490                 data->chip_idx = CHIP_IDX_RT9120;
 491                 break;
 492         case RT9120S_VENDOR_ID:
 493                 data->chip_idx = CHIP_IDX_RT9120S;
 494                 break;
 495         default:
 496                 dev_err(data->dev, "DEVID not correct [0x%0x]\n", devid);
 497                 return -ENODEV;
 498         }
 499
 500         return 0;
 501 }
 502
 503 static int rt9120_do_register_reset(struct rt9120_data *data)
 504 {
 505         int ret;
 506
 507         ret = regmap_write(data->regmap, RT9120_REG_SWRESET,
 508                            RT9120_SWRST_MASK);
 509         if (ret)
 510                 return ret;
 511
 512         msleep(RT9120_RESET_WAITMS);
 513         return 0;
 514 }
 515
 516 static int rt9120_probe(struct i2c_client *i2c)
 517 {
 518         struct rt9120_data *data;
 519         struct regulator *dvdd_supply;
 520         int dvdd_supply_volt, ret;
 521
 522         data = devm_kzalloc(&i2c->dev, sizeof(*data), GFP_KERNEL);
 523         if (!data)
 524                 return -ENOMEM;
 525
 526         data->dev = &i2c->dev;
 527         i2c_set_clientdata(i2c, data);
 528
 529         data->pwdnn_gpio = devm_gpiod_get_optional(&i2c->dev, "pwdnn",
 530                                                    GPIOD_OUT_HIGH);
 531         if (IS_ERR(data->pwdnn_gpio)) {
 532                 dev_err(&i2c->dev, "Failed to initialize 'pwdnn' gpio\n");
 533                 return PTR_ERR(data->pwdnn_gpio);
 534         } else if (data->pwdnn_gpio) {
 535                 dev_dbg(&i2c->dev, "'pwdnn' from low to high, wait chip on\n");
 536                 msleep(RT9120_CHIPON_WAITMS);
 537         }
 538
 539         data->regmap = devm_regmap_init(&i2c->dev, NULL, data,
 540                                         &rt9120_regmap_config);
 541         if (IS_ERR(data->regmap)) {
 542                 ret = PTR_ERR(data->regmap);
 543                 dev_err(&i2c->dev, "Failed to init regmap [%d]\n", ret);
 544                 return ret;
 545         }
 546
 547         ret = rt9120_check_vendor_info(data);
 548         if (ret) {
 549                 dev_err(&i2c->dev, "Failed to check vendor info\n");
 550                 return ret;
 551         }
 552
 553         ret = rt9120_do_register_reset(data);
 554         if (ret) {
 555                 dev_err(&i2c->dev, "Failed to do register reset\n");
 556                 return ret;
 557         }
 558
 559         dvdd_supply = devm_regulator_get(&i2c->dev, "dvdd");
 560         if (IS_ERR(dvdd_supply)) {
 561                 dev_err(&i2c->dev, "No dvdd regulator found\n");
 562                 return PTR_ERR(dvdd_supply);
 563         }
 564
 565         dvdd_supply_volt = regulator_get_voltage(dvdd_supply);
 566         if (dvdd_supply_volt <= RT9120_LVAPP_THRESUV) {
 567                 dev_dbg(&i2c->dev, "dvdd low voltage design\n");
 568                 ret = regmap_update_bits(data->regmap, RT9120_REG_UVPOPT,
 569                                          RT9120_DVDD_UVSEL_MASK, 0);
 570                 if (ret) {
 571                         dev_err(&i2c->dev, "Failed to config dvdd uvsel\n");
 572                         return ret;
 573                 }
 574         }
 575
 576         pm_runtime_set_autosuspend_delay(&i2c->dev, 1000);
 577         pm_runtime_use_autosuspend(&i2c->dev);
 578         pm_runtime_set_active(&i2c->dev);
 579         pm_runtime_mark_last_busy(&i2c->dev);
 580         pm_runtime_enable(&i2c->dev);
 581
 582         return devm_snd_soc_register_component(&i2c->dev,
 583                                                &rt9120_component_driver,
 584                                                &rt9120_dai, 1);
 585 }
 586
 587 static void rt9120_remove(struct i2c_client *i2c)
 588 {
 589         pm_runtime_disable(&i2c->dev);
 590         pm_runtime_set_suspended(&i2c->dev);
 591 }
 592
 593 static int __maybe_unused rt9120_runtime_suspend(struct device *dev)
 594 {
 595         struct rt9120_data *data = dev_get_drvdata(dev);
 596
 597         if (data->pwdnn_gpio) {
 598                 regcache_cache_only(data->regmap, true);
 599                 regcache_mark_dirty(data->regmap);
 600                 gpiod_set_value(data->pwdnn_gpio, 0);
 601         }
 602
 603         return 0;
 604 }
 605
 606 static int __maybe_unused rt9120_runtime_resume(struct device *dev)
 607 {
 608         struct rt9120_data *data = dev_get_drvdata(dev);
 609
 610         if (data->pwdnn_gpio) {
 611                 gpiod_set_value(data->pwdnn_gpio, 1);
 612                 msleep(RT9120_CHIPON_WAITMS);
 613                 regcache_cache_only(data->regmap, false);
 614                 regcache_sync(data->regmap);
 615         }
 616
 617         return 0;
 618 }
 619
 620 static const struct dev_pm_ops rt9120_pm_ops = {
 621         SET_RUNTIME_PM_OPS(rt9120_runtime_suspend, rt9120_runtime_resume, NULL)
 622 };
 623
 624 static const struct of_device_id __maybe_unused rt9120_device_table[] = {
 625         { .compatible = "richtek,rt9120", },
 626         { }
 627 };
 628 MODULE_DEVICE_TABLE(of, rt9120_device_table);
 629
 630 static struct i2c_driver rt9120_driver = {
 631         .driver = {
 632                 .name = "rt9120",
 633                 .of_match_table = rt9120_device_table,
 634                 .pm = &rt9120_pm_ops,
 635         },
 636         .probe = rt9120_probe,
 637         .remove = rt9120_remove,
 638 };
 639 module_i2c_driver(rt9120_driver);
 640
 641 MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>");
 642 MODULE_DESCRIPTION("RT9120 Audio Amplifier Driver");
 643 MODULE_LICENSE("GPL");