sound/soc/fsl/fsl_sai.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright 2012-2013 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __FSL_SAI_H
   7 #define __FSL_SAI_H
   8
   9 #include <linux/dma/imx-dma.h>
  10 #include <sound/dmaengine_pcm.h>
  11
  12 #define FSL_SAI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  13                          SNDRV_PCM_FMTBIT_S20_3LE |\
  14                          SNDRV_PCM_FMTBIT_S24_LE |\
  15                          SNDRV_PCM_FMTBIT_S32_LE |\
  16                          SNDRV_PCM_FMTBIT_DSD_U8 |\
  17                          SNDRV_PCM_FMTBIT_DSD_U16_LE |\
  18                          SNDRV_PCM_FMTBIT_DSD_U32_LE)
  19
  20 /* SAI Register Map Register */
  21 #define FSL_SAI_VERID   0x00 /* SAI Version ID Register */
  22 #define FSL_SAI_PARAM   0x04 /* SAI Parameter Register */
  23 #define FSL_SAI_TCSR(ofs)       (0x00 + ofs) /* SAI Transmit Control */
  24 #define FSL_SAI_TCR1(ofs)       (0x04 + ofs) /* SAI Transmit Configuration 1 */
  25 #define FSL_SAI_TCR2(ofs)       (0x08 + ofs) /* SAI Transmit Configuration 2 */
  26 #define FSL_SAI_TCR3(ofs)       (0x0c + ofs) /* SAI Transmit Configuration 3 */
  27 #define FSL_SAI_TCR4(ofs)       (0x10 + ofs) /* SAI Transmit Configuration 4 */
  28 #define FSL_SAI_TCR5(ofs)       (0x14 + ofs) /* SAI Transmit Configuration 5 */
  29 #define FSL_SAI_TDR0    0x20 /* SAI Transmit Data 0 */
  30 #define FSL_SAI_TDR1    0x24 /* SAI Transmit Data 1 */
  31 #define FSL_SAI_TDR2    0x28 /* SAI Transmit Data 2 */
  32 #define FSL_SAI_TDR3    0x2C /* SAI Transmit Data 3 */
  33 #define FSL_SAI_TDR4    0x30 /* SAI Transmit Data 4 */
  34 #define FSL_SAI_TDR5    0x34 /* SAI Transmit Data 5 */
  35 #define FSL_SAI_TDR6    0x38 /* SAI Transmit Data 6 */
  36 #define FSL_SAI_TDR7    0x3C /* SAI Transmit Data 7 */
  37 #define FSL_SAI_TFR0    0x40 /* SAI Transmit FIFO 0 */
  38 #define FSL_SAI_TFR1    0x44 /* SAI Transmit FIFO 1 */
  39 #define FSL_SAI_TFR2    0x48 /* SAI Transmit FIFO 2 */
  40 #define FSL_SAI_TFR3    0x4C /* SAI Transmit FIFO 3 */
  41 #define FSL_SAI_TFR4    0x50 /* SAI Transmit FIFO 4 */
  42 #define FSL_SAI_TFR5    0x54 /* SAI Transmit FIFO 5 */
  43 #define FSL_SAI_TFR6    0x58 /* SAI Transmit FIFO 6 */
  44 #define FSL_SAI_TFR7    0x5C /* SAI Transmit FIFO 7 */
  45 #define FSL_SAI_TMR     0x60 /* SAI Transmit Mask */
  46 #define FSL_SAI_TTCTL   0x70 /* SAI Transmit Timestamp Control Register */
  47 #define FSL_SAI_TTCTN   0x74 /* SAI Transmit Timestamp Counter Register */
  48 #define FSL_SAI_TBCTN   0x78 /* SAI Transmit Bit Counter Register */
  49 #define FSL_SAI_TTCAP   0x7C /* SAI Transmit Timestamp Capture */
  50 #define FSL_SAI_RCSR(ofs)       (0x80 + ofs) /* SAI Receive Control */
  51 #define FSL_SAI_RCR1(ofs)       (0x84 + ofs)/* SAI Receive Configuration 1 */
  52 #define FSL_SAI_RCR2(ofs)       (0x88 + ofs) /* SAI Receive Configuration 2 */
  53 #define FSL_SAI_RCR3(ofs)       (0x8c + ofs) /* SAI Receive Configuration 3 */
  54 #define FSL_SAI_RCR4(ofs)       (0x90 + ofs) /* SAI Receive Configuration 4 */
  55 #define FSL_SAI_RCR5(ofs)       (0x94 + ofs) /* SAI Receive Configuration 5 */
  56 #define FSL_SAI_RDR0    0xa0 /* SAI Receive Data 0 */
  57 #define FSL_SAI_RDR1    0xa4 /* SAI Receive Data 1 */
  58 #define FSL_SAI_RDR2    0xa8 /* SAI Receive Data 2 */
  59 #define FSL_SAI_RDR3    0xac /* SAI Receive Data 3 */
  60 #define FSL_SAI_RDR4    0xb0 /* SAI Receive Data 4 */
  61 #define FSL_SAI_RDR5    0xb4 /* SAI Receive Data 5 */
  62 #define FSL_SAI_RDR6    0xb8 /* SAI Receive Data 6 */
  63 #define FSL_SAI_RDR7    0xbc /* SAI Receive Data 7 */
  64 #define FSL_SAI_RFR0    0xc0 /* SAI Receive FIFO 0 */
  65 #define FSL_SAI_RFR1    0xc4 /* SAI Receive FIFO 1 */
  66 #define FSL_SAI_RFR2    0xc8 /* SAI Receive FIFO 2 */
  67 #define FSL_SAI_RFR3    0xcc /* SAI Receive FIFO 3 */
  68 #define FSL_SAI_RFR4    0xd0 /* SAI Receive FIFO 4 */
  69 #define FSL_SAI_RFR5    0xd4 /* SAI Receive FIFO 5 */
  70 #define FSL_SAI_RFR6    0xd8 /* SAI Receive FIFO 6 */
  71 #define FSL_SAI_RFR7    0xdc /* SAI Receive FIFO 7 */
  72 #define FSL_SAI_RMR     0xe0 /* SAI Receive Mask */
  73 #define FSL_SAI_RTCTL   0xf0 /* SAI Receive Timestamp Control Register */
  74 #define FSL_SAI_RTCTN   0xf4 /* SAI Receive Timestamp Counter Register */
  75 #define FSL_SAI_RBCTN   0xf8 /* SAI Receive Bit Counter Register */
  76 #define FSL_SAI_RTCAP   0xfc /* SAI Receive Timestamp Capture */
  77
  78 #define FSL_SAI_MCTL    0x100 /* SAI MCLK Control Register */
  79 #define FSL_SAI_MDIV    0x104 /* SAI MCLK Divide Register */
  80
  81 #define FSL_SAI_xCSR(tx, ofs)   (tx ? FSL_SAI_TCSR(ofs) : FSL_SAI_RCSR(ofs))
  82 #define FSL_SAI_xCR1(tx, ofs)   (tx ? FSL_SAI_TCR1(ofs) : FSL_SAI_RCR1(ofs))
  83 #define FSL_SAI_xCR2(tx, ofs)   (tx ? FSL_SAI_TCR2(ofs) : FSL_SAI_RCR2(ofs))
  84 #define FSL_SAI_xCR3(tx, ofs)   (tx ? FSL_SAI_TCR3(ofs) : FSL_SAI_RCR3(ofs))
  85 #define FSL_SAI_xCR4(tx, ofs)   (tx ? FSL_SAI_TCR4(ofs) : FSL_SAI_RCR4(ofs))
  86 #define FSL_SAI_xCR5(tx, ofs)   (tx ? FSL_SAI_TCR5(ofs) : FSL_SAI_RCR5(ofs))
  87 #define FSL_SAI_xDR0(tx)        (tx ? FSL_SAI_TDR0 : FSL_SAI_RDR0)
  88 #define FSL_SAI_xFR0(tx)        (tx ? FSL_SAI_TFR0 : FSL_SAI_RFR0)
  89 #define FSL_SAI_xMR(tx)         (tx ? FSL_SAI_TMR : FSL_SAI_RMR)
  90
  91 /* SAI Transmit/Receive Control Register */
  92 #define FSL_SAI_CSR_TERE        BIT(31)
  93 #define FSL_SAI_CSR_SE          BIT(30)
  94 #define FSL_SAI_CSR_BCE         BIT(28)
  95 #define FSL_SAI_CSR_FR          BIT(25)
  96 #define FSL_SAI_CSR_SR          BIT(24)
  97 #define FSL_SAI_CSR_xF_SHIFT    16
  98 #define FSL_SAI_CSR_xF_W_SHIFT  18
  99 #define FSL_SAI_CSR_xF_MASK     (0x1f << FSL_SAI_CSR_xF_SHIFT)
 100 #define FSL_SAI_CSR_xF_W_MASK   (0x7 << FSL_SAI_CSR_xF_W_SHIFT)
 101 #define FSL_SAI_CSR_WSF         BIT(20)
 102 #define FSL_SAI_CSR_SEF         BIT(19)
 103 #define FSL_SAI_CSR_FEF         BIT(18)
 104 #define FSL_SAI_CSR_FWF         BIT(17)
 105 #define FSL_SAI_CSR_FRF         BIT(16)
 106 #define FSL_SAI_CSR_xIE_SHIFT   8
 107 #define FSL_SAI_CSR_xIE_MASK    (0x1f << FSL_SAI_CSR_xIE_SHIFT)
 108 #define FSL_SAI_CSR_WSIE        BIT(12)
 109 #define FSL_SAI_CSR_SEIE        BIT(11)
 110 #define FSL_SAI_CSR_FEIE        BIT(10)
 111 #define FSL_SAI_CSR_FWIE        BIT(9)
 112 #define FSL_SAI_CSR_FRIE        BIT(8)
 113 #define FSL_SAI_CSR_FRDE        BIT(0)
 114
 115 /* SAI Transmit and Receive Configuration 1 Register */
 116 #define FSL_SAI_CR1_RFW_MASK(x) ((x) - 1)
 117
 118 /* SAI Transmit and Receive Configuration 2 Register */
 119 #define FSL_SAI_CR2_SYNC        BIT(30)
 120 #define FSL_SAI_CR2_BCI         BIT(28)
 121 #define FSL_SAI_CR2_MSEL_MASK   (0x3 << 26)
 122 #define FSL_SAI_CR2_MSEL_BUS    0
 123 #define FSL_SAI_CR2_MSEL_MCLK1  BIT(26)
 124 #define FSL_SAI_CR2_MSEL_MCLK2  BIT(27)
 125 #define FSL_SAI_CR2_MSEL_MCLK3  (BIT(26) | BIT(27))
 126 #define FSL_SAI_CR2_MSEL(ID)    ((ID) << 26)
 127 #define FSL_SAI_CR2_BCP         BIT(25)
 128 #define FSL_SAI_CR2_BCD_MSTR    BIT(24)
 129 #define FSL_SAI_CR2_BYP         BIT(23) /* BCLK bypass */
 130 #define FSL_SAI_CR2_DIV_MASK    0xff
 131
 132 /* SAI Transmit and Receive Configuration 3 Register */
 133 #define FSL_SAI_CR3_TRCE(x)     ((x) << 16)
 134 #define FSL_SAI_CR3_TRCE_MASK   GENMASK(23, 16)
 135 #define FSL_SAI_CR3_WDFL(x)     (x)
 136 #define FSL_SAI_CR3_WDFL_MASK   0x1f
 137
 138 /* SAI Transmit and Receive Configuration 4 Register */
 139
 140 #define FSL_SAI_CR4_FCONT_MASK  BIT(28)
 141 #define FSL_SAI_CR4_FCONT       BIT(28)
 142 #define FSL_SAI_CR4_FCOMB_SHIFT BIT(26)
 143 #define FSL_SAI_CR4_FCOMB_SOFT  BIT(27)
 144 #define FSL_SAI_CR4_FCOMB_MASK  (0x3 << 26)
 145 #define FSL_SAI_CR4_FPACK_8     (0x2 << 24)
 146 #define FSL_SAI_CR4_FPACK_16    (0x3 << 24)
 147 #define FSL_SAI_CR4_FRSZ(x)     (((x) - 1) << 16)
 148 #define FSL_SAI_CR4_FRSZ_MASK   (0x1f << 16)
 149 #define FSL_SAI_CR4_SYWD(x)     (((x) - 1) << 8)
 150 #define FSL_SAI_CR4_SYWD_MASK   (0x1f << 8)
 151 #define FSL_SAI_CR4_CHMOD       BIT(5)
 152 #define FSL_SAI_CR4_CHMOD_MASK  BIT(5)
 153 #define FSL_SAI_CR4_MF          BIT(4)
 154 #define FSL_SAI_CR4_FSE         BIT(3)
 155 #define FSL_SAI_CR4_FSP         BIT(1)
 156 #define FSL_SAI_CR4_FSD_MSTR    BIT(0)
 157
 158 /* SAI Transmit and Receive Configuration 5 Register */
 159 #define FSL_SAI_CR5_WNW(x)      (((x) - 1) << 24)
 160 #define FSL_SAI_CR5_WNW_MASK    (0x1f << 24)
 161 #define FSL_SAI_CR5_W0W(x)      (((x) - 1) << 16)
 162 #define FSL_SAI_CR5_W0W_MASK    (0x1f << 16)
 163 #define FSL_SAI_CR5_FBT(x)      ((x) << 8)
 164 #define FSL_SAI_CR5_FBT_MASK    (0x1f << 8)
 165
 166 /* SAI MCLK Control Register */
 167 #define FSL_SAI_MCTL_MCLK_EN    BIT(30) /* MCLK Enable */
 168 #define FSL_SAI_MCTL_MSEL_MASK  (0x3 << 24)
 169 #define FSL_SAI_MCTL_MSEL(ID)   ((ID) << 24)
 170 #define FSL_SAI_MCTL_MSEL_BUS   0
 171 #define FSL_SAI_MCTL_MSEL_MCLK1 BIT(24)
 172 #define FSL_SAI_MCTL_MSEL_MCLK2 BIT(25)
 173 #define FSL_SAI_MCTL_MSEL_MCLK3 (BIT(24) | BIT(25))
 174 #define FSL_SAI_MCTL_DIV_EN     BIT(23)
 175 #define FSL_SAI_MCTL_DIV_MASK   0xFF
 176
 177 /* SAI VERID Register */
 178 #define FSL_SAI_VERID_MAJOR_SHIFT   24
 179 #define FSL_SAI_VERID_MAJOR_MASK    GENMASK(31, 24)
 180 #define FSL_SAI_VERID_MINOR_SHIFT   16
 181 #define FSL_SAI_VERID_MINOR_MASK    GENMASK(23, 16)
 182 #define FSL_SAI_VERID_FEATURE_SHIFT 0
 183 #define FSL_SAI_VERID_FEATURE_MASK  GENMASK(15, 0)
 184 #define FSL_SAI_VERID_EFIFO_EN      BIT(0)
 185 #define FSL_SAI_VERID_TSTMP_EN      BIT(1)
 186
 187 /* SAI PARAM Register */
 188 #define FSL_SAI_PARAM_SPF_SHIFT     16
 189 #define FSL_SAI_PARAM_SPF_MASK      GENMASK(19, 16)
 190 #define FSL_SAI_PARAM_WPF_SHIFT     8
 191 #define FSL_SAI_PARAM_WPF_MASK      GENMASK(11, 8)
 192 #define FSL_SAI_PARAM_DLN_MASK      GENMASK(3, 0)
 193
 194 /* SAI MCLK Divide Register */
 195 #define FSL_SAI_MDIV_MASK           0xFFFFF
 196
 197 /* SAI timestamp and bitcounter */
 198 #define FSL_SAI_xTCTL_TSEN         BIT(0)
 199 #define FSL_SAI_xTCTL_TSINC        BIT(1)
 200 #define FSL_SAI_xTCTL_RTSC         BIT(8)
 201 #define FSL_SAI_xTCTL_RBC          BIT(9)
 202
 203 /* SAI type */
 204 #define FSL_SAI_DMA             BIT(0)
 205 #define FSL_SAI_USE_AC97        BIT(1)
 206 #define FSL_SAI_NET             BIT(2)
 207 #define FSL_SAI_TRA_SYN         BIT(3)
 208 #define FSL_SAI_REC_SYN         BIT(4)
 209 #define FSL_SAI_USE_I2S_SLAVE   BIT(5)
 210
 211 /* SAI clock sources */
 212 #define FSL_SAI_CLK_BUS         0
 213 #define FSL_SAI_CLK_MAST1       1
 214 #define FSL_SAI_CLK_MAST2       2
 215 #define FSL_SAI_CLK_MAST3       3
 216
 217 #define FSL_SAI_MCLK_MAX        4
 218
 219 /* SAI data transfer numbers per DMA request */
 220 #define FSL_SAI_MAXBURST_TX 6
 221 #define FSL_SAI_MAXBURST_RX 6
 222
 223 #define PMQOS_CPU_LATENCY   BIT(0)
 224
 225 /* Max number of dataline */
 226 #define FSL_SAI_DL_NUM          (8)
 227 /* default dataline type is zero */
 228 #define FSL_SAI_DL_DEFAULT      (0)
 229 #define FSL_SAI_DL_I2S          BIT(0)
 230 #define FSL_SAI_DL_PDM          BIT(1)
 231
 232 struct fsl_sai_soc_data {
 233         bool use_imx_pcm;
 234         bool use_edma;
 235         bool mclk0_is_mclk1;
 236         bool mclk_with_tere;
 237         unsigned int fifo_depth;
 238         unsigned int pins;
 239         unsigned int reg_offset;
 240         unsigned int flags;
 241         unsigned int max_register;
 242         unsigned int max_burst[2];
 243 };
 244
 245 /**
 246  * struct fsl_sai_verid - version id data
 247  * @version: version number
 248  * @feature: feature specification number
 249  *           0000000000000000b - Standard feature set
 250  *           0000000000000000b - Standard feature set
 251  */
 252 struct fsl_sai_verid {
 253         u32 version;
 254         u32 feature;
 255 };
 256
 257 /**
 258  * struct fsl_sai_param - parameter data
 259  * @slot_num: The maximum number of slots per frame
 260  * @fifo_depth: The number of words in each FIFO (depth)
 261  * @dataline: The number of datalines implemented
 262  */
 263 struct fsl_sai_param {
 264         u32 slot_num;
 265         u32 fifo_depth;
 266         u32 dataline;
 267 };
 268
 269 struct fsl_sai_dl_cfg {
 270         unsigned int type;
 271         unsigned int pins[2];
 272         unsigned int mask[2];
 273         unsigned int start_off[2];
 274         unsigned int next_off[2];
 275 };
 276
 277 struct fsl_sai {
 278         struct platform_device *pdev;
 279         struct regmap *regmap;
 280         struct clk *bus_clk;
 281         struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
 282         struct clk *pll8k_clk;
 283         struct clk *pll11k_clk;
 284         struct resource *res;
 285
 286         bool is_consumer_mode[2];
 287         bool is_lsb_first;
 288         bool is_dsp_mode;
 289         bool is_pdm_mode;
 290         bool is_multi_fifo_dma;
 291         bool synchronous[2];
 292         struct fsl_sai_dl_cfg *dl_cfg;
 293         unsigned int dl_cfg_cnt;
 294         bool mclk_direction_output;
 295
 296         unsigned int mclk_id[2];
 297         unsigned int mclk_streams;
 298         unsigned int slots;
 299         unsigned int slot_width;
 300         unsigned int bclk_ratio;
 301
 302         const struct fsl_sai_soc_data *soc_data;
 303         struct snd_soc_dai_driver cpu_dai_drv[3];
 304         struct snd_dmaengine_dai_dma_data dma_params_rx;
 305         struct snd_dmaengine_dai_dma_data dma_params_tx;
 306         struct fsl_sai_verid verid;
 307         struct fsl_sai_param param;
 308         struct pm_qos_request pm_qos_req;
 309         struct pinctrl *pinctrl;
 310         struct pinctrl_state *pins_state;
 311         struct sdma_peripheral_config audio_config[2];
 312 };
 313
 314 #define TX 1
 315 #define RX 0
 316
 317 #endif /* __FSL_SAI_H */