1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 IPC controller
10 The IPCC block provides a non blocking signaling mechanism to post and
11 retrieve messages in an atomic way between two processors.
12 It provides the signaling for N bidirectionnal channels. The number of
13 channels (N) can be read from a dedicated register.
16 - Fabien Dessenne <fabien.dessenne@foss.st.com>
17 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
21 const: st,stm32mp1-ipcc
31 - description: rx channel occupied
32 - description: tx channel free
45 description: Processor id using the mailbox (0 or 1)
46 $ref: /schemas/types.yaml#/definitions/uint32
58 additionalProperties: false
62 #include <dt-bindings/interrupt-controller/arm-gic.h>
63 #include <dt-bindings/clock/stm32mp1-clks.h>
64 ipcc: mailbox@4c001000 {
65 compatible = "st,stm32mp1-ipcc";
67 reg = <0x4c001000 0x400>;
69 interrupts-extended = <&exti 61 1>,
70 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
71 interrupt-names = "rx", "tx";
72 clocks = <&rcc_clk IPCC>;