Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: HiSilicon Kirin SoCs PCIe host DT description
   8
   9 maintainers:
  10   - Xiaowei Song <songxiaowei@hisilicon.com>
  11   - Binghui Wang <wangbinghui@hisilicon.com>
  12
  13 description: |
  14   Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
  15   It shares common functions with the PCIe DesignWare core driver and
  16   inherits common properties defined in
  17   Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
  18
  19 allOf:
  20   - $ref: /schemas/pci/snps,dw-pcie.yaml#
  21
  22 properties:
  23   compatible:
  24     contains:
  25       enum:
  26         - hisilicon,kirin960-pcie
  27         - hisilicon,kirin970-pcie
  28
  29   reg:
  30     description: |
  31       Should contain dbi, apb, config registers location and length.
  32       For hisilicon,kirin960-pcie, it should also contain phy.
  33     minItems: 3
  34     maxItems: 4
  35
  36   reg-names:
  37     minItems: 3
  38     maxItems: 4
  39
  40   clocks:
  41     maxItems: 5
  42
  43   clock-names:
  44     items:
  45       - const: pcie_phy_ref
  46       - const: pcie_aux
  47       - const: pcie_apb_phy
  48       - const: pcie_apb_sys
  49       - const: pcie_aclk
  50
  51   phys:
  52     maxItems: 1
  53
  54   hisilicon,clken-gpios:
  55     description: |
  56       Clock input enablement GPIOs from PCI devices like Ethernet, M.2 and
  57       mini-PCIe slots.
  58
  59 required:
  60   - compatible
  61   - reg
  62   - reg-names
  63
  64 unevaluatedProperties: false
  65
  66 examples:
  67   - |
  68     #include <dt-bindings/interrupt-controller/arm-gic.h>
  69     #include <dt-bindings/clock/hi3660-clock.h>
  70     #include <dt-bindings/clock/hi3670-clock.h>
  71
  72     soc {
  73       #address-cells = <2>;
  74       #size-cells = <2>;
  75
  76       pcie@f4000000 {
  77         compatible = "hisilicon,kirin960-pcie";
  78         reg = <0x0 0xf4000000 0x0 0x1000>,
  79               <0x0 0xff3fe000 0x0 0x1000>,
  80               <0x0 0xf3f20000 0x0 0x40000>,
  81               <0x0 0xf5000000 0x0 0x2000>;
  82         reg-names = "dbi", "apb", "phy", "config";
  83         bus-range = <0x0  0xff>;
  84         #address-cells = <3>;
  85         #size-cells = <2>;
  86         device_type = "pci";
  87         ranges = <0x02000000 0x0 0x00000000
  88                   0x0 0xf6000000
  89                   0x0 0x02000000>;
  90         num-lanes = <1>;
  91         #interrupt-cells = <1>;
  92         interrupts = <0 283 4>;
  93         interrupt-names = "msi";
  94         interrupt-map-mask = <0xf800 0 0 7>;
  95         interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
  96                         <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
  97                         <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
  98                         <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
  99         clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
 100                  <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
 101                  <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
 102                  <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
 103                  <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
 104         clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy",
 105                       "pcie_apb_sys", "pcie_aclk";
 106       };
 107
 108       pcie@f5000000 {
 109         compatible = "hisilicon,kirin970-pcie";
 110         reg = <0x0 0xf4000000 0x0 0x1000000>,
 111               <0x0 0xfc180000 0x0 0x1000>,
 112               <0x0 0xf5000000 0x0 0x2000>;
 113         reg-names = "dbi", "apb", "config";
 114         bus-range = <0x0  0xff>;
 115         #address-cells = <3>;
 116         #size-cells = <2>;
 117         device_type = "pci";
 118         phys = <&pcie_phy>;
 119         ranges = <0x02000000 0x0 0x00000000
 120                   0x0 0xf6000000
 121                   0x0 0x02000000>;
 122         num-lanes = <1>;
 123         #interrupt-cells = <1>;
 124         interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
 125         interrupt-names = "msi";
 126         interrupt-map-mask = <0 0 0 7>;
 127         interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
 128                         <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
 129                         <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
 130                         <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
 131         reset-gpios = <&gpio7 0 0>;
 132         hisilicon,clken-gpios = <&gpio27 3 0>, <&gpio17 0 0>, <&gpio20 6 0>;
 133         pcie@0,0 { // Lane 0: PCIe switch: Bus 1, Device 0
 134           reg = <0 0 0 0 0>;
 135           compatible = "pciclass,0604";
 136           device_type = "pci";
 137           #address-cells = <3>;
 138           #size-cells = <2>;
 139           ranges;
 140
 141           pcie@0,0 { // Lane 0: upstream
 142             reg = <0 0 0 0 0>;
 143             compatible = "pciclass,0604";
 144             device_type = "pci";
 145             #address-cells = <3>;
 146             #size-cells = <2>;
 147             ranges;
 148
 149             pcie@1,0 { // Lane 4: M.2
 150               reg = <0x0800 0 0 0 0>;
 151               compatible = "pciclass,0604";
 152               device_type = "pci";
 153               reset-gpios = <&gpio3 1 0>;
 154               #address-cells = <3>;
 155               #size-cells = <2>;
 156               ranges;
 157             };
 158
 159             pcie@5,0 { // Lane 5: Mini PCIe
 160               reg = <0x2800 0 0 0 0>;
 161               compatible = "pciclass,0604";
 162               device_type = "pci";
 163               reset-gpios = <&gpio27 4 0 >;
 164               #address-cells = <3>;
 165               #size-cells = <2>;
 166               ranges;
 167             };
 168
 169             pcie@7,0 { // Lane 6: Ethernet
 170               reg = <0x03800 0 0 0 0>;
 171               compatible = "pciclass,0604";
 172               device_type = "pci";
 173               reset-gpios = <&gpio25 2 0 >;
 174               #address-cells = <3>;
 175               #size-cells = <2>;
 176               ranges;
 177             };
 178           };
 179         };
 180       };
 181     };