Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 # Copyright (C) 2022-2023 Renesas Electronics Corp.
   3 %YAML 1.2
   4 ---
   5 $id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml#
   6 $schema: http://devicetree.org/meta-schemas/core.yaml#
   7
   8 title: Renesas R-Car Gen4 PCIe Endpoint
   9
  10 maintainers:
  11   - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
  12
  13 allOf:
  14   - $ref: snps,dw-pcie-ep.yaml#
  15
  16 properties:
  17   compatible:
  18     items:
  19       - enum:
  20           - renesas,r8a779f0-pcie-ep      # R-Car S4-8
  21           - renesas,r8a779g0-pcie-ep      # R-Car V4H
  22           - renesas,r8a779h0-pcie-ep      # R-Car V4M
  23       - const: renesas,rcar-gen4-pcie-ep  # R-Car Gen4
  24
  25   reg:
  26     maxItems: 7
  27
  28   reg-names:
  29     items:
  30       - const: dbi
  31       - const: dbi2
  32       - const: atu
  33       - const: dma
  34       - const: app
  35       - const: phy
  36       - const: addr_space
  37
  38   interrupts:
  39     maxItems: 3
  40
  41   interrupt-names:
  42     items:
  43       - const: dma
  44       - const: sft_ce
  45       - const: app
  46
  47   clocks:
  48     maxItems: 2
  49
  50   clock-names:
  51     items:
  52       - const: core
  53       - const: ref
  54
  55   power-domains:
  56     maxItems: 1
  57
  58   resets:
  59     maxItems: 1
  60
  61   reset-names:
  62     items:
  63       - const: pwr
  64
  65   max-link-speed:
  66     maximum: 4
  67
  68   num-lanes:
  69     maximum: 4
  70
  71   max-functions:
  72     maximum: 2
  73
  74 required:
  75   - compatible
  76   - reg
  77   - reg-names
  78   - interrupts
  79   - interrupt-names
  80   - clocks
  81   - clock-names
  82   - power-domains
  83   - resets
  84   - reset-names
  85
  86 unevaluatedProperties: false
  87
  88 examples:
  89   - |
  90     #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
  91     #include <dt-bindings/interrupt-controller/arm-gic.h>
  92     #include <dt-bindings/power/r8a779f0-sysc.h>
  93
  94     soc {
  95         #address-cells = <2>;
  96         #size-cells = <2>;
  97
  98         pcie0_ep: pcie-ep@e65d0000 {
  99             compatible = "renesas,r8a779f0-pcie-ep", "renesas,rcar-gen4-pcie-ep";
 100             reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
 101                   <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
 102                   <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
 103                   <0 0xfe000000 0 0x400000>;
 104             reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
 105             interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
 106                          <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
 107                          <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
 108             interrupt-names = "dma", "sft_ce", "app";
 109             clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
 110             clock-names = "core", "ref";
 111             power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 112             resets = <&cpg 624>;
 113             reset-names = "pwr";
 114             max-link-speed = <4>;
 115             num-lanes = <2>;
 116             max-functions = /bits/ 8 <2>;
 117         };
 118     };