Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: StarFive JH7110 PCIe host controller
   8
   9 maintainers:
  10   - Kevin Xie <kevin.xie@starfivetech.com>
  11
  12 allOf:
  13   - $ref: plda,xpressrich3-axi-common.yaml#
  14
  15 properties:
  16   compatible:
  17     const: starfive,jh7110-pcie
  18
  19   clocks:
  20     items:
  21       - description: NOC bus clock
  22       - description: Transport layer clock
  23       - description: AXI MST0 clock
  24       - description: APB clock
  25
  26   clock-names:
  27     items:
  28       - const: noc
  29       - const: tl
  30       - const: axi_mst0
  31       - const: apb
  32
  33   resets:
  34     items:
  35       - description: AXI MST0 reset
  36       - description: AXI SLAVE0 reset
  37       - description: AXI SLAVE reset
  38       - description: PCIE BRIDGE reset
  39       - description: PCIE CORE reset
  40       - description: PCIE APB reset
  41
  42   reset-names:
  43     items:
  44       - const: mst0
  45       - const: slv0
  46       - const: slv
  47       - const: brg
  48       - const: core
  49       - const: apb
  50
  51   starfive,stg-syscon:
  52     $ref: /schemas/types.yaml#/definitions/phandle-array
  53     description:
  54       The phandle to System Register Controller syscon node.
  55
  56   perst-gpios:
  57     description: GPIO controlled connection to PERST# signal
  58     maxItems: 1
  59
  60   phys:
  61     description:
  62       Specified PHY is attached to PCIe controller.
  63     maxItems: 1
  64
  65 required:
  66   - clocks
  67   - resets
  68   - starfive,stg-syscon
  69
  70 unevaluatedProperties: false
  71
  72 examples:
  73   - |
  74     #include <dt-bindings/gpio/gpio.h>
  75     soc {
  76         #address-cells = <2>;
  77         #size-cells = <2>;
  78
  79         pcie@940000000 {
  80             compatible = "starfive,jh7110-pcie";
  81             reg = <0x9 0x40000000 0x0 0x10000000>,
  82                   <0x0 0x2b000000 0x0 0x1000000>;
  83             reg-names = "cfg", "apb";
  84             #address-cells = <3>;
  85             #size-cells = <2>;
  86             #interrupt-cells = <1>;
  87             device_type = "pci";
  88             ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
  89                      <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
  90             starfive,stg-syscon = <&stg_syscon>;
  91             bus-range = <0x0 0xff>;
  92             interrupt-parent = <&plic>;
  93             interrupts = <56>;
  94             interrupt-map-mask = <0x0 0x0 0x0 0x7>;
  95             interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
  96                             <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
  97                             <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
  98                             <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
  99             msi-controller;
 100             clocks = <&syscrg 86>,
 101                      <&stgcrg 10>,
 102                      <&stgcrg 8>,
 103                      <&stgcrg 9>;
 104             clock-names = "noc", "tl", "axi_mst0", "apb";
 105             resets = <&stgcrg 11>,
 106                      <&stgcrg 12>,
 107                      <&stgcrg 13>,
 108                      <&stgcrg 14>,
 109                      <&stgcrg 15>,
 110                      <&stgcrg 16>;
 111             perst-gpios = <&gpios 26 GPIO_ACTIVE_LOW>;
 112             phys = <&pciephy0>;
 113
 114             pcie_intc0: interrupt-controller {
 115                 #address-cells = <0>;
 116                 #interrupt-cells = <1>;
 117                 interrupt-controller;
 118             };
 119         };
 120     };