1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/phy/allwinner,sun9i-a80-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A80 USB PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
18 const: allwinner,sun9i-a80-usb-phy
26 description: Main PHY Clock
29 - description: Main PHY clock
30 - description: HSIC 12MHz clock
31 - description: HSIC 480MHz clock
45 - description: Normal USB PHY reset
46 - description: HSIC Reset
57 When absent, the PHY type will be assumed to be normal USB.
61 Regulator that powers VBUS
72 additionalProperties: false
98 #include <dt-bindings/clock/sun9i-a80-usb.h>
99 #include <dt-bindings/reset/sun9i-a80-usb.h>
101 usbphy1: phy@a00800 {
102 compatible = "allwinner,sun9i-a80-usb-phy";
103 reg = <0x00a00800 0x4>;
104 clocks = <&usb_clocks CLK_USB0_PHY>;
106 resets = <&usb_clocks RST_USB0_PHY>;
108 phy-supply = <®_usb1_vbus>;
113 #include <dt-bindings/clock/sun9i-a80-usb.h>
114 #include <dt-bindings/reset/sun9i-a80-usb.h>
116 usbphy3: phy@a02800 {
117 compatible = "allwinner,sun9i-a80-usb-phy";
118 reg = <0x00a02800 0x4>;
119 clocks = <&usb_clocks CLK_USB2_PHY>,
120 <&usb_clocks CLK_USB_HSIC>,
121 <&usb_clocks CLK_USB2_HSIC>;
125 resets = <&usb_clocks RST_USB2_PHY>,
126 <&usb_clocks RST_USB2_HSIC>;
130 phy-supply = <®_usb3_vbus>;