Documentation/devicetree/bindings/phy/hisilicon,hi3798cv200-combphy.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/phy/hisilicon,hi3798cv200-combphy.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: HiSilicon STB PCIE/SATA/USB3 PHY
   8
   9 maintainers:
  10   - Shawn Guo <shawn.guo@linaro.org>
  11
  12 properties:
  13   compatible:
  14     const: hisilicon,hi3798cv200-combphy
  15
  16   reg:
  17     maxItems: 1
  18
  19   '#phy-cells':
  20     description: The cell contains the PHY mode
  21     const: 1
  22
  23   clocks:
  24     maxItems: 1
  25
  26   resets:
  27     maxItems: 1
  28
  29   hisilicon,fixed-mode:
  30     description: If the phy device doesn't support mode select but a fixed mode
  31       setting, the property should be present to specify the particular mode.
  32     $ref: /schemas/types.yaml#/definitions/uint32
  33     enum: [ 1, 2, 4]  # SATA, PCIE, USB3
  34
  35   hisilicon,mode-select-bits:
  36     description: If the phy device support mode select, this property should be
  37       present to specify the register bits in peripheral controller.
  38     items:
  39       - description: register_offset
  40       - description: bit shift
  41       - description: bit mask
  42
  43 required:
  44   - compatible
  45   - reg
  46   - '#phy-cells'
  47   - clocks
  48   - resets
  49
  50 oneOf:
  51   - required: ['hisilicon,fixed-mode']
  52   - required: ['hisilicon,mode-select-bits']
  53
  54 additionalProperties: false
  55
  56 ...