drm/bridge: Fix assignment of the of_node of the parent to aux bridge
[drm/drm-misc.git] / Documentation / devicetree / bindings / rtc / xlnx,zynqmp-rtc.yaml
blob01cc90fee81e5e88eda793d658e5c9aa43cf8554
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/rtc/xlnx,zynqmp-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
9 description:
10   RTC controller for the Xilinx Zynq MPSoC Real Time Clock.
11   The RTC controller has separate IRQ lines for seconds and alarm.
13 maintainers:
14   - Michal Simek <michal.simek@amd.com>
16 allOf:
17   - $ref: rtc.yaml#
19 properties:
20   compatible:
21     oneOf:
22       - const: xlnx,zynqmp-rtc
23       - items:
24           - enum:
25               - xlnx,versal-rtc
26               - xlnx,versal-net-rtc
27           - const: xlnx,zynqmp-rtc
29   reg:
30     maxItems: 1
32   clocks:
33     maxItems: 1
35   clock-names:
36     items:
37       - const: rtc
39   interrupts:
40     maxItems: 2
42   interrupt-names:
43     items:
44       - const: alarm
45       - const: sec
47   calibration:
48     description: |
49       calibration value for 1 sec period which will
50       be programmed directly to calibration register.
51     $ref: /schemas/types.yaml#/definitions/uint32
52     minimum: 0x1
53     maximum: 0x1FFFFF
54     default: 0x198233
55     deprecated: true
57   power-domains:
58     maxItems: 1
60 required:
61   - compatible
62   - reg
63   - interrupts
64   - interrupt-names
66 additionalProperties: false
68 examples:
69   - |
70     soc {
71       #address-cells = <2>;
72       #size-cells = <2>;
74       rtc: rtc@ffa60000 {
75         compatible = "xlnx,zynqmp-rtc";
76         reg = <0x0 0xffa60000 0x0 0x100>;
77         interrupt-parent = <&gic>;
78         interrupts = <0 26 4>, <0 27 4>;
79         interrupt-names = "alarm", "sec";
80         calibration = <0x198233>;
81         clock-names = "rtc";
82         clocks = <&rtc_clk>;
83       };
84     };