1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/spi/nvidia,tegra20-sflash.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 SFLASH controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra20-sflash
25 - description: module clock
29 - description: module reset
37 - description: DMA channel used for reception
38 - description: DMA channel used for transmission
46 description: Maximum SPI clocking speed of the controller in Hz.
47 $ref: /schemas/types.yaml#/definitions/uint32
50 - $ref: spi-controller.yaml
52 unevaluatedProperties: false
66 #include <dt-bindings/clock/tegra20-car.h>
67 #include <dt-bindings/interrupt-controller/arm-gic.h>
70 compatible = "nvidia,tegra20-sflash";
71 reg = <0x7000c380 0x80>;
72 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
73 spi-max-frequency = <25000000>;
76 clocks = <&tegra_car TEGRA20_CLK_SPI>;
77 resets = <&tegra_car 43>;
79 dmas = <&apbdma 11>, <&apbdma 11>;
80 dma-names = "rx", "tx";